1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 #define IFLIB_RXEOF_MORE (1U << 0) 133 #define IFLIB_RXEOF_EMPTY (2U << 0) 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 static void iflib_timer(void *arg); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 199 qidx_t ifc_sysctl_ntxds[8]; 200 qidx_t ifc_sysctl_nrxds[8]; 201 struct if_txrx ifc_txrx; 202 #define isc_txd_encap ifc_txrx.ift_txd_encap 203 #define isc_txd_flush ifc_txrx.ift_txd_flush 204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 205 #define isc_rxd_available ifc_txrx.ift_rxd_available 206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 210 eventhandler_tag ifc_vlan_attach_event; 211 eventhandler_tag ifc_vlan_detach_event; 212 struct ether_addr ifc_mac; 213 }; 214 215 void * 216 iflib_get_softc(if_ctx_t ctx) 217 { 218 219 return (ctx->ifc_softc); 220 } 221 222 device_t 223 iflib_get_dev(if_ctx_t ctx) 224 { 225 226 return (ctx->ifc_dev); 227 } 228 229 if_t 230 iflib_get_ifp(if_ctx_t ctx) 231 { 232 233 return (ctx->ifc_ifp); 234 } 235 236 struct ifmedia * 237 iflib_get_media(if_ctx_t ctx) 238 { 239 240 return (ctx->ifc_mediap); 241 } 242 243 uint32_t 244 iflib_get_flags(if_ctx_t ctx) 245 { 246 return (ctx->ifc_flags); 247 } 248 249 void 250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 251 { 252 253 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 254 } 255 256 if_softc_ctx_t 257 iflib_get_softc_ctx(if_ctx_t ctx) 258 { 259 260 return (&ctx->ifc_softc_ctx); 261 } 262 263 if_shared_ctx_t 264 iflib_get_sctx(if_ctx_t ctx) 265 { 266 267 return (ctx->ifc_sctx); 268 } 269 270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 273 274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 276 277 typedef struct iflib_sw_rx_desc_array { 278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 279 struct mbuf **ifsd_m; /* pkthdr mbufs */ 280 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 281 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 282 } iflib_rxsd_array_t; 283 284 typedef struct iflib_sw_tx_desc_array { 285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 286 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 287 struct mbuf **ifsd_m; /* pkthdr mbufs */ 288 } if_txsd_vec_t; 289 290 /* magic number that should be high enough for any hardware */ 291 #define IFLIB_MAX_TX_SEGS 128 292 #define IFLIB_RX_COPY_THRESH 128 293 #define IFLIB_MAX_RX_REFRESH 32 294 /* The minimum descriptors per second before we start coalescing */ 295 #define IFLIB_MIN_DESC_SEC 16384 296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 297 #define IFLIB_QUEUE_IDLE 0 298 #define IFLIB_QUEUE_HUNG 1 299 #define IFLIB_QUEUE_WORKING 2 300 /* maximum number of txqs that can share an rx interrupt */ 301 #define IFLIB_MAX_TX_SHARED_INTR 4 302 303 /* this should really scale with ring size - this is a fairly arbitrary value */ 304 #define TX_BATCH_SIZE 32 305 306 #define IFLIB_RESTART_BUDGET 8 307 308 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 309 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 310 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 311 312 struct iflib_txq { 313 qidx_t ift_in_use; 314 qidx_t ift_cidx; 315 qidx_t ift_cidx_processed; 316 qidx_t ift_pidx; 317 uint8_t ift_gen; 318 uint8_t ift_br_offset; 319 uint16_t ift_npending; 320 uint16_t ift_db_pending; 321 uint16_t ift_rs_pending; 322 /* implicit pad */ 323 uint8_t ift_txd_size[8]; 324 uint64_t ift_processed; 325 uint64_t ift_cleaned; 326 uint64_t ift_cleaned_prev; 327 #if MEMORY_LOGGING 328 uint64_t ift_enqueued; 329 uint64_t ift_dequeued; 330 #endif 331 uint64_t ift_no_tx_dma_setup; 332 uint64_t ift_no_desc_avail; 333 uint64_t ift_mbuf_defrag_failed; 334 uint64_t ift_mbuf_defrag; 335 uint64_t ift_map_failed; 336 uint64_t ift_txd_encap_efbig; 337 uint64_t ift_pullups; 338 uint64_t ift_last_timer_tick; 339 340 struct mtx ift_mtx; 341 struct mtx ift_db_mtx; 342 343 /* constant values */ 344 if_ctx_t ift_ctx; 345 struct ifmp_ring *ift_br; 346 struct grouptask ift_task; 347 qidx_t ift_size; 348 uint16_t ift_id; 349 struct callout ift_timer; 350 351 if_txsd_vec_t ift_sds; 352 uint8_t ift_qstatus; 353 uint8_t ift_closed; 354 uint8_t ift_update_freq; 355 struct iflib_filter_info ift_filter_info; 356 bus_dma_tag_t ift_buf_tag; 357 bus_dma_tag_t ift_tso_buf_tag; 358 iflib_dma_info_t ift_ifdi; 359 #define MTX_NAME_LEN 32 360 char ift_mtx_name[MTX_NAME_LEN]; 361 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 362 #ifdef IFLIB_DIAGNOSTICS 363 uint64_t ift_cpu_exec_count[256]; 364 #endif 365 } __aligned(CACHE_LINE_SIZE); 366 367 struct iflib_fl { 368 qidx_t ifl_cidx; 369 qidx_t ifl_pidx; 370 qidx_t ifl_credits; 371 uint8_t ifl_gen; 372 uint8_t ifl_rxd_size; 373 #if MEMORY_LOGGING 374 uint64_t ifl_m_enqueued; 375 uint64_t ifl_m_dequeued; 376 uint64_t ifl_cl_enqueued; 377 uint64_t ifl_cl_dequeued; 378 #endif 379 /* implicit pad */ 380 bitstr_t *ifl_rx_bitmap; 381 qidx_t ifl_fragidx; 382 /* constant */ 383 qidx_t ifl_size; 384 uint16_t ifl_buf_size; 385 uint16_t ifl_cltype; 386 uma_zone_t ifl_zone; 387 iflib_rxsd_array_t ifl_sds; 388 iflib_rxq_t ifl_rxq; 389 uint8_t ifl_id; 390 bus_dma_tag_t ifl_buf_tag; 391 iflib_dma_info_t ifl_ifdi; 392 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 394 } __aligned(CACHE_LINE_SIZE); 395 396 static inline qidx_t 397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 398 { 399 qidx_t used; 400 401 if (pidx > cidx) 402 used = pidx - cidx; 403 else if (pidx < cidx) 404 used = size - cidx + pidx; 405 else if (gen == 0 && pidx == cidx) 406 used = 0; 407 else if (gen == 1 && pidx == cidx) 408 used = size; 409 else 410 panic("bad state"); 411 412 return (used); 413 } 414 415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 416 417 #define IDXDIFF(head, tail, wrap) \ 418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 419 420 struct iflib_rxq { 421 if_ctx_t ifr_ctx; 422 iflib_fl_t ifr_fl; 423 uint64_t ifr_rx_irq; 424 struct pfil_head *pfil; 425 /* 426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 427 * the command queue consumer index. Otherwise it's unused. 428 */ 429 qidx_t ifr_cq_cidx; 430 uint16_t ifr_id; 431 uint8_t ifr_nfl; 432 uint8_t ifr_ntxqirq; 433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 434 uint8_t ifr_fl_offset; 435 struct lro_ctrl ifr_lc; 436 struct grouptask ifr_task; 437 struct callout ifr_watchdog; 438 struct iflib_filter_info ifr_filter_info; 439 iflib_dma_info_t ifr_ifdi; 440 441 /* dynamically allocate if any drivers need a value substantially larger than this */ 442 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 443 #ifdef IFLIB_DIAGNOSTICS 444 uint64_t ifr_cpu_exec_count[256]; 445 #endif 446 } __aligned(CACHE_LINE_SIZE); 447 448 typedef struct if_rxsd { 449 caddr_t *ifsd_cl; 450 iflib_fl_t ifsd_fl; 451 } *if_rxsd_t; 452 453 /* multiple of word size */ 454 #ifdef __LP64__ 455 #define PKT_INFO_SIZE 6 456 #define RXD_INFO_SIZE 5 457 #define PKT_TYPE uint64_t 458 #else 459 #define PKT_INFO_SIZE 11 460 #define RXD_INFO_SIZE 8 461 #define PKT_TYPE uint32_t 462 #endif 463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 465 466 typedef struct if_pkt_info_pad { 467 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 468 } *if_pkt_info_pad_t; 469 typedef struct if_rxd_info_pad { 470 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 471 } *if_rxd_info_pad_t; 472 473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 475 476 477 static inline void 478 pkt_info_zero(if_pkt_info_t pi) 479 { 480 if_pkt_info_pad_t pi_pad; 481 482 pi_pad = (if_pkt_info_pad_t)pi; 483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 485 #ifndef __LP64__ 486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 488 #endif 489 } 490 491 static device_method_t iflib_pseudo_methods[] = { 492 DEVMETHOD(device_attach, noop_attach), 493 DEVMETHOD(device_detach, iflib_pseudo_detach), 494 DEVMETHOD_END 495 }; 496 497 driver_t iflib_pseudodriver = { 498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 499 }; 500 501 static inline void 502 rxd_info_zero(if_rxd_info_t ri) 503 { 504 if_rxd_info_pad_t ri_pad; 505 int i; 506 507 ri_pad = (if_rxd_info_pad_t)ri; 508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 509 ri_pad->rxd_val[i] = 0; 510 ri_pad->rxd_val[i+1] = 0; 511 ri_pad->rxd_val[i+2] = 0; 512 ri_pad->rxd_val[i+3] = 0; 513 } 514 #ifdef __LP64__ 515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 516 #endif 517 } 518 519 /* 520 * Only allow a single packet to take up most 1/nth of the tx ring 521 */ 522 #define MAX_SINGLE_PACKET_FRACTION 12 523 #define IF_BAD_DMA (bus_addr_t)-1 524 525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 526 527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 531 532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 536 537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 539 540 void 541 iflib_set_detach(if_ctx_t ctx) 542 { 543 STATE_LOCK(ctx); 544 ctx->ifc_flags |= IFC_IN_DETACH; 545 STATE_UNLOCK(ctx); 546 } 547 548 /* Our boot-time initialization hook */ 549 static int iflib_module_event_handler(module_t, int, void *); 550 551 static moduledata_t iflib_moduledata = { 552 "iflib", 553 iflib_module_event_handler, 554 NULL 555 }; 556 557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 558 MODULE_VERSION(iflib, 1); 559 560 MODULE_DEPEND(iflib, pci, 1, 1, 1); 561 MODULE_DEPEND(iflib, ether, 1, 1, 1); 562 563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 565 566 #ifndef IFLIB_DEBUG_COUNTERS 567 #ifdef INVARIANTS 568 #define IFLIB_DEBUG_COUNTERS 1 569 #else 570 #define IFLIB_DEBUG_COUNTERS 0 571 #endif /* !INVARIANTS */ 572 #endif 573 574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 575 "iflib driver parameters"); 576 577 /* 578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 579 */ 580 static int iflib_min_tx_latency = 0; 581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 583 static int iflib_no_tx_batch = 0; 584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 586 587 588 #if IFLIB_DEBUG_COUNTERS 589 590 static int iflib_tx_seen; 591 static int iflib_tx_sent; 592 static int iflib_tx_encap; 593 static int iflib_rx_allocs; 594 static int iflib_fl_refills; 595 static int iflib_fl_refills_large; 596 static int iflib_tx_frees; 597 598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 599 &iflib_tx_seen, 0, "# TX mbufs seen"); 600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 601 &iflib_tx_sent, 0, "# TX mbufs sent"); 602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 603 &iflib_tx_encap, 0, "# TX mbufs encapped"); 604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 605 &iflib_tx_frees, 0, "# TX frees"); 606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 607 &iflib_rx_allocs, 0, "# RX allocations"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 609 &iflib_fl_refills, 0, "# refills"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 611 &iflib_fl_refills_large, 0, "# large refills"); 612 613 614 static int iflib_txq_drain_flushing; 615 static int iflib_txq_drain_oactive; 616 static int iflib_txq_drain_notready; 617 618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 619 &iflib_txq_drain_flushing, 0, "# drain flushes"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 621 &iflib_txq_drain_oactive, 0, "# drain oactives"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 623 &iflib_txq_drain_notready, 0, "# drain notready"); 624 625 626 static int iflib_encap_load_mbuf_fail; 627 static int iflib_encap_pad_mbuf_fail; 628 static int iflib_encap_txq_avail_fail; 629 static int iflib_encap_txd_encap_fail; 630 631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 639 640 static int iflib_task_fn_rxs; 641 static int iflib_rx_intr_enables; 642 static int iflib_fast_intrs; 643 static int iflib_rx_unavail; 644 static int iflib_rx_ctx_inactive; 645 static int iflib_rx_if_input; 646 static int iflib_rxd_flush; 647 648 static int iflib_verbose_debug; 649 650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 653 &iflib_rx_intr_enables, 0, "# RX intr enables"); 654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 655 &iflib_fast_intrs, 0, "# fast_intr calls"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 657 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 661 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 663 &iflib_rxd_flush, 0, "# times rxd_flush called"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 665 &iflib_verbose_debug, 0, "enable verbose debugging"); 666 667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 668 static void 669 iflib_debug_reset(void) 670 { 671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 673 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 674 iflib_txq_drain_notready = 675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 678 iflib_rx_unavail = 679 iflib_rx_ctx_inactive = iflib_rx_if_input = 680 iflib_rxd_flush = 0; 681 } 682 683 #else 684 #define DBG_COUNTER_INC(name) 685 static void iflib_debug_reset(void) {} 686 #endif 687 688 #define IFLIB_DEBUG 0 689 690 static void iflib_tx_structures_free(if_ctx_t ctx); 691 static void iflib_rx_structures_free(if_ctx_t ctx); 692 static int iflib_queues_alloc(if_ctx_t ctx); 693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 695 static int iflib_qset_structures_setup(if_ctx_t ctx); 696 static int iflib_msix_init(if_ctx_t ctx); 697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 700 #ifdef ALTQ 701 static void iflib_altq_if_start(if_t ifp); 702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 703 #endif 704 static int iflib_register(if_ctx_t); 705 static void iflib_deregister(if_ctx_t); 706 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 707 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 708 static void iflib_init_locked(if_ctx_t ctx); 709 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 710 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 711 static void iflib_ifmp_purge(iflib_txq_t txq); 712 static void _iflib_pre_assert(if_softc_ctx_t scctx); 713 static void iflib_if_init_locked(if_ctx_t ctx); 714 static void iflib_free_intr_mem(if_ctx_t ctx); 715 #ifndef __NO_STRICT_ALIGNMENT 716 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 717 #endif 718 719 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 720 SLIST_HEAD_INITIALIZER(cpu_offsets); 721 struct cpu_offset { 722 SLIST_ENTRY(cpu_offset) entries; 723 cpuset_t set; 724 unsigned int refcount; 725 uint16_t offset; 726 }; 727 static struct mtx cpu_offset_mtx; 728 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 729 MTX_DEF); 730 731 DEBUGNET_DEFINE(iflib); 732 733 #ifdef DEV_NETMAP 734 #include <sys/selinfo.h> 735 #include <net/netmap.h> 736 #include <dev/netmap/netmap_kern.h> 737 738 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 739 740 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 741 742 /* 743 * device-specific sysctl variables: 744 * 745 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 746 * During regular operations the CRC is stripped, but on some 747 * hardware reception of frames not multiple of 64 is slower, 748 * so using crcstrip=0 helps in benchmarks. 749 * 750 * iflib_rx_miss, iflib_rx_miss_bufs: 751 * count packets that might be missed due to lost interrupts. 752 */ 753 SYSCTL_DECL(_dev_netmap); 754 /* 755 * The xl driver by default strips CRCs and we do not override it. 756 */ 757 758 int iflib_crcstrip = 1; 759 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 760 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 761 762 int iflib_rx_miss, iflib_rx_miss_bufs; 763 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 764 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 765 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 766 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 767 768 /* 769 * Register/unregister. We are already under netmap lock. 770 * Only called on the first register or the last unregister. 771 */ 772 static int 773 iflib_netmap_register(struct netmap_adapter *na, int onoff) 774 { 775 if_t ifp = na->ifp; 776 if_ctx_t ctx = ifp->if_softc; 777 int status; 778 779 CTX_LOCK(ctx); 780 IFDI_INTR_DISABLE(ctx); 781 782 /* Tell the stack that the interface is no longer active */ 783 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 784 785 if (!CTX_IS_VF(ctx)) 786 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 787 788 iflib_stop(ctx); 789 790 /* 791 * Enable (or disable) netmap flags, and intercept (or restore) 792 * ifp->if_transmit. This is done once the device has been stopped 793 * to prevent race conditions. 794 */ 795 if (onoff) { 796 nm_set_native_flags(na); 797 } else { 798 nm_clear_native_flags(na); 799 } 800 801 iflib_init_locked(ctx); 802 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 803 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 804 if (status) 805 nm_clear_native_flags(na); 806 CTX_UNLOCK(ctx); 807 return (status); 808 } 809 810 static int 811 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 812 { 813 struct netmap_adapter *na = kring->na; 814 u_int const lim = kring->nkr_num_slots - 1; 815 u_int head = kring->rhead; 816 struct netmap_ring *ring = kring->ring; 817 bus_dmamap_t *map; 818 struct if_rxd_update iru; 819 if_ctx_t ctx = rxq->ifr_ctx; 820 iflib_fl_t fl = &rxq->ifr_fl[0]; 821 uint32_t refill_pidx, nic_i; 822 #if IFLIB_DEBUG_COUNTERS 823 int rf_count = 0; 824 #endif 825 826 if (nm_i == head && __predict_true(!init)) 827 return 0; 828 iru_init(&iru, rxq, 0 /* flid */); 829 map = fl->ifl_sds.ifsd_map; 830 refill_pidx = netmap_idx_k2n(kring, nm_i); 831 /* 832 * IMPORTANT: we must leave one free slot in the ring, 833 * so move head back by one unit 834 */ 835 head = nm_prev(head, lim); 836 nic_i = UINT_MAX; 837 DBG_COUNTER_INC(fl_refills); 838 while (nm_i != head) { 839 #if IFLIB_DEBUG_COUNTERS 840 if (++rf_count == 9) 841 DBG_COUNTER_INC(fl_refills_large); 842 #endif 843 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 844 struct netmap_slot *slot = &ring->slot[nm_i]; 845 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 846 uint32_t nic_i_dma = refill_pidx; 847 nic_i = netmap_idx_k2n(kring, nm_i); 848 849 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 850 851 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 852 return netmap_ring_reinit(kring); 853 854 if (__predict_false(init)) { 855 netmap_load_map(na, fl->ifl_buf_tag, 856 map[nic_i], addr); 857 } else if (slot->flags & NS_BUF_CHANGED) { 858 /* buffer has changed, reload map */ 859 netmap_reload_map(na, fl->ifl_buf_tag, 860 map[nic_i], addr); 861 } 862 slot->flags &= ~NS_BUF_CHANGED; 863 864 nm_i = nm_next(nm_i, lim); 865 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 866 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 867 continue; 868 869 iru.iru_pidx = refill_pidx; 870 iru.iru_count = tmp_pidx+1; 871 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 872 refill_pidx = nic_i; 873 for (int n = 0; n < iru.iru_count; n++) { 874 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 875 BUS_DMASYNC_PREREAD); 876 /* XXX - change this to not use the netmap func*/ 877 nic_i_dma = nm_next(nic_i_dma, lim); 878 } 879 } 880 } 881 kring->nr_hwcur = head; 882 883 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 884 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 885 if (__predict_true(nic_i != UINT_MAX)) { 886 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 887 DBG_COUNTER_INC(rxd_flush); 888 } 889 return (0); 890 } 891 892 /* 893 * Reconcile kernel and user view of the transmit ring. 894 * 895 * All information is in the kring. 896 * Userspace wants to send packets up to the one before kring->rhead, 897 * kernel knows kring->nr_hwcur is the first unsent packet. 898 * 899 * Here we push packets out (as many as possible), and possibly 900 * reclaim buffers from previously completed transmission. 901 * 902 * The caller (netmap) guarantees that there is only one instance 903 * running at any time. Any interference with other driver 904 * methods should be handled by the individual drivers. 905 */ 906 static int 907 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 908 { 909 struct netmap_adapter *na = kring->na; 910 if_t ifp = na->ifp; 911 struct netmap_ring *ring = kring->ring; 912 u_int nm_i; /* index into the netmap kring */ 913 u_int nic_i; /* index into the NIC ring */ 914 u_int n; 915 u_int const lim = kring->nkr_num_slots - 1; 916 u_int const head = kring->rhead; 917 struct if_pkt_info pi; 918 919 /* 920 * interrupts on every tx packet are expensive so request 921 * them every half ring, or where NS_REPORT is set 922 */ 923 u_int report_frequency = kring->nkr_num_slots >> 1; 924 /* device-specific */ 925 if_ctx_t ctx = ifp->if_softc; 926 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 927 928 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 929 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 930 931 /* 932 * First part: process new packets to send. 933 * nm_i is the current index in the netmap kring, 934 * nic_i is the corresponding index in the NIC ring. 935 * 936 * If we have packets to send (nm_i != head) 937 * iterate over the netmap ring, fetch length and update 938 * the corresponding slot in the NIC ring. Some drivers also 939 * need to update the buffer's physical address in the NIC slot 940 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 941 * 942 * The netmap_reload_map() calls is especially expensive, 943 * even when (as in this case) the tag is 0, so do only 944 * when the buffer has actually changed. 945 * 946 * If possible do not set the report/intr bit on all slots, 947 * but only a few times per ring or when NS_REPORT is set. 948 * 949 * Finally, on 10G and faster drivers, it might be useful 950 * to prefetch the next slot and txr entry. 951 */ 952 953 nm_i = kring->nr_hwcur; 954 if (nm_i != head) { /* we have new packets to send */ 955 pkt_info_zero(&pi); 956 pi.ipi_segs = txq->ift_segs; 957 pi.ipi_qsidx = kring->ring_id; 958 nic_i = netmap_idx_k2n(kring, nm_i); 959 960 __builtin_prefetch(&ring->slot[nm_i]); 961 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 962 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 963 964 for (n = 0; nm_i != head; n++) { 965 struct netmap_slot *slot = &ring->slot[nm_i]; 966 u_int len = slot->len; 967 uint64_t paddr; 968 void *addr = PNMB(na, slot, &paddr); 969 int flags = (slot->flags & NS_REPORT || 970 nic_i == 0 || nic_i == report_frequency) ? 971 IPI_TX_INTR : 0; 972 973 /* device-specific */ 974 pi.ipi_len = len; 975 pi.ipi_segs[0].ds_addr = paddr; 976 pi.ipi_segs[0].ds_len = len; 977 pi.ipi_nsegs = 1; 978 pi.ipi_ndescs = 0; 979 pi.ipi_pidx = nic_i; 980 pi.ipi_flags = flags; 981 982 /* Fill the slot in the NIC ring. */ 983 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 984 DBG_COUNTER_INC(tx_encap); 985 986 /* prefetch for next round */ 987 __builtin_prefetch(&ring->slot[nm_i + 1]); 988 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 989 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 990 991 NM_CHECK_ADDR_LEN(na, addr, len); 992 993 if (slot->flags & NS_BUF_CHANGED) { 994 /* buffer has changed, reload map */ 995 netmap_reload_map(na, txq->ift_buf_tag, 996 txq->ift_sds.ifsd_map[nic_i], addr); 997 } 998 /* make sure changes to the buffer are synced */ 999 bus_dmamap_sync(txq->ift_buf_tag, 1000 txq->ift_sds.ifsd_map[nic_i], 1001 BUS_DMASYNC_PREWRITE); 1002 1003 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1004 nm_i = nm_next(nm_i, lim); 1005 nic_i = nm_next(nic_i, lim); 1006 } 1007 kring->nr_hwcur = nm_i; 1008 1009 /* synchronize the NIC ring */ 1010 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1011 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1012 1013 /* (re)start the tx unit up to slot nic_i (excluded) */ 1014 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1015 } 1016 1017 /* 1018 * Second part: reclaim buffers for completed transmissions. 1019 * 1020 * If there are unclaimed buffers, attempt to reclaim them. 1021 * If none are reclaimed, and TX IRQs are not in use, do an initial 1022 * minimal delay, then trigger the tx handler which will spin in the 1023 * group task queue. 1024 */ 1025 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1026 if (iflib_tx_credits_update(ctx, txq)) { 1027 /* some tx completed, increment avail */ 1028 nic_i = txq->ift_cidx_processed; 1029 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1030 } 1031 } 1032 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1033 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1034 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1035 iflib_timer, txq, txq->ift_timer.c_cpu); 1036 } 1037 return (0); 1038 } 1039 1040 /* 1041 * Reconcile kernel and user view of the receive ring. 1042 * Same as for the txsync, this routine must be efficient. 1043 * The caller guarantees a single invocations, but races against 1044 * the rest of the driver should be handled here. 1045 * 1046 * On call, kring->rhead is the first packet that userspace wants 1047 * to keep, and kring->rcur is the wakeup point. 1048 * The kernel has previously reported packets up to kring->rtail. 1049 * 1050 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1051 * of whether or not we received an interrupt. 1052 */ 1053 static int 1054 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1055 { 1056 struct netmap_adapter *na = kring->na; 1057 struct netmap_ring *ring = kring->ring; 1058 if_t ifp = na->ifp; 1059 iflib_fl_t fl; 1060 uint32_t nm_i; /* index into the netmap ring */ 1061 uint32_t nic_i; /* index into the NIC ring */ 1062 u_int i, n; 1063 u_int const lim = kring->nkr_num_slots - 1; 1064 u_int const head = kring->rhead; 1065 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1066 struct if_rxd_info ri; 1067 1068 if_ctx_t ctx = ifp->if_softc; 1069 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1070 if (head > lim) 1071 return netmap_ring_reinit(kring); 1072 1073 /* 1074 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1075 */ 1076 1077 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1078 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1079 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1080 } 1081 1082 /* 1083 * First part: import newly received packets. 1084 * 1085 * nm_i is the index of the next free slot in the netmap ring, 1086 * nic_i is the index of the next received packet in the NIC ring, 1087 * and they may differ in case if_init() has been called while 1088 * in netmap mode. For the receive ring we have 1089 * 1090 * nic_i = rxr->next_check; 1091 * nm_i = kring->nr_hwtail (previous) 1092 * and 1093 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1094 * 1095 * rxr->next_check is set to 0 on a ring reinit 1096 */ 1097 if (netmap_no_pendintr || force_update) { 1098 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1099 int crclen = iflib_crcstrip ? 0 : 4; 1100 int error, avail; 1101 1102 for (i = 0; i < rxq->ifr_nfl; i++) { 1103 fl = &rxq->ifr_fl[i]; 1104 nic_i = fl->ifl_cidx; 1105 nm_i = netmap_idx_n2k(kring, nic_i); 1106 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1107 rxq->ifr_id, nic_i, USHRT_MAX); 1108 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1109 rxd_info_zero(&ri); 1110 ri.iri_frags = rxq->ifr_frags; 1111 ri.iri_qsidx = kring->ring_id; 1112 ri.iri_ifp = ctx->ifc_ifp; 1113 ri.iri_cidx = nic_i; 1114 1115 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1116 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1117 ring->slot[nm_i].flags = 0; 1118 bus_dmamap_sync(fl->ifl_buf_tag, 1119 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1120 nm_i = nm_next(nm_i, lim); 1121 nic_i = nm_next(nic_i, lim); 1122 } 1123 if (n) { /* update the state variables */ 1124 if (netmap_no_pendintr && !force_update) { 1125 /* diagnostics */ 1126 iflib_rx_miss ++; 1127 iflib_rx_miss_bufs += n; 1128 } 1129 fl->ifl_cidx = nic_i; 1130 kring->nr_hwtail = nm_i; 1131 } 1132 kring->nr_kflags &= ~NKR_PENDINTR; 1133 } 1134 } 1135 /* 1136 * Second part: skip past packets that userspace has released. 1137 * (kring->nr_hwcur to head excluded), 1138 * and make the buffers available for reception. 1139 * As usual nm_i is the index in the netmap ring, 1140 * nic_i is the index in the NIC ring, and 1141 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1142 */ 1143 /* XXX not sure how this will work with multiple free lists */ 1144 nm_i = kring->nr_hwcur; 1145 1146 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1147 } 1148 1149 static void 1150 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1151 { 1152 if_ctx_t ctx = na->ifp->if_softc; 1153 1154 CTX_LOCK(ctx); 1155 if (onoff) { 1156 IFDI_INTR_ENABLE(ctx); 1157 } else { 1158 IFDI_INTR_DISABLE(ctx); 1159 } 1160 CTX_UNLOCK(ctx); 1161 } 1162 1163 1164 static int 1165 iflib_netmap_attach(if_ctx_t ctx) 1166 { 1167 struct netmap_adapter na; 1168 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1169 1170 bzero(&na, sizeof(na)); 1171 1172 na.ifp = ctx->ifc_ifp; 1173 na.na_flags = NAF_BDG_MAYSLEEP; 1174 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1175 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1176 1177 na.num_tx_desc = scctx->isc_ntxd[0]; 1178 na.num_rx_desc = scctx->isc_nrxd[0]; 1179 na.nm_txsync = iflib_netmap_txsync; 1180 na.nm_rxsync = iflib_netmap_rxsync; 1181 na.nm_register = iflib_netmap_register; 1182 na.nm_intr = iflib_netmap_intr; 1183 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1184 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1185 return (netmap_attach(&na)); 1186 } 1187 1188 static int 1189 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1190 { 1191 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1192 struct netmap_slot *slot; 1193 1194 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1195 if (slot == NULL) 1196 return (0); 1197 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1198 1199 /* 1200 * In netmap mode, set the map for the packet buffer. 1201 * NOTE: Some drivers (not this one) also need to set 1202 * the physical buffer address in the NIC ring. 1203 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1204 * netmap slot index, si 1205 */ 1206 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1207 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1208 NMB(na, slot + si)); 1209 } 1210 return (1); 1211 } 1212 1213 static int 1214 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1215 { 1216 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1217 struct netmap_kring *kring; 1218 struct netmap_slot *slot; 1219 uint32_t nm_i; 1220 1221 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1222 if (slot == NULL) 1223 return (0); 1224 kring = na->rx_rings[rxq->ifr_id]; 1225 nm_i = netmap_idx_n2k(kring, 0); 1226 netmap_fl_refill(rxq, kring, nm_i, true); 1227 return (1); 1228 } 1229 1230 static void 1231 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1232 { 1233 struct netmap_kring *kring; 1234 uint16_t txqid; 1235 1236 txqid = txq->ift_id; 1237 kring = netmap_kring_on(NA(ctx->ifc_ifp), txqid, NR_TX); 1238 if (kring == NULL) 1239 return; 1240 1241 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1242 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1243 BUS_DMASYNC_POSTREAD); 1244 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1245 netmap_tx_irq(ctx->ifc_ifp, txqid); 1246 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1247 if (hz < 2000) 1248 *reset_on = 1; 1249 else 1250 *reset_on = hz / 1000; 1251 } 1252 } 1253 } 1254 1255 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1256 1257 #else 1258 #define iflib_netmap_txq_init(ctx, txq) (0) 1259 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1260 #define iflib_netmap_detach(ifp) 1261 1262 #define iflib_netmap_attach(ctx) (0) 1263 #define netmap_rx_irq(ifp, qid, budget) (0) 1264 #define netmap_tx_irq(ifp, qid) do {} while (0) 1265 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1266 #endif 1267 1268 #if defined(__i386__) || defined(__amd64__) 1269 static __inline void 1270 prefetch(void *x) 1271 { 1272 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1273 } 1274 static __inline void 1275 prefetch2cachelines(void *x) 1276 { 1277 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1278 #if (CACHE_LINE_SIZE < 128) 1279 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1280 #endif 1281 } 1282 #else 1283 #define prefetch(x) 1284 #define prefetch2cachelines(x) 1285 #endif 1286 1287 static void 1288 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1289 { 1290 iflib_fl_t fl; 1291 1292 fl = &rxq->ifr_fl[flid]; 1293 iru->iru_paddrs = fl->ifl_bus_addrs; 1294 iru->iru_idxs = fl->ifl_rxd_idxs; 1295 iru->iru_qsidx = rxq->ifr_id; 1296 iru->iru_buf_size = fl->ifl_buf_size; 1297 iru->iru_flidx = fl->ifl_id; 1298 } 1299 1300 static void 1301 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1302 { 1303 if (err) 1304 return; 1305 *(bus_addr_t *) arg = segs[0].ds_addr; 1306 } 1307 1308 int 1309 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1310 { 1311 int err; 1312 device_t dev = ctx->ifc_dev; 1313 1314 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1315 align, 0, /* alignment, bounds */ 1316 BUS_SPACE_MAXADDR, /* lowaddr */ 1317 BUS_SPACE_MAXADDR, /* highaddr */ 1318 NULL, NULL, /* filter, filterarg */ 1319 size, /* maxsize */ 1320 1, /* nsegments */ 1321 size, /* maxsegsize */ 1322 BUS_DMA_ALLOCNOW, /* flags */ 1323 NULL, /* lockfunc */ 1324 NULL, /* lockarg */ 1325 &dma->idi_tag); 1326 if (err) { 1327 device_printf(dev, 1328 "%s: bus_dma_tag_create failed: %d\n", 1329 __func__, err); 1330 goto fail_0; 1331 } 1332 1333 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1334 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1335 if (err) { 1336 device_printf(dev, 1337 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1338 __func__, (uintmax_t)size, err); 1339 goto fail_1; 1340 } 1341 1342 dma->idi_paddr = IF_BAD_DMA; 1343 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1344 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1345 if (err || dma->idi_paddr == IF_BAD_DMA) { 1346 device_printf(dev, 1347 "%s: bus_dmamap_load failed: %d\n", 1348 __func__, err); 1349 goto fail_2; 1350 } 1351 1352 dma->idi_size = size; 1353 return (0); 1354 1355 fail_2: 1356 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1357 fail_1: 1358 bus_dma_tag_destroy(dma->idi_tag); 1359 fail_0: 1360 dma->idi_tag = NULL; 1361 1362 return (err); 1363 } 1364 1365 int 1366 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1367 { 1368 if_shared_ctx_t sctx = ctx->ifc_sctx; 1369 1370 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1371 1372 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1373 } 1374 1375 int 1376 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1377 { 1378 int i, err; 1379 iflib_dma_info_t *dmaiter; 1380 1381 dmaiter = dmalist; 1382 for (i = 0; i < count; i++, dmaiter++) { 1383 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1384 break; 1385 } 1386 if (err) 1387 iflib_dma_free_multi(dmalist, i); 1388 return (err); 1389 } 1390 1391 void 1392 iflib_dma_free(iflib_dma_info_t dma) 1393 { 1394 if (dma->idi_tag == NULL) 1395 return; 1396 if (dma->idi_paddr != IF_BAD_DMA) { 1397 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1398 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1399 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1400 dma->idi_paddr = IF_BAD_DMA; 1401 } 1402 if (dma->idi_vaddr != NULL) { 1403 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1404 dma->idi_vaddr = NULL; 1405 } 1406 bus_dma_tag_destroy(dma->idi_tag); 1407 dma->idi_tag = NULL; 1408 } 1409 1410 void 1411 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1412 { 1413 int i; 1414 iflib_dma_info_t *dmaiter = dmalist; 1415 1416 for (i = 0; i < count; i++, dmaiter++) 1417 iflib_dma_free(*dmaiter); 1418 } 1419 1420 static int 1421 iflib_fast_intr(void *arg) 1422 { 1423 iflib_filter_info_t info = arg; 1424 struct grouptask *gtask = info->ifi_task; 1425 int result; 1426 1427 DBG_COUNTER_INC(fast_intrs); 1428 if (info->ifi_filter != NULL) { 1429 result = info->ifi_filter(info->ifi_filter_arg); 1430 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1431 return (result); 1432 } 1433 1434 GROUPTASK_ENQUEUE(gtask); 1435 return (FILTER_HANDLED); 1436 } 1437 1438 static int 1439 iflib_fast_intr_rxtx(void *arg) 1440 { 1441 iflib_filter_info_t info = arg; 1442 struct grouptask *gtask = info->ifi_task; 1443 if_ctx_t ctx; 1444 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1445 iflib_txq_t txq; 1446 void *sc; 1447 int i, cidx, result; 1448 qidx_t txqid; 1449 bool intr_enable, intr_legacy; 1450 1451 DBG_COUNTER_INC(fast_intrs); 1452 if (info->ifi_filter != NULL) { 1453 result = info->ifi_filter(info->ifi_filter_arg); 1454 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1455 return (result); 1456 } 1457 1458 ctx = rxq->ifr_ctx; 1459 sc = ctx->ifc_softc; 1460 intr_enable = false; 1461 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1462 MPASS(rxq->ifr_ntxqirq); 1463 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1464 txqid = rxq->ifr_txqid[i]; 1465 txq = &ctx->ifc_txqs[txqid]; 1466 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1467 BUS_DMASYNC_POSTREAD); 1468 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1469 if (intr_legacy) 1470 intr_enable = true; 1471 else 1472 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1473 continue; 1474 } 1475 GROUPTASK_ENQUEUE(&txq->ift_task); 1476 } 1477 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1478 cidx = rxq->ifr_cq_cidx; 1479 else 1480 cidx = rxq->ifr_fl[0].ifl_cidx; 1481 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1482 GROUPTASK_ENQUEUE(gtask); 1483 else { 1484 if (intr_legacy) 1485 intr_enable = true; 1486 else 1487 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1488 DBG_COUNTER_INC(rx_intr_enables); 1489 } 1490 if (intr_enable) 1491 IFDI_INTR_ENABLE(ctx); 1492 return (FILTER_HANDLED); 1493 } 1494 1495 1496 static int 1497 iflib_fast_intr_ctx(void *arg) 1498 { 1499 iflib_filter_info_t info = arg; 1500 struct grouptask *gtask = info->ifi_task; 1501 int result; 1502 1503 DBG_COUNTER_INC(fast_intrs); 1504 if (info->ifi_filter != NULL) { 1505 result = info->ifi_filter(info->ifi_filter_arg); 1506 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1507 return (result); 1508 } 1509 1510 GROUPTASK_ENQUEUE(gtask); 1511 return (FILTER_HANDLED); 1512 } 1513 1514 static int 1515 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1516 driver_filter_t filter, driver_intr_t handler, void *arg, 1517 const char *name) 1518 { 1519 struct resource *res; 1520 void *tag = NULL; 1521 device_t dev = ctx->ifc_dev; 1522 int flags, i, rc; 1523 1524 flags = RF_ACTIVE; 1525 if (ctx->ifc_flags & IFC_LEGACY) 1526 flags |= RF_SHAREABLE; 1527 MPASS(rid < 512); 1528 i = rid; 1529 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1530 if (res == NULL) { 1531 device_printf(dev, 1532 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1533 return (ENOMEM); 1534 } 1535 irq->ii_res = res; 1536 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1537 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1538 filter, handler, arg, &tag); 1539 if (rc != 0) { 1540 device_printf(dev, 1541 "failed to setup interrupt for rid %d, name %s: %d\n", 1542 rid, name ? name : "unknown", rc); 1543 return (rc); 1544 } else if (name) 1545 bus_describe_intr(dev, res, tag, "%s", name); 1546 1547 irq->ii_tag = tag; 1548 return (0); 1549 } 1550 1551 /********************************************************************* 1552 * 1553 * Allocate DMA resources for TX buffers as well as memory for the TX 1554 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1555 * iflib_sw_tx_desc_array structure, storing all the information that 1556 * is needed to transmit a packet on the wire. This is called only 1557 * once at attach, setup is done every reset. 1558 * 1559 **********************************************************************/ 1560 static int 1561 iflib_txsd_alloc(iflib_txq_t txq) 1562 { 1563 if_ctx_t ctx = txq->ift_ctx; 1564 if_shared_ctx_t sctx = ctx->ifc_sctx; 1565 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1566 device_t dev = ctx->ifc_dev; 1567 bus_size_t tsomaxsize; 1568 int err, nsegments, ntsosegments; 1569 bool tso; 1570 1571 nsegments = scctx->isc_tx_nsegments; 1572 ntsosegments = scctx->isc_tx_tso_segments_max; 1573 tsomaxsize = scctx->isc_tx_tso_size_max; 1574 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1575 tsomaxsize += sizeof(struct ether_vlan_header); 1576 MPASS(scctx->isc_ntxd[0] > 0); 1577 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1578 MPASS(nsegments > 0); 1579 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1580 MPASS(ntsosegments > 0); 1581 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1582 } 1583 1584 /* 1585 * Set up DMA tags for TX buffers. 1586 */ 1587 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1588 1, 0, /* alignment, bounds */ 1589 BUS_SPACE_MAXADDR, /* lowaddr */ 1590 BUS_SPACE_MAXADDR, /* highaddr */ 1591 NULL, NULL, /* filter, filterarg */ 1592 sctx->isc_tx_maxsize, /* maxsize */ 1593 nsegments, /* nsegments */ 1594 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1595 0, /* flags */ 1596 NULL, /* lockfunc */ 1597 NULL, /* lockfuncarg */ 1598 &txq->ift_buf_tag))) { 1599 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1600 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1601 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1602 goto fail; 1603 } 1604 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1605 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1606 1, 0, /* alignment, bounds */ 1607 BUS_SPACE_MAXADDR, /* lowaddr */ 1608 BUS_SPACE_MAXADDR, /* highaddr */ 1609 NULL, NULL, /* filter, filterarg */ 1610 tsomaxsize, /* maxsize */ 1611 ntsosegments, /* nsegments */ 1612 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1613 0, /* flags */ 1614 NULL, /* lockfunc */ 1615 NULL, /* lockfuncarg */ 1616 &txq->ift_tso_buf_tag))) { 1617 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1618 err); 1619 goto fail; 1620 } 1621 1622 /* Allocate memory for the TX mbuf map. */ 1623 if (!(txq->ift_sds.ifsd_m = 1624 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1625 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1626 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1627 err = ENOMEM; 1628 goto fail; 1629 } 1630 1631 /* 1632 * Create the DMA maps for TX buffers. 1633 */ 1634 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1635 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1636 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1637 device_printf(dev, 1638 "Unable to allocate TX buffer DMA map memory\n"); 1639 err = ENOMEM; 1640 goto fail; 1641 } 1642 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1643 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1644 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1645 device_printf(dev, 1646 "Unable to allocate TSO TX buffer map memory\n"); 1647 err = ENOMEM; 1648 goto fail; 1649 } 1650 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1651 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1652 &txq->ift_sds.ifsd_map[i]); 1653 if (err != 0) { 1654 device_printf(dev, "Unable to create TX DMA map\n"); 1655 goto fail; 1656 } 1657 if (!tso) 1658 continue; 1659 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1660 &txq->ift_sds.ifsd_tso_map[i]); 1661 if (err != 0) { 1662 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1663 goto fail; 1664 } 1665 } 1666 return (0); 1667 fail: 1668 /* We free all, it handles case where we are in the middle */ 1669 iflib_tx_structures_free(ctx); 1670 return (err); 1671 } 1672 1673 static void 1674 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1675 { 1676 bus_dmamap_t map; 1677 1678 if (txq->ift_sds.ifsd_map != NULL) { 1679 map = txq->ift_sds.ifsd_map[i]; 1680 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1681 bus_dmamap_unload(txq->ift_buf_tag, map); 1682 bus_dmamap_destroy(txq->ift_buf_tag, map); 1683 txq->ift_sds.ifsd_map[i] = NULL; 1684 } 1685 1686 if (txq->ift_sds.ifsd_tso_map != NULL) { 1687 map = txq->ift_sds.ifsd_tso_map[i]; 1688 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1689 BUS_DMASYNC_POSTWRITE); 1690 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1691 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1692 txq->ift_sds.ifsd_tso_map[i] = NULL; 1693 } 1694 } 1695 1696 static void 1697 iflib_txq_destroy(iflib_txq_t txq) 1698 { 1699 if_ctx_t ctx = txq->ift_ctx; 1700 1701 for (int i = 0; i < txq->ift_size; i++) 1702 iflib_txsd_destroy(ctx, txq, i); 1703 1704 if (txq->ift_br != NULL) { 1705 ifmp_ring_free(txq->ift_br); 1706 txq->ift_br = NULL; 1707 } 1708 1709 mtx_destroy(&txq->ift_mtx); 1710 1711 if (txq->ift_sds.ifsd_map != NULL) { 1712 free(txq->ift_sds.ifsd_map, M_IFLIB); 1713 txq->ift_sds.ifsd_map = NULL; 1714 } 1715 if (txq->ift_sds.ifsd_tso_map != NULL) { 1716 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1717 txq->ift_sds.ifsd_tso_map = NULL; 1718 } 1719 if (txq->ift_sds.ifsd_m != NULL) { 1720 free(txq->ift_sds.ifsd_m, M_IFLIB); 1721 txq->ift_sds.ifsd_m = NULL; 1722 } 1723 if (txq->ift_buf_tag != NULL) { 1724 bus_dma_tag_destroy(txq->ift_buf_tag); 1725 txq->ift_buf_tag = NULL; 1726 } 1727 if (txq->ift_tso_buf_tag != NULL) { 1728 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1729 txq->ift_tso_buf_tag = NULL; 1730 } 1731 if (txq->ift_ifdi != NULL) { 1732 free(txq->ift_ifdi, M_IFLIB); 1733 } 1734 } 1735 1736 static void 1737 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1738 { 1739 struct mbuf **mp; 1740 1741 mp = &txq->ift_sds.ifsd_m[i]; 1742 if (*mp == NULL) 1743 return; 1744 1745 if (txq->ift_sds.ifsd_map != NULL) { 1746 bus_dmamap_sync(txq->ift_buf_tag, 1747 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1748 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1749 } 1750 if (txq->ift_sds.ifsd_tso_map != NULL) { 1751 bus_dmamap_sync(txq->ift_tso_buf_tag, 1752 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1753 bus_dmamap_unload(txq->ift_tso_buf_tag, 1754 txq->ift_sds.ifsd_tso_map[i]); 1755 } 1756 m_free(*mp); 1757 DBG_COUNTER_INC(tx_frees); 1758 *mp = NULL; 1759 } 1760 1761 static int 1762 iflib_txq_setup(iflib_txq_t txq) 1763 { 1764 if_ctx_t ctx = txq->ift_ctx; 1765 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1766 if_shared_ctx_t sctx = ctx->ifc_sctx; 1767 iflib_dma_info_t di; 1768 int i; 1769 1770 /* Set number of descriptors available */ 1771 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1772 /* XXX make configurable */ 1773 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1774 1775 /* Reset indices */ 1776 txq->ift_cidx_processed = 0; 1777 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1778 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1779 1780 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1781 bzero((void *)di->idi_vaddr, di->idi_size); 1782 1783 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1784 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1785 bus_dmamap_sync(di->idi_tag, di->idi_map, 1786 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1787 return (0); 1788 } 1789 1790 /********************************************************************* 1791 * 1792 * Allocate DMA resources for RX buffers as well as memory for the RX 1793 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1794 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1795 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1796 * Since we use use one entry in iflib_sw_rx_desc_array per received 1797 * packet, the maximum number of entries we'll need is equal to the 1798 * number of hardware receive descriptors that we've allocated. 1799 * 1800 **********************************************************************/ 1801 static int 1802 iflib_rxsd_alloc(iflib_rxq_t rxq) 1803 { 1804 if_ctx_t ctx = rxq->ifr_ctx; 1805 if_shared_ctx_t sctx = ctx->ifc_sctx; 1806 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1807 device_t dev = ctx->ifc_dev; 1808 iflib_fl_t fl; 1809 int err; 1810 1811 MPASS(scctx->isc_nrxd[0] > 0); 1812 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1813 1814 fl = rxq->ifr_fl; 1815 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1816 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1817 /* Set up DMA tag for RX buffers. */ 1818 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1819 1, 0, /* alignment, bounds */ 1820 BUS_SPACE_MAXADDR, /* lowaddr */ 1821 BUS_SPACE_MAXADDR, /* highaddr */ 1822 NULL, NULL, /* filter, filterarg */ 1823 sctx->isc_rx_maxsize, /* maxsize */ 1824 sctx->isc_rx_nsegments, /* nsegments */ 1825 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1826 0, /* flags */ 1827 NULL, /* lockfunc */ 1828 NULL, /* lockarg */ 1829 &fl->ifl_buf_tag); 1830 if (err) { 1831 device_printf(dev, 1832 "Unable to allocate RX DMA tag: %d\n", err); 1833 goto fail; 1834 } 1835 1836 /* Allocate memory for the RX mbuf map. */ 1837 if (!(fl->ifl_sds.ifsd_m = 1838 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1839 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1840 device_printf(dev, 1841 "Unable to allocate RX mbuf map memory\n"); 1842 err = ENOMEM; 1843 goto fail; 1844 } 1845 1846 /* Allocate memory for the direct RX cluster pointer map. */ 1847 if (!(fl->ifl_sds.ifsd_cl = 1848 (caddr_t *) malloc(sizeof(caddr_t) * 1849 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1850 device_printf(dev, 1851 "Unable to allocate RX cluster map memory\n"); 1852 err = ENOMEM; 1853 goto fail; 1854 } 1855 1856 /* Allocate memory for the RX cluster bus address map. */ 1857 if (!(fl->ifl_sds.ifsd_ba = 1858 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1859 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1860 device_printf(dev, 1861 "Unable to allocate RX bus address map memory\n"); 1862 err = ENOMEM; 1863 goto fail; 1864 } 1865 1866 /* 1867 * Create the DMA maps for RX buffers. 1868 */ 1869 if (!(fl->ifl_sds.ifsd_map = 1870 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1871 device_printf(dev, 1872 "Unable to allocate RX buffer DMA map memory\n"); 1873 err = ENOMEM; 1874 goto fail; 1875 } 1876 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1877 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1878 &fl->ifl_sds.ifsd_map[i]); 1879 if (err != 0) { 1880 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1881 goto fail; 1882 } 1883 } 1884 } 1885 return (0); 1886 1887 fail: 1888 iflib_rx_structures_free(ctx); 1889 return (err); 1890 } 1891 1892 1893 /* 1894 * Internal service routines 1895 */ 1896 1897 struct rxq_refill_cb_arg { 1898 int error; 1899 bus_dma_segment_t seg; 1900 int nseg; 1901 }; 1902 1903 static void 1904 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1905 { 1906 struct rxq_refill_cb_arg *cb_arg = arg; 1907 1908 cb_arg->error = error; 1909 cb_arg->seg = segs[0]; 1910 cb_arg->nseg = nseg; 1911 } 1912 1913 /** 1914 * iflib_fl_refill - refill an rxq free-buffer list 1915 * @ctx: the iflib context 1916 * @fl: the free list to refill 1917 * @count: the number of new buffers to allocate 1918 * 1919 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1920 * The caller must assure that @count does not exceed the queue's capacity. 1921 */ 1922 static uint8_t 1923 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1924 { 1925 struct if_rxd_update iru; 1926 struct rxq_refill_cb_arg cb_arg; 1927 struct mbuf *m; 1928 caddr_t cl, *sd_cl; 1929 struct mbuf **sd_m; 1930 bus_dmamap_t *sd_map; 1931 bus_addr_t bus_addr, *sd_ba; 1932 int err, frag_idx, i, idx, n, pidx; 1933 qidx_t credits; 1934 1935 sd_m = fl->ifl_sds.ifsd_m; 1936 sd_map = fl->ifl_sds.ifsd_map; 1937 sd_cl = fl->ifl_sds.ifsd_cl; 1938 sd_ba = fl->ifl_sds.ifsd_ba; 1939 pidx = fl->ifl_pidx; 1940 idx = pidx; 1941 frag_idx = fl->ifl_fragidx; 1942 credits = fl->ifl_credits; 1943 1944 i = 0; 1945 n = count; 1946 MPASS(n > 0); 1947 MPASS(credits + n <= fl->ifl_size); 1948 1949 if (pidx < fl->ifl_cidx) 1950 MPASS(pidx + n <= fl->ifl_cidx); 1951 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1952 MPASS(fl->ifl_gen == 0); 1953 if (pidx > fl->ifl_cidx) 1954 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1955 1956 DBG_COUNTER_INC(fl_refills); 1957 if (n > 8) 1958 DBG_COUNTER_INC(fl_refills_large); 1959 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1960 while (n-- > 0) { 1961 /* 1962 * We allocate an uninitialized mbuf + cluster, mbuf is 1963 * initialized after rx. 1964 * 1965 * If the cluster is still set then we know a minimum sized 1966 * packet was received 1967 */ 1968 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1969 &frag_idx); 1970 if (frag_idx < 0) 1971 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1972 MPASS(frag_idx >= 0); 1973 if ((cl = sd_cl[frag_idx]) == NULL) { 1974 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 1975 if (__predict_false(cl == NULL)) 1976 break; 1977 1978 cb_arg.error = 0; 1979 MPASS(sd_map != NULL); 1980 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 1981 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 1982 BUS_DMA_NOWAIT); 1983 if (__predict_false(err != 0 || cb_arg.error)) { 1984 uma_zfree(fl->ifl_zone, cl); 1985 break; 1986 } 1987 1988 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 1989 sd_cl[frag_idx] = cl; 1990 #if MEMORY_LOGGING 1991 fl->ifl_cl_enqueued++; 1992 #endif 1993 } else { 1994 bus_addr = sd_ba[frag_idx]; 1995 } 1996 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 1997 BUS_DMASYNC_PREREAD); 1998 1999 if (sd_m[frag_idx] == NULL) { 2000 m = m_gethdr(M_NOWAIT, MT_NOINIT); 2001 if (__predict_false(m == NULL)) 2002 break; 2003 sd_m[frag_idx] = m; 2004 } 2005 bit_set(fl->ifl_rx_bitmap, frag_idx); 2006 #if MEMORY_LOGGING 2007 fl->ifl_m_enqueued++; 2008 #endif 2009 2010 DBG_COUNTER_INC(rx_allocs); 2011 fl->ifl_rxd_idxs[i] = frag_idx; 2012 fl->ifl_bus_addrs[i] = bus_addr; 2013 credits++; 2014 i++; 2015 MPASS(credits <= fl->ifl_size); 2016 if (++idx == fl->ifl_size) { 2017 #ifdef INVARIANTS 2018 fl->ifl_gen = 1; 2019 #endif 2020 idx = 0; 2021 } 2022 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2023 iru.iru_pidx = pidx; 2024 iru.iru_count = i; 2025 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2026 fl->ifl_pidx = idx; 2027 fl->ifl_credits = credits; 2028 pidx = idx; 2029 i = 0; 2030 } 2031 } 2032 2033 if (n < count - 1) { 2034 if (i != 0) { 2035 iru.iru_pidx = pidx; 2036 iru.iru_count = i; 2037 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2038 fl->ifl_pidx = idx; 2039 fl->ifl_credits = credits; 2040 } 2041 DBG_COUNTER_INC(rxd_flush); 2042 if (fl->ifl_pidx == 0) 2043 pidx = fl->ifl_size - 1; 2044 else 2045 pidx = fl->ifl_pidx - 1; 2046 2047 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2048 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2049 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2050 fl->ifl_id, pidx); 2051 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2052 fl->ifl_fragidx = frag_idx + 1; 2053 if (fl->ifl_fragidx == fl->ifl_size) 2054 fl->ifl_fragidx = 0; 2055 } else { 2056 fl->ifl_fragidx = frag_idx; 2057 } 2058 } 2059 2060 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2061 } 2062 2063 static inline uint8_t 2064 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2065 { 2066 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2067 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2068 #ifdef INVARIANTS 2069 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2070 #endif 2071 2072 MPASS(fl->ifl_credits <= fl->ifl_size); 2073 MPASS(reclaimable == delta); 2074 2075 if (reclaimable > 0) 2076 return (iflib_fl_refill(ctx, fl, reclaimable)); 2077 return (0); 2078 } 2079 2080 uint8_t 2081 iflib_in_detach(if_ctx_t ctx) 2082 { 2083 bool in_detach; 2084 2085 STATE_LOCK(ctx); 2086 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2087 STATE_UNLOCK(ctx); 2088 return (in_detach); 2089 } 2090 2091 static void 2092 iflib_fl_bufs_free(iflib_fl_t fl) 2093 { 2094 iflib_dma_info_t idi = fl->ifl_ifdi; 2095 bus_dmamap_t sd_map; 2096 uint32_t i; 2097 2098 for (i = 0; i < fl->ifl_size; i++) { 2099 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2100 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2101 2102 if (*sd_cl != NULL) { 2103 sd_map = fl->ifl_sds.ifsd_map[i]; 2104 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2105 BUS_DMASYNC_POSTREAD); 2106 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2107 uma_zfree(fl->ifl_zone, *sd_cl); 2108 *sd_cl = NULL; 2109 if (*sd_m != NULL) { 2110 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2111 uma_zfree(zone_mbuf, *sd_m); 2112 *sd_m = NULL; 2113 } 2114 } else { 2115 MPASS(*sd_m == NULL); 2116 } 2117 #if MEMORY_LOGGING 2118 fl->ifl_m_dequeued++; 2119 fl->ifl_cl_dequeued++; 2120 #endif 2121 } 2122 #ifdef INVARIANTS 2123 for (i = 0; i < fl->ifl_size; i++) { 2124 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2125 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2126 } 2127 #endif 2128 /* 2129 * Reset free list values 2130 */ 2131 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2132 bzero(idi->idi_vaddr, idi->idi_size); 2133 } 2134 2135 /********************************************************************* 2136 * 2137 * Initialize a free list and its buffers. 2138 * 2139 **********************************************************************/ 2140 static int 2141 iflib_fl_setup(iflib_fl_t fl) 2142 { 2143 iflib_rxq_t rxq = fl->ifl_rxq; 2144 if_ctx_t ctx = rxq->ifr_ctx; 2145 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2146 int qidx; 2147 2148 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2149 /* 2150 ** Free current RX buffer structs and their mbufs 2151 */ 2152 iflib_fl_bufs_free(fl); 2153 /* Now replenish the mbufs */ 2154 MPASS(fl->ifl_credits == 0); 2155 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2156 if (scctx->isc_rxd_buf_size[qidx] != 0) 2157 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2158 else 2159 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2160 /* 2161 * ifl_buf_size may be a driver-supplied value, so pull it up 2162 * to the selected mbuf size. 2163 */ 2164 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2165 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2166 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2167 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2168 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2169 2170 2171 /* avoid pre-allocating zillions of clusters to an idle card 2172 * potentially speeding up attach 2173 */ 2174 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2175 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2176 if (min(128, fl->ifl_size) != fl->ifl_credits) 2177 return (ENOBUFS); 2178 /* 2179 * handle failure 2180 */ 2181 MPASS(rxq != NULL); 2182 MPASS(fl->ifl_ifdi != NULL); 2183 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2184 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2185 return (0); 2186 } 2187 2188 /********************************************************************* 2189 * 2190 * Free receive ring data structures 2191 * 2192 **********************************************************************/ 2193 static void 2194 iflib_rx_sds_free(iflib_rxq_t rxq) 2195 { 2196 iflib_fl_t fl; 2197 int i, j; 2198 2199 if (rxq->ifr_fl != NULL) { 2200 for (i = 0; i < rxq->ifr_nfl; i++) { 2201 fl = &rxq->ifr_fl[i]; 2202 if (fl->ifl_buf_tag != NULL) { 2203 if (fl->ifl_sds.ifsd_map != NULL) { 2204 for (j = 0; j < fl->ifl_size; j++) { 2205 bus_dmamap_sync( 2206 fl->ifl_buf_tag, 2207 fl->ifl_sds.ifsd_map[j], 2208 BUS_DMASYNC_POSTREAD); 2209 bus_dmamap_unload( 2210 fl->ifl_buf_tag, 2211 fl->ifl_sds.ifsd_map[j]); 2212 bus_dmamap_destroy( 2213 fl->ifl_buf_tag, 2214 fl->ifl_sds.ifsd_map[j]); 2215 } 2216 } 2217 bus_dma_tag_destroy(fl->ifl_buf_tag); 2218 fl->ifl_buf_tag = NULL; 2219 } 2220 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2221 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2222 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2223 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2224 fl->ifl_sds.ifsd_m = NULL; 2225 fl->ifl_sds.ifsd_cl = NULL; 2226 fl->ifl_sds.ifsd_ba = NULL; 2227 fl->ifl_sds.ifsd_map = NULL; 2228 } 2229 free(rxq->ifr_fl, M_IFLIB); 2230 rxq->ifr_fl = NULL; 2231 free(rxq->ifr_ifdi, M_IFLIB); 2232 rxq->ifr_ifdi = NULL; 2233 rxq->ifr_cq_cidx = 0; 2234 } 2235 } 2236 2237 /* 2238 * Timer routine 2239 */ 2240 static void 2241 iflib_timer(void *arg) 2242 { 2243 iflib_txq_t txq = arg; 2244 if_ctx_t ctx = txq->ift_ctx; 2245 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2246 uint64_t this_tick = ticks; 2247 uint32_t reset_on = hz / 2; 2248 2249 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2250 return; 2251 2252 /* 2253 ** Check on the state of the TX queue(s), this 2254 ** can be done without the lock because its RO 2255 ** and the HUNG state will be static if set. 2256 */ 2257 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2258 txq->ift_last_timer_tick = this_tick; 2259 IFDI_TIMER(ctx, txq->ift_id); 2260 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2261 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2262 (sctx->isc_pause_frames == 0))) 2263 goto hung; 2264 2265 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2266 ifmp_ring_is_stalled(txq->ift_br)) { 2267 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down")); 2268 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2269 } 2270 txq->ift_cleaned_prev = txq->ift_cleaned; 2271 } 2272 #ifdef DEV_NETMAP 2273 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2274 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2275 #endif 2276 /* handle any laggards */ 2277 if (txq->ift_db_pending) 2278 GROUPTASK_ENQUEUE(&txq->ift_task); 2279 2280 sctx->isc_pause_frames = 0; 2281 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2282 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2283 return; 2284 2285 hung: 2286 device_printf(ctx->ifc_dev, 2287 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2288 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2289 STATE_LOCK(ctx); 2290 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2291 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2292 iflib_admin_intr_deferred(ctx); 2293 STATE_UNLOCK(ctx); 2294 } 2295 2296 static uint16_t 2297 iflib_get_mbuf_size_for(unsigned int size) 2298 { 2299 2300 if (size <= MCLBYTES) 2301 return (MCLBYTES); 2302 else 2303 return (MJUMPAGESIZE); 2304 } 2305 2306 static void 2307 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2308 { 2309 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2310 2311 /* 2312 * XXX don't set the max_frame_size to larger 2313 * than the hardware can handle 2314 */ 2315 ctx->ifc_rx_mbuf_sz = 2316 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2317 } 2318 2319 uint32_t 2320 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2321 { 2322 2323 return (ctx->ifc_rx_mbuf_sz); 2324 } 2325 2326 static void 2327 iflib_init_locked(if_ctx_t ctx) 2328 { 2329 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2330 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2331 if_t ifp = ctx->ifc_ifp; 2332 iflib_fl_t fl; 2333 iflib_txq_t txq; 2334 iflib_rxq_t rxq; 2335 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2336 2337 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2338 IFDI_INTR_DISABLE(ctx); 2339 2340 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2341 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2342 /* Set hardware offload abilities */ 2343 if_clearhwassist(ifp); 2344 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2345 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2346 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2347 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2348 if (if_getcapenable(ifp) & IFCAP_TSO4) 2349 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2350 if (if_getcapenable(ifp) & IFCAP_TSO6) 2351 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2352 2353 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2354 CALLOUT_LOCK(txq); 2355 callout_stop(&txq->ift_timer); 2356 CALLOUT_UNLOCK(txq); 2357 iflib_netmap_txq_init(ctx, txq); 2358 } 2359 2360 /* 2361 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2362 * that drivers can use the value when setting up the hardware receive 2363 * buffers. 2364 */ 2365 iflib_calc_rx_mbuf_sz(ctx); 2366 2367 #ifdef INVARIANTS 2368 i = if_getdrvflags(ifp); 2369 #endif 2370 IFDI_INIT(ctx); 2371 MPASS(if_getdrvflags(ifp) == i); 2372 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2373 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2374 /* This rxq is in netmap mode. Skip normal init. */ 2375 continue; 2376 } 2377 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2378 if (iflib_fl_setup(fl)) { 2379 device_printf(ctx->ifc_dev, 2380 "setting up free list %d failed - " 2381 "check cluster settings\n", j); 2382 goto done; 2383 } 2384 } 2385 } 2386 done: 2387 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2388 IFDI_INTR_ENABLE(ctx); 2389 txq = ctx->ifc_txqs; 2390 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2391 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2392 txq->ift_timer.c_cpu); 2393 } 2394 2395 static int 2396 iflib_media_change(if_t ifp) 2397 { 2398 if_ctx_t ctx = if_getsoftc(ifp); 2399 int err; 2400 2401 CTX_LOCK(ctx); 2402 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2403 iflib_init_locked(ctx); 2404 CTX_UNLOCK(ctx); 2405 return (err); 2406 } 2407 2408 static void 2409 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2410 { 2411 if_ctx_t ctx = if_getsoftc(ifp); 2412 2413 CTX_LOCK(ctx); 2414 IFDI_UPDATE_ADMIN_STATUS(ctx); 2415 IFDI_MEDIA_STATUS(ctx, ifmr); 2416 CTX_UNLOCK(ctx); 2417 } 2418 2419 void 2420 iflib_stop(if_ctx_t ctx) 2421 { 2422 iflib_txq_t txq = ctx->ifc_txqs; 2423 iflib_rxq_t rxq = ctx->ifc_rxqs; 2424 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2425 if_shared_ctx_t sctx = ctx->ifc_sctx; 2426 iflib_dma_info_t di; 2427 iflib_fl_t fl; 2428 int i, j; 2429 2430 /* Tell the stack that the interface is no longer active */ 2431 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2432 2433 IFDI_INTR_DISABLE(ctx); 2434 DELAY(1000); 2435 IFDI_STOP(ctx); 2436 DELAY(1000); 2437 2438 iflib_debug_reset(); 2439 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2440 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2441 /* make sure all transmitters have completed before proceeding XXX */ 2442 2443 CALLOUT_LOCK(txq); 2444 callout_stop(&txq->ift_timer); 2445 CALLOUT_UNLOCK(txq); 2446 2447 /* clean any enqueued buffers */ 2448 iflib_ifmp_purge(txq); 2449 /* Free any existing tx buffers. */ 2450 for (j = 0; j < txq->ift_size; j++) { 2451 iflib_txsd_free(ctx, txq, j); 2452 } 2453 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2454 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2455 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2456 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2457 txq->ift_pullups = 0; 2458 ifmp_ring_reset_stats(txq->ift_br); 2459 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2460 bzero((void *)di->idi_vaddr, di->idi_size); 2461 } 2462 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2463 /* make sure all transmitters have completed before proceeding XXX */ 2464 2465 rxq->ifr_cq_cidx = 0; 2466 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2467 bzero((void *)di->idi_vaddr, di->idi_size); 2468 /* also resets the free lists pidx/cidx */ 2469 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2470 iflib_fl_bufs_free(fl); 2471 } 2472 } 2473 2474 static inline caddr_t 2475 calc_next_rxd(iflib_fl_t fl, int cidx) 2476 { 2477 qidx_t size; 2478 int nrxd; 2479 caddr_t start, end, cur, next; 2480 2481 nrxd = fl->ifl_size; 2482 size = fl->ifl_rxd_size; 2483 start = fl->ifl_ifdi->idi_vaddr; 2484 2485 if (__predict_false(size == 0)) 2486 return (start); 2487 cur = start + size*cidx; 2488 end = start + size*nrxd; 2489 next = CACHE_PTR_NEXT(cur); 2490 return (next < end ? next : start); 2491 } 2492 2493 static inline void 2494 prefetch_pkts(iflib_fl_t fl, int cidx) 2495 { 2496 int nextptr; 2497 int nrxd = fl->ifl_size; 2498 caddr_t next_rxd; 2499 2500 2501 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2502 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2503 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2504 next_rxd = calc_next_rxd(fl, cidx); 2505 prefetch(next_rxd); 2506 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2507 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2508 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2509 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2510 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2511 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2512 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2513 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2514 } 2515 2516 static struct mbuf * 2517 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2518 int *pf_rv, if_rxd_info_t ri) 2519 { 2520 bus_dmamap_t map; 2521 iflib_fl_t fl; 2522 caddr_t payload; 2523 struct mbuf *m; 2524 int flid, cidx, len, next; 2525 2526 map = NULL; 2527 flid = irf->irf_flid; 2528 cidx = irf->irf_idx; 2529 fl = &rxq->ifr_fl[flid]; 2530 sd->ifsd_fl = fl; 2531 m = fl->ifl_sds.ifsd_m[cidx]; 2532 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2533 fl->ifl_credits--; 2534 #if MEMORY_LOGGING 2535 fl->ifl_m_dequeued++; 2536 #endif 2537 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2538 prefetch_pkts(fl, cidx); 2539 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2540 prefetch(&fl->ifl_sds.ifsd_map[next]); 2541 map = fl->ifl_sds.ifsd_map[cidx]; 2542 2543 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2544 2545 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2546 irf->irf_len != 0) { 2547 payload = *sd->ifsd_cl; 2548 payload += ri->iri_pad; 2549 len = ri->iri_len - ri->iri_pad; 2550 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2551 len | PFIL_MEMPTR | PFIL_IN, NULL); 2552 switch (*pf_rv) { 2553 case PFIL_DROPPED: 2554 case PFIL_CONSUMED: 2555 /* 2556 * The filter ate it. Everything is recycled. 2557 */ 2558 m = NULL; 2559 unload = 0; 2560 break; 2561 case PFIL_REALLOCED: 2562 /* 2563 * The filter copied it. Everything is recycled. 2564 */ 2565 m = pfil_mem2mbuf(payload); 2566 unload = 0; 2567 break; 2568 case PFIL_PASS: 2569 /* 2570 * Filter said it was OK, so receive like 2571 * normal 2572 */ 2573 fl->ifl_sds.ifsd_m[cidx] = NULL; 2574 break; 2575 default: 2576 MPASS(0); 2577 } 2578 } else { 2579 fl->ifl_sds.ifsd_m[cidx] = NULL; 2580 *pf_rv = PFIL_PASS; 2581 } 2582 2583 if (unload && irf->irf_len != 0) 2584 bus_dmamap_unload(fl->ifl_buf_tag, map); 2585 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2586 if (__predict_false(fl->ifl_cidx == 0)) 2587 fl->ifl_gen = 0; 2588 bit_clear(fl->ifl_rx_bitmap, cidx); 2589 return (m); 2590 } 2591 2592 static struct mbuf * 2593 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2594 { 2595 struct mbuf *m, *mh, *mt; 2596 caddr_t cl; 2597 int *pf_rv_ptr, flags, i, padlen; 2598 bool consumed; 2599 2600 i = 0; 2601 mh = NULL; 2602 consumed = false; 2603 *pf_rv = PFIL_PASS; 2604 pf_rv_ptr = pf_rv; 2605 do { 2606 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2607 pf_rv_ptr, ri); 2608 2609 MPASS(*sd->ifsd_cl != NULL); 2610 2611 /* 2612 * Exclude zero-length frags & frags from 2613 * packets the filter has consumed or dropped 2614 */ 2615 if (ri->iri_frags[i].irf_len == 0 || consumed || 2616 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2617 if (mh == NULL) { 2618 /* everything saved here */ 2619 consumed = true; 2620 pf_rv_ptr = NULL; 2621 continue; 2622 } 2623 /* XXX we can save the cluster here, but not the mbuf */ 2624 m_init(m, M_NOWAIT, MT_DATA, 0); 2625 m_free(m); 2626 continue; 2627 } 2628 if (mh == NULL) { 2629 flags = M_PKTHDR|M_EXT; 2630 mh = mt = m; 2631 padlen = ri->iri_pad; 2632 } else { 2633 flags = M_EXT; 2634 mt->m_next = m; 2635 mt = m; 2636 /* assuming padding is only on the first fragment */ 2637 padlen = 0; 2638 } 2639 cl = *sd->ifsd_cl; 2640 *sd->ifsd_cl = NULL; 2641 2642 /* Can these two be made one ? */ 2643 m_init(m, M_NOWAIT, MT_DATA, flags); 2644 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2645 /* 2646 * These must follow m_init and m_cljset 2647 */ 2648 m->m_data += padlen; 2649 ri->iri_len -= padlen; 2650 m->m_len = ri->iri_frags[i].irf_len; 2651 } while (++i < ri->iri_nfrags); 2652 2653 return (mh); 2654 } 2655 2656 /* 2657 * Process one software descriptor 2658 */ 2659 static struct mbuf * 2660 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2661 { 2662 struct if_rxsd sd; 2663 struct mbuf *m; 2664 int pf_rv; 2665 2666 /* should I merge this back in now that the two paths are basically duplicated? */ 2667 if (ri->iri_nfrags == 1 && 2668 ri->iri_frags[0].irf_len != 0 && 2669 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2670 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2671 &pf_rv, ri); 2672 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2673 return (m); 2674 if (pf_rv == PFIL_PASS) { 2675 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2676 #ifndef __NO_STRICT_ALIGNMENT 2677 if (!IP_ALIGNED(m)) 2678 m->m_data += 2; 2679 #endif 2680 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2681 m->m_len = ri->iri_frags[0].irf_len; 2682 } 2683 } else { 2684 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2685 if (m == NULL) 2686 return (NULL); 2687 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2688 return (m); 2689 } 2690 m->m_pkthdr.len = ri->iri_len; 2691 m->m_pkthdr.rcvif = ri->iri_ifp; 2692 m->m_flags |= ri->iri_flags; 2693 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2694 m->m_pkthdr.flowid = ri->iri_flowid; 2695 M_HASHTYPE_SET(m, ri->iri_rsstype); 2696 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2697 m->m_pkthdr.csum_data = ri->iri_csum_data; 2698 return (m); 2699 } 2700 2701 #if defined(INET6) || defined(INET) 2702 static void 2703 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2704 { 2705 CURVNET_SET(lc->ifp->if_vnet); 2706 #if defined(INET6) 2707 *v6 = V_ip6_forwarding; 2708 #endif 2709 #if defined(INET) 2710 *v4 = V_ipforwarding; 2711 #endif 2712 CURVNET_RESTORE(); 2713 } 2714 2715 /* 2716 * Returns true if it's possible this packet could be LROed. 2717 * if it returns false, it is guaranteed that tcp_lro_rx() 2718 * would not return zero. 2719 */ 2720 static bool 2721 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2722 { 2723 struct ether_header *eh; 2724 2725 eh = mtod(m, struct ether_header *); 2726 switch (eh->ether_type) { 2727 #if defined(INET6) 2728 case htons(ETHERTYPE_IPV6): 2729 return (!v6_forwarding); 2730 #endif 2731 #if defined (INET) 2732 case htons(ETHERTYPE_IP): 2733 return (!v4_forwarding); 2734 #endif 2735 } 2736 2737 return false; 2738 } 2739 #else 2740 static void 2741 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2742 { 2743 } 2744 #endif 2745 2746 static void 2747 _task_fn_rx_watchdog(void *context) 2748 { 2749 iflib_rxq_t rxq = context; 2750 2751 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2752 } 2753 2754 static uint8_t 2755 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2756 { 2757 if_t ifp; 2758 if_ctx_t ctx = rxq->ifr_ctx; 2759 if_shared_ctx_t sctx = ctx->ifc_sctx; 2760 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2761 int avail, i; 2762 qidx_t *cidxp; 2763 struct if_rxd_info ri; 2764 int err, budget_left, rx_bytes, rx_pkts; 2765 iflib_fl_t fl; 2766 int lro_enabled; 2767 bool v4_forwarding, v6_forwarding, lro_possible; 2768 uint8_t retval = 0; 2769 2770 /* 2771 * XXX early demux data packets so that if_input processing only handles 2772 * acks in interrupt context 2773 */ 2774 struct mbuf *m, *mh, *mt, *mf; 2775 2776 NET_EPOCH_ASSERT(); 2777 2778 lro_possible = v4_forwarding = v6_forwarding = false; 2779 ifp = ctx->ifc_ifp; 2780 mh = mt = NULL; 2781 MPASS(budget > 0); 2782 rx_pkts = rx_bytes = 0; 2783 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2784 cidxp = &rxq->ifr_cq_cidx; 2785 else 2786 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2787 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2788 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2789 retval |= iflib_fl_refill_all(ctx, fl); 2790 DBG_COUNTER_INC(rx_unavail); 2791 return (retval); 2792 } 2793 2794 /* pfil needs the vnet to be set */ 2795 CURVNET_SET_QUIET(ifp->if_vnet); 2796 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2797 if (__predict_false(!CTX_ACTIVE(ctx))) { 2798 DBG_COUNTER_INC(rx_ctx_inactive); 2799 break; 2800 } 2801 /* 2802 * Reset client set fields to their default values 2803 */ 2804 rxd_info_zero(&ri); 2805 ri.iri_qsidx = rxq->ifr_id; 2806 ri.iri_cidx = *cidxp; 2807 ri.iri_ifp = ifp; 2808 ri.iri_frags = rxq->ifr_frags; 2809 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2810 2811 if (err) 2812 goto err; 2813 rx_pkts += 1; 2814 rx_bytes += ri.iri_len; 2815 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2816 *cidxp = ri.iri_cidx; 2817 /* Update our consumer index */ 2818 /* XXX NB: shurd - check if this is still safe */ 2819 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2820 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2821 /* was this only a completion queue message? */ 2822 if (__predict_false(ri.iri_nfrags == 0)) 2823 continue; 2824 } 2825 MPASS(ri.iri_nfrags != 0); 2826 MPASS(ri.iri_len != 0); 2827 2828 /* will advance the cidx on the corresponding free lists */ 2829 m = iflib_rxd_pkt_get(rxq, &ri); 2830 avail--; 2831 budget_left--; 2832 if (avail == 0 && budget_left) 2833 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2834 2835 if (__predict_false(m == NULL)) 2836 continue; 2837 2838 /* imm_pkt: -- cxgb */ 2839 if (mh == NULL) 2840 mh = mt = m; 2841 else { 2842 mt->m_nextpkt = m; 2843 mt = m; 2844 } 2845 } 2846 CURVNET_RESTORE(); 2847 /* make sure that we can refill faster than drain */ 2848 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2849 retval |= iflib_fl_refill_all(ctx, fl); 2850 2851 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2852 if (lro_enabled) 2853 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2854 mt = mf = NULL; 2855 while (mh != NULL) { 2856 m = mh; 2857 mh = mh->m_nextpkt; 2858 m->m_nextpkt = NULL; 2859 #ifndef __NO_STRICT_ALIGNMENT 2860 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2861 continue; 2862 #endif 2863 rx_bytes += m->m_pkthdr.len; 2864 rx_pkts++; 2865 #if defined(INET6) || defined(INET) 2866 if (lro_enabled) { 2867 if (!lro_possible) { 2868 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2869 if (lro_possible && mf != NULL) { 2870 ifp->if_input(ifp, mf); 2871 DBG_COUNTER_INC(rx_if_input); 2872 mt = mf = NULL; 2873 } 2874 } 2875 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2876 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2877 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2878 continue; 2879 } 2880 } 2881 #endif 2882 if (lro_possible) { 2883 ifp->if_input(ifp, m); 2884 DBG_COUNTER_INC(rx_if_input); 2885 continue; 2886 } 2887 2888 if (mf == NULL) 2889 mf = m; 2890 if (mt != NULL) 2891 mt->m_nextpkt = m; 2892 mt = m; 2893 } 2894 if (mf != NULL) { 2895 ifp->if_input(ifp, mf); 2896 DBG_COUNTER_INC(rx_if_input); 2897 } 2898 2899 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2900 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2901 2902 /* 2903 * Flush any outstanding LRO work 2904 */ 2905 #if defined(INET6) || defined(INET) 2906 tcp_lro_flush_all(&rxq->ifr_lc); 2907 #endif 2908 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 2909 retval |= IFLIB_RXEOF_MORE; 2910 return (retval); 2911 err: 2912 STATE_LOCK(ctx); 2913 ctx->ifc_flags |= IFC_DO_RESET; 2914 iflib_admin_intr_deferred(ctx); 2915 STATE_UNLOCK(ctx); 2916 return (0); 2917 } 2918 2919 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2920 static inline qidx_t 2921 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2922 { 2923 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2924 qidx_t minthresh = txq->ift_size / 8; 2925 if (in_use > 4*minthresh) 2926 return (notify_count); 2927 if (in_use > 2*minthresh) 2928 return (notify_count >> 1); 2929 if (in_use > minthresh) 2930 return (notify_count >> 3); 2931 return (0); 2932 } 2933 2934 static inline qidx_t 2935 txq_max_rs_deferred(iflib_txq_t txq) 2936 { 2937 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2938 qidx_t minthresh = txq->ift_size / 8; 2939 if (txq->ift_in_use > 4*minthresh) 2940 return (notify_count); 2941 if (txq->ift_in_use > 2*minthresh) 2942 return (notify_count >> 1); 2943 if (txq->ift_in_use > minthresh) 2944 return (notify_count >> 2); 2945 return (2); 2946 } 2947 2948 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2949 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2950 2951 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2952 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2953 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2954 2955 /* forward compatibility for cxgb */ 2956 #define FIRST_QSET(ctx) 0 2957 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2958 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2959 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2960 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2961 2962 /* XXX we should be setting this to something other than zero */ 2963 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2964 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2965 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2966 2967 static inline bool 2968 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2969 { 2970 qidx_t dbval, max; 2971 bool rang; 2972 2973 rang = false; 2974 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2975 if (ring || txq->ift_db_pending >= max) { 2976 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2977 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2978 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2979 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2980 txq->ift_db_pending = txq->ift_npending = 0; 2981 rang = true; 2982 } 2983 return (rang); 2984 } 2985 2986 #ifdef PKT_DEBUG 2987 static void 2988 print_pkt(if_pkt_info_t pi) 2989 { 2990 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2991 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2992 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2993 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2994 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2995 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2996 } 2997 #endif 2998 2999 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3000 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3001 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3002 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3003 3004 static int 3005 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3006 { 3007 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3008 struct ether_vlan_header *eh; 3009 struct mbuf *m; 3010 3011 m = *mp; 3012 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3013 M_WRITABLE(m) == 0) { 3014 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3015 return (ENOMEM); 3016 } else { 3017 m_freem(*mp); 3018 DBG_COUNTER_INC(tx_frees); 3019 *mp = m; 3020 } 3021 } 3022 3023 /* 3024 * Determine where frame payload starts. 3025 * Jump over vlan headers if already present, 3026 * helpful for QinQ too. 3027 */ 3028 if (__predict_false(m->m_len < sizeof(*eh))) { 3029 txq->ift_pullups++; 3030 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3031 return (ENOMEM); 3032 } 3033 eh = mtod(m, struct ether_vlan_header *); 3034 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3035 pi->ipi_etype = ntohs(eh->evl_proto); 3036 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3037 } else { 3038 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3039 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3040 } 3041 3042 switch (pi->ipi_etype) { 3043 #ifdef INET 3044 case ETHERTYPE_IP: 3045 { 3046 struct mbuf *n; 3047 struct ip *ip = NULL; 3048 struct tcphdr *th = NULL; 3049 int minthlen; 3050 3051 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3052 if (__predict_false(m->m_len < minthlen)) { 3053 /* 3054 * if this code bloat is causing too much of a hit 3055 * move it to a separate function and mark it noinline 3056 */ 3057 if (m->m_len == pi->ipi_ehdrlen) { 3058 n = m->m_next; 3059 MPASS(n); 3060 if (n->m_len >= sizeof(*ip)) { 3061 ip = (struct ip *)n->m_data; 3062 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3063 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3064 } else { 3065 txq->ift_pullups++; 3066 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3067 return (ENOMEM); 3068 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3069 } 3070 } else { 3071 txq->ift_pullups++; 3072 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3073 return (ENOMEM); 3074 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3075 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3076 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3077 } 3078 } else { 3079 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3080 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3081 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3082 } 3083 pi->ipi_ip_hlen = ip->ip_hl << 2; 3084 pi->ipi_ipproto = ip->ip_p; 3085 pi->ipi_flags |= IPI_TX_IPV4; 3086 3087 /* TCP checksum offload may require TCP header length */ 3088 if (IS_TX_OFFLOAD4(pi)) { 3089 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3090 if (__predict_false(th == NULL)) { 3091 txq->ift_pullups++; 3092 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3093 return (ENOMEM); 3094 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3095 } 3096 pi->ipi_tcp_hflags = th->th_flags; 3097 pi->ipi_tcp_hlen = th->th_off << 2; 3098 pi->ipi_tcp_seq = th->th_seq; 3099 } 3100 if (IS_TSO4(pi)) { 3101 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3102 return (ENXIO); 3103 /* 3104 * TSO always requires hardware checksum offload. 3105 */ 3106 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3107 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3108 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3109 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3110 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3111 ip->ip_sum = 0; 3112 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3113 } 3114 } 3115 } 3116 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3117 ip->ip_sum = 0; 3118 3119 break; 3120 } 3121 #endif 3122 #ifdef INET6 3123 case ETHERTYPE_IPV6: 3124 { 3125 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3126 struct tcphdr *th; 3127 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3128 3129 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3130 txq->ift_pullups++; 3131 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3132 return (ENOMEM); 3133 } 3134 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3135 3136 /* XXX-BZ this will go badly in case of ext hdrs. */ 3137 pi->ipi_ipproto = ip6->ip6_nxt; 3138 pi->ipi_flags |= IPI_TX_IPV6; 3139 3140 /* TCP checksum offload may require TCP header length */ 3141 if (IS_TX_OFFLOAD6(pi)) { 3142 if (pi->ipi_ipproto == IPPROTO_TCP) { 3143 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3144 txq->ift_pullups++; 3145 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3146 return (ENOMEM); 3147 } 3148 pi->ipi_tcp_hflags = th->th_flags; 3149 pi->ipi_tcp_hlen = th->th_off << 2; 3150 pi->ipi_tcp_seq = th->th_seq; 3151 } 3152 if (IS_TSO6(pi)) { 3153 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3154 return (ENXIO); 3155 /* 3156 * TSO always requires hardware checksum offload. 3157 */ 3158 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3159 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3160 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3161 } 3162 } 3163 break; 3164 } 3165 #endif 3166 default: 3167 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3168 pi->ipi_ip_hlen = 0; 3169 break; 3170 } 3171 *mp = m; 3172 3173 return (0); 3174 } 3175 3176 /* 3177 * If dodgy hardware rejects the scatter gather chain we've handed it 3178 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3179 * m_defrag'd mbufs 3180 */ 3181 static __noinline struct mbuf * 3182 iflib_remove_mbuf(iflib_txq_t txq) 3183 { 3184 int ntxd, pidx; 3185 struct mbuf *m, **ifsd_m; 3186 3187 ifsd_m = txq->ift_sds.ifsd_m; 3188 ntxd = txq->ift_size; 3189 pidx = txq->ift_pidx & (ntxd - 1); 3190 ifsd_m = txq->ift_sds.ifsd_m; 3191 m = ifsd_m[pidx]; 3192 ifsd_m[pidx] = NULL; 3193 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3194 if (txq->ift_sds.ifsd_tso_map != NULL) 3195 bus_dmamap_unload(txq->ift_tso_buf_tag, 3196 txq->ift_sds.ifsd_tso_map[pidx]); 3197 #if MEMORY_LOGGING 3198 txq->ift_dequeued++; 3199 #endif 3200 return (m); 3201 } 3202 3203 static inline caddr_t 3204 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3205 { 3206 qidx_t size; 3207 int ntxd; 3208 caddr_t start, end, cur, next; 3209 3210 ntxd = txq->ift_size; 3211 size = txq->ift_txd_size[qid]; 3212 start = txq->ift_ifdi[qid].idi_vaddr; 3213 3214 if (__predict_false(size == 0)) 3215 return (start); 3216 cur = start + size*cidx; 3217 end = start + size*ntxd; 3218 next = CACHE_PTR_NEXT(cur); 3219 return (next < end ? next : start); 3220 } 3221 3222 /* 3223 * Pad an mbuf to ensure a minimum ethernet frame size. 3224 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3225 */ 3226 static __noinline int 3227 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3228 { 3229 /* 3230 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3231 * and ARP message is the smallest common payload I can think of 3232 */ 3233 static char pad[18]; /* just zeros */ 3234 int n; 3235 struct mbuf *new_head; 3236 3237 if (!M_WRITABLE(*m_head)) { 3238 new_head = m_dup(*m_head, M_NOWAIT); 3239 if (new_head == NULL) { 3240 m_freem(*m_head); 3241 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3242 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3243 DBG_COUNTER_INC(tx_frees); 3244 return ENOMEM; 3245 } 3246 m_freem(*m_head); 3247 *m_head = new_head; 3248 } 3249 3250 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3251 n > 0; n -= sizeof(pad)) 3252 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3253 break; 3254 3255 if (n > 0) { 3256 m_freem(*m_head); 3257 device_printf(dev, "cannot pad short frame\n"); 3258 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3259 DBG_COUNTER_INC(tx_frees); 3260 return (ENOBUFS); 3261 } 3262 3263 return 0; 3264 } 3265 3266 static int 3267 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3268 { 3269 if_ctx_t ctx; 3270 if_shared_ctx_t sctx; 3271 if_softc_ctx_t scctx; 3272 bus_dma_tag_t buf_tag; 3273 bus_dma_segment_t *segs; 3274 struct mbuf *m_head, **ifsd_m; 3275 void *next_txd; 3276 bus_dmamap_t map; 3277 struct if_pkt_info pi; 3278 int remap = 0; 3279 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3280 3281 ctx = txq->ift_ctx; 3282 sctx = ctx->ifc_sctx; 3283 scctx = &ctx->ifc_softc_ctx; 3284 segs = txq->ift_segs; 3285 ntxd = txq->ift_size; 3286 m_head = *m_headp; 3287 map = NULL; 3288 3289 /* 3290 * If we're doing TSO the next descriptor to clean may be quite far ahead 3291 */ 3292 cidx = txq->ift_cidx; 3293 pidx = txq->ift_pidx; 3294 if (ctx->ifc_flags & IFC_PREFETCH) { 3295 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3296 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3297 next_txd = calc_next_txd(txq, cidx, 0); 3298 prefetch(next_txd); 3299 } 3300 3301 /* prefetch the next cache line of mbuf pointers and flags */ 3302 prefetch(&txq->ift_sds.ifsd_m[next]); 3303 prefetch(&txq->ift_sds.ifsd_map[next]); 3304 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3305 } 3306 map = txq->ift_sds.ifsd_map[pidx]; 3307 ifsd_m = txq->ift_sds.ifsd_m; 3308 3309 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3310 buf_tag = txq->ift_tso_buf_tag; 3311 max_segs = scctx->isc_tx_tso_segments_max; 3312 map = txq->ift_sds.ifsd_tso_map[pidx]; 3313 MPASS(buf_tag != NULL); 3314 MPASS(max_segs > 0); 3315 } else { 3316 buf_tag = txq->ift_buf_tag; 3317 max_segs = scctx->isc_tx_nsegments; 3318 map = txq->ift_sds.ifsd_map[pidx]; 3319 } 3320 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3321 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3322 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3323 if (err) { 3324 DBG_COUNTER_INC(encap_txd_encap_fail); 3325 return err; 3326 } 3327 } 3328 m_head = *m_headp; 3329 3330 pkt_info_zero(&pi); 3331 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3332 pi.ipi_pidx = pidx; 3333 pi.ipi_qsidx = txq->ift_id; 3334 pi.ipi_len = m_head->m_pkthdr.len; 3335 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3336 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3337 3338 /* deliberate bitwise OR to make one condition */ 3339 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3340 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3341 DBG_COUNTER_INC(encap_txd_encap_fail); 3342 return (err); 3343 } 3344 m_head = *m_headp; 3345 } 3346 3347 retry: 3348 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3349 BUS_DMA_NOWAIT); 3350 defrag: 3351 if (__predict_false(err)) { 3352 switch (err) { 3353 case EFBIG: 3354 /* try collapse once and defrag once */ 3355 if (remap == 0) { 3356 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3357 /* try defrag if collapsing fails */ 3358 if (m_head == NULL) 3359 remap++; 3360 } 3361 if (remap == 1) { 3362 txq->ift_mbuf_defrag++; 3363 m_head = m_defrag(*m_headp, M_NOWAIT); 3364 } 3365 /* 3366 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3367 * failed to map an mbuf that was run through m_defrag 3368 */ 3369 MPASS(remap <= 1); 3370 if (__predict_false(m_head == NULL || remap > 1)) 3371 goto defrag_failed; 3372 remap++; 3373 *m_headp = m_head; 3374 goto retry; 3375 break; 3376 case ENOMEM: 3377 txq->ift_no_tx_dma_setup++; 3378 break; 3379 default: 3380 txq->ift_no_tx_dma_setup++; 3381 m_freem(*m_headp); 3382 DBG_COUNTER_INC(tx_frees); 3383 *m_headp = NULL; 3384 break; 3385 } 3386 txq->ift_map_failed++; 3387 DBG_COUNTER_INC(encap_load_mbuf_fail); 3388 DBG_COUNTER_INC(encap_txd_encap_fail); 3389 return (err); 3390 } 3391 ifsd_m[pidx] = m_head; 3392 /* 3393 * XXX assumes a 1 to 1 relationship between segments and 3394 * descriptors - this does not hold true on all drivers, e.g. 3395 * cxgb 3396 */ 3397 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3398 txq->ift_no_desc_avail++; 3399 bus_dmamap_unload(buf_tag, map); 3400 DBG_COUNTER_INC(encap_txq_avail_fail); 3401 DBG_COUNTER_INC(encap_txd_encap_fail); 3402 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3403 GROUPTASK_ENQUEUE(&txq->ift_task); 3404 return (ENOBUFS); 3405 } 3406 /* 3407 * On Intel cards we can greatly reduce the number of TX interrupts 3408 * we see by only setting report status on every Nth descriptor. 3409 * However, this also means that the driver will need to keep track 3410 * of the descriptors that RS was set on to check them for the DD bit. 3411 */ 3412 txq->ift_rs_pending += nsegs + 1; 3413 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3414 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3415 pi.ipi_flags |= IPI_TX_INTR; 3416 txq->ift_rs_pending = 0; 3417 } 3418 3419 pi.ipi_segs = segs; 3420 pi.ipi_nsegs = nsegs; 3421 3422 MPASS(pidx >= 0 && pidx < txq->ift_size); 3423 #ifdef PKT_DEBUG 3424 print_pkt(&pi); 3425 #endif 3426 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3427 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3428 DBG_COUNTER_INC(tx_encap); 3429 MPASS(pi.ipi_new_pidx < txq->ift_size); 3430 3431 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3432 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3433 ndesc += txq->ift_size; 3434 txq->ift_gen = 1; 3435 } 3436 /* 3437 * drivers can need as many as 3438 * two sentinels 3439 */ 3440 MPASS(ndesc <= pi.ipi_nsegs + 2); 3441 MPASS(pi.ipi_new_pidx != pidx); 3442 MPASS(ndesc > 0); 3443 txq->ift_in_use += ndesc; 3444 3445 /* 3446 * We update the last software descriptor again here because there may 3447 * be a sentinel and/or there may be more mbufs than segments 3448 */ 3449 txq->ift_pidx = pi.ipi_new_pidx; 3450 txq->ift_npending += pi.ipi_ndescs; 3451 } else { 3452 *m_headp = m_head = iflib_remove_mbuf(txq); 3453 if (err == EFBIG) { 3454 txq->ift_txd_encap_efbig++; 3455 if (remap < 2) { 3456 remap = 1; 3457 goto defrag; 3458 } 3459 } 3460 goto defrag_failed; 3461 } 3462 /* 3463 * err can't possibly be non-zero here, so we don't neet to test it 3464 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3465 */ 3466 return (err); 3467 3468 defrag_failed: 3469 txq->ift_mbuf_defrag_failed++; 3470 txq->ift_map_failed++; 3471 m_freem(*m_headp); 3472 DBG_COUNTER_INC(tx_frees); 3473 *m_headp = NULL; 3474 DBG_COUNTER_INC(encap_txd_encap_fail); 3475 return (ENOMEM); 3476 } 3477 3478 static void 3479 iflib_tx_desc_free(iflib_txq_t txq, int n) 3480 { 3481 uint32_t qsize, cidx, mask, gen; 3482 struct mbuf *m, **ifsd_m; 3483 bool do_prefetch; 3484 3485 cidx = txq->ift_cidx; 3486 gen = txq->ift_gen; 3487 qsize = txq->ift_size; 3488 mask = qsize-1; 3489 ifsd_m = txq->ift_sds.ifsd_m; 3490 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3491 3492 while (n-- > 0) { 3493 if (do_prefetch) { 3494 prefetch(ifsd_m[(cidx + 3) & mask]); 3495 prefetch(ifsd_m[(cidx + 4) & mask]); 3496 } 3497 if ((m = ifsd_m[cidx]) != NULL) { 3498 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3499 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3500 bus_dmamap_sync(txq->ift_tso_buf_tag, 3501 txq->ift_sds.ifsd_tso_map[cidx], 3502 BUS_DMASYNC_POSTWRITE); 3503 bus_dmamap_unload(txq->ift_tso_buf_tag, 3504 txq->ift_sds.ifsd_tso_map[cidx]); 3505 } else { 3506 bus_dmamap_sync(txq->ift_buf_tag, 3507 txq->ift_sds.ifsd_map[cidx], 3508 BUS_DMASYNC_POSTWRITE); 3509 bus_dmamap_unload(txq->ift_buf_tag, 3510 txq->ift_sds.ifsd_map[cidx]); 3511 } 3512 /* XXX we don't support any drivers that batch packets yet */ 3513 MPASS(m->m_nextpkt == NULL); 3514 m_freem(m); 3515 ifsd_m[cidx] = NULL; 3516 #if MEMORY_LOGGING 3517 txq->ift_dequeued++; 3518 #endif 3519 DBG_COUNTER_INC(tx_frees); 3520 } 3521 if (__predict_false(++cidx == qsize)) { 3522 cidx = 0; 3523 gen = 0; 3524 } 3525 } 3526 txq->ift_cidx = cidx; 3527 txq->ift_gen = gen; 3528 } 3529 3530 static __inline int 3531 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3532 { 3533 int reclaim; 3534 if_ctx_t ctx = txq->ift_ctx; 3535 3536 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3537 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3538 3539 /* 3540 * Need a rate-limiting check so that this isn't called every time 3541 */ 3542 iflib_tx_credits_update(ctx, txq); 3543 reclaim = DESC_RECLAIMABLE(txq); 3544 3545 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3546 #ifdef INVARIANTS 3547 if (iflib_verbose_debug) { 3548 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3549 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3550 reclaim, thresh); 3551 3552 } 3553 #endif 3554 return (0); 3555 } 3556 iflib_tx_desc_free(txq, reclaim); 3557 txq->ift_cleaned += reclaim; 3558 txq->ift_in_use -= reclaim; 3559 3560 return (reclaim); 3561 } 3562 3563 static struct mbuf ** 3564 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3565 { 3566 int next, size; 3567 struct mbuf **items; 3568 3569 size = r->size; 3570 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3571 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3572 3573 prefetch(items[(cidx + offset) & (size-1)]); 3574 if (remaining > 1) { 3575 prefetch2cachelines(&items[next]); 3576 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3577 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3578 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3579 } 3580 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3581 } 3582 3583 static void 3584 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3585 { 3586 3587 ifmp_ring_check_drainage(txq->ift_br, budget); 3588 } 3589 3590 static uint32_t 3591 iflib_txq_can_drain(struct ifmp_ring *r) 3592 { 3593 iflib_txq_t txq = r->cookie; 3594 if_ctx_t ctx = txq->ift_ctx; 3595 3596 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3597 return (1); 3598 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3599 BUS_DMASYNC_POSTREAD); 3600 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3601 false)); 3602 } 3603 3604 static uint32_t 3605 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3606 { 3607 iflib_txq_t txq = r->cookie; 3608 if_ctx_t ctx = txq->ift_ctx; 3609 if_t ifp = ctx->ifc_ifp; 3610 struct mbuf *m, **mp; 3611 int avail, bytes_sent, consumed, count, err, i, in_use_prev; 3612 int mcast_sent, pkt_sent, reclaimed, txq_avail; 3613 bool do_prefetch, rang, ring; 3614 3615 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3616 !LINK_ACTIVE(ctx))) { 3617 DBG_COUNTER_INC(txq_drain_notready); 3618 return (0); 3619 } 3620 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3621 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3622 avail = IDXDIFF(pidx, cidx, r->size); 3623 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3624 DBG_COUNTER_INC(txq_drain_flushing); 3625 for (i = 0; i < avail; i++) { 3626 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3627 m_free(r->items[(cidx + i) & (r->size-1)]); 3628 r->items[(cidx + i) & (r->size-1)] = NULL; 3629 } 3630 return (avail); 3631 } 3632 3633 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3634 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3635 CALLOUT_LOCK(txq); 3636 callout_stop(&txq->ift_timer); 3637 CALLOUT_UNLOCK(txq); 3638 DBG_COUNTER_INC(txq_drain_oactive); 3639 return (0); 3640 } 3641 if (reclaimed) 3642 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3643 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3644 count = MIN(avail, TX_BATCH_SIZE); 3645 #ifdef INVARIANTS 3646 if (iflib_verbose_debug) 3647 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3648 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3649 #endif 3650 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3651 txq_avail = TXQ_AVAIL(txq); 3652 err = 0; 3653 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) { 3654 int rem = do_prefetch ? count - i : 0; 3655 3656 mp = _ring_peek_one(r, cidx, i, rem); 3657 MPASS(mp != NULL && *mp != NULL); 3658 if (__predict_false(*mp == (struct mbuf *)txq)) { 3659 consumed++; 3660 continue; 3661 } 3662 in_use_prev = txq->ift_in_use; 3663 err = iflib_encap(txq, mp); 3664 if (__predict_false(err)) { 3665 /* no room - bail out */ 3666 if (err == ENOBUFS) 3667 break; 3668 consumed++; 3669 /* we can't send this packet - skip it */ 3670 continue; 3671 } 3672 consumed++; 3673 pkt_sent++; 3674 m = *mp; 3675 DBG_COUNTER_INC(tx_sent); 3676 bytes_sent += m->m_pkthdr.len; 3677 mcast_sent += !!(m->m_flags & M_MCAST); 3678 txq_avail = TXQ_AVAIL(txq); 3679 3680 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3681 ETHER_BPF_MTAP(ifp, m); 3682 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3683 break; 3684 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3685 } 3686 3687 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3688 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3689 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3690 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3691 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3692 if (mcast_sent) 3693 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3694 #ifdef INVARIANTS 3695 if (iflib_verbose_debug) 3696 printf("consumed=%d\n", consumed); 3697 #endif 3698 return (consumed); 3699 } 3700 3701 static uint32_t 3702 iflib_txq_drain_always(struct ifmp_ring *r) 3703 { 3704 return (1); 3705 } 3706 3707 static uint32_t 3708 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3709 { 3710 int i, avail; 3711 struct mbuf **mp; 3712 iflib_txq_t txq; 3713 3714 txq = r->cookie; 3715 3716 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3717 CALLOUT_LOCK(txq); 3718 callout_stop(&txq->ift_timer); 3719 CALLOUT_UNLOCK(txq); 3720 3721 avail = IDXDIFF(pidx, cidx, r->size); 3722 for (i = 0; i < avail; i++) { 3723 mp = _ring_peek_one(r, cidx, i, avail - i); 3724 if (__predict_false(*mp == (struct mbuf *)txq)) 3725 continue; 3726 m_freem(*mp); 3727 DBG_COUNTER_INC(tx_frees); 3728 } 3729 MPASS(ifmp_ring_is_stalled(r) == 0); 3730 return (avail); 3731 } 3732 3733 static void 3734 iflib_ifmp_purge(iflib_txq_t txq) 3735 { 3736 struct ifmp_ring *r; 3737 3738 r = txq->ift_br; 3739 r->drain = iflib_txq_drain_free; 3740 r->can_drain = iflib_txq_drain_always; 3741 3742 ifmp_ring_check_drainage(r, r->size); 3743 3744 r->drain = iflib_txq_drain; 3745 r->can_drain = iflib_txq_can_drain; 3746 } 3747 3748 static void 3749 _task_fn_tx(void *context) 3750 { 3751 iflib_txq_t txq = context; 3752 if_ctx_t ctx = txq->ift_ctx; 3753 if_t ifp = ctx->ifc_ifp; 3754 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3755 3756 #ifdef IFLIB_DIAGNOSTICS 3757 txq->ift_cpu_exec_count[curcpu]++; 3758 #endif 3759 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3760 return; 3761 #ifdef DEV_NETMAP 3762 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3763 netmap_tx_irq(ifp, txq->ift_id)) 3764 goto skip_ifmp; 3765 #endif 3766 #ifdef ALTQ 3767 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3768 iflib_altq_if_start(ifp); 3769 #endif 3770 if (txq->ift_db_pending) 3771 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3772 else if (!abdicate) 3773 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3774 /* 3775 * When abdicating, we always need to check drainage, not just when we don't enqueue 3776 */ 3777 if (abdicate) 3778 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3779 #ifdef DEV_NETMAP 3780 skip_ifmp: 3781 #endif 3782 if (ctx->ifc_flags & IFC_LEGACY) 3783 IFDI_INTR_ENABLE(ctx); 3784 else 3785 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3786 } 3787 3788 static void 3789 _task_fn_rx(void *context) 3790 { 3791 iflib_rxq_t rxq = context; 3792 if_ctx_t ctx = rxq->ifr_ctx; 3793 uint8_t more; 3794 uint16_t budget; 3795 #ifdef DEV_NETMAP 3796 u_int work = 0; 3797 int nmirq; 3798 #endif 3799 3800 #ifdef IFLIB_DIAGNOSTICS 3801 rxq->ifr_cpu_exec_count[curcpu]++; 3802 #endif 3803 DBG_COUNTER_INC(task_fn_rxs); 3804 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3805 return; 3806 #ifdef DEV_NETMAP 3807 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 3808 if (nmirq != NM_IRQ_PASS) { 3809 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 3810 goto skip_rxeof; 3811 } 3812 #endif 3813 budget = ctx->ifc_sysctl_rx_budget; 3814 if (budget == 0) 3815 budget = 16; /* XXX */ 3816 more = iflib_rxeof(rxq, budget); 3817 #ifdef DEV_NETMAP 3818 skip_rxeof: 3819 #endif 3820 if ((more & IFLIB_RXEOF_MORE) == 0) { 3821 if (ctx->ifc_flags & IFC_LEGACY) 3822 IFDI_INTR_ENABLE(ctx); 3823 else 3824 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3825 DBG_COUNTER_INC(rx_intr_enables); 3826 } 3827 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3828 return; 3829 3830 if (more & IFLIB_RXEOF_MORE) 3831 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3832 else if (more & IFLIB_RXEOF_EMPTY) 3833 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 3834 } 3835 3836 static void 3837 _task_fn_admin(void *context) 3838 { 3839 if_ctx_t ctx = context; 3840 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3841 iflib_txq_t txq; 3842 int i; 3843 bool oactive, running, do_reset, do_watchdog, in_detach; 3844 uint32_t reset_on = hz / 2; 3845 3846 STATE_LOCK(ctx); 3847 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3848 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3849 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3850 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3851 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3852 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3853 STATE_UNLOCK(ctx); 3854 3855 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3856 return; 3857 if (in_detach) 3858 return; 3859 3860 CTX_LOCK(ctx); 3861 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3862 CALLOUT_LOCK(txq); 3863 callout_stop(&txq->ift_timer); 3864 CALLOUT_UNLOCK(txq); 3865 } 3866 if (do_watchdog) { 3867 ctx->ifc_watchdog_events++; 3868 IFDI_WATCHDOG_RESET(ctx); 3869 } 3870 IFDI_UPDATE_ADMIN_STATUS(ctx); 3871 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3872 #ifdef DEV_NETMAP 3873 reset_on = hz / 2; 3874 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3875 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3876 #endif 3877 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3878 } 3879 IFDI_LINK_INTR_ENABLE(ctx); 3880 if (do_reset) 3881 iflib_if_init_locked(ctx); 3882 CTX_UNLOCK(ctx); 3883 3884 if (LINK_ACTIVE(ctx) == 0) 3885 return; 3886 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3887 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3888 } 3889 3890 3891 static void 3892 _task_fn_iov(void *context) 3893 { 3894 if_ctx_t ctx = context; 3895 3896 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3897 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3898 return; 3899 3900 CTX_LOCK(ctx); 3901 IFDI_VFLR_HANDLE(ctx); 3902 CTX_UNLOCK(ctx); 3903 } 3904 3905 static int 3906 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3907 { 3908 int err; 3909 if_int_delay_info_t info; 3910 if_ctx_t ctx; 3911 3912 info = (if_int_delay_info_t)arg1; 3913 ctx = info->iidi_ctx; 3914 info->iidi_req = req; 3915 info->iidi_oidp = oidp; 3916 CTX_LOCK(ctx); 3917 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3918 CTX_UNLOCK(ctx); 3919 return (err); 3920 } 3921 3922 /********************************************************************* 3923 * 3924 * IFNET FUNCTIONS 3925 * 3926 **********************************************************************/ 3927 3928 static void 3929 iflib_if_init_locked(if_ctx_t ctx) 3930 { 3931 iflib_stop(ctx); 3932 iflib_init_locked(ctx); 3933 } 3934 3935 3936 static void 3937 iflib_if_init(void *arg) 3938 { 3939 if_ctx_t ctx = arg; 3940 3941 CTX_LOCK(ctx); 3942 iflib_if_init_locked(ctx); 3943 CTX_UNLOCK(ctx); 3944 } 3945 3946 static int 3947 iflib_if_transmit(if_t ifp, struct mbuf *m) 3948 { 3949 if_ctx_t ctx = if_getsoftc(ifp); 3950 3951 iflib_txq_t txq; 3952 int err, qidx; 3953 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3954 3955 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3956 DBG_COUNTER_INC(tx_frees); 3957 m_freem(m); 3958 return (ENETDOWN); 3959 } 3960 3961 MPASS(m->m_nextpkt == NULL); 3962 /* ALTQ-enabled interfaces always use queue 0. */ 3963 qidx = 0; 3964 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3965 qidx = QIDX(ctx, m); 3966 /* 3967 * XXX calculate buf_ring based on flowid (divvy up bits?) 3968 */ 3969 txq = &ctx->ifc_txqs[qidx]; 3970 3971 #ifdef DRIVER_BACKPRESSURE 3972 if (txq->ift_closed) { 3973 while (m != NULL) { 3974 next = m->m_nextpkt; 3975 m->m_nextpkt = NULL; 3976 m_freem(m); 3977 DBG_COUNTER_INC(tx_frees); 3978 m = next; 3979 } 3980 return (ENOBUFS); 3981 } 3982 #endif 3983 #ifdef notyet 3984 qidx = count = 0; 3985 mp = marr; 3986 next = m; 3987 do { 3988 count++; 3989 next = next->m_nextpkt; 3990 } while (next != NULL); 3991 3992 if (count > nitems(marr)) 3993 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3994 /* XXX check nextpkt */ 3995 m_freem(m); 3996 /* XXX simplify for now */ 3997 DBG_COUNTER_INC(tx_frees); 3998 return (ENOBUFS); 3999 } 4000 for (next = m, i = 0; next != NULL; i++) { 4001 mp[i] = next; 4002 next = next->m_nextpkt; 4003 mp[i]->m_nextpkt = NULL; 4004 } 4005 #endif 4006 DBG_COUNTER_INC(tx_seen); 4007 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4008 4009 if (abdicate) 4010 GROUPTASK_ENQUEUE(&txq->ift_task); 4011 if (err) { 4012 if (!abdicate) 4013 GROUPTASK_ENQUEUE(&txq->ift_task); 4014 /* support forthcoming later */ 4015 #ifdef DRIVER_BACKPRESSURE 4016 txq->ift_closed = TRUE; 4017 #endif 4018 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4019 m_freem(m); 4020 DBG_COUNTER_INC(tx_frees); 4021 } 4022 4023 return (err); 4024 } 4025 4026 #ifdef ALTQ 4027 /* 4028 * The overall approach to integrating iflib with ALTQ is to continue to use 4029 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4030 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4031 * is redundant/unnecessary, but doing so minimizes the amount of 4032 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4033 * redundantly queueing to an intermediate mp_ring is swamped by the 4034 * performance limitations inherent in using ALTQ. 4035 * 4036 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4037 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4038 * given interface. If ALTQ is enabled for an interface, then all 4039 * transmitted packets for that interface will be submitted to the ALTQ 4040 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4041 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4042 * update stats that the iflib machinery handles, and which is sensitve to 4043 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4044 * will be installed as the start routine for use by ALTQ facilities that 4045 * need to trigger queue drains on a scheduled basis. 4046 * 4047 */ 4048 static void 4049 iflib_altq_if_start(if_t ifp) 4050 { 4051 struct ifaltq *ifq = &ifp->if_snd; 4052 struct mbuf *m; 4053 4054 IFQ_LOCK(ifq); 4055 IFQ_DEQUEUE_NOLOCK(ifq, m); 4056 while (m != NULL) { 4057 iflib_if_transmit(ifp, m); 4058 IFQ_DEQUEUE_NOLOCK(ifq, m); 4059 } 4060 IFQ_UNLOCK(ifq); 4061 } 4062 4063 static int 4064 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4065 { 4066 int err; 4067 4068 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4069 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4070 if (err == 0) 4071 iflib_altq_if_start(ifp); 4072 } else 4073 err = iflib_if_transmit(ifp, m); 4074 4075 return (err); 4076 } 4077 #endif /* ALTQ */ 4078 4079 static void 4080 iflib_if_qflush(if_t ifp) 4081 { 4082 if_ctx_t ctx = if_getsoftc(ifp); 4083 iflib_txq_t txq = ctx->ifc_txqs; 4084 int i; 4085 4086 STATE_LOCK(ctx); 4087 ctx->ifc_flags |= IFC_QFLUSH; 4088 STATE_UNLOCK(ctx); 4089 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4090 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4091 iflib_txq_check_drain(txq, 0); 4092 STATE_LOCK(ctx); 4093 ctx->ifc_flags &= ~IFC_QFLUSH; 4094 STATE_UNLOCK(ctx); 4095 4096 /* 4097 * When ALTQ is enabled, this will also take care of purging the 4098 * ALTQ queue(s). 4099 */ 4100 if_qflush(ifp); 4101 } 4102 4103 4104 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4105 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4106 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4107 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4108 4109 static int 4110 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4111 { 4112 if_ctx_t ctx = if_getsoftc(ifp); 4113 struct ifreq *ifr = (struct ifreq *)data; 4114 #if defined(INET) || defined(INET6) 4115 struct ifaddr *ifa = (struct ifaddr *)data; 4116 #endif 4117 bool avoid_reset = false; 4118 int err = 0, reinit = 0, bits; 4119 4120 switch (command) { 4121 case SIOCSIFADDR: 4122 #ifdef INET 4123 if (ifa->ifa_addr->sa_family == AF_INET) 4124 avoid_reset = true; 4125 #endif 4126 #ifdef INET6 4127 if (ifa->ifa_addr->sa_family == AF_INET6) 4128 avoid_reset = true; 4129 #endif 4130 /* 4131 ** Calling init results in link renegotiation, 4132 ** so we avoid doing it when possible. 4133 */ 4134 if (avoid_reset) { 4135 if_setflagbits(ifp, IFF_UP,0); 4136 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4137 reinit = 1; 4138 #ifdef INET 4139 if (!(if_getflags(ifp) & IFF_NOARP)) 4140 arp_ifinit(ifp, ifa); 4141 #endif 4142 } else 4143 err = ether_ioctl(ifp, command, data); 4144 break; 4145 case SIOCSIFMTU: 4146 CTX_LOCK(ctx); 4147 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4148 CTX_UNLOCK(ctx); 4149 break; 4150 } 4151 bits = if_getdrvflags(ifp); 4152 /* stop the driver and free any clusters before proceeding */ 4153 iflib_stop(ctx); 4154 4155 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4156 STATE_LOCK(ctx); 4157 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4158 ctx->ifc_flags |= IFC_MULTISEG; 4159 else 4160 ctx->ifc_flags &= ~IFC_MULTISEG; 4161 STATE_UNLOCK(ctx); 4162 err = if_setmtu(ifp, ifr->ifr_mtu); 4163 } 4164 iflib_init_locked(ctx); 4165 STATE_LOCK(ctx); 4166 if_setdrvflags(ifp, bits); 4167 STATE_UNLOCK(ctx); 4168 CTX_UNLOCK(ctx); 4169 break; 4170 case SIOCSIFFLAGS: 4171 CTX_LOCK(ctx); 4172 if (if_getflags(ifp) & IFF_UP) { 4173 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4174 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4175 (IFF_PROMISC | IFF_ALLMULTI)) { 4176 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4177 } 4178 } else 4179 reinit = 1; 4180 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4181 iflib_stop(ctx); 4182 } 4183 ctx->ifc_if_flags = if_getflags(ifp); 4184 CTX_UNLOCK(ctx); 4185 break; 4186 case SIOCADDMULTI: 4187 case SIOCDELMULTI: 4188 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4189 CTX_LOCK(ctx); 4190 IFDI_INTR_DISABLE(ctx); 4191 IFDI_MULTI_SET(ctx); 4192 IFDI_INTR_ENABLE(ctx); 4193 CTX_UNLOCK(ctx); 4194 } 4195 break; 4196 case SIOCSIFMEDIA: 4197 CTX_LOCK(ctx); 4198 IFDI_MEDIA_SET(ctx); 4199 CTX_UNLOCK(ctx); 4200 /* FALLTHROUGH */ 4201 case SIOCGIFMEDIA: 4202 case SIOCGIFXMEDIA: 4203 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4204 break; 4205 case SIOCGI2C: 4206 { 4207 struct ifi2creq i2c; 4208 4209 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4210 if (err != 0) 4211 break; 4212 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4213 err = EINVAL; 4214 break; 4215 } 4216 if (i2c.len > sizeof(i2c.data)) { 4217 err = EINVAL; 4218 break; 4219 } 4220 4221 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4222 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4223 sizeof(i2c)); 4224 break; 4225 } 4226 case SIOCSIFCAP: 4227 { 4228 int mask, setmask, oldmask; 4229 4230 oldmask = if_getcapenable(ifp); 4231 mask = ifr->ifr_reqcap ^ oldmask; 4232 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4233 setmask = 0; 4234 #ifdef TCP_OFFLOAD 4235 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4236 #endif 4237 setmask |= (mask & IFCAP_FLAGS); 4238 setmask |= (mask & IFCAP_WOL); 4239 4240 /* 4241 * If any RX csum has changed, change all the ones that 4242 * are supported by the driver. 4243 */ 4244 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4245 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4246 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4247 } 4248 4249 /* 4250 * want to ensure that traffic has stopped before we change any of the flags 4251 */ 4252 if (setmask) { 4253 CTX_LOCK(ctx); 4254 bits = if_getdrvflags(ifp); 4255 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4256 iflib_stop(ctx); 4257 STATE_LOCK(ctx); 4258 if_togglecapenable(ifp, setmask); 4259 STATE_UNLOCK(ctx); 4260 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4261 iflib_init_locked(ctx); 4262 STATE_LOCK(ctx); 4263 if_setdrvflags(ifp, bits); 4264 STATE_UNLOCK(ctx); 4265 CTX_UNLOCK(ctx); 4266 } 4267 if_vlancap(ifp); 4268 break; 4269 } 4270 case SIOCGPRIVATE_0: 4271 case SIOCSDRVSPEC: 4272 case SIOCGDRVSPEC: 4273 CTX_LOCK(ctx); 4274 err = IFDI_PRIV_IOCTL(ctx, command, data); 4275 CTX_UNLOCK(ctx); 4276 break; 4277 default: 4278 err = ether_ioctl(ifp, command, data); 4279 break; 4280 } 4281 if (reinit) 4282 iflib_if_init(ctx); 4283 return (err); 4284 } 4285 4286 static uint64_t 4287 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4288 { 4289 if_ctx_t ctx = if_getsoftc(ifp); 4290 4291 return (IFDI_GET_COUNTER(ctx, cnt)); 4292 } 4293 4294 /********************************************************************* 4295 * 4296 * OTHER FUNCTIONS EXPORTED TO THE STACK 4297 * 4298 **********************************************************************/ 4299 4300 static void 4301 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4302 { 4303 if_ctx_t ctx = if_getsoftc(ifp); 4304 4305 if ((void *)ctx != arg) 4306 return; 4307 4308 if ((vtag == 0) || (vtag > 4095)) 4309 return; 4310 4311 if (iflib_in_detach(ctx)) 4312 return; 4313 4314 CTX_LOCK(ctx); 4315 /* Driver may need all untagged packets to be flushed */ 4316 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4317 iflib_stop(ctx); 4318 IFDI_VLAN_REGISTER(ctx, vtag); 4319 /* Re-init to load the changes, if required */ 4320 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4321 iflib_init_locked(ctx); 4322 CTX_UNLOCK(ctx); 4323 } 4324 4325 static void 4326 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4327 { 4328 if_ctx_t ctx = if_getsoftc(ifp); 4329 4330 if ((void *)ctx != arg) 4331 return; 4332 4333 if ((vtag == 0) || (vtag > 4095)) 4334 return; 4335 4336 CTX_LOCK(ctx); 4337 /* Driver may need all tagged packets to be flushed */ 4338 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4339 iflib_stop(ctx); 4340 IFDI_VLAN_UNREGISTER(ctx, vtag); 4341 /* Re-init to load the changes, if required */ 4342 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4343 iflib_init_locked(ctx); 4344 CTX_UNLOCK(ctx); 4345 } 4346 4347 static void 4348 iflib_led_func(void *arg, int onoff) 4349 { 4350 if_ctx_t ctx = arg; 4351 4352 CTX_LOCK(ctx); 4353 IFDI_LED_FUNC(ctx, onoff); 4354 CTX_UNLOCK(ctx); 4355 } 4356 4357 /********************************************************************* 4358 * 4359 * BUS FUNCTION DEFINITIONS 4360 * 4361 **********************************************************************/ 4362 4363 int 4364 iflib_device_probe(device_t dev) 4365 { 4366 const pci_vendor_info_t *ent; 4367 if_shared_ctx_t sctx; 4368 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4369 uint16_t pci_vendor_id; 4370 4371 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4372 return (ENOTSUP); 4373 4374 pci_vendor_id = pci_get_vendor(dev); 4375 pci_device_id = pci_get_device(dev); 4376 pci_subvendor_id = pci_get_subvendor(dev); 4377 pci_subdevice_id = pci_get_subdevice(dev); 4378 pci_rev_id = pci_get_revid(dev); 4379 if (sctx->isc_parse_devinfo != NULL) 4380 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4381 4382 ent = sctx->isc_vendor_info; 4383 while (ent->pvi_vendor_id != 0) { 4384 if (pci_vendor_id != ent->pvi_vendor_id) { 4385 ent++; 4386 continue; 4387 } 4388 if ((pci_device_id == ent->pvi_device_id) && 4389 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4390 (ent->pvi_subvendor_id == 0)) && 4391 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4392 (ent->pvi_subdevice_id == 0)) && 4393 ((pci_rev_id == ent->pvi_rev_id) || 4394 (ent->pvi_rev_id == 0))) { 4395 4396 device_set_desc_copy(dev, ent->pvi_name); 4397 /* this needs to be changed to zero if the bus probing code 4398 * ever stops re-probing on best match because the sctx 4399 * may have its values over written by register calls 4400 * in subsequent probes 4401 */ 4402 return (BUS_PROBE_DEFAULT); 4403 } 4404 ent++; 4405 } 4406 return (ENXIO); 4407 } 4408 4409 int 4410 iflib_device_probe_vendor(device_t dev) 4411 { 4412 int probe; 4413 4414 probe = iflib_device_probe(dev); 4415 if (probe == BUS_PROBE_DEFAULT) 4416 return (BUS_PROBE_VENDOR); 4417 else 4418 return (probe); 4419 } 4420 4421 static void 4422 iflib_reset_qvalues(if_ctx_t ctx) 4423 { 4424 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4425 if_shared_ctx_t sctx = ctx->ifc_sctx; 4426 device_t dev = ctx->ifc_dev; 4427 int i; 4428 4429 if (ctx->ifc_sysctl_ntxqs != 0) 4430 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4431 if (ctx->ifc_sysctl_nrxqs != 0) 4432 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4433 4434 for (i = 0; i < sctx->isc_ntxqs; i++) { 4435 if (ctx->ifc_sysctl_ntxds[i] != 0) 4436 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4437 else 4438 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4439 } 4440 4441 for (i = 0; i < sctx->isc_nrxqs; i++) { 4442 if (ctx->ifc_sysctl_nrxds[i] != 0) 4443 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4444 else 4445 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4446 } 4447 4448 for (i = 0; i < sctx->isc_nrxqs; i++) { 4449 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4450 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4451 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4452 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4453 } 4454 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4455 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4456 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4457 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4458 } 4459 if (!powerof2(scctx->isc_nrxd[i])) { 4460 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4461 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4462 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4463 } 4464 } 4465 4466 for (i = 0; i < sctx->isc_ntxqs; i++) { 4467 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4468 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4469 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4470 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4471 } 4472 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4473 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4474 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4475 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4476 } 4477 if (!powerof2(scctx->isc_ntxd[i])) { 4478 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4479 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4480 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4481 } 4482 } 4483 } 4484 4485 static void 4486 iflib_add_pfil(if_ctx_t ctx) 4487 { 4488 struct pfil_head *pfil; 4489 struct pfil_head_args pa; 4490 iflib_rxq_t rxq; 4491 int i; 4492 4493 pa.pa_version = PFIL_VERSION; 4494 pa.pa_flags = PFIL_IN; 4495 pa.pa_type = PFIL_TYPE_ETHERNET; 4496 pa.pa_headname = ctx->ifc_ifp->if_xname; 4497 pfil = pfil_head_register(&pa); 4498 4499 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4500 rxq->pfil = pfil; 4501 } 4502 } 4503 4504 static void 4505 iflib_rem_pfil(if_ctx_t ctx) 4506 { 4507 struct pfil_head *pfil; 4508 iflib_rxq_t rxq; 4509 int i; 4510 4511 rxq = ctx->ifc_rxqs; 4512 pfil = rxq->pfil; 4513 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4514 rxq->pfil = NULL; 4515 } 4516 pfil_head_unregister(pfil); 4517 } 4518 4519 static uint16_t 4520 get_ctx_core_offset(if_ctx_t ctx) 4521 { 4522 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4523 struct cpu_offset *op; 4524 uint16_t qc; 4525 uint16_t ret = ctx->ifc_sysctl_core_offset; 4526 4527 if (ret != CORE_OFFSET_UNSPECIFIED) 4528 return (ret); 4529 4530 if (ctx->ifc_sysctl_separate_txrx) 4531 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4532 else 4533 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4534 4535 mtx_lock(&cpu_offset_mtx); 4536 SLIST_FOREACH(op, &cpu_offsets, entries) { 4537 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4538 ret = op->offset; 4539 op->offset += qc; 4540 MPASS(op->refcount < UINT_MAX); 4541 op->refcount++; 4542 break; 4543 } 4544 } 4545 if (ret == CORE_OFFSET_UNSPECIFIED) { 4546 ret = 0; 4547 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4548 M_NOWAIT | M_ZERO); 4549 if (op == NULL) { 4550 device_printf(ctx->ifc_dev, 4551 "allocation for cpu offset failed.\n"); 4552 } else { 4553 op->offset = qc; 4554 op->refcount = 1; 4555 CPU_COPY(&ctx->ifc_cpus, &op->set); 4556 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4557 } 4558 } 4559 mtx_unlock(&cpu_offset_mtx); 4560 4561 return (ret); 4562 } 4563 4564 static void 4565 unref_ctx_core_offset(if_ctx_t ctx) 4566 { 4567 struct cpu_offset *op, *top; 4568 4569 mtx_lock(&cpu_offset_mtx); 4570 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4571 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4572 MPASS(op->refcount > 0); 4573 op->refcount--; 4574 if (op->refcount == 0) { 4575 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4576 free(op, M_IFLIB); 4577 } 4578 break; 4579 } 4580 } 4581 mtx_unlock(&cpu_offset_mtx); 4582 } 4583 4584 int 4585 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4586 { 4587 if_ctx_t ctx; 4588 if_t ifp; 4589 if_softc_ctx_t scctx; 4590 kobjop_desc_t kobj_desc; 4591 kobj_method_t *kobj_method; 4592 int err, msix, rid; 4593 uint16_t main_rxq, main_txq; 4594 4595 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4596 4597 if (sc == NULL) { 4598 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4599 device_set_softc(dev, ctx); 4600 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4601 } 4602 4603 ctx->ifc_sctx = sctx; 4604 ctx->ifc_dev = dev; 4605 ctx->ifc_softc = sc; 4606 4607 if ((err = iflib_register(ctx)) != 0) { 4608 device_printf(dev, "iflib_register failed %d\n", err); 4609 goto fail_ctx_free; 4610 } 4611 iflib_add_device_sysctl_pre(ctx); 4612 4613 scctx = &ctx->ifc_softc_ctx; 4614 ifp = ctx->ifc_ifp; 4615 4616 iflib_reset_qvalues(ctx); 4617 CTX_LOCK(ctx); 4618 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4619 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4620 goto fail_unlock; 4621 } 4622 _iflib_pre_assert(scctx); 4623 ctx->ifc_txrx = *scctx->isc_txrx; 4624 4625 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4626 ctx->ifc_mediap = scctx->isc_media; 4627 4628 #ifdef INVARIANTS 4629 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4630 MPASS(scctx->isc_tx_csum_flags); 4631 #endif 4632 4633 if_setcapabilities(ifp, 4634 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4635 if_setcapenable(ifp, 4636 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4637 4638 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4639 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4640 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4641 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4642 4643 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4644 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4645 4646 /* XXX change for per-queue sizes */ 4647 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4648 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4649 4650 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4651 MAX_SINGLE_PACKET_FRACTION) 4652 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4653 MAX_SINGLE_PACKET_FRACTION); 4654 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4655 MAX_SINGLE_PACKET_FRACTION) 4656 scctx->isc_tx_tso_segments_max = max(1, 4657 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4658 4659 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4660 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4661 /* 4662 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4663 * but some MACs do. 4664 */ 4665 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4666 IP_MAXPACKET)); 4667 /* 4668 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4669 * into account. In the worst case, each of these calls will 4670 * add another mbuf and, thus, the requirement for another DMA 4671 * segment. So for best performance, it doesn't make sense to 4672 * advertize a maximum of TSO segments that typically will 4673 * require defragmentation in iflib_encap(). 4674 */ 4675 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4676 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4677 } 4678 if (scctx->isc_rss_table_size == 0) 4679 scctx->isc_rss_table_size = 64; 4680 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4681 4682 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4683 /* XXX format name */ 4684 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4685 NULL, NULL, "admin"); 4686 4687 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4688 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4689 device_printf(dev, "Unable to fetch CPU list\n"); 4690 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4691 } 4692 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4693 4694 /* 4695 ** Now set up MSI or MSI-X, should return us the number of supported 4696 ** vectors (will be 1 for a legacy interrupt and MSI). 4697 */ 4698 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4699 msix = scctx->isc_vectors; 4700 } else if (scctx->isc_msix_bar != 0) 4701 /* 4702 * The simple fact that isc_msix_bar is not 0 does not mean we 4703 * we have a good value there that is known to work. 4704 */ 4705 msix = iflib_msix_init(ctx); 4706 else { 4707 scctx->isc_vectors = 1; 4708 scctx->isc_ntxqsets = 1; 4709 scctx->isc_nrxqsets = 1; 4710 scctx->isc_intr = IFLIB_INTR_LEGACY; 4711 msix = 0; 4712 } 4713 /* Get memory for the station queues */ 4714 if ((err = iflib_queues_alloc(ctx))) { 4715 device_printf(dev, "Unable to allocate queue memory\n"); 4716 goto fail_intr_free; 4717 } 4718 4719 if ((err = iflib_qset_structures_setup(ctx))) 4720 goto fail_queues; 4721 4722 /* 4723 * Now that we know how many queues there are, get the core offset. 4724 */ 4725 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4726 4727 if (msix > 1) { 4728 /* 4729 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4730 * aren't the default NULL implementation. 4731 */ 4732 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4733 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4734 kobj_desc); 4735 if (kobj_method == &kobj_desc->deflt) { 4736 device_printf(dev, 4737 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4738 err = EOPNOTSUPP; 4739 goto fail_queues; 4740 } 4741 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4742 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4743 kobj_desc); 4744 if (kobj_method == &kobj_desc->deflt) { 4745 device_printf(dev, 4746 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4747 err = EOPNOTSUPP; 4748 goto fail_queues; 4749 } 4750 4751 /* 4752 * Assign the MSI-X vectors. 4753 * Note that the default NULL ifdi_msix_intr_assign method will 4754 * fail here, too. 4755 */ 4756 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4757 if (err != 0) { 4758 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4759 err); 4760 goto fail_queues; 4761 } 4762 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4763 rid = 0; 4764 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4765 MPASS(msix == 1); 4766 rid = 1; 4767 } 4768 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4769 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4770 goto fail_queues; 4771 } 4772 } else { 4773 device_printf(dev, 4774 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4775 err = ENODEV; 4776 goto fail_intr_free; 4777 } 4778 4779 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4780 4781 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4782 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4783 goto fail_detach; 4784 } 4785 4786 /* 4787 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4788 * This must appear after the call to ether_ifattach() because 4789 * ether_ifattach() sets if_hdrlen to the default value. 4790 */ 4791 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4792 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4793 4794 if ((err = iflib_netmap_attach(ctx))) { 4795 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4796 goto fail_detach; 4797 } 4798 *ctxp = ctx; 4799 4800 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4801 4802 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4803 iflib_add_device_sysctl_post(ctx); 4804 iflib_add_pfil(ctx); 4805 ctx->ifc_flags |= IFC_INIT_DONE; 4806 CTX_UNLOCK(ctx); 4807 4808 return (0); 4809 4810 fail_detach: 4811 ether_ifdetach(ctx->ifc_ifp); 4812 fail_intr_free: 4813 iflib_free_intr_mem(ctx); 4814 fail_queues: 4815 iflib_tx_structures_free(ctx); 4816 iflib_rx_structures_free(ctx); 4817 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4818 IFDI_DETACH(ctx); 4819 fail_unlock: 4820 CTX_UNLOCK(ctx); 4821 iflib_deregister(ctx); 4822 fail_ctx_free: 4823 device_set_softc(ctx->ifc_dev, NULL); 4824 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4825 free(ctx->ifc_softc, M_IFLIB); 4826 free(ctx, M_IFLIB); 4827 return (err); 4828 } 4829 4830 int 4831 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4832 struct iflib_cloneattach_ctx *clctx) 4833 { 4834 int err; 4835 if_ctx_t ctx; 4836 if_t ifp; 4837 if_softc_ctx_t scctx; 4838 int i; 4839 void *sc; 4840 uint16_t main_txq; 4841 uint16_t main_rxq; 4842 4843 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4844 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4845 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4846 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4847 ctx->ifc_flags |= IFC_PSEUDO; 4848 4849 ctx->ifc_sctx = sctx; 4850 ctx->ifc_softc = sc; 4851 ctx->ifc_dev = dev; 4852 4853 if ((err = iflib_register(ctx)) != 0) { 4854 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4855 goto fail_ctx_free; 4856 } 4857 iflib_add_device_sysctl_pre(ctx); 4858 4859 scctx = &ctx->ifc_softc_ctx; 4860 ifp = ctx->ifc_ifp; 4861 4862 iflib_reset_qvalues(ctx); 4863 CTX_LOCK(ctx); 4864 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4865 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4866 goto fail_unlock; 4867 } 4868 if (sctx->isc_flags & IFLIB_GEN_MAC) 4869 ether_gen_addr(ifp, &ctx->ifc_mac); 4870 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4871 clctx->cc_params)) != 0) { 4872 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4873 goto fail_unlock; 4874 } 4875 #ifdef INVARIANTS 4876 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4877 MPASS(scctx->isc_tx_csum_flags); 4878 #endif 4879 4880 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4881 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4882 4883 ifp->if_flags |= IFF_NOGROUP; 4884 if (sctx->isc_flags & IFLIB_PSEUDO) { 4885 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4886 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4887 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 4888 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4889 } else { 4890 if_attach(ctx->ifc_ifp); 4891 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 4892 } 4893 4894 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4895 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4896 goto fail_detach; 4897 } 4898 *ctxp = ctx; 4899 4900 /* 4901 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4902 * This must appear after the call to ether_ifattach() because 4903 * ether_ifattach() sets if_hdrlen to the default value. 4904 */ 4905 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4906 if_setifheaderlen(ifp, 4907 sizeof(struct ether_vlan_header)); 4908 4909 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4910 iflib_add_device_sysctl_post(ctx); 4911 ctx->ifc_flags |= IFC_INIT_DONE; 4912 CTX_UNLOCK(ctx); 4913 return (0); 4914 } 4915 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4916 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4917 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4918 4919 _iflib_pre_assert(scctx); 4920 ctx->ifc_txrx = *scctx->isc_txrx; 4921 4922 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4923 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4924 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4925 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4926 4927 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4928 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4929 4930 /* XXX change for per-queue sizes */ 4931 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4932 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4933 4934 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4935 MAX_SINGLE_PACKET_FRACTION) 4936 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4937 MAX_SINGLE_PACKET_FRACTION); 4938 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4939 MAX_SINGLE_PACKET_FRACTION) 4940 scctx->isc_tx_tso_segments_max = max(1, 4941 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4942 4943 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4944 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4945 /* 4946 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4947 * but some MACs do. 4948 */ 4949 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4950 IP_MAXPACKET)); 4951 /* 4952 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4953 * into account. In the worst case, each of these calls will 4954 * add another mbuf and, thus, the requirement for another DMA 4955 * segment. So for best performance, it doesn't make sense to 4956 * advertize a maximum of TSO segments that typically will 4957 * require defragmentation in iflib_encap(). 4958 */ 4959 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4960 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4961 } 4962 if (scctx->isc_rss_table_size == 0) 4963 scctx->isc_rss_table_size = 64; 4964 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4965 4966 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4967 /* XXX format name */ 4968 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4969 NULL, NULL, "admin"); 4970 4971 /* XXX --- can support > 1 -- but keep it simple for now */ 4972 scctx->isc_intr = IFLIB_INTR_LEGACY; 4973 4974 /* Get memory for the station queues */ 4975 if ((err = iflib_queues_alloc(ctx))) { 4976 device_printf(dev, "Unable to allocate queue memory\n"); 4977 goto fail_iflib_detach; 4978 } 4979 4980 if ((err = iflib_qset_structures_setup(ctx))) { 4981 device_printf(dev, "qset structure setup failed %d\n", err); 4982 goto fail_queues; 4983 } 4984 4985 /* 4986 * XXX What if anything do we want to do about interrupts? 4987 */ 4988 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4989 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4990 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4991 goto fail_detach; 4992 } 4993 4994 /* 4995 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4996 * This must appear after the call to ether_ifattach() because 4997 * ether_ifattach() sets if_hdrlen to the default value. 4998 */ 4999 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5000 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5001 5002 /* XXX handle more than one queue */ 5003 for (i = 0; i < scctx->isc_nrxqsets; i++) 5004 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5005 5006 *ctxp = ctx; 5007 5008 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5009 iflib_add_device_sysctl_post(ctx); 5010 ctx->ifc_flags |= IFC_INIT_DONE; 5011 CTX_UNLOCK(ctx); 5012 5013 return (0); 5014 fail_detach: 5015 ether_ifdetach(ctx->ifc_ifp); 5016 fail_queues: 5017 iflib_tx_structures_free(ctx); 5018 iflib_rx_structures_free(ctx); 5019 fail_iflib_detach: 5020 IFDI_DETACH(ctx); 5021 fail_unlock: 5022 CTX_UNLOCK(ctx); 5023 iflib_deregister(ctx); 5024 fail_ctx_free: 5025 free(ctx->ifc_softc, M_IFLIB); 5026 free(ctx, M_IFLIB); 5027 return (err); 5028 } 5029 5030 int 5031 iflib_pseudo_deregister(if_ctx_t ctx) 5032 { 5033 if_t ifp = ctx->ifc_ifp; 5034 if_shared_ctx_t sctx = ctx->ifc_sctx; 5035 iflib_txq_t txq; 5036 iflib_rxq_t rxq; 5037 int i, j; 5038 struct taskqgroup *tqg; 5039 iflib_fl_t fl; 5040 5041 /* Unregister VLAN event handlers early */ 5042 iflib_unregister_vlan_handlers(ctx); 5043 5044 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5045 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5046 bpfdetach(ifp); 5047 if_detach(ifp); 5048 } else { 5049 ether_ifdetach(ifp); 5050 } 5051 /* XXX drain any dependent tasks */ 5052 tqg = qgroup_if_io_tqg; 5053 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5054 callout_drain(&txq->ift_timer); 5055 if (txq->ift_task.gt_uniq != NULL) 5056 taskqgroup_detach(tqg, &txq->ift_task); 5057 } 5058 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5059 callout_drain(&rxq->ifr_watchdog); 5060 if (rxq->ifr_task.gt_uniq != NULL) 5061 taskqgroup_detach(tqg, &rxq->ifr_task); 5062 5063 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5064 free(fl->ifl_rx_bitmap, M_IFLIB); 5065 } 5066 tqg = qgroup_if_config_tqg; 5067 if (ctx->ifc_admin_task.gt_uniq != NULL) 5068 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5069 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5070 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5071 5072 iflib_tx_structures_free(ctx); 5073 iflib_rx_structures_free(ctx); 5074 5075 iflib_deregister(ctx); 5076 5077 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5078 free(ctx->ifc_softc, M_IFLIB); 5079 free(ctx, M_IFLIB); 5080 return (0); 5081 } 5082 5083 int 5084 iflib_device_attach(device_t dev) 5085 { 5086 if_ctx_t ctx; 5087 if_shared_ctx_t sctx; 5088 5089 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5090 return (ENOTSUP); 5091 5092 pci_enable_busmaster(dev); 5093 5094 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5095 } 5096 5097 int 5098 iflib_device_deregister(if_ctx_t ctx) 5099 { 5100 if_t ifp = ctx->ifc_ifp; 5101 iflib_txq_t txq; 5102 iflib_rxq_t rxq; 5103 device_t dev = ctx->ifc_dev; 5104 int i, j; 5105 struct taskqgroup *tqg; 5106 iflib_fl_t fl; 5107 5108 /* Make sure VLANS are not using driver */ 5109 if (if_vlantrunkinuse(ifp)) { 5110 device_printf(dev, "Vlan in use, detach first\n"); 5111 return (EBUSY); 5112 } 5113 #ifdef PCI_IOV 5114 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5115 device_printf(dev, "SR-IOV in use; detach first.\n"); 5116 return (EBUSY); 5117 } 5118 #endif 5119 5120 STATE_LOCK(ctx); 5121 ctx->ifc_flags |= IFC_IN_DETACH; 5122 STATE_UNLOCK(ctx); 5123 5124 /* Unregister VLAN handlers before calling iflib_stop() */ 5125 iflib_unregister_vlan_handlers(ctx); 5126 5127 iflib_netmap_detach(ifp); 5128 ether_ifdetach(ifp); 5129 5130 CTX_LOCK(ctx); 5131 iflib_stop(ctx); 5132 CTX_UNLOCK(ctx); 5133 5134 iflib_rem_pfil(ctx); 5135 if (ctx->ifc_led_dev != NULL) 5136 led_destroy(ctx->ifc_led_dev); 5137 /* XXX drain any dependent tasks */ 5138 tqg = qgroup_if_io_tqg; 5139 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5140 callout_drain(&txq->ift_timer); 5141 if (txq->ift_task.gt_uniq != NULL) 5142 taskqgroup_detach(tqg, &txq->ift_task); 5143 } 5144 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5145 if (rxq->ifr_task.gt_uniq != NULL) 5146 taskqgroup_detach(tqg, &rxq->ifr_task); 5147 5148 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5149 free(fl->ifl_rx_bitmap, M_IFLIB); 5150 } 5151 tqg = qgroup_if_config_tqg; 5152 if (ctx->ifc_admin_task.gt_uniq != NULL) 5153 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5154 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5155 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5156 CTX_LOCK(ctx); 5157 IFDI_DETACH(ctx); 5158 CTX_UNLOCK(ctx); 5159 5160 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5161 iflib_free_intr_mem(ctx); 5162 5163 bus_generic_detach(dev); 5164 5165 iflib_tx_structures_free(ctx); 5166 iflib_rx_structures_free(ctx); 5167 5168 iflib_deregister(ctx); 5169 5170 device_set_softc(ctx->ifc_dev, NULL); 5171 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5172 free(ctx->ifc_softc, M_IFLIB); 5173 unref_ctx_core_offset(ctx); 5174 free(ctx, M_IFLIB); 5175 return (0); 5176 } 5177 5178 static void 5179 iflib_free_intr_mem(if_ctx_t ctx) 5180 { 5181 5182 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5183 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5184 } 5185 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5186 pci_release_msi(ctx->ifc_dev); 5187 } 5188 if (ctx->ifc_msix_mem != NULL) { 5189 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5190 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5191 ctx->ifc_msix_mem = NULL; 5192 } 5193 } 5194 5195 int 5196 iflib_device_detach(device_t dev) 5197 { 5198 if_ctx_t ctx = device_get_softc(dev); 5199 5200 return (iflib_device_deregister(ctx)); 5201 } 5202 5203 int 5204 iflib_device_suspend(device_t dev) 5205 { 5206 if_ctx_t ctx = device_get_softc(dev); 5207 5208 CTX_LOCK(ctx); 5209 IFDI_SUSPEND(ctx); 5210 CTX_UNLOCK(ctx); 5211 5212 return bus_generic_suspend(dev); 5213 } 5214 int 5215 iflib_device_shutdown(device_t dev) 5216 { 5217 if_ctx_t ctx = device_get_softc(dev); 5218 5219 CTX_LOCK(ctx); 5220 IFDI_SHUTDOWN(ctx); 5221 CTX_UNLOCK(ctx); 5222 5223 return bus_generic_suspend(dev); 5224 } 5225 5226 5227 int 5228 iflib_device_resume(device_t dev) 5229 { 5230 if_ctx_t ctx = device_get_softc(dev); 5231 iflib_txq_t txq = ctx->ifc_txqs; 5232 5233 CTX_LOCK(ctx); 5234 IFDI_RESUME(ctx); 5235 iflib_if_init_locked(ctx); 5236 CTX_UNLOCK(ctx); 5237 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5238 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5239 5240 return (bus_generic_resume(dev)); 5241 } 5242 5243 int 5244 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5245 { 5246 int error; 5247 if_ctx_t ctx = device_get_softc(dev); 5248 5249 CTX_LOCK(ctx); 5250 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5251 CTX_UNLOCK(ctx); 5252 5253 return (error); 5254 } 5255 5256 void 5257 iflib_device_iov_uninit(device_t dev) 5258 { 5259 if_ctx_t ctx = device_get_softc(dev); 5260 5261 CTX_LOCK(ctx); 5262 IFDI_IOV_UNINIT(ctx); 5263 CTX_UNLOCK(ctx); 5264 } 5265 5266 int 5267 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5268 { 5269 int error; 5270 if_ctx_t ctx = device_get_softc(dev); 5271 5272 CTX_LOCK(ctx); 5273 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5274 CTX_UNLOCK(ctx); 5275 5276 return (error); 5277 } 5278 5279 /********************************************************************* 5280 * 5281 * MODULE FUNCTION DEFINITIONS 5282 * 5283 **********************************************************************/ 5284 5285 /* 5286 * - Start a fast taskqueue thread for each core 5287 * - Start a taskqueue for control operations 5288 */ 5289 static int 5290 iflib_module_init(void) 5291 { 5292 return (0); 5293 } 5294 5295 static int 5296 iflib_module_event_handler(module_t mod, int what, void *arg) 5297 { 5298 int err; 5299 5300 switch (what) { 5301 case MOD_LOAD: 5302 if ((err = iflib_module_init()) != 0) 5303 return (err); 5304 break; 5305 case MOD_UNLOAD: 5306 return (EBUSY); 5307 default: 5308 return (EOPNOTSUPP); 5309 } 5310 5311 return (0); 5312 } 5313 5314 /********************************************************************* 5315 * 5316 * PUBLIC FUNCTION DEFINITIONS 5317 * ordered as in iflib.h 5318 * 5319 **********************************************************************/ 5320 5321 5322 static void 5323 _iflib_assert(if_shared_ctx_t sctx) 5324 { 5325 int i; 5326 5327 MPASS(sctx->isc_tx_maxsize); 5328 MPASS(sctx->isc_tx_maxsegsize); 5329 5330 MPASS(sctx->isc_rx_maxsize); 5331 MPASS(sctx->isc_rx_nsegments); 5332 MPASS(sctx->isc_rx_maxsegsize); 5333 5334 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5335 for (i = 0; i < sctx->isc_nrxqs; i++) { 5336 MPASS(sctx->isc_nrxd_min[i]); 5337 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5338 MPASS(sctx->isc_nrxd_max[i]); 5339 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5340 MPASS(sctx->isc_nrxd_default[i]); 5341 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5342 } 5343 5344 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5345 for (i = 0; i < sctx->isc_ntxqs; i++) { 5346 MPASS(sctx->isc_ntxd_min[i]); 5347 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5348 MPASS(sctx->isc_ntxd_max[i]); 5349 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5350 MPASS(sctx->isc_ntxd_default[i]); 5351 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5352 } 5353 } 5354 5355 static void 5356 _iflib_pre_assert(if_softc_ctx_t scctx) 5357 { 5358 5359 MPASS(scctx->isc_txrx->ift_txd_encap); 5360 MPASS(scctx->isc_txrx->ift_txd_flush); 5361 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5362 MPASS(scctx->isc_txrx->ift_rxd_available); 5363 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5364 MPASS(scctx->isc_txrx->ift_rxd_refill); 5365 MPASS(scctx->isc_txrx->ift_rxd_flush); 5366 } 5367 5368 static int 5369 iflib_register(if_ctx_t ctx) 5370 { 5371 if_shared_ctx_t sctx = ctx->ifc_sctx; 5372 driver_t *driver = sctx->isc_driver; 5373 device_t dev = ctx->ifc_dev; 5374 if_t ifp; 5375 u_char type; 5376 int iflags; 5377 5378 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5379 _iflib_assert(sctx); 5380 5381 CTX_LOCK_INIT(ctx); 5382 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5383 if (sctx->isc_flags & IFLIB_PSEUDO) { 5384 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5385 type = IFT_ETHER; 5386 else 5387 type = IFT_PPP; 5388 } else 5389 type = IFT_ETHER; 5390 ifp = ctx->ifc_ifp = if_alloc(type); 5391 if (ifp == NULL) { 5392 device_printf(dev, "can not allocate ifnet structure\n"); 5393 return (ENOMEM); 5394 } 5395 5396 /* 5397 * Initialize our context's device specific methods 5398 */ 5399 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5400 kobj_class_compile((kobj_class_t) driver); 5401 5402 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5403 if_setsoftc(ifp, ctx); 5404 if_setdev(ifp, dev); 5405 if_setinitfn(ifp, iflib_if_init); 5406 if_setioctlfn(ifp, iflib_if_ioctl); 5407 #ifdef ALTQ 5408 if_setstartfn(ifp, iflib_altq_if_start); 5409 if_settransmitfn(ifp, iflib_altq_if_transmit); 5410 if_setsendqready(ifp); 5411 #else 5412 if_settransmitfn(ifp, iflib_if_transmit); 5413 #endif 5414 if_setqflushfn(ifp, iflib_if_qflush); 5415 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5416 5417 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5418 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5419 iflags |= IFF_POINTOPOINT; 5420 else 5421 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5422 if_setflags(ifp, iflags); 5423 ctx->ifc_vlan_attach_event = 5424 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5425 EVENTHANDLER_PRI_FIRST); 5426 ctx->ifc_vlan_detach_event = 5427 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5428 EVENTHANDLER_PRI_FIRST); 5429 5430 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5431 ctx->ifc_mediap = &ctx->ifc_media; 5432 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5433 iflib_media_change, iflib_media_status); 5434 } 5435 return (0); 5436 } 5437 5438 static void 5439 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5440 { 5441 /* Unregister VLAN events */ 5442 if (ctx->ifc_vlan_attach_event != NULL) { 5443 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5444 ctx->ifc_vlan_attach_event = NULL; 5445 } 5446 if (ctx->ifc_vlan_detach_event != NULL) { 5447 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5448 ctx->ifc_vlan_detach_event = NULL; 5449 } 5450 5451 } 5452 5453 static void 5454 iflib_deregister(if_ctx_t ctx) 5455 { 5456 if_t ifp = ctx->ifc_ifp; 5457 5458 /* Remove all media */ 5459 ifmedia_removeall(&ctx->ifc_media); 5460 5461 /* Ensure that VLAN event handlers are unregistered */ 5462 iflib_unregister_vlan_handlers(ctx); 5463 5464 /* Release kobject reference */ 5465 kobj_delete((kobj_t) ctx, NULL); 5466 5467 /* Free the ifnet structure */ 5468 if_free(ifp); 5469 5470 STATE_LOCK_DESTROY(ctx); 5471 5472 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5473 CTX_LOCK_DESTROY(ctx); 5474 } 5475 5476 static int 5477 iflib_queues_alloc(if_ctx_t ctx) 5478 { 5479 if_shared_ctx_t sctx = ctx->ifc_sctx; 5480 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5481 device_t dev = ctx->ifc_dev; 5482 int nrxqsets = scctx->isc_nrxqsets; 5483 int ntxqsets = scctx->isc_ntxqsets; 5484 iflib_txq_t txq; 5485 iflib_rxq_t rxq; 5486 iflib_fl_t fl = NULL; 5487 int i, j, cpu, err, txconf, rxconf; 5488 iflib_dma_info_t ifdip; 5489 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5490 uint32_t *txqsizes = scctx->isc_txqsizes; 5491 uint8_t nrxqs = sctx->isc_nrxqs; 5492 uint8_t ntxqs = sctx->isc_ntxqs; 5493 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5494 caddr_t *vaddrs; 5495 uint64_t *paddrs; 5496 5497 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5498 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5499 5500 /* Allocate the TX ring struct memory */ 5501 if (!(ctx->ifc_txqs = 5502 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5503 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5504 device_printf(dev, "Unable to allocate TX ring memory\n"); 5505 err = ENOMEM; 5506 goto fail; 5507 } 5508 5509 /* Now allocate the RX */ 5510 if (!(ctx->ifc_rxqs = 5511 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5512 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5513 device_printf(dev, "Unable to allocate RX ring memory\n"); 5514 err = ENOMEM; 5515 goto rx_fail; 5516 } 5517 5518 txq = ctx->ifc_txqs; 5519 rxq = ctx->ifc_rxqs; 5520 5521 /* 5522 * XXX handle allocation failure 5523 */ 5524 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5525 /* Set up some basics */ 5526 5527 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5528 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5529 device_printf(dev, 5530 "Unable to allocate TX DMA info memory\n"); 5531 err = ENOMEM; 5532 goto err_tx_desc; 5533 } 5534 txq->ift_ifdi = ifdip; 5535 for (j = 0; j < ntxqs; j++, ifdip++) { 5536 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5537 device_printf(dev, 5538 "Unable to allocate TX descriptors\n"); 5539 err = ENOMEM; 5540 goto err_tx_desc; 5541 } 5542 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5543 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5544 } 5545 txq->ift_ctx = ctx; 5546 txq->ift_id = i; 5547 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5548 txq->ift_br_offset = 1; 5549 } else { 5550 txq->ift_br_offset = 0; 5551 } 5552 /* XXX fix this */ 5553 txq->ift_timer.c_cpu = cpu; 5554 5555 if (iflib_txsd_alloc(txq)) { 5556 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5557 err = ENOMEM; 5558 goto err_tx_desc; 5559 } 5560 5561 /* Initialize the TX lock */ 5562 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5563 device_get_nameunit(dev), txq->ift_id); 5564 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5565 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5566 5567 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5568 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5569 if (err) { 5570 /* XXX free any allocated rings */ 5571 device_printf(dev, "Unable to allocate buf_ring\n"); 5572 goto err_tx_desc; 5573 } 5574 } 5575 5576 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5577 /* Set up some basics */ 5578 callout_init(&rxq->ifr_watchdog, 1); 5579 5580 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5581 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5582 device_printf(dev, 5583 "Unable to allocate RX DMA info memory\n"); 5584 err = ENOMEM; 5585 goto err_tx_desc; 5586 } 5587 5588 rxq->ifr_ifdi = ifdip; 5589 /* XXX this needs to be changed if #rx queues != #tx queues */ 5590 rxq->ifr_ntxqirq = 1; 5591 rxq->ifr_txqid[0] = i; 5592 for (j = 0; j < nrxqs; j++, ifdip++) { 5593 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5594 device_printf(dev, 5595 "Unable to allocate RX descriptors\n"); 5596 err = ENOMEM; 5597 goto err_tx_desc; 5598 } 5599 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5600 } 5601 rxq->ifr_ctx = ctx; 5602 rxq->ifr_id = i; 5603 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5604 rxq->ifr_fl_offset = 1; 5605 } else { 5606 rxq->ifr_fl_offset = 0; 5607 } 5608 rxq->ifr_nfl = nfree_lists; 5609 if (!(fl = 5610 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5611 device_printf(dev, "Unable to allocate free list memory\n"); 5612 err = ENOMEM; 5613 goto err_tx_desc; 5614 } 5615 rxq->ifr_fl = fl; 5616 for (j = 0; j < nfree_lists; j++) { 5617 fl[j].ifl_rxq = rxq; 5618 fl[j].ifl_id = j; 5619 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5620 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5621 } 5622 /* Allocate receive buffers for the ring */ 5623 if (iflib_rxsd_alloc(rxq)) { 5624 device_printf(dev, 5625 "Critical Failure setting up receive buffers\n"); 5626 err = ENOMEM; 5627 goto err_rx_desc; 5628 } 5629 5630 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5631 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5632 M_WAITOK); 5633 } 5634 5635 /* TXQs */ 5636 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5637 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5638 for (i = 0; i < ntxqsets; i++) { 5639 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5640 5641 for (j = 0; j < ntxqs; j++, di++) { 5642 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5643 paddrs[i*ntxqs + j] = di->idi_paddr; 5644 } 5645 } 5646 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5647 device_printf(ctx->ifc_dev, 5648 "Unable to allocate device TX queue\n"); 5649 iflib_tx_structures_free(ctx); 5650 free(vaddrs, M_IFLIB); 5651 free(paddrs, M_IFLIB); 5652 goto err_rx_desc; 5653 } 5654 free(vaddrs, M_IFLIB); 5655 free(paddrs, M_IFLIB); 5656 5657 /* RXQs */ 5658 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5659 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5660 for (i = 0; i < nrxqsets; i++) { 5661 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5662 5663 for (j = 0; j < nrxqs; j++, di++) { 5664 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5665 paddrs[i*nrxqs + j] = di->idi_paddr; 5666 } 5667 } 5668 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5669 device_printf(ctx->ifc_dev, 5670 "Unable to allocate device RX queue\n"); 5671 iflib_tx_structures_free(ctx); 5672 free(vaddrs, M_IFLIB); 5673 free(paddrs, M_IFLIB); 5674 goto err_rx_desc; 5675 } 5676 free(vaddrs, M_IFLIB); 5677 free(paddrs, M_IFLIB); 5678 5679 return (0); 5680 5681 /* XXX handle allocation failure changes */ 5682 err_rx_desc: 5683 err_tx_desc: 5684 rx_fail: 5685 if (ctx->ifc_rxqs != NULL) 5686 free(ctx->ifc_rxqs, M_IFLIB); 5687 ctx->ifc_rxqs = NULL; 5688 if (ctx->ifc_txqs != NULL) 5689 free(ctx->ifc_txqs, M_IFLIB); 5690 ctx->ifc_txqs = NULL; 5691 fail: 5692 return (err); 5693 } 5694 5695 static int 5696 iflib_tx_structures_setup(if_ctx_t ctx) 5697 { 5698 iflib_txq_t txq = ctx->ifc_txqs; 5699 int i; 5700 5701 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5702 iflib_txq_setup(txq); 5703 5704 return (0); 5705 } 5706 5707 static void 5708 iflib_tx_structures_free(if_ctx_t ctx) 5709 { 5710 iflib_txq_t txq = ctx->ifc_txqs; 5711 if_shared_ctx_t sctx = ctx->ifc_sctx; 5712 int i, j; 5713 5714 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5715 for (j = 0; j < sctx->isc_ntxqs; j++) 5716 iflib_dma_free(&txq->ift_ifdi[j]); 5717 iflib_txq_destroy(txq); 5718 } 5719 free(ctx->ifc_txqs, M_IFLIB); 5720 ctx->ifc_txqs = NULL; 5721 IFDI_QUEUES_FREE(ctx); 5722 } 5723 5724 /********************************************************************* 5725 * 5726 * Initialize all receive rings. 5727 * 5728 **********************************************************************/ 5729 static int 5730 iflib_rx_structures_setup(if_ctx_t ctx) 5731 { 5732 iflib_rxq_t rxq = ctx->ifc_rxqs; 5733 int q; 5734 #if defined(INET6) || defined(INET) 5735 int err, i; 5736 #endif 5737 5738 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5739 #if defined(INET6) || defined(INET) 5740 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5741 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5742 TCP_LRO_ENTRIES, min(1024, 5743 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5744 if (err != 0) { 5745 device_printf(ctx->ifc_dev, 5746 "LRO Initialization failed!\n"); 5747 goto fail; 5748 } 5749 } 5750 #endif 5751 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5752 } 5753 return (0); 5754 #if defined(INET6) || defined(INET) 5755 fail: 5756 /* 5757 * Free LRO resources allocated so far, we will only handle 5758 * the rings that completed, the failing case will have 5759 * cleaned up for itself. 'q' failed, so its the terminus. 5760 */ 5761 rxq = ctx->ifc_rxqs; 5762 for (i = 0; i < q; ++i, rxq++) { 5763 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5764 tcp_lro_free(&rxq->ifr_lc); 5765 } 5766 return (err); 5767 #endif 5768 } 5769 5770 /********************************************************************* 5771 * 5772 * Free all receive rings. 5773 * 5774 **********************************************************************/ 5775 static void 5776 iflib_rx_structures_free(if_ctx_t ctx) 5777 { 5778 iflib_rxq_t rxq = ctx->ifc_rxqs; 5779 if_shared_ctx_t sctx = ctx->ifc_sctx; 5780 int i, j; 5781 5782 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5783 for (j = 0; j < sctx->isc_nrxqs; j++) 5784 iflib_dma_free(&rxq->ifr_ifdi[j]); 5785 iflib_rx_sds_free(rxq); 5786 #if defined(INET6) || defined(INET) 5787 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5788 tcp_lro_free(&rxq->ifr_lc); 5789 #endif 5790 } 5791 free(ctx->ifc_rxqs, M_IFLIB); 5792 ctx->ifc_rxqs = NULL; 5793 } 5794 5795 static int 5796 iflib_qset_structures_setup(if_ctx_t ctx) 5797 { 5798 int err; 5799 5800 /* 5801 * It is expected that the caller takes care of freeing queues if this 5802 * fails. 5803 */ 5804 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5805 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5806 return (err); 5807 } 5808 5809 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5810 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5811 5812 return (err); 5813 } 5814 5815 int 5816 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5817 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5818 { 5819 5820 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5821 } 5822 5823 #ifdef SMP 5824 static int 5825 find_nth(if_ctx_t ctx, int qid) 5826 { 5827 cpuset_t cpus; 5828 int i, cpuid, eqid, count; 5829 5830 CPU_COPY(&ctx->ifc_cpus, &cpus); 5831 count = CPU_COUNT(&cpus); 5832 eqid = qid % count; 5833 /* clear up to the qid'th bit */ 5834 for (i = 0; i < eqid; i++) { 5835 cpuid = CPU_FFS(&cpus); 5836 MPASS(cpuid != 0); 5837 CPU_CLR(cpuid-1, &cpus); 5838 } 5839 cpuid = CPU_FFS(&cpus); 5840 MPASS(cpuid != 0); 5841 return (cpuid-1); 5842 } 5843 5844 #ifdef SCHED_ULE 5845 extern struct cpu_group *cpu_top; /* CPU topology */ 5846 5847 static int 5848 find_child_with_core(int cpu, struct cpu_group *grp) 5849 { 5850 int i; 5851 5852 if (grp->cg_children == 0) 5853 return -1; 5854 5855 MPASS(grp->cg_child); 5856 for (i = 0; i < grp->cg_children; i++) { 5857 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5858 return i; 5859 } 5860 5861 return -1; 5862 } 5863 5864 /* 5865 * Find the nth "close" core to the specified core 5866 * "close" is defined as the deepest level that shares 5867 * at least an L2 cache. With threads, this will be 5868 * threads on the same core. If the shared cache is L3 5869 * or higher, simply returns the same core. 5870 */ 5871 static int 5872 find_close_core(int cpu, int core_offset) 5873 { 5874 struct cpu_group *grp; 5875 int i; 5876 int fcpu; 5877 cpuset_t cs; 5878 5879 grp = cpu_top; 5880 if (grp == NULL) 5881 return cpu; 5882 i = 0; 5883 while ((i = find_child_with_core(cpu, grp)) != -1) { 5884 /* If the child only has one cpu, don't descend */ 5885 if (grp->cg_child[i].cg_count <= 1) 5886 break; 5887 grp = &grp->cg_child[i]; 5888 } 5889 5890 /* If they don't share at least an L2 cache, use the same CPU */ 5891 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5892 return cpu; 5893 5894 /* Now pick one */ 5895 CPU_COPY(&grp->cg_mask, &cs); 5896 5897 /* Add the selected CPU offset to core offset. */ 5898 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5899 if (fcpu - 1 == cpu) 5900 break; 5901 CPU_CLR(fcpu - 1, &cs); 5902 } 5903 MPASS(fcpu); 5904 5905 core_offset += i; 5906 5907 CPU_COPY(&grp->cg_mask, &cs); 5908 for (i = core_offset % grp->cg_count; i > 0; i--) { 5909 MPASS(CPU_FFS(&cs)); 5910 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5911 } 5912 MPASS(CPU_FFS(&cs)); 5913 return CPU_FFS(&cs) - 1; 5914 } 5915 #else 5916 static int 5917 find_close_core(int cpu, int core_offset __unused) 5918 { 5919 return cpu; 5920 } 5921 #endif 5922 5923 static int 5924 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5925 { 5926 switch (type) { 5927 case IFLIB_INTR_TX: 5928 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5929 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5930 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5931 case IFLIB_INTR_RX: 5932 case IFLIB_INTR_RXTX: 5933 /* RX queues get the specified core */ 5934 return qid / CPU_COUNT(&ctx->ifc_cpus); 5935 default: 5936 return -1; 5937 } 5938 } 5939 #else 5940 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5941 #define find_close_core(cpuid, tid) CPU_FIRST() 5942 #define find_nth(ctx, gid) CPU_FIRST() 5943 #endif 5944 5945 /* Just to avoid copy/paste */ 5946 static inline int 5947 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5948 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5949 const char *name) 5950 { 5951 device_t dev; 5952 int co, cpuid, err, tid; 5953 5954 dev = ctx->ifc_dev; 5955 co = ctx->ifc_sysctl_core_offset; 5956 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5957 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5958 cpuid = find_nth(ctx, qid + co); 5959 tid = get_core_offset(ctx, type, qid); 5960 if (tid < 0) { 5961 device_printf(dev, "get_core_offset failed\n"); 5962 return (EOPNOTSUPP); 5963 } 5964 cpuid = find_close_core(cpuid, tid); 5965 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5966 name); 5967 if (err) { 5968 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5969 return (err); 5970 } 5971 #ifdef notyet 5972 if (cpuid > ctx->ifc_cpuid_highest) 5973 ctx->ifc_cpuid_highest = cpuid; 5974 #endif 5975 return (0); 5976 } 5977 5978 int 5979 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5980 iflib_intr_type_t type, driver_filter_t *filter, 5981 void *filter_arg, int qid, const char *name) 5982 { 5983 device_t dev; 5984 struct grouptask *gtask; 5985 struct taskqgroup *tqg; 5986 iflib_filter_info_t info; 5987 gtask_fn_t *fn; 5988 int tqrid, err; 5989 driver_filter_t *intr_fast; 5990 void *q; 5991 5992 info = &ctx->ifc_filter_info; 5993 tqrid = rid; 5994 5995 switch (type) { 5996 /* XXX merge tx/rx for netmap? */ 5997 case IFLIB_INTR_TX: 5998 q = &ctx->ifc_txqs[qid]; 5999 info = &ctx->ifc_txqs[qid].ift_filter_info; 6000 gtask = &ctx->ifc_txqs[qid].ift_task; 6001 tqg = qgroup_if_io_tqg; 6002 fn = _task_fn_tx; 6003 intr_fast = iflib_fast_intr; 6004 GROUPTASK_INIT(gtask, 0, fn, q); 6005 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6006 break; 6007 case IFLIB_INTR_RX: 6008 q = &ctx->ifc_rxqs[qid]; 6009 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6010 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6011 tqg = qgroup_if_io_tqg; 6012 fn = _task_fn_rx; 6013 intr_fast = iflib_fast_intr; 6014 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6015 break; 6016 case IFLIB_INTR_RXTX: 6017 q = &ctx->ifc_rxqs[qid]; 6018 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6019 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6020 tqg = qgroup_if_io_tqg; 6021 fn = _task_fn_rx; 6022 intr_fast = iflib_fast_intr_rxtx; 6023 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6024 break; 6025 case IFLIB_INTR_ADMIN: 6026 q = ctx; 6027 tqrid = -1; 6028 info = &ctx->ifc_filter_info; 6029 gtask = &ctx->ifc_admin_task; 6030 tqg = qgroup_if_config_tqg; 6031 fn = _task_fn_admin; 6032 intr_fast = iflib_fast_intr_ctx; 6033 break; 6034 default: 6035 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6036 __func__); 6037 return (EINVAL); 6038 } 6039 6040 info->ifi_filter = filter; 6041 info->ifi_filter_arg = filter_arg; 6042 info->ifi_task = gtask; 6043 info->ifi_ctx = q; 6044 6045 dev = ctx->ifc_dev; 6046 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6047 if (err != 0) { 6048 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6049 return (err); 6050 } 6051 if (type == IFLIB_INTR_ADMIN) 6052 return (0); 6053 6054 if (tqrid != -1) { 6055 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6056 q, name); 6057 if (err) 6058 return (err); 6059 } else { 6060 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6061 } 6062 6063 return (0); 6064 } 6065 6066 void 6067 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6068 { 6069 struct grouptask *gtask; 6070 struct taskqgroup *tqg; 6071 gtask_fn_t *fn; 6072 void *q; 6073 int err; 6074 6075 switch (type) { 6076 case IFLIB_INTR_TX: 6077 q = &ctx->ifc_txqs[qid]; 6078 gtask = &ctx->ifc_txqs[qid].ift_task; 6079 tqg = qgroup_if_io_tqg; 6080 fn = _task_fn_tx; 6081 GROUPTASK_INIT(gtask, 0, fn, q); 6082 break; 6083 case IFLIB_INTR_RX: 6084 q = &ctx->ifc_rxqs[qid]; 6085 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6086 tqg = qgroup_if_io_tqg; 6087 fn = _task_fn_rx; 6088 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6089 break; 6090 case IFLIB_INTR_IOV: 6091 q = ctx; 6092 gtask = &ctx->ifc_vflr_task; 6093 tqg = qgroup_if_config_tqg; 6094 fn = _task_fn_iov; 6095 GROUPTASK_INIT(gtask, 0, fn, q); 6096 break; 6097 default: 6098 panic("unknown net intr type"); 6099 } 6100 if (irq != NULL) { 6101 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6102 q, name); 6103 if (err) 6104 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6105 irq->ii_res, name); 6106 } else { 6107 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6108 } 6109 } 6110 6111 void 6112 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6113 { 6114 6115 if (irq->ii_tag) 6116 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6117 6118 if (irq->ii_res) 6119 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6120 rman_get_rid(irq->ii_res), irq->ii_res); 6121 } 6122 6123 static int 6124 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6125 { 6126 iflib_txq_t txq = ctx->ifc_txqs; 6127 iflib_rxq_t rxq = ctx->ifc_rxqs; 6128 if_irq_t irq = &ctx->ifc_legacy_irq; 6129 iflib_filter_info_t info; 6130 device_t dev; 6131 struct grouptask *gtask; 6132 struct resource *res; 6133 struct taskqgroup *tqg; 6134 void *q; 6135 int err, tqrid; 6136 bool rx_only; 6137 6138 q = &ctx->ifc_rxqs[0]; 6139 info = &rxq[0].ifr_filter_info; 6140 gtask = &rxq[0].ifr_task; 6141 tqg = qgroup_if_io_tqg; 6142 tqrid = *rid; 6143 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6144 6145 ctx->ifc_flags |= IFC_LEGACY; 6146 info->ifi_filter = filter; 6147 info->ifi_filter_arg = filter_arg; 6148 info->ifi_task = gtask; 6149 info->ifi_ctx = rx_only ? ctx : q; 6150 6151 dev = ctx->ifc_dev; 6152 /* We allocate a single interrupt resource */ 6153 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6154 iflib_fast_intr_rxtx, NULL, info, name); 6155 if (err != 0) 6156 return (err); 6157 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6158 res = irq->ii_res; 6159 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6160 6161 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6162 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6163 "tx"); 6164 return (0); 6165 } 6166 6167 void 6168 iflib_led_create(if_ctx_t ctx) 6169 { 6170 6171 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6172 device_get_nameunit(ctx->ifc_dev)); 6173 } 6174 6175 void 6176 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6177 { 6178 6179 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6180 } 6181 6182 void 6183 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6184 { 6185 6186 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6187 } 6188 6189 void 6190 iflib_admin_intr_deferred(if_ctx_t ctx) 6191 { 6192 6193 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6194 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6195 } 6196 6197 void 6198 iflib_iov_intr_deferred(if_ctx_t ctx) 6199 { 6200 6201 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6202 } 6203 6204 void 6205 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6206 { 6207 6208 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6209 name); 6210 } 6211 6212 void 6213 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6214 const char *name) 6215 { 6216 6217 GROUPTASK_INIT(gtask, 0, fn, ctx); 6218 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6219 name); 6220 } 6221 6222 void 6223 iflib_config_gtask_deinit(struct grouptask *gtask) 6224 { 6225 6226 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6227 } 6228 6229 void 6230 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6231 { 6232 if_t ifp = ctx->ifc_ifp; 6233 iflib_txq_t txq = ctx->ifc_txqs; 6234 6235 if_setbaudrate(ifp, baudrate); 6236 if (baudrate >= IF_Gbps(10)) { 6237 STATE_LOCK(ctx); 6238 ctx->ifc_flags |= IFC_PREFETCH; 6239 STATE_UNLOCK(ctx); 6240 } 6241 /* If link down, disable watchdog */ 6242 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6243 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6244 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6245 } 6246 ctx->ifc_link_state = link_state; 6247 if_link_state_change(ifp, link_state); 6248 } 6249 6250 static int 6251 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6252 { 6253 int credits; 6254 #ifdef INVARIANTS 6255 int credits_pre = txq->ift_cidx_processed; 6256 #endif 6257 6258 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6259 BUS_DMASYNC_POSTREAD); 6260 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6261 return (0); 6262 6263 txq->ift_processed += credits; 6264 txq->ift_cidx_processed += credits; 6265 6266 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6267 if (txq->ift_cidx_processed >= txq->ift_size) 6268 txq->ift_cidx_processed -= txq->ift_size; 6269 return (credits); 6270 } 6271 6272 static int 6273 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6274 { 6275 iflib_fl_t fl; 6276 u_int i; 6277 6278 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6279 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6280 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6281 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6282 budget)); 6283 } 6284 6285 void 6286 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6287 const char *description, if_int_delay_info_t info, 6288 int offset, int value) 6289 { 6290 info->iidi_ctx = ctx; 6291 info->iidi_offset = offset; 6292 info->iidi_value = value; 6293 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6294 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6295 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6296 info, 0, iflib_sysctl_int_delay, "I", description); 6297 } 6298 6299 struct sx * 6300 iflib_ctx_lock_get(if_ctx_t ctx) 6301 { 6302 6303 return (&ctx->ifc_ctx_sx); 6304 } 6305 6306 static int 6307 iflib_msix_init(if_ctx_t ctx) 6308 { 6309 device_t dev = ctx->ifc_dev; 6310 if_shared_ctx_t sctx = ctx->ifc_sctx; 6311 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6312 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6313 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6314 6315 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6316 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6317 6318 if (bootverbose) 6319 device_printf(dev, "msix_init qsets capped at %d\n", 6320 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6321 6322 /* Override by tuneable */ 6323 if (scctx->isc_disable_msix) 6324 goto msi; 6325 6326 /* First try MSI-X */ 6327 if ((msgs = pci_msix_count(dev)) == 0) { 6328 if (bootverbose) 6329 device_printf(dev, "MSI-X not supported or disabled\n"); 6330 goto msi; 6331 } 6332 6333 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6334 /* 6335 * bar == -1 => "trust me I know what I'm doing" 6336 * Some drivers are for hardware that is so shoddily 6337 * documented that no one knows which bars are which 6338 * so the developer has to map all bars. This hack 6339 * allows shoddy garbage to use MSI-X in this framework. 6340 */ 6341 if (bar != -1) { 6342 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6343 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6344 if (ctx->ifc_msix_mem == NULL) { 6345 device_printf(dev, "Unable to map MSI-X table\n"); 6346 goto msi; 6347 } 6348 } 6349 6350 admincnt = sctx->isc_admin_intrcnt; 6351 #if IFLIB_DEBUG 6352 /* use only 1 qset in debug mode */ 6353 queuemsgs = min(msgs - admincnt, 1); 6354 #else 6355 queuemsgs = msgs - admincnt; 6356 #endif 6357 #ifdef RSS 6358 queues = imin(queuemsgs, rss_getnumbuckets()); 6359 #else 6360 queues = queuemsgs; 6361 #endif 6362 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6363 if (bootverbose) 6364 device_printf(dev, 6365 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6366 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6367 #ifdef RSS 6368 /* If we're doing RSS, clamp at the number of RSS buckets */ 6369 if (queues > rss_getnumbuckets()) 6370 queues = rss_getnumbuckets(); 6371 #endif 6372 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6373 rx_queues = iflib_num_rx_queues; 6374 else 6375 rx_queues = queues; 6376 6377 if (rx_queues > scctx->isc_nrxqsets) 6378 rx_queues = scctx->isc_nrxqsets; 6379 6380 /* 6381 * We want this to be all logical CPUs by default 6382 */ 6383 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6384 tx_queues = iflib_num_tx_queues; 6385 else 6386 tx_queues = mp_ncpus; 6387 6388 if (tx_queues > scctx->isc_ntxqsets) 6389 tx_queues = scctx->isc_ntxqsets; 6390 6391 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6392 #ifdef INVARIANTS 6393 if (tx_queues != rx_queues) 6394 device_printf(dev, 6395 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6396 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6397 #endif 6398 tx_queues = min(rx_queues, tx_queues); 6399 rx_queues = min(rx_queues, tx_queues); 6400 } 6401 6402 vectors = rx_queues + admincnt; 6403 if (msgs < vectors) { 6404 device_printf(dev, 6405 "insufficient number of MSI-X vectors " 6406 "(supported %d, need %d)\n", msgs, vectors); 6407 goto msi; 6408 } 6409 6410 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6411 tx_queues); 6412 msgs = vectors; 6413 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6414 if (vectors != msgs) { 6415 device_printf(dev, 6416 "Unable to allocate sufficient MSI-X vectors " 6417 "(got %d, need %d)\n", vectors, msgs); 6418 pci_release_msi(dev); 6419 if (bar != -1) { 6420 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6421 ctx->ifc_msix_mem); 6422 ctx->ifc_msix_mem = NULL; 6423 } 6424 goto msi; 6425 } 6426 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6427 vectors); 6428 scctx->isc_vectors = vectors; 6429 scctx->isc_nrxqsets = rx_queues; 6430 scctx->isc_ntxqsets = tx_queues; 6431 scctx->isc_intr = IFLIB_INTR_MSIX; 6432 6433 return (vectors); 6434 } else { 6435 device_printf(dev, 6436 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6437 err); 6438 if (bar != -1) { 6439 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6440 ctx->ifc_msix_mem); 6441 ctx->ifc_msix_mem = NULL; 6442 } 6443 } 6444 6445 msi: 6446 vectors = pci_msi_count(dev); 6447 scctx->isc_nrxqsets = 1; 6448 scctx->isc_ntxqsets = 1; 6449 scctx->isc_vectors = vectors; 6450 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6451 device_printf(dev,"Using an MSI interrupt\n"); 6452 scctx->isc_intr = IFLIB_INTR_MSI; 6453 } else { 6454 scctx->isc_vectors = 1; 6455 device_printf(dev,"Using a Legacy interrupt\n"); 6456 scctx->isc_intr = IFLIB_INTR_LEGACY; 6457 } 6458 6459 return (vectors); 6460 } 6461 6462 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6463 6464 static int 6465 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6466 { 6467 int rc; 6468 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6469 struct sbuf *sb; 6470 const char *ring_state = "UNKNOWN"; 6471 6472 /* XXX needed ? */ 6473 rc = sysctl_wire_old_buffer(req, 0); 6474 MPASS(rc == 0); 6475 if (rc != 0) 6476 return (rc); 6477 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6478 MPASS(sb != NULL); 6479 if (sb == NULL) 6480 return (ENOMEM); 6481 if (state[3] <= 3) 6482 ring_state = ring_states[state[3]]; 6483 6484 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6485 state[0], state[1], state[2], ring_state); 6486 rc = sbuf_finish(sb); 6487 sbuf_delete(sb); 6488 return(rc); 6489 } 6490 6491 enum iflib_ndesc_handler { 6492 IFLIB_NTXD_HANDLER, 6493 IFLIB_NRXD_HANDLER, 6494 }; 6495 6496 static int 6497 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6498 { 6499 if_ctx_t ctx = (void *)arg1; 6500 enum iflib_ndesc_handler type = arg2; 6501 char buf[256] = {0}; 6502 qidx_t *ndesc; 6503 char *p, *next; 6504 int nqs, rc, i; 6505 6506 nqs = 8; 6507 switch(type) { 6508 case IFLIB_NTXD_HANDLER: 6509 ndesc = ctx->ifc_sysctl_ntxds; 6510 if (ctx->ifc_sctx) 6511 nqs = ctx->ifc_sctx->isc_ntxqs; 6512 break; 6513 case IFLIB_NRXD_HANDLER: 6514 ndesc = ctx->ifc_sysctl_nrxds; 6515 if (ctx->ifc_sctx) 6516 nqs = ctx->ifc_sctx->isc_nrxqs; 6517 break; 6518 default: 6519 printf("%s: unhandled type\n", __func__); 6520 return (EINVAL); 6521 } 6522 if (nqs == 0) 6523 nqs = 8; 6524 6525 for (i=0; i<8; i++) { 6526 if (i >= nqs) 6527 break; 6528 if (i) 6529 strcat(buf, ","); 6530 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6531 } 6532 6533 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6534 if (rc || req->newptr == NULL) 6535 return rc; 6536 6537 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6538 i++, p = strsep(&next, " ,")) { 6539 ndesc[i] = strtoul(p, NULL, 10); 6540 } 6541 6542 return(rc); 6543 } 6544 6545 #define NAME_BUFLEN 32 6546 static void 6547 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6548 { 6549 device_t dev = iflib_get_dev(ctx); 6550 struct sysctl_oid_list *child, *oid_list; 6551 struct sysctl_ctx_list *ctx_list; 6552 struct sysctl_oid *node; 6553 6554 ctx_list = device_get_sysctl_ctx(dev); 6555 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6556 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6557 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6558 oid_list = SYSCTL_CHILDREN(node); 6559 6560 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6561 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6562 "driver version"); 6563 6564 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6565 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6566 "# of txqs to use, 0 => use default #"); 6567 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6568 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6569 "# of rxqs to use, 0 => use default #"); 6570 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6571 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6572 "permit #txq != #rxq"); 6573 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6574 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6575 "disable MSI-X (default 0)"); 6576 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6577 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6578 "set the RX budget"); 6579 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6580 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6581 "cause TX to abdicate instead of running to completion"); 6582 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6583 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6584 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6585 "offset to start using cores at"); 6586 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6587 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6588 "use separate cores for TX and RX"); 6589 6590 /* XXX change for per-queue sizes */ 6591 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6592 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6593 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6594 "list of # of TX descriptors to use, 0 = use default #"); 6595 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6596 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6597 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6598 "list of # of RX descriptors to use, 0 = use default #"); 6599 } 6600 6601 static void 6602 iflib_add_device_sysctl_post(if_ctx_t ctx) 6603 { 6604 if_shared_ctx_t sctx = ctx->ifc_sctx; 6605 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6606 device_t dev = iflib_get_dev(ctx); 6607 struct sysctl_oid_list *child; 6608 struct sysctl_ctx_list *ctx_list; 6609 iflib_fl_t fl; 6610 iflib_txq_t txq; 6611 iflib_rxq_t rxq; 6612 int i, j; 6613 char namebuf[NAME_BUFLEN]; 6614 char *qfmt; 6615 struct sysctl_oid *queue_node, *fl_node, *node; 6616 struct sysctl_oid_list *queue_list, *fl_list; 6617 ctx_list = device_get_sysctl_ctx(dev); 6618 6619 node = ctx->ifc_sysctl_node; 6620 child = SYSCTL_CHILDREN(node); 6621 6622 if (scctx->isc_ntxqsets > 100) 6623 qfmt = "txq%03d"; 6624 else if (scctx->isc_ntxqsets > 10) 6625 qfmt = "txq%02d"; 6626 else 6627 qfmt = "txq%d"; 6628 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6629 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6630 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6631 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6632 queue_list = SYSCTL_CHILDREN(queue_node); 6633 #if MEMORY_LOGGING 6634 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6635 CTLFLAG_RD, 6636 &txq->ift_dequeued, "total mbufs freed"); 6637 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6638 CTLFLAG_RD, 6639 &txq->ift_enqueued, "total mbufs enqueued"); 6640 #endif 6641 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6642 CTLFLAG_RD, 6643 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6644 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6645 CTLFLAG_RD, 6646 &txq->ift_pullups, "# of times m_pullup was called"); 6647 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6648 CTLFLAG_RD, 6649 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6650 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6651 CTLFLAG_RD, 6652 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6653 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6654 CTLFLAG_RD, 6655 &txq->ift_map_failed, "# of times DMA map failed"); 6656 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6657 CTLFLAG_RD, 6658 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6659 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6660 CTLFLAG_RD, 6661 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6662 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6663 CTLFLAG_RD, 6664 &txq->ift_pidx, 1, "Producer Index"); 6665 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6666 CTLFLAG_RD, 6667 &txq->ift_cidx, 1, "Consumer Index"); 6668 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6669 CTLFLAG_RD, 6670 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6671 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6672 CTLFLAG_RD, 6673 &txq->ift_in_use, 1, "descriptors in use"); 6674 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6675 CTLFLAG_RD, 6676 &txq->ift_processed, "descriptors procesed for clean"); 6677 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6678 CTLFLAG_RD, 6679 &txq->ift_cleaned, "total cleaned"); 6680 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6681 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6682 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6683 mp_ring_state_handler, "A", "soft ring state"); 6684 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6685 CTLFLAG_RD, &txq->ift_br->enqueues, 6686 "# of enqueues to the mp_ring for this queue"); 6687 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6688 CTLFLAG_RD, &txq->ift_br->drops, 6689 "# of drops in the mp_ring for this queue"); 6690 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6691 CTLFLAG_RD, &txq->ift_br->starts, 6692 "# of normal consumer starts in the mp_ring for this queue"); 6693 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6694 CTLFLAG_RD, &txq->ift_br->stalls, 6695 "# of consumer stalls in the mp_ring for this queue"); 6696 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6697 CTLFLAG_RD, &txq->ift_br->restarts, 6698 "# of consumer restarts in the mp_ring for this queue"); 6699 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6700 CTLFLAG_RD, &txq->ift_br->abdications, 6701 "# of consumer abdications in the mp_ring for this queue"); 6702 } 6703 6704 if (scctx->isc_nrxqsets > 100) 6705 qfmt = "rxq%03d"; 6706 else if (scctx->isc_nrxqsets > 10) 6707 qfmt = "rxq%02d"; 6708 else 6709 qfmt = "rxq%d"; 6710 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6711 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6712 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6713 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6714 queue_list = SYSCTL_CHILDREN(queue_node); 6715 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6716 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6717 CTLFLAG_RD, 6718 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6719 } 6720 6721 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6722 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6723 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6724 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 6725 fl_list = SYSCTL_CHILDREN(fl_node); 6726 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6727 CTLFLAG_RD, 6728 &fl->ifl_pidx, 1, "Producer Index"); 6729 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6730 CTLFLAG_RD, 6731 &fl->ifl_cidx, 1, "Consumer Index"); 6732 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6733 CTLFLAG_RD, 6734 &fl->ifl_credits, 1, "credits available"); 6735 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 6736 CTLFLAG_RD, 6737 &fl->ifl_buf_size, 1, "buffer size"); 6738 #if MEMORY_LOGGING 6739 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6740 CTLFLAG_RD, 6741 &fl->ifl_m_enqueued, "mbufs allocated"); 6742 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6743 CTLFLAG_RD, 6744 &fl->ifl_m_dequeued, "mbufs freed"); 6745 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6746 CTLFLAG_RD, 6747 &fl->ifl_cl_enqueued, "clusters allocated"); 6748 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6749 CTLFLAG_RD, 6750 &fl->ifl_cl_dequeued, "clusters freed"); 6751 #endif 6752 6753 } 6754 } 6755 6756 } 6757 6758 void 6759 iflib_request_reset(if_ctx_t ctx) 6760 { 6761 6762 STATE_LOCK(ctx); 6763 ctx->ifc_flags |= IFC_DO_RESET; 6764 STATE_UNLOCK(ctx); 6765 } 6766 6767 #ifndef __NO_STRICT_ALIGNMENT 6768 static struct mbuf * 6769 iflib_fixup_rx(struct mbuf *m) 6770 { 6771 struct mbuf *n; 6772 6773 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6774 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6775 m->m_data += ETHER_HDR_LEN; 6776 n = m; 6777 } else { 6778 MGETHDR(n, M_NOWAIT, MT_DATA); 6779 if (n == NULL) { 6780 m_freem(m); 6781 return (NULL); 6782 } 6783 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6784 m->m_data += ETHER_HDR_LEN; 6785 m->m_len -= ETHER_HDR_LEN; 6786 n->m_len = ETHER_HDR_LEN; 6787 M_MOVE_PKTHDR(n, m); 6788 n->m_next = m; 6789 } 6790 return (n); 6791 } 6792 #endif 6793 6794 #ifdef DEBUGNET 6795 static void 6796 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6797 { 6798 if_ctx_t ctx; 6799 6800 ctx = if_getsoftc(ifp); 6801 CTX_LOCK(ctx); 6802 *nrxr = NRXQSETS(ctx); 6803 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6804 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6805 CTX_UNLOCK(ctx); 6806 } 6807 6808 static void 6809 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6810 { 6811 if_ctx_t ctx; 6812 if_softc_ctx_t scctx; 6813 iflib_fl_t fl; 6814 iflib_rxq_t rxq; 6815 int i, j; 6816 6817 ctx = if_getsoftc(ifp); 6818 scctx = &ctx->ifc_softc_ctx; 6819 6820 switch (event) { 6821 case DEBUGNET_START: 6822 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6823 rxq = &ctx->ifc_rxqs[i]; 6824 for (j = 0; j < rxq->ifr_nfl; j++) { 6825 fl = rxq->ifr_fl; 6826 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6827 } 6828 } 6829 iflib_no_tx_batch = 1; 6830 break; 6831 default: 6832 break; 6833 } 6834 } 6835 6836 static int 6837 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6838 { 6839 if_ctx_t ctx; 6840 iflib_txq_t txq; 6841 int error; 6842 6843 ctx = if_getsoftc(ifp); 6844 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6845 IFF_DRV_RUNNING) 6846 return (EBUSY); 6847 6848 txq = &ctx->ifc_txqs[0]; 6849 error = iflib_encap(txq, &m); 6850 if (error == 0) 6851 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6852 return (error); 6853 } 6854 6855 static int 6856 iflib_debugnet_poll(if_t ifp, int count) 6857 { 6858 struct epoch_tracker et; 6859 if_ctx_t ctx; 6860 if_softc_ctx_t scctx; 6861 iflib_txq_t txq; 6862 int i; 6863 6864 ctx = if_getsoftc(ifp); 6865 scctx = &ctx->ifc_softc_ctx; 6866 6867 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6868 IFF_DRV_RUNNING) 6869 return (EBUSY); 6870 6871 txq = &ctx->ifc_txqs[0]; 6872 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6873 6874 NET_EPOCH_ENTER(et); 6875 for (i = 0; i < scctx->isc_nrxqsets; i++) 6876 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6877 NET_EPOCH_EXIT(et); 6878 return (0); 6879 } 6880 #endif /* DEBUGNET */ 6881