1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/jail.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/md5.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/kobj.h> 47 #include <sys/rman.h> 48 #include <sys/proc.h> 49 #include <sys/sbuf.h> 50 #include <sys/smp.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/syslog.h> 55 #include <sys/taskqueue.h> 56 #include <sys/limits.h> 57 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet/netdump/netdump.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 #include <net/iflib_private.h> 92 93 #include "ifdi_if.h" 94 95 #ifdef PCI_IOV 96 #include <dev/pci/pci_iov.h> 97 #endif 98 99 #include <sys/bitstring.h> 100 /* 101 * enable accounting of every mbuf as it comes in to and goes out of 102 * iflib's software descriptor references 103 */ 104 #define MEMORY_LOGGING 0 105 /* 106 * Enable mbuf vectors for compressing long mbuf chains 107 */ 108 109 /* 110 * NB: 111 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 112 * we prefetch needs to be determined by the time spent in m_free vis a vis 113 * the cost of a prefetch. This will of course vary based on the workload: 114 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 115 * is quite expensive, thus suggesting very little prefetch. 116 * - small packet forwarding which is just returning a single mbuf to 117 * UMA will typically be very fast vis a vis the cost of a memory 118 * access. 119 */ 120 121 122 /* 123 * File organization: 124 * - private structures 125 * - iflib private utility functions 126 * - ifnet functions 127 * - vlan registry and other exported functions 128 * - iflib public core functions 129 * 130 * 131 */ 132 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct sx ifc_ctx_sx; 167 struct mtx ifc_state_mtx; 168 169 iflib_txq_t ifc_txqs; 170 iflib_rxq_t ifc_rxqs; 171 uint32_t ifc_if_flags; 172 uint32_t ifc_flags; 173 uint32_t ifc_max_fl_buf_size; 174 175 int ifc_link_state; 176 int ifc_link_irq; 177 int ifc_watchdog_events; 178 struct cdev *ifc_led_dev; 179 struct resource *ifc_msix_mem; 180 181 struct if_irq ifc_legacy_irq; 182 struct grouptask ifc_admin_task; 183 struct grouptask ifc_vflr_task; 184 struct iflib_filter_info ifc_filter_info; 185 struct ifmedia ifc_media; 186 187 struct sysctl_oid *ifc_sysctl_node; 188 uint16_t ifc_sysctl_ntxqs; 189 uint16_t ifc_sysctl_nrxqs; 190 uint16_t ifc_sysctl_qs_eq_override; 191 uint16_t ifc_sysctl_rx_budget; 192 uint16_t ifc_sysctl_tx_abdicate; 193 194 qidx_t ifc_sysctl_ntxds[8]; 195 qidx_t ifc_sysctl_nrxds[8]; 196 struct if_txrx ifc_txrx; 197 #define isc_txd_encap ifc_txrx.ift_txd_encap 198 #define isc_txd_flush ifc_txrx.ift_txd_flush 199 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 200 #define isc_rxd_available ifc_txrx.ift_rxd_available 201 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 202 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 203 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 206 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 207 eventhandler_tag ifc_vlan_attach_event; 208 eventhandler_tag ifc_vlan_detach_event; 209 uint8_t ifc_mac[ETHER_ADDR_LEN]; 210 char ifc_mtx_name[16]; 211 }; 212 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (&ctx->ifc_media); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 290 /* magic number that should be high enough for any hardware */ 291 #define IFLIB_MAX_TX_SEGS 128 292 #define IFLIB_RX_COPY_THRESH 128 293 #define IFLIB_MAX_RX_REFRESH 32 294 /* The minimum descriptors per second before we start coalescing */ 295 #define IFLIB_MIN_DESC_SEC 16384 296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 297 #define IFLIB_QUEUE_IDLE 0 298 #define IFLIB_QUEUE_HUNG 1 299 #define IFLIB_QUEUE_WORKING 2 300 /* maximum number of txqs that can share an rx interrupt */ 301 #define IFLIB_MAX_TX_SHARED_INTR 4 302 303 /* this should really scale with ring size - this is a fairly arbitrary value */ 304 #define TX_BATCH_SIZE 32 305 306 #define IFLIB_RESTART_BUDGET 8 307 308 309 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 310 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 311 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 312 struct iflib_txq { 313 qidx_t ift_in_use; 314 qidx_t ift_cidx; 315 qidx_t ift_cidx_processed; 316 qidx_t ift_pidx; 317 uint8_t ift_gen; 318 uint8_t ift_br_offset; 319 uint16_t ift_npending; 320 uint16_t ift_db_pending; 321 uint16_t ift_rs_pending; 322 /* implicit pad */ 323 uint8_t ift_txd_size[8]; 324 uint64_t ift_processed; 325 uint64_t ift_cleaned; 326 uint64_t ift_cleaned_prev; 327 #if MEMORY_LOGGING 328 uint64_t ift_enqueued; 329 uint64_t ift_dequeued; 330 #endif 331 uint64_t ift_no_tx_dma_setup; 332 uint64_t ift_no_desc_avail; 333 uint64_t ift_mbuf_defrag_failed; 334 uint64_t ift_mbuf_defrag; 335 uint64_t ift_map_failed; 336 uint64_t ift_txd_encap_efbig; 337 uint64_t ift_pullups; 338 uint64_t ift_last_timer_tick; 339 340 struct mtx ift_mtx; 341 struct mtx ift_db_mtx; 342 343 /* constant values */ 344 if_ctx_t ift_ctx; 345 struct ifmp_ring *ift_br; 346 struct grouptask ift_task; 347 qidx_t ift_size; 348 uint16_t ift_id; 349 struct callout ift_timer; 350 351 if_txsd_vec_t ift_sds; 352 uint8_t ift_qstatus; 353 uint8_t ift_closed; 354 uint8_t ift_update_freq; 355 struct iflib_filter_info ift_filter_info; 356 bus_dma_tag_t ift_desc_tag; 357 bus_dma_tag_t ift_tso_desc_tag; 358 iflib_dma_info_t ift_ifdi; 359 #define MTX_NAME_LEN 16 360 char ift_mtx_name[MTX_NAME_LEN]; 361 char ift_db_mtx_name[MTX_NAME_LEN]; 362 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 363 #ifdef IFLIB_DIAGNOSTICS 364 uint64_t ift_cpu_exec_count[256]; 365 #endif 366 } __aligned(CACHE_LINE_SIZE); 367 368 struct iflib_fl { 369 qidx_t ifl_cidx; 370 qidx_t ifl_pidx; 371 qidx_t ifl_credits; 372 uint8_t ifl_gen; 373 uint8_t ifl_rxd_size; 374 #if MEMORY_LOGGING 375 uint64_t ifl_m_enqueued; 376 uint64_t ifl_m_dequeued; 377 uint64_t ifl_cl_enqueued; 378 uint64_t ifl_cl_dequeued; 379 #endif 380 /* implicit pad */ 381 382 bitstr_t *ifl_rx_bitmap; 383 qidx_t ifl_fragidx; 384 /* constant */ 385 qidx_t ifl_size; 386 uint16_t ifl_buf_size; 387 uint16_t ifl_cltype; 388 uma_zone_t ifl_zone; 389 iflib_rxsd_array_t ifl_sds; 390 iflib_rxq_t ifl_rxq; 391 uint8_t ifl_id; 392 bus_dma_tag_t ifl_desc_tag; 393 iflib_dma_info_t ifl_ifdi; 394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 395 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 397 } __aligned(CACHE_LINE_SIZE); 398 399 static inline qidx_t 400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 401 { 402 qidx_t used; 403 404 if (pidx > cidx) 405 used = pidx - cidx; 406 else if (pidx < cidx) 407 used = size - cidx + pidx; 408 else if (gen == 0 && pidx == cidx) 409 used = 0; 410 else if (gen == 1 && pidx == cidx) 411 used = size; 412 else 413 panic("bad state"); 414 415 return (used); 416 } 417 418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 419 420 #define IDXDIFF(head, tail, wrap) \ 421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 422 423 struct iflib_rxq { 424 /* If there is a separate completion queue - 425 * these are the cq cidx and pidx. Otherwise 426 * these are unused. 427 */ 428 qidx_t ifr_size; 429 qidx_t ifr_cq_cidx; 430 qidx_t ifr_cq_pidx; 431 uint8_t ifr_cq_gen; 432 uint8_t ifr_fl_offset; 433 434 if_ctx_t ifr_ctx; 435 iflib_fl_t ifr_fl; 436 uint64_t ifr_rx_irq; 437 uint16_t ifr_id; 438 uint8_t ifr_lro_enabled; 439 uint8_t ifr_nfl; 440 uint8_t ifr_ntxqirq; 441 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 442 struct lro_ctrl ifr_lc; 443 struct grouptask ifr_task; 444 struct iflib_filter_info ifr_filter_info; 445 iflib_dma_info_t ifr_ifdi; 446 447 /* dynamically allocate if any drivers need a value substantially larger than this */ 448 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 449 #ifdef IFLIB_DIAGNOSTICS 450 uint64_t ifr_cpu_exec_count[256]; 451 #endif 452 } __aligned(CACHE_LINE_SIZE); 453 454 typedef struct if_rxsd { 455 caddr_t *ifsd_cl; 456 struct mbuf **ifsd_m; 457 iflib_fl_t ifsd_fl; 458 qidx_t ifsd_cidx; 459 } *if_rxsd_t; 460 461 /* multiple of word size */ 462 #ifdef __LP64__ 463 #define PKT_INFO_SIZE 6 464 #define RXD_INFO_SIZE 5 465 #define PKT_TYPE uint64_t 466 #else 467 #define PKT_INFO_SIZE 11 468 #define RXD_INFO_SIZE 8 469 #define PKT_TYPE uint32_t 470 #endif 471 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 472 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 473 474 typedef struct if_pkt_info_pad { 475 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 476 } *if_pkt_info_pad_t; 477 typedef struct if_rxd_info_pad { 478 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 479 } *if_rxd_info_pad_t; 480 481 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 482 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 483 484 485 static inline void 486 pkt_info_zero(if_pkt_info_t pi) 487 { 488 if_pkt_info_pad_t pi_pad; 489 490 pi_pad = (if_pkt_info_pad_t)pi; 491 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 492 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 493 #ifndef __LP64__ 494 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 495 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 496 #endif 497 } 498 499 static device_method_t iflib_pseudo_methods[] = { 500 DEVMETHOD(device_attach, noop_attach), 501 DEVMETHOD(device_detach, iflib_pseudo_detach), 502 DEVMETHOD_END 503 }; 504 505 driver_t iflib_pseudodriver = { 506 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 507 }; 508 509 static inline void 510 rxd_info_zero(if_rxd_info_t ri) 511 { 512 if_rxd_info_pad_t ri_pad; 513 int i; 514 515 ri_pad = (if_rxd_info_pad_t)ri; 516 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 517 ri_pad->rxd_val[i] = 0; 518 ri_pad->rxd_val[i+1] = 0; 519 ri_pad->rxd_val[i+2] = 0; 520 ri_pad->rxd_val[i+3] = 0; 521 } 522 #ifdef __LP64__ 523 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 524 #endif 525 } 526 527 /* 528 * Only allow a single packet to take up most 1/nth of the tx ring 529 */ 530 #define MAX_SINGLE_PACKET_FRACTION 12 531 #define IF_BAD_DMA (bus_addr_t)-1 532 533 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 534 535 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 536 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 537 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 538 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 539 540 541 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 542 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 543 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 544 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 545 546 547 548 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 549 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 550 551 void 552 iflib_set_detach(if_ctx_t ctx) 553 { 554 STATE_LOCK(ctx); 555 ctx->ifc_flags |= IFC_IN_DETACH; 556 STATE_UNLOCK(ctx); 557 } 558 559 /* Our boot-time initialization hook */ 560 static int iflib_module_event_handler(module_t, int, void *); 561 562 static moduledata_t iflib_moduledata = { 563 "iflib", 564 iflib_module_event_handler, 565 NULL 566 }; 567 568 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 569 MODULE_VERSION(iflib, 1); 570 571 MODULE_DEPEND(iflib, pci, 1, 1, 1); 572 MODULE_DEPEND(iflib, ether, 1, 1, 1); 573 574 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 575 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 576 577 #ifndef IFLIB_DEBUG_COUNTERS 578 #ifdef INVARIANTS 579 #define IFLIB_DEBUG_COUNTERS 1 580 #else 581 #define IFLIB_DEBUG_COUNTERS 0 582 #endif /* !INVARIANTS */ 583 #endif 584 585 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 586 "iflib driver parameters"); 587 588 /* 589 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 590 */ 591 static int iflib_min_tx_latency = 0; 592 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 593 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 594 static int iflib_no_tx_batch = 0; 595 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 596 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 597 598 599 #if IFLIB_DEBUG_COUNTERS 600 601 static int iflib_tx_seen; 602 static int iflib_tx_sent; 603 static int iflib_tx_encap; 604 static int iflib_rx_allocs; 605 static int iflib_fl_refills; 606 static int iflib_fl_refills_large; 607 static int iflib_tx_frees; 608 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 610 &iflib_tx_seen, 0, "# tx mbufs seen"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 612 &iflib_tx_sent, 0, "# tx mbufs sent"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 614 &iflib_tx_encap, 0, "# tx mbufs encapped"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 616 &iflib_tx_frees, 0, "# tx frees"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 618 &iflib_rx_allocs, 0, "# rx allocations"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 620 &iflib_fl_refills, 0, "# refills"); 621 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 622 &iflib_fl_refills_large, 0, "# large refills"); 623 624 625 static int iflib_txq_drain_flushing; 626 static int iflib_txq_drain_oactive; 627 static int iflib_txq_drain_notready; 628 629 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 630 &iflib_txq_drain_flushing, 0, "# drain flushes"); 631 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 632 &iflib_txq_drain_oactive, 0, "# drain oactives"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 634 &iflib_txq_drain_notready, 0, "# drain notready"); 635 636 637 static int iflib_encap_load_mbuf_fail; 638 static int iflib_encap_pad_mbuf_fail; 639 static int iflib_encap_txq_avail_fail; 640 static int iflib_encap_txd_encap_fail; 641 642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 643 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 644 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 645 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 646 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 647 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 648 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 649 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 650 651 static int iflib_task_fn_rxs; 652 static int iflib_rx_intr_enables; 653 static int iflib_fast_intrs; 654 static int iflib_rx_unavail; 655 static int iflib_rx_ctx_inactive; 656 static int iflib_rx_if_input; 657 static int iflib_rx_mbuf_null; 658 static int iflib_rxd_flush; 659 660 static int iflib_verbose_debug; 661 662 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 663 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 665 &iflib_rx_intr_enables, 0, "# rx intr enables"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 667 &iflib_fast_intrs, 0, "# fast_intr calls"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 669 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 671 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 673 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 675 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 676 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 677 &iflib_rxd_flush, 0, "# times rxd_flush called"); 678 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 679 &iflib_verbose_debug, 0, "enable verbose debugging"); 680 681 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 682 static void 683 iflib_debug_reset(void) 684 { 685 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 686 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 687 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 688 iflib_txq_drain_notready = 689 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 690 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 691 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 692 iflib_rx_unavail = 693 iflib_rx_ctx_inactive = iflib_rx_if_input = 694 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 695 } 696 697 #else 698 #define DBG_COUNTER_INC(name) 699 static void iflib_debug_reset(void) {} 700 #endif 701 702 #define IFLIB_DEBUG 0 703 704 static void iflib_tx_structures_free(if_ctx_t ctx); 705 static void iflib_rx_structures_free(if_ctx_t ctx); 706 static int iflib_queues_alloc(if_ctx_t ctx); 707 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 708 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 709 static int iflib_qset_structures_setup(if_ctx_t ctx); 710 static int iflib_msix_init(if_ctx_t ctx); 711 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 712 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 713 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 714 #ifdef ALTQ 715 static void iflib_altq_if_start(if_t ifp); 716 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 717 #endif 718 static int iflib_register(if_ctx_t); 719 static void iflib_init_locked(if_ctx_t ctx); 720 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 721 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 722 static void iflib_ifmp_purge(iflib_txq_t txq); 723 static void _iflib_pre_assert(if_softc_ctx_t scctx); 724 static void iflib_if_init_locked(if_ctx_t ctx); 725 static void iflib_free_intr_mem(if_ctx_t ctx); 726 #ifndef __NO_STRICT_ALIGNMENT 727 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 728 #endif 729 730 NETDUMP_DEFINE(iflib); 731 732 #ifdef DEV_NETMAP 733 #include <sys/selinfo.h> 734 #include <net/netmap.h> 735 #include <dev/netmap/netmap_kern.h> 736 737 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 738 739 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 740 741 /* 742 * device-specific sysctl variables: 743 * 744 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 745 * During regular operations the CRC is stripped, but on some 746 * hardware reception of frames not multiple of 64 is slower, 747 * so using crcstrip=0 helps in benchmarks. 748 * 749 * iflib_rx_miss, iflib_rx_miss_bufs: 750 * count packets that might be missed due to lost interrupts. 751 */ 752 SYSCTL_DECL(_dev_netmap); 753 /* 754 * The xl driver by default strips CRCs and we do not override it. 755 */ 756 757 int iflib_crcstrip = 1; 758 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 759 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 760 761 int iflib_rx_miss, iflib_rx_miss_bufs; 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 763 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 765 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 766 767 /* 768 * Register/unregister. We are already under netmap lock. 769 * Only called on the first register or the last unregister. 770 */ 771 static int 772 iflib_netmap_register(struct netmap_adapter *na, int onoff) 773 { 774 struct ifnet *ifp = na->ifp; 775 if_ctx_t ctx = ifp->if_softc; 776 int status; 777 778 CTX_LOCK(ctx); 779 IFDI_INTR_DISABLE(ctx); 780 781 /* Tell the stack that the interface is no longer active */ 782 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 783 784 if (!CTX_IS_VF(ctx)) 785 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 786 787 /* enable or disable flags and callbacks in na and ifp */ 788 if (onoff) { 789 nm_set_native_flags(na); 790 } else { 791 nm_clear_native_flags(na); 792 } 793 iflib_stop(ctx); 794 iflib_init_locked(ctx); 795 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 796 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 797 if (status) 798 nm_clear_native_flags(na); 799 CTX_UNLOCK(ctx); 800 return (status); 801 } 802 803 static int 804 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 805 { 806 struct netmap_adapter *na = kring->na; 807 u_int const lim = kring->nkr_num_slots - 1; 808 u_int head = kring->rhead; 809 struct netmap_ring *ring = kring->ring; 810 bus_dmamap_t *map; 811 struct if_rxd_update iru; 812 if_ctx_t ctx = rxq->ifr_ctx; 813 iflib_fl_t fl = &rxq->ifr_fl[0]; 814 uint32_t refill_pidx, nic_i; 815 #if IFLIB_DEBUG_COUNTERS 816 int rf_count = 0; 817 #endif 818 819 if (nm_i == head && __predict_true(!init)) 820 return 0; 821 iru_init(&iru, rxq, 0 /* flid */); 822 map = fl->ifl_sds.ifsd_map; 823 refill_pidx = netmap_idx_k2n(kring, nm_i); 824 /* 825 * IMPORTANT: we must leave one free slot in the ring, 826 * so move head back by one unit 827 */ 828 head = nm_prev(head, lim); 829 nic_i = UINT_MAX; 830 DBG_COUNTER_INC(fl_refills); 831 while (nm_i != head) { 832 #if IFLIB_DEBUG_COUNTERS 833 if (++rf_count == 9) 834 DBG_COUNTER_INC(fl_refills_large); 835 #endif 836 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 837 struct netmap_slot *slot = &ring->slot[nm_i]; 838 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 839 uint32_t nic_i_dma = refill_pidx; 840 nic_i = netmap_idx_k2n(kring, nm_i); 841 842 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 843 844 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 845 return netmap_ring_reinit(kring); 846 847 fl->ifl_vm_addrs[tmp_pidx] = addr; 848 if (__predict_false(init) && map) { 849 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 850 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 851 /* buffer has changed, reload map */ 852 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 853 } 854 slot->flags &= ~NS_BUF_CHANGED; 855 856 nm_i = nm_next(nm_i, lim); 857 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 858 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 859 continue; 860 861 iru.iru_pidx = refill_pidx; 862 iru.iru_count = tmp_pidx+1; 863 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 864 865 refill_pidx = nic_i; 866 if (map == NULL) 867 continue; 868 869 for (int n = 0; n < iru.iru_count; n++) { 870 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 871 BUS_DMASYNC_PREREAD); 872 /* XXX - change this to not use the netmap func*/ 873 nic_i_dma = nm_next(nic_i_dma, lim); 874 } 875 } 876 } 877 kring->nr_hwcur = head; 878 879 if (map) 880 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 881 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 882 if (__predict_true(nic_i != UINT_MAX)) { 883 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 884 DBG_COUNTER_INC(rxd_flush); 885 } 886 return (0); 887 } 888 889 /* 890 * Reconcile kernel and user view of the transmit ring. 891 * 892 * All information is in the kring. 893 * Userspace wants to send packets up to the one before kring->rhead, 894 * kernel knows kring->nr_hwcur is the first unsent packet. 895 * 896 * Here we push packets out (as many as possible), and possibly 897 * reclaim buffers from previously completed transmission. 898 * 899 * The caller (netmap) guarantees that there is only one instance 900 * running at any time. Any interference with other driver 901 * methods should be handled by the individual drivers. 902 */ 903 static int 904 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 905 { 906 struct netmap_adapter *na = kring->na; 907 struct ifnet *ifp = na->ifp; 908 struct netmap_ring *ring = kring->ring; 909 u_int nm_i; /* index into the netmap kring */ 910 u_int nic_i; /* index into the NIC ring */ 911 u_int n; 912 u_int const lim = kring->nkr_num_slots - 1; 913 u_int const head = kring->rhead; 914 struct if_pkt_info pi; 915 916 /* 917 * interrupts on every tx packet are expensive so request 918 * them every half ring, or where NS_REPORT is set 919 */ 920 u_int report_frequency = kring->nkr_num_slots >> 1; 921 /* device-specific */ 922 if_ctx_t ctx = ifp->if_softc; 923 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 924 925 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 926 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 927 928 929 /* 930 * First part: process new packets to send. 931 * nm_i is the current index in the netmap kring, 932 * nic_i is the corresponding index in the NIC ring. 933 * 934 * If we have packets to send (nm_i != head) 935 * iterate over the netmap ring, fetch length and update 936 * the corresponding slot in the NIC ring. Some drivers also 937 * need to update the buffer's physical address in the NIC slot 938 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 939 * 940 * The netmap_reload_map() calls is especially expensive, 941 * even when (as in this case) the tag is 0, so do only 942 * when the buffer has actually changed. 943 * 944 * If possible do not set the report/intr bit on all slots, 945 * but only a few times per ring or when NS_REPORT is set. 946 * 947 * Finally, on 10G and faster drivers, it might be useful 948 * to prefetch the next slot and txr entry. 949 */ 950 951 nm_i = kring->nr_hwcur; 952 if (nm_i != head) { /* we have new packets to send */ 953 pkt_info_zero(&pi); 954 pi.ipi_segs = txq->ift_segs; 955 pi.ipi_qsidx = kring->ring_id; 956 nic_i = netmap_idx_k2n(kring, nm_i); 957 958 __builtin_prefetch(&ring->slot[nm_i]); 959 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 960 if (txq->ift_sds.ifsd_map) 961 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 962 963 for (n = 0; nm_i != head; n++) { 964 struct netmap_slot *slot = &ring->slot[nm_i]; 965 u_int len = slot->len; 966 uint64_t paddr; 967 void *addr = PNMB(na, slot, &paddr); 968 int flags = (slot->flags & NS_REPORT || 969 nic_i == 0 || nic_i == report_frequency) ? 970 IPI_TX_INTR : 0; 971 972 /* device-specific */ 973 pi.ipi_len = len; 974 pi.ipi_segs[0].ds_addr = paddr; 975 pi.ipi_segs[0].ds_len = len; 976 pi.ipi_nsegs = 1; 977 pi.ipi_ndescs = 0; 978 pi.ipi_pidx = nic_i; 979 pi.ipi_flags = flags; 980 981 /* Fill the slot in the NIC ring. */ 982 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 983 DBG_COUNTER_INC(tx_encap); 984 985 /* prefetch for next round */ 986 __builtin_prefetch(&ring->slot[nm_i + 1]); 987 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 988 if (txq->ift_sds.ifsd_map) { 989 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 990 991 NM_CHECK_ADDR_LEN(na, addr, len); 992 993 if (slot->flags & NS_BUF_CHANGED) { 994 /* buffer has changed, reload map */ 995 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 996 } 997 /* make sure changes to the buffer are synced */ 998 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 999 BUS_DMASYNC_PREWRITE); 1000 } 1001 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1002 nm_i = nm_next(nm_i, lim); 1003 nic_i = nm_next(nic_i, lim); 1004 } 1005 kring->nr_hwcur = nm_i; 1006 1007 /* synchronize the NIC ring */ 1008 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1009 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1010 1011 /* (re)start the tx unit up to slot nic_i (excluded) */ 1012 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1013 } 1014 1015 /* 1016 * Second part: reclaim buffers for completed transmissions. 1017 * 1018 * If there are unclaimed buffers, attempt to reclaim them. 1019 * If none are reclaimed, and TX IRQs are not in use, do an initial 1020 * minimal delay, then trigger the tx handler which will spin in the 1021 * group task queue. 1022 */ 1023 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1024 if (iflib_tx_credits_update(ctx, txq)) { 1025 /* some tx completed, increment avail */ 1026 nic_i = txq->ift_cidx_processed; 1027 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1028 } 1029 } 1030 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1031 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1032 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1033 iflib_timer, txq, txq->ift_timer.c_cpu); 1034 } 1035 return (0); 1036 } 1037 1038 /* 1039 * Reconcile kernel and user view of the receive ring. 1040 * Same as for the txsync, this routine must be efficient. 1041 * The caller guarantees a single invocations, but races against 1042 * the rest of the driver should be handled here. 1043 * 1044 * On call, kring->rhead is the first packet that userspace wants 1045 * to keep, and kring->rcur is the wakeup point. 1046 * The kernel has previously reported packets up to kring->rtail. 1047 * 1048 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1049 * of whether or not we received an interrupt. 1050 */ 1051 static int 1052 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1053 { 1054 struct netmap_adapter *na = kring->na; 1055 struct netmap_ring *ring = kring->ring; 1056 uint32_t nm_i; /* index into the netmap ring */ 1057 uint32_t nic_i; /* index into the NIC ring */ 1058 u_int i, n; 1059 u_int const lim = kring->nkr_num_slots - 1; 1060 u_int const head = kring->rhead; 1061 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1062 struct if_rxd_info ri; 1063 1064 struct ifnet *ifp = na->ifp; 1065 if_ctx_t ctx = ifp->if_softc; 1066 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1067 iflib_fl_t fl = rxq->ifr_fl; 1068 if (head > lim) 1069 return netmap_ring_reinit(kring); 1070 1071 /* XXX check sync modes */ 1072 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1073 if (fl->ifl_sds.ifsd_map == NULL) 1074 continue; 1075 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1076 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1077 } 1078 /* 1079 * First part: import newly received packets. 1080 * 1081 * nm_i is the index of the next free slot in the netmap ring, 1082 * nic_i is the index of the next received packet in the NIC ring, 1083 * and they may differ in case if_init() has been called while 1084 * in netmap mode. For the receive ring we have 1085 * 1086 * nic_i = rxr->next_check; 1087 * nm_i = kring->nr_hwtail (previous) 1088 * and 1089 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1090 * 1091 * rxr->next_check is set to 0 on a ring reinit 1092 */ 1093 if (netmap_no_pendintr || force_update) { 1094 int crclen = iflib_crcstrip ? 0 : 4; 1095 int error, avail; 1096 1097 for (i = 0; i < rxq->ifr_nfl; i++) { 1098 fl = &rxq->ifr_fl[i]; 1099 nic_i = fl->ifl_cidx; 1100 nm_i = netmap_idx_n2k(kring, nic_i); 1101 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1102 for (n = 0; avail > 0; n++, avail--) { 1103 rxd_info_zero(&ri); 1104 ri.iri_frags = rxq->ifr_frags; 1105 ri.iri_qsidx = kring->ring_id; 1106 ri.iri_ifp = ctx->ifc_ifp; 1107 ri.iri_cidx = nic_i; 1108 1109 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1110 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1111 ring->slot[nm_i].flags = 0; 1112 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1113 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1114 nm_i = nm_next(nm_i, lim); 1115 nic_i = nm_next(nic_i, lim); 1116 } 1117 if (n) { /* update the state variables */ 1118 if (netmap_no_pendintr && !force_update) { 1119 /* diagnostics */ 1120 iflib_rx_miss ++; 1121 iflib_rx_miss_bufs += n; 1122 } 1123 fl->ifl_cidx = nic_i; 1124 kring->nr_hwtail = nm_i; 1125 } 1126 kring->nr_kflags &= ~NKR_PENDINTR; 1127 } 1128 } 1129 /* 1130 * Second part: skip past packets that userspace has released. 1131 * (kring->nr_hwcur to head excluded), 1132 * and make the buffers available for reception. 1133 * As usual nm_i is the index in the netmap ring, 1134 * nic_i is the index in the NIC ring, and 1135 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1136 */ 1137 /* XXX not sure how this will work with multiple free lists */ 1138 nm_i = kring->nr_hwcur; 1139 1140 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1141 } 1142 1143 static void 1144 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1145 { 1146 struct ifnet *ifp = na->ifp; 1147 if_ctx_t ctx = ifp->if_softc; 1148 1149 CTX_LOCK(ctx); 1150 if (onoff) { 1151 IFDI_INTR_ENABLE(ctx); 1152 } else { 1153 IFDI_INTR_DISABLE(ctx); 1154 } 1155 CTX_UNLOCK(ctx); 1156 } 1157 1158 1159 static int 1160 iflib_netmap_attach(if_ctx_t ctx) 1161 { 1162 struct netmap_adapter na; 1163 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1164 1165 bzero(&na, sizeof(na)); 1166 1167 na.ifp = ctx->ifc_ifp; 1168 na.na_flags = NAF_BDG_MAYSLEEP; 1169 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1170 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1171 1172 na.num_tx_desc = scctx->isc_ntxd[0]; 1173 na.num_rx_desc = scctx->isc_nrxd[0]; 1174 na.nm_txsync = iflib_netmap_txsync; 1175 na.nm_rxsync = iflib_netmap_rxsync; 1176 na.nm_register = iflib_netmap_register; 1177 na.nm_intr = iflib_netmap_intr; 1178 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1179 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1180 return (netmap_attach(&na)); 1181 } 1182 1183 static void 1184 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1185 { 1186 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1187 struct netmap_slot *slot; 1188 1189 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1190 if (slot == NULL) 1191 return; 1192 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1193 1194 /* 1195 * In netmap mode, set the map for the packet buffer. 1196 * NOTE: Some drivers (not this one) also need to set 1197 * the physical buffer address in the NIC ring. 1198 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1199 * netmap slot index, si 1200 */ 1201 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1202 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1203 } 1204 } 1205 1206 static void 1207 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1208 { 1209 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1210 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1211 struct netmap_slot *slot; 1212 uint32_t nm_i; 1213 1214 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1215 if (slot == NULL) 1216 return; 1217 nm_i = netmap_idx_n2k(kring, 0); 1218 netmap_fl_refill(rxq, kring, nm_i, true); 1219 } 1220 1221 static void 1222 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on) 1223 { 1224 struct netmap_kring *kring; 1225 1226 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1227 1228 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1229 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1230 netmap_tx_irq(ctx->ifc_ifp, txqid); 1231 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1232 if (hz < 2000) 1233 *reset_on = 1; 1234 else 1235 *reset_on = hz / 1000; 1236 } 1237 } 1238 } 1239 1240 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1241 1242 #else 1243 #define iflib_netmap_txq_init(ctx, txq) 1244 #define iflib_netmap_rxq_init(ctx, rxq) 1245 #define iflib_netmap_detach(ifp) 1246 1247 #define iflib_netmap_attach(ctx) (0) 1248 #define netmap_rx_irq(ifp, qid, budget) (0) 1249 #define netmap_tx_irq(ifp, qid) do {} while (0) 1250 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on) 1251 1252 #endif 1253 1254 #if defined(__i386__) || defined(__amd64__) 1255 static __inline void 1256 prefetch(void *x) 1257 { 1258 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1259 } 1260 static __inline void 1261 prefetch2cachelines(void *x) 1262 { 1263 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1264 #if (CACHE_LINE_SIZE < 128) 1265 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1266 #endif 1267 } 1268 #else 1269 #define prefetch(x) 1270 #define prefetch2cachelines(x) 1271 #endif 1272 1273 static void 1274 iflib_gen_mac(if_ctx_t ctx) 1275 { 1276 struct thread *td; 1277 MD5_CTX mdctx; 1278 char uuid[HOSTUUIDLEN+1]; 1279 char buf[HOSTUUIDLEN+16]; 1280 uint8_t *mac; 1281 unsigned char digest[16]; 1282 1283 td = curthread; 1284 mac = ctx->ifc_mac; 1285 uuid[HOSTUUIDLEN] = 0; 1286 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN); 1287 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev)); 1288 /* 1289 * Generate a pseudo-random, deterministic MAC 1290 * address based on the UUID and unit number. 1291 * The FreeBSD Foundation OUI of 58-9C-FC is used. 1292 */ 1293 MD5Init(&mdctx); 1294 MD5Update(&mdctx, buf, strlen(buf)); 1295 MD5Final(digest, &mdctx); 1296 1297 mac[0] = 0x58; 1298 mac[1] = 0x9C; 1299 mac[2] = 0xFC; 1300 mac[3] = digest[0]; 1301 mac[4] = digest[1]; 1302 mac[5] = digest[2]; 1303 } 1304 1305 static void 1306 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1307 { 1308 iflib_fl_t fl; 1309 1310 fl = &rxq->ifr_fl[flid]; 1311 iru->iru_paddrs = fl->ifl_bus_addrs; 1312 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1313 iru->iru_idxs = fl->ifl_rxd_idxs; 1314 iru->iru_qsidx = rxq->ifr_id; 1315 iru->iru_buf_size = fl->ifl_buf_size; 1316 iru->iru_flidx = fl->ifl_id; 1317 } 1318 1319 static void 1320 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1321 { 1322 if (err) 1323 return; 1324 *(bus_addr_t *) arg = segs[0].ds_addr; 1325 } 1326 1327 int 1328 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1329 { 1330 int err; 1331 device_t dev = ctx->ifc_dev; 1332 1333 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1334 align, 0, /* alignment, bounds */ 1335 BUS_SPACE_MAXADDR, /* lowaddr */ 1336 BUS_SPACE_MAXADDR, /* highaddr */ 1337 NULL, NULL, /* filter, filterarg */ 1338 size, /* maxsize */ 1339 1, /* nsegments */ 1340 size, /* maxsegsize */ 1341 BUS_DMA_ALLOCNOW, /* flags */ 1342 NULL, /* lockfunc */ 1343 NULL, /* lockarg */ 1344 &dma->idi_tag); 1345 if (err) { 1346 device_printf(dev, 1347 "%s: bus_dma_tag_create failed: %d\n", 1348 __func__, err); 1349 goto fail_0; 1350 } 1351 1352 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1353 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1354 if (err) { 1355 device_printf(dev, 1356 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1357 __func__, (uintmax_t)size, err); 1358 goto fail_1; 1359 } 1360 1361 dma->idi_paddr = IF_BAD_DMA; 1362 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1363 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1364 if (err || dma->idi_paddr == IF_BAD_DMA) { 1365 device_printf(dev, 1366 "%s: bus_dmamap_load failed: %d\n", 1367 __func__, err); 1368 goto fail_2; 1369 } 1370 1371 dma->idi_size = size; 1372 return (0); 1373 1374 fail_2: 1375 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1376 fail_1: 1377 bus_dma_tag_destroy(dma->idi_tag); 1378 fail_0: 1379 dma->idi_tag = NULL; 1380 1381 return (err); 1382 } 1383 1384 int 1385 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1386 { 1387 if_shared_ctx_t sctx = ctx->ifc_sctx; 1388 1389 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1390 1391 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1392 } 1393 1394 int 1395 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1396 { 1397 int i, err; 1398 iflib_dma_info_t *dmaiter; 1399 1400 dmaiter = dmalist; 1401 for (i = 0; i < count; i++, dmaiter++) { 1402 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1403 break; 1404 } 1405 if (err) 1406 iflib_dma_free_multi(dmalist, i); 1407 return (err); 1408 } 1409 1410 void 1411 iflib_dma_free(iflib_dma_info_t dma) 1412 { 1413 if (dma->idi_tag == NULL) 1414 return; 1415 if (dma->idi_paddr != IF_BAD_DMA) { 1416 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1417 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1418 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1419 dma->idi_paddr = IF_BAD_DMA; 1420 } 1421 if (dma->idi_vaddr != NULL) { 1422 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1423 dma->idi_vaddr = NULL; 1424 } 1425 bus_dma_tag_destroy(dma->idi_tag); 1426 dma->idi_tag = NULL; 1427 } 1428 1429 void 1430 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1431 { 1432 int i; 1433 iflib_dma_info_t *dmaiter = dmalist; 1434 1435 for (i = 0; i < count; i++, dmaiter++) 1436 iflib_dma_free(*dmaiter); 1437 } 1438 1439 #ifdef EARLY_AP_STARTUP 1440 static const int iflib_started = 1; 1441 #else 1442 /* 1443 * We used to abuse the smp_started flag to decide if the queues have been 1444 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1445 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1446 * is set. Run a SYSINIT() strictly after that to just set a usable 1447 * completion flag. 1448 */ 1449 1450 static int iflib_started; 1451 1452 static void 1453 iflib_record_started(void *arg) 1454 { 1455 iflib_started = 1; 1456 } 1457 1458 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1459 iflib_record_started, NULL); 1460 #endif 1461 1462 static int 1463 iflib_fast_intr(void *arg) 1464 { 1465 iflib_filter_info_t info = arg; 1466 struct grouptask *gtask = info->ifi_task; 1467 if (!iflib_started) 1468 return (FILTER_HANDLED); 1469 1470 DBG_COUNTER_INC(fast_intrs); 1471 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1472 return (FILTER_HANDLED); 1473 1474 GROUPTASK_ENQUEUE(gtask); 1475 return (FILTER_HANDLED); 1476 } 1477 1478 static int 1479 iflib_fast_intr_rxtx(void *arg) 1480 { 1481 iflib_filter_info_t info = arg; 1482 struct grouptask *gtask = info->ifi_task; 1483 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1484 if_ctx_t ctx = NULL;; 1485 int i, cidx; 1486 1487 if (!iflib_started) 1488 return (FILTER_HANDLED); 1489 1490 DBG_COUNTER_INC(fast_intrs); 1491 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1492 return (FILTER_HANDLED); 1493 1494 MPASS(rxq->ifr_ntxqirq); 1495 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1496 qidx_t txqid = rxq->ifr_txqid[i]; 1497 1498 ctx = rxq->ifr_ctx; 1499 1500 bus_dmamap_sync(rxq->ifr_ifdi->idi_tag, rxq->ifr_ifdi->idi_map, 1501 BUS_DMASYNC_POSTREAD); 1502 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1503 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1504 continue; 1505 } 1506 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1507 } 1508 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1509 cidx = rxq->ifr_cq_cidx; 1510 else 1511 cidx = rxq->ifr_fl[0].ifl_cidx; 1512 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1513 GROUPTASK_ENQUEUE(gtask); 1514 else { 1515 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1516 DBG_COUNTER_INC(rx_intr_enables); 1517 } 1518 return (FILTER_HANDLED); 1519 } 1520 1521 1522 static int 1523 iflib_fast_intr_ctx(void *arg) 1524 { 1525 iflib_filter_info_t info = arg; 1526 struct grouptask *gtask = info->ifi_task; 1527 1528 if (!iflib_started) 1529 return (FILTER_HANDLED); 1530 1531 DBG_COUNTER_INC(fast_intrs); 1532 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1533 return (FILTER_HANDLED); 1534 1535 GROUPTASK_ENQUEUE(gtask); 1536 return (FILTER_HANDLED); 1537 } 1538 1539 static int 1540 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1541 driver_filter_t filter, driver_intr_t handler, void *arg, 1542 const char *name) 1543 { 1544 int rc, flags; 1545 struct resource *res; 1546 void *tag = NULL; 1547 device_t dev = ctx->ifc_dev; 1548 1549 flags = RF_ACTIVE; 1550 if (ctx->ifc_flags & IFC_LEGACY) 1551 flags |= RF_SHAREABLE; 1552 MPASS(rid < 512); 1553 irq->ii_rid = rid; 1554 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1555 if (res == NULL) { 1556 device_printf(dev, 1557 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1558 return (ENOMEM); 1559 } 1560 irq->ii_res = res; 1561 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1562 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1563 filter, handler, arg, &tag); 1564 if (rc != 0) { 1565 device_printf(dev, 1566 "failed to setup interrupt for rid %d, name %s: %d\n", 1567 rid, name ? name : "unknown", rc); 1568 return (rc); 1569 } else if (name) 1570 bus_describe_intr(dev, res, tag, "%s", name); 1571 1572 irq->ii_tag = tag; 1573 return (0); 1574 } 1575 1576 1577 /********************************************************************* 1578 * 1579 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1580 * the information needed to transmit a packet on the wire. This is 1581 * called only once at attach, setup is done every reset. 1582 * 1583 **********************************************************************/ 1584 1585 static int 1586 iflib_txsd_alloc(iflib_txq_t txq) 1587 { 1588 if_ctx_t ctx = txq->ift_ctx; 1589 if_shared_ctx_t sctx = ctx->ifc_sctx; 1590 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1591 device_t dev = ctx->ifc_dev; 1592 bus_size_t tsomaxsize; 1593 int err, nsegments, ntsosegments; 1594 bool tso; 1595 1596 nsegments = scctx->isc_tx_nsegments; 1597 ntsosegments = scctx->isc_tx_tso_segments_max; 1598 tsomaxsize = scctx->isc_tx_tso_size_max; 1599 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1600 tsomaxsize += sizeof(struct ether_vlan_header); 1601 MPASS(scctx->isc_ntxd[0] > 0); 1602 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1603 MPASS(nsegments > 0); 1604 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1605 MPASS(ntsosegments > 0); 1606 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1607 } 1608 1609 /* 1610 * Setup DMA descriptor areas. 1611 */ 1612 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1613 1, 0, /* alignment, bounds */ 1614 BUS_SPACE_MAXADDR, /* lowaddr */ 1615 BUS_SPACE_MAXADDR, /* highaddr */ 1616 NULL, NULL, /* filter, filterarg */ 1617 sctx->isc_tx_maxsize, /* maxsize */ 1618 nsegments, /* nsegments */ 1619 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1620 0, /* flags */ 1621 NULL, /* lockfunc */ 1622 NULL, /* lockfuncarg */ 1623 &txq->ift_desc_tag))) { 1624 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1625 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1626 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1627 goto fail; 1628 } 1629 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1630 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1631 1, 0, /* alignment, bounds */ 1632 BUS_SPACE_MAXADDR, /* lowaddr */ 1633 BUS_SPACE_MAXADDR, /* highaddr */ 1634 NULL, NULL, /* filter, filterarg */ 1635 tsomaxsize, /* maxsize */ 1636 ntsosegments, /* nsegments */ 1637 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1638 0, /* flags */ 1639 NULL, /* lockfunc */ 1640 NULL, /* lockfuncarg */ 1641 &txq->ift_tso_desc_tag))) { 1642 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1643 goto fail; 1644 } 1645 if (!(txq->ift_sds.ifsd_m = 1646 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1647 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1648 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1649 err = ENOMEM; 1650 goto fail; 1651 } 1652 1653 /* Create the descriptor buffer dma maps */ 1654 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1655 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1656 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1657 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1658 err = ENOMEM; 1659 goto fail; 1660 } 1661 1662 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1663 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1664 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1665 device_printf(dev, "Unable to allocate TSO tx_buffer " 1666 "map memory\n"); 1667 err = ENOMEM; 1668 goto fail; 1669 } 1670 1671 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1672 err = bus_dmamap_create(txq->ift_desc_tag, 0, 1673 &txq->ift_sds.ifsd_map[i]); 1674 if (err != 0) { 1675 device_printf(dev, "Unable to create TX DMA map\n"); 1676 goto fail; 1677 } 1678 if (!tso) 1679 continue; 1680 err = bus_dmamap_create(txq->ift_tso_desc_tag, 0, 1681 &txq->ift_sds.ifsd_tso_map[i]); 1682 if (err != 0) { 1683 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1684 goto fail; 1685 } 1686 } 1687 return (0); 1688 fail: 1689 /* We free all, it handles case where we are in the middle */ 1690 iflib_tx_structures_free(ctx); 1691 return (err); 1692 } 1693 1694 static void 1695 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1696 { 1697 bus_dmamap_t map; 1698 1699 map = NULL; 1700 if (txq->ift_sds.ifsd_map != NULL) 1701 map = txq->ift_sds.ifsd_map[i]; 1702 if (map != NULL) { 1703 bus_dmamap_sync(txq->ift_desc_tag, map, BUS_DMASYNC_POSTWRITE); 1704 bus_dmamap_unload(txq->ift_desc_tag, map); 1705 bus_dmamap_destroy(txq->ift_desc_tag, map); 1706 txq->ift_sds.ifsd_map[i] = NULL; 1707 } 1708 1709 map = NULL; 1710 if (txq->ift_sds.ifsd_tso_map != NULL) 1711 map = txq->ift_sds.ifsd_tso_map[i]; 1712 if (map != NULL) { 1713 bus_dmamap_sync(txq->ift_tso_desc_tag, map, 1714 BUS_DMASYNC_POSTWRITE); 1715 bus_dmamap_unload(txq->ift_tso_desc_tag, map); 1716 bus_dmamap_destroy(txq->ift_tso_desc_tag, map); 1717 txq->ift_sds.ifsd_tso_map[i] = NULL; 1718 } 1719 } 1720 1721 static void 1722 iflib_txq_destroy(iflib_txq_t txq) 1723 { 1724 if_ctx_t ctx = txq->ift_ctx; 1725 1726 for (int i = 0; i < txq->ift_size; i++) 1727 iflib_txsd_destroy(ctx, txq, i); 1728 if (txq->ift_sds.ifsd_map != NULL) { 1729 free(txq->ift_sds.ifsd_map, M_IFLIB); 1730 txq->ift_sds.ifsd_map = NULL; 1731 } 1732 if (txq->ift_sds.ifsd_tso_map != NULL) { 1733 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1734 txq->ift_sds.ifsd_tso_map = NULL; 1735 } 1736 if (txq->ift_sds.ifsd_m != NULL) { 1737 free(txq->ift_sds.ifsd_m, M_IFLIB); 1738 txq->ift_sds.ifsd_m = NULL; 1739 } 1740 if (txq->ift_desc_tag != NULL) { 1741 bus_dma_tag_destroy(txq->ift_desc_tag); 1742 txq->ift_desc_tag = NULL; 1743 } 1744 if (txq->ift_tso_desc_tag != NULL) { 1745 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1746 txq->ift_tso_desc_tag = NULL; 1747 } 1748 } 1749 1750 static void 1751 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1752 { 1753 struct mbuf **mp; 1754 1755 mp = &txq->ift_sds.ifsd_m[i]; 1756 if (*mp == NULL) 1757 return; 1758 1759 if (txq->ift_sds.ifsd_map != NULL) { 1760 bus_dmamap_sync(txq->ift_desc_tag, 1761 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1762 bus_dmamap_unload(txq->ift_desc_tag, txq->ift_sds.ifsd_map[i]); 1763 } 1764 if (txq->ift_sds.ifsd_tso_map != NULL) { 1765 bus_dmamap_sync(txq->ift_tso_desc_tag, 1766 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1767 bus_dmamap_unload(txq->ift_tso_desc_tag, 1768 txq->ift_sds.ifsd_tso_map[i]); 1769 } 1770 m_free(*mp); 1771 DBG_COUNTER_INC(tx_frees); 1772 *mp = NULL; 1773 } 1774 1775 static int 1776 iflib_txq_setup(iflib_txq_t txq) 1777 { 1778 if_ctx_t ctx = txq->ift_ctx; 1779 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1780 if_shared_ctx_t sctx = ctx->ifc_sctx; 1781 iflib_dma_info_t di; 1782 int i; 1783 1784 /* Set number of descriptors available */ 1785 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1786 /* XXX make configurable */ 1787 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1788 1789 /* Reset indices */ 1790 txq->ift_cidx_processed = 0; 1791 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1792 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1793 1794 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1795 bzero((void *)di->idi_vaddr, di->idi_size); 1796 1797 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1798 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1799 bus_dmamap_sync(di->idi_tag, di->idi_map, 1800 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1801 return (0); 1802 } 1803 1804 /********************************************************************* 1805 * 1806 * Allocate memory for rx_buffer structures. Since we use one 1807 * rx_buffer per received packet, the maximum number of rx_buffer's 1808 * that we'll need is equal to the number of receive descriptors 1809 * that we've allocated. 1810 * 1811 **********************************************************************/ 1812 static int 1813 iflib_rxsd_alloc(iflib_rxq_t rxq) 1814 { 1815 if_ctx_t ctx = rxq->ifr_ctx; 1816 if_shared_ctx_t sctx = ctx->ifc_sctx; 1817 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1818 device_t dev = ctx->ifc_dev; 1819 iflib_fl_t fl; 1820 int err; 1821 1822 MPASS(scctx->isc_nrxd[0] > 0); 1823 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1824 1825 fl = rxq->ifr_fl; 1826 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1827 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1828 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1829 1, 0, /* alignment, bounds */ 1830 BUS_SPACE_MAXADDR, /* lowaddr */ 1831 BUS_SPACE_MAXADDR, /* highaddr */ 1832 NULL, NULL, /* filter, filterarg */ 1833 sctx->isc_rx_maxsize, /* maxsize */ 1834 sctx->isc_rx_nsegments, /* nsegments */ 1835 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1836 0, /* flags */ 1837 NULL, /* lockfunc */ 1838 NULL, /* lockarg */ 1839 &fl->ifl_desc_tag); 1840 if (err) { 1841 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1842 __func__, err); 1843 goto fail; 1844 } 1845 if (!(fl->ifl_sds.ifsd_m = 1846 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1847 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1848 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1849 err = ENOMEM; 1850 goto fail; 1851 } 1852 if (!(fl->ifl_sds.ifsd_cl = 1853 (caddr_t *) malloc(sizeof(caddr_t) * 1854 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1855 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1856 err = ENOMEM; 1857 goto fail; 1858 } 1859 1860 if (!(fl->ifl_sds.ifsd_ba = 1861 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1862 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1863 device_printf(dev, "Unable to allocate rx bus addr memory\n"); 1864 err = ENOMEM; 1865 goto fail; 1866 } 1867 1868 /* Create the descriptor buffer dma maps */ 1869 if (!(fl->ifl_sds.ifsd_map = 1870 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1871 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1872 err = ENOMEM; 1873 goto fail; 1874 } 1875 1876 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1877 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1878 if (err != 0) { 1879 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1880 goto fail; 1881 } 1882 } 1883 } 1884 return (0); 1885 1886 fail: 1887 iflib_rx_structures_free(ctx); 1888 return (err); 1889 } 1890 1891 1892 /* 1893 * Internal service routines 1894 */ 1895 1896 struct rxq_refill_cb_arg { 1897 int error; 1898 bus_dma_segment_t seg; 1899 int nseg; 1900 }; 1901 1902 static void 1903 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1904 { 1905 struct rxq_refill_cb_arg *cb_arg = arg; 1906 1907 cb_arg->error = error; 1908 cb_arg->seg = segs[0]; 1909 cb_arg->nseg = nseg; 1910 } 1911 1912 /** 1913 * rxq_refill - refill an rxq free-buffer list 1914 * @ctx: the iflib context 1915 * @rxq: the free-list to refill 1916 * @n: the number of new buffers to allocate 1917 * 1918 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1919 * The caller must assure that @n does not exceed the queue's capacity. 1920 */ 1921 static void 1922 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1923 { 1924 struct mbuf *m; 1925 int idx, frag_idx = fl->ifl_fragidx; 1926 int pidx = fl->ifl_pidx; 1927 caddr_t cl, *sd_cl; 1928 struct mbuf **sd_m; 1929 struct if_rxd_update iru; 1930 struct rxq_refill_cb_arg cb_arg; 1931 bus_dmamap_t *sd_map; 1932 int n, i = 0; 1933 bus_addr_t bus_addr, *sd_ba; 1934 int err; 1935 qidx_t credits; 1936 1937 sd_m = fl->ifl_sds.ifsd_m; 1938 sd_map = fl->ifl_sds.ifsd_map; 1939 sd_cl = fl->ifl_sds.ifsd_cl; 1940 sd_ba = fl->ifl_sds.ifsd_ba; 1941 idx = pidx; 1942 credits = fl->ifl_credits; 1943 1944 n = count; 1945 MPASS(n > 0); 1946 MPASS(credits + n <= fl->ifl_size); 1947 1948 if (pidx < fl->ifl_cidx) 1949 MPASS(pidx + n <= fl->ifl_cidx); 1950 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1951 MPASS(fl->ifl_gen == 0); 1952 if (pidx > fl->ifl_cidx) 1953 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1954 1955 DBG_COUNTER_INC(fl_refills); 1956 if (n > 8) 1957 DBG_COUNTER_INC(fl_refills_large); 1958 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1959 while (n--) { 1960 /* 1961 * We allocate an uninitialized mbuf + cluster, mbuf is 1962 * initialized after rx. 1963 * 1964 * If the cluster is still set then we know a minimum sized packet was received 1965 */ 1966 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1967 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1968 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1969 if ((cl = sd_cl[frag_idx]) == NULL) { 1970 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1971 break; 1972 1973 cb_arg.error = 0; 1974 MPASS(sd_map != NULL); 1975 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1976 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 1977 BUS_DMA_NOWAIT); 1978 if (err != 0 || cb_arg.error) { 1979 /* 1980 * !zone_pack ? 1981 */ 1982 if (fl->ifl_zone == zone_pack) 1983 uma_zfree(fl->ifl_zone, cl); 1984 break; 1985 } 1986 1987 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1988 BUS_DMASYNC_PREREAD); 1989 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 1990 sd_cl[frag_idx] = cl; 1991 #if MEMORY_LOGGING 1992 fl->ifl_cl_enqueued++; 1993 #endif 1994 } else { 1995 bus_addr = sd_ba[frag_idx]; 1996 } 1997 1998 bit_set(fl->ifl_rx_bitmap, frag_idx); 1999 MPASS(sd_m[frag_idx] == NULL); 2000 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2001 break; 2002 } 2003 sd_m[frag_idx] = m; 2004 #if MEMORY_LOGGING 2005 fl->ifl_m_enqueued++; 2006 #endif 2007 2008 DBG_COUNTER_INC(rx_allocs); 2009 fl->ifl_rxd_idxs[i] = frag_idx; 2010 fl->ifl_bus_addrs[i] = bus_addr; 2011 fl->ifl_vm_addrs[i] = cl; 2012 credits++; 2013 i++; 2014 MPASS(credits <= fl->ifl_size); 2015 if (++idx == fl->ifl_size) { 2016 fl->ifl_gen = 1; 2017 idx = 0; 2018 } 2019 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2020 iru.iru_pidx = pidx; 2021 iru.iru_count = i; 2022 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2023 i = 0; 2024 pidx = idx; 2025 fl->ifl_pidx = idx; 2026 fl->ifl_credits = credits; 2027 } 2028 2029 } 2030 2031 if (i) { 2032 iru.iru_pidx = pidx; 2033 iru.iru_count = i; 2034 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2035 fl->ifl_pidx = idx; 2036 fl->ifl_credits = credits; 2037 } 2038 DBG_COUNTER_INC(rxd_flush); 2039 if (fl->ifl_pidx == 0) 2040 pidx = fl->ifl_size - 1; 2041 else 2042 pidx = fl->ifl_pidx - 1; 2043 2044 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2045 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2046 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2047 fl->ifl_fragidx = frag_idx; 2048 } 2049 2050 static __inline void 2051 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2052 { 2053 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2054 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2055 #ifdef INVARIANTS 2056 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2057 #endif 2058 2059 MPASS(fl->ifl_credits <= fl->ifl_size); 2060 MPASS(reclaimable == delta); 2061 2062 if (reclaimable > 0) 2063 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2064 } 2065 2066 uint8_t 2067 iflib_in_detach(if_ctx_t ctx) 2068 { 2069 bool in_detach; 2070 STATE_LOCK(ctx); 2071 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2072 STATE_UNLOCK(ctx); 2073 return (in_detach); 2074 } 2075 2076 static void 2077 iflib_fl_bufs_free(iflib_fl_t fl) 2078 { 2079 iflib_dma_info_t idi = fl->ifl_ifdi; 2080 bus_dmamap_t sd_map; 2081 uint32_t i; 2082 2083 for (i = 0; i < fl->ifl_size; i++) { 2084 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2085 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2086 2087 if (*sd_cl != NULL) { 2088 sd_map = fl->ifl_sds.ifsd_map[i]; 2089 bus_dmamap_sync(fl->ifl_desc_tag, sd_map, 2090 BUS_DMASYNC_POSTREAD); 2091 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 2092 if (*sd_cl != NULL) 2093 uma_zfree(fl->ifl_zone, *sd_cl); 2094 // XXX: Should this get moved out? 2095 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2096 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 2097 if (*sd_m != NULL) { 2098 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2099 uma_zfree(zone_mbuf, *sd_m); 2100 } 2101 } else { 2102 MPASS(*sd_cl == NULL); 2103 MPASS(*sd_m == NULL); 2104 } 2105 #if MEMORY_LOGGING 2106 fl->ifl_m_dequeued++; 2107 fl->ifl_cl_dequeued++; 2108 #endif 2109 *sd_cl = NULL; 2110 *sd_m = NULL; 2111 } 2112 #ifdef INVARIANTS 2113 for (i = 0; i < fl->ifl_size; i++) { 2114 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2115 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2116 } 2117 #endif 2118 /* 2119 * Reset free list values 2120 */ 2121 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2122 bzero(idi->idi_vaddr, idi->idi_size); 2123 } 2124 2125 /********************************************************************* 2126 * 2127 * Initialize a receive ring and its buffers. 2128 * 2129 **********************************************************************/ 2130 static int 2131 iflib_fl_setup(iflib_fl_t fl) 2132 { 2133 iflib_rxq_t rxq = fl->ifl_rxq; 2134 if_ctx_t ctx = rxq->ifr_ctx; 2135 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2136 2137 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2138 /* 2139 ** Free current RX buffer structs and their mbufs 2140 */ 2141 iflib_fl_bufs_free(fl); 2142 /* Now replenish the mbufs */ 2143 MPASS(fl->ifl_credits == 0); 2144 /* 2145 * XXX don't set the max_frame_size to larger 2146 * than the hardware can handle 2147 */ 2148 if (sctx->isc_max_frame_size <= 2048) 2149 fl->ifl_buf_size = MCLBYTES; 2150 #ifndef CONTIGMALLOC_WORKS 2151 else 2152 fl->ifl_buf_size = MJUMPAGESIZE; 2153 #else 2154 else if (sctx->isc_max_frame_size <= 4096) 2155 fl->ifl_buf_size = MJUMPAGESIZE; 2156 else if (sctx->isc_max_frame_size <= 9216) 2157 fl->ifl_buf_size = MJUM9BYTES; 2158 else 2159 fl->ifl_buf_size = MJUM16BYTES; 2160 #endif 2161 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2162 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2163 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2164 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2165 2166 2167 /* avoid pre-allocating zillions of clusters to an idle card 2168 * potentially speeding up attach 2169 */ 2170 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2171 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2172 if (min(128, fl->ifl_size) != fl->ifl_credits) 2173 return (ENOBUFS); 2174 /* 2175 * handle failure 2176 */ 2177 MPASS(rxq != NULL); 2178 MPASS(fl->ifl_ifdi != NULL); 2179 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2180 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2181 return (0); 2182 } 2183 2184 /********************************************************************* 2185 * 2186 * Free receive ring data structures 2187 * 2188 **********************************************************************/ 2189 static void 2190 iflib_rx_sds_free(iflib_rxq_t rxq) 2191 { 2192 iflib_fl_t fl; 2193 int i, j; 2194 2195 if (rxq->ifr_fl != NULL) { 2196 for (i = 0; i < rxq->ifr_nfl; i++) { 2197 fl = &rxq->ifr_fl[i]; 2198 if (fl->ifl_desc_tag != NULL) { 2199 if (fl->ifl_sds.ifsd_map != NULL) { 2200 for (j = 0; j < fl->ifl_size; j++) { 2201 if (fl->ifl_sds.ifsd_map[j] == 2202 NULL) 2203 continue; 2204 bus_dmamap_sync( 2205 fl->ifl_desc_tag, 2206 fl->ifl_sds.ifsd_map[j], 2207 BUS_DMASYNC_POSTREAD); 2208 bus_dmamap_unload( 2209 fl->ifl_desc_tag, 2210 fl->ifl_sds.ifsd_map[j]); 2211 } 2212 } 2213 bus_dma_tag_destroy(fl->ifl_desc_tag); 2214 fl->ifl_desc_tag = NULL; 2215 } 2216 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2217 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2218 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2219 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2220 fl->ifl_sds.ifsd_m = NULL; 2221 fl->ifl_sds.ifsd_cl = NULL; 2222 fl->ifl_sds.ifsd_ba = NULL; 2223 fl->ifl_sds.ifsd_map = NULL; 2224 } 2225 free(rxq->ifr_fl, M_IFLIB); 2226 rxq->ifr_fl = NULL; 2227 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2228 } 2229 } 2230 2231 /* 2232 * MI independent logic 2233 * 2234 */ 2235 static void 2236 iflib_timer(void *arg) 2237 { 2238 iflib_txq_t txq = arg; 2239 if_ctx_t ctx = txq->ift_ctx; 2240 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2241 uint64_t this_tick = ticks; 2242 uint32_t reset_on = hz / 2; 2243 2244 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2245 return; 2246 /* 2247 ** Check on the state of the TX queue(s), this 2248 ** can be done without the lock because its RO 2249 ** and the HUNG state will be static if set. 2250 */ 2251 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2252 txq->ift_last_timer_tick = this_tick; 2253 IFDI_TIMER(ctx, txq->ift_id); 2254 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2255 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2256 (sctx->isc_pause_frames == 0))) 2257 goto hung; 2258 2259 if (ifmp_ring_is_stalled(txq->ift_br)) 2260 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2261 txq->ift_cleaned_prev = txq->ift_cleaned; 2262 } 2263 #ifdef DEV_NETMAP 2264 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2265 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on); 2266 #endif 2267 /* handle any laggards */ 2268 if (txq->ift_db_pending) 2269 GROUPTASK_ENQUEUE(&txq->ift_task); 2270 2271 sctx->isc_pause_frames = 0; 2272 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2273 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2274 return; 2275 hung: 2276 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2277 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2278 STATE_LOCK(ctx); 2279 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2280 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2281 iflib_admin_intr_deferred(ctx); 2282 STATE_UNLOCK(ctx); 2283 } 2284 2285 static void 2286 iflib_init_locked(if_ctx_t ctx) 2287 { 2288 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2289 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2290 if_t ifp = ctx->ifc_ifp; 2291 iflib_fl_t fl; 2292 iflib_txq_t txq; 2293 iflib_rxq_t rxq; 2294 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2295 2296 2297 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2298 IFDI_INTR_DISABLE(ctx); 2299 2300 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2301 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2302 /* Set hardware offload abilities */ 2303 if_clearhwassist(ifp); 2304 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2305 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2306 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2307 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2308 if (if_getcapenable(ifp) & IFCAP_TSO4) 2309 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2310 if (if_getcapenable(ifp) & IFCAP_TSO6) 2311 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2312 2313 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2314 CALLOUT_LOCK(txq); 2315 callout_stop(&txq->ift_timer); 2316 CALLOUT_UNLOCK(txq); 2317 iflib_netmap_txq_init(ctx, txq); 2318 } 2319 #ifdef INVARIANTS 2320 i = if_getdrvflags(ifp); 2321 #endif 2322 IFDI_INIT(ctx); 2323 MPASS(if_getdrvflags(ifp) == i); 2324 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2325 /* XXX this should really be done on a per-queue basis */ 2326 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2327 MPASS(rxq->ifr_id == i); 2328 iflib_netmap_rxq_init(ctx, rxq); 2329 continue; 2330 } 2331 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2332 if (iflib_fl_setup(fl)) { 2333 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2334 goto done; 2335 } 2336 } 2337 } 2338 done: 2339 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2340 IFDI_INTR_ENABLE(ctx); 2341 txq = ctx->ifc_txqs; 2342 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2343 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2344 txq->ift_timer.c_cpu); 2345 } 2346 2347 static int 2348 iflib_media_change(if_t ifp) 2349 { 2350 if_ctx_t ctx = if_getsoftc(ifp); 2351 int err; 2352 2353 CTX_LOCK(ctx); 2354 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2355 iflib_init_locked(ctx); 2356 CTX_UNLOCK(ctx); 2357 return (err); 2358 } 2359 2360 static void 2361 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2362 { 2363 if_ctx_t ctx = if_getsoftc(ifp); 2364 2365 CTX_LOCK(ctx); 2366 IFDI_UPDATE_ADMIN_STATUS(ctx); 2367 IFDI_MEDIA_STATUS(ctx, ifmr); 2368 CTX_UNLOCK(ctx); 2369 } 2370 2371 void 2372 iflib_stop(if_ctx_t ctx) 2373 { 2374 iflib_txq_t txq = ctx->ifc_txqs; 2375 iflib_rxq_t rxq = ctx->ifc_rxqs; 2376 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2377 if_shared_ctx_t sctx = ctx->ifc_sctx; 2378 iflib_dma_info_t di; 2379 iflib_fl_t fl; 2380 int i, j; 2381 2382 /* Tell the stack that the interface is no longer active */ 2383 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2384 2385 IFDI_INTR_DISABLE(ctx); 2386 DELAY(1000); 2387 IFDI_STOP(ctx); 2388 DELAY(1000); 2389 2390 iflib_debug_reset(); 2391 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2392 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2393 /* make sure all transmitters have completed before proceeding XXX */ 2394 2395 CALLOUT_LOCK(txq); 2396 callout_stop(&txq->ift_timer); 2397 CALLOUT_UNLOCK(txq); 2398 2399 /* clean any enqueued buffers */ 2400 iflib_ifmp_purge(txq); 2401 /* Free any existing tx buffers. */ 2402 for (j = 0; j < txq->ift_size; j++) { 2403 iflib_txsd_free(ctx, txq, j); 2404 } 2405 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2406 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2407 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2408 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2409 txq->ift_pullups = 0; 2410 ifmp_ring_reset_stats(txq->ift_br); 2411 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2412 bzero((void *)di->idi_vaddr, di->idi_size); 2413 } 2414 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2415 /* make sure all transmitters have completed before proceeding XXX */ 2416 2417 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2418 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2419 bzero((void *)di->idi_vaddr, di->idi_size); 2420 /* also resets the free lists pidx/cidx */ 2421 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2422 iflib_fl_bufs_free(fl); 2423 } 2424 } 2425 2426 static inline caddr_t 2427 calc_next_rxd(iflib_fl_t fl, int cidx) 2428 { 2429 qidx_t size; 2430 int nrxd; 2431 caddr_t start, end, cur, next; 2432 2433 nrxd = fl->ifl_size; 2434 size = fl->ifl_rxd_size; 2435 start = fl->ifl_ifdi->idi_vaddr; 2436 2437 if (__predict_false(size == 0)) 2438 return (start); 2439 cur = start + size*cidx; 2440 end = start + size*nrxd; 2441 next = CACHE_PTR_NEXT(cur); 2442 return (next < end ? next : start); 2443 } 2444 2445 static inline void 2446 prefetch_pkts(iflib_fl_t fl, int cidx) 2447 { 2448 int nextptr; 2449 int nrxd = fl->ifl_size; 2450 caddr_t next_rxd; 2451 2452 2453 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2454 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2455 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2456 next_rxd = calc_next_rxd(fl, cidx); 2457 prefetch(next_rxd); 2458 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2459 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2460 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2461 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2462 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2463 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2464 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2465 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2466 } 2467 2468 static void 2469 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2470 { 2471 int flid, cidx; 2472 bus_dmamap_t map; 2473 iflib_fl_t fl; 2474 iflib_dma_info_t di; 2475 int next; 2476 2477 map = NULL; 2478 flid = irf->irf_flid; 2479 cidx = irf->irf_idx; 2480 fl = &rxq->ifr_fl[flid]; 2481 sd->ifsd_fl = fl; 2482 sd->ifsd_cidx = cidx; 2483 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2484 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2485 fl->ifl_credits--; 2486 #if MEMORY_LOGGING 2487 fl->ifl_m_dequeued++; 2488 #endif 2489 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2490 prefetch_pkts(fl, cidx); 2491 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2492 prefetch(&fl->ifl_sds.ifsd_map[next]); 2493 map = fl->ifl_sds.ifsd_map[cidx]; 2494 di = fl->ifl_ifdi; 2495 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2496 2497 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2498 MPASS(fl->ifl_cidx == cidx); 2499 bus_dmamap_sync(fl->ifl_desc_tag, map, BUS_DMASYNC_POSTREAD); 2500 if (unload) 2501 bus_dmamap_unload(fl->ifl_desc_tag, map); 2502 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2503 if (__predict_false(fl->ifl_cidx == 0)) 2504 fl->ifl_gen = 0; 2505 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2506 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2507 bit_clear(fl->ifl_rx_bitmap, cidx); 2508 } 2509 2510 static struct mbuf * 2511 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2512 { 2513 int i, padlen , flags; 2514 struct mbuf *m, *mh, *mt; 2515 caddr_t cl; 2516 2517 i = 0; 2518 mh = NULL; 2519 do { 2520 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2521 2522 MPASS(*sd->ifsd_cl != NULL); 2523 MPASS(*sd->ifsd_m != NULL); 2524 2525 /* Don't include zero-length frags */ 2526 if (ri->iri_frags[i].irf_len == 0) { 2527 /* XXX we can save the cluster here, but not the mbuf */ 2528 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2529 m_free(*sd->ifsd_m); 2530 *sd->ifsd_m = NULL; 2531 continue; 2532 } 2533 m = *sd->ifsd_m; 2534 *sd->ifsd_m = NULL; 2535 if (mh == NULL) { 2536 flags = M_PKTHDR|M_EXT; 2537 mh = mt = m; 2538 padlen = ri->iri_pad; 2539 } else { 2540 flags = M_EXT; 2541 mt->m_next = m; 2542 mt = m; 2543 /* assuming padding is only on the first fragment */ 2544 padlen = 0; 2545 } 2546 cl = *sd->ifsd_cl; 2547 *sd->ifsd_cl = NULL; 2548 2549 /* Can these two be made one ? */ 2550 m_init(m, M_NOWAIT, MT_DATA, flags); 2551 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2552 /* 2553 * These must follow m_init and m_cljset 2554 */ 2555 m->m_data += padlen; 2556 ri->iri_len -= padlen; 2557 m->m_len = ri->iri_frags[i].irf_len; 2558 } while (++i < ri->iri_nfrags); 2559 2560 return (mh); 2561 } 2562 2563 /* 2564 * Process one software descriptor 2565 */ 2566 static struct mbuf * 2567 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2568 { 2569 struct if_rxsd sd; 2570 struct mbuf *m; 2571 2572 /* should I merge this back in now that the two paths are basically duplicated? */ 2573 if (ri->iri_nfrags == 1 && 2574 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2575 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2576 m = *sd.ifsd_m; 2577 *sd.ifsd_m = NULL; 2578 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2579 #ifndef __NO_STRICT_ALIGNMENT 2580 if (!IP_ALIGNED(m)) 2581 m->m_data += 2; 2582 #endif 2583 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2584 bus_dmamap_sync(rxq->ifr_fl->ifl_desc_tag, 2585 rxq->ifr_fl->ifl_sds.ifsd_map[ri->iri_frags[0].irf_idx], 2586 BUS_DMASYNC_PREREAD); 2587 m->m_len = ri->iri_frags[0].irf_len; 2588 } else { 2589 m = assemble_segments(rxq, ri, &sd); 2590 } 2591 m->m_pkthdr.len = ri->iri_len; 2592 m->m_pkthdr.rcvif = ri->iri_ifp; 2593 m->m_flags |= ri->iri_flags; 2594 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2595 m->m_pkthdr.flowid = ri->iri_flowid; 2596 M_HASHTYPE_SET(m, ri->iri_rsstype); 2597 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2598 m->m_pkthdr.csum_data = ri->iri_csum_data; 2599 return (m); 2600 } 2601 2602 #if defined(INET6) || defined(INET) 2603 static void 2604 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2605 { 2606 CURVNET_SET(lc->ifp->if_vnet); 2607 #if defined(INET6) 2608 *v6 = VNET(ip6_forwarding); 2609 #endif 2610 #if defined(INET) 2611 *v4 = VNET(ipforwarding); 2612 #endif 2613 CURVNET_RESTORE(); 2614 } 2615 2616 /* 2617 * Returns true if it's possible this packet could be LROed. 2618 * if it returns false, it is guaranteed that tcp_lro_rx() 2619 * would not return zero. 2620 */ 2621 static bool 2622 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2623 { 2624 struct ether_header *eh; 2625 uint16_t eh_type; 2626 2627 eh = mtod(m, struct ether_header *); 2628 eh_type = ntohs(eh->ether_type); 2629 switch (eh_type) { 2630 #if defined(INET6) 2631 case ETHERTYPE_IPV6: 2632 return !v6_forwarding; 2633 #endif 2634 #if defined (INET) 2635 case ETHERTYPE_IP: 2636 return !v4_forwarding; 2637 #endif 2638 } 2639 2640 return false; 2641 } 2642 #else 2643 static void 2644 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2645 { 2646 } 2647 #endif 2648 2649 static bool 2650 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2651 { 2652 if_ctx_t ctx = rxq->ifr_ctx; 2653 if_shared_ctx_t sctx = ctx->ifc_sctx; 2654 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2655 iflib_dma_info_t di; 2656 int avail, i; 2657 qidx_t *cidxp; 2658 struct if_rxd_info ri; 2659 int err, budget_left, rx_bytes, rx_pkts; 2660 iflib_fl_t fl; 2661 struct ifnet *ifp; 2662 int lro_enabled; 2663 bool v4_forwarding, v6_forwarding, lro_possible; 2664 2665 /* 2666 * XXX early demux data packets so that if_input processing only handles 2667 * acks in interrupt context 2668 */ 2669 struct mbuf *m, *mh, *mt, *mf; 2670 2671 lro_possible = v4_forwarding = v6_forwarding = false; 2672 ifp = ctx->ifc_ifp; 2673 mh = mt = NULL; 2674 MPASS(budget > 0); 2675 rx_pkts = rx_bytes = 0; 2676 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2677 cidxp = &rxq->ifr_cq_cidx; 2678 else 2679 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2680 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2681 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2682 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2683 DBG_COUNTER_INC(rx_unavail); 2684 return (false); 2685 } 2686 2687 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2688 if (__predict_false(!CTX_ACTIVE(ctx))) { 2689 DBG_COUNTER_INC(rx_ctx_inactive); 2690 break; 2691 } 2692 /* 2693 * Reset client set fields to their default values 2694 */ 2695 rxd_info_zero(&ri); 2696 ri.iri_qsidx = rxq->ifr_id; 2697 ri.iri_cidx = *cidxp; 2698 ri.iri_ifp = ifp; 2699 ri.iri_frags = rxq->ifr_frags; 2700 di = rxq->ifr_fl[rxq->ifr_frags[0].irf_flid].ifl_ifdi; 2701 bus_dmamap_sync(di->idi_tag, di->idi_map, 2702 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2703 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2704 2705 if (err) 2706 goto err; 2707 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2708 *cidxp = ri.iri_cidx; 2709 /* Update our consumer index */ 2710 /* XXX NB: shurd - check if this is still safe */ 2711 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2712 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2713 rxq->ifr_cq_gen = 0; 2714 } 2715 /* was this only a completion queue message? */ 2716 if (__predict_false(ri.iri_nfrags == 0)) 2717 continue; 2718 } 2719 MPASS(ri.iri_nfrags != 0); 2720 MPASS(ri.iri_len != 0); 2721 2722 /* will advance the cidx on the corresponding free lists */ 2723 m = iflib_rxd_pkt_get(rxq, &ri); 2724 avail--; 2725 budget_left--; 2726 if (avail == 0 && budget_left) 2727 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2728 2729 if (__predict_false(m == NULL)) { 2730 DBG_COUNTER_INC(rx_mbuf_null); 2731 continue; 2732 } 2733 /* imm_pkt: -- cxgb */ 2734 if (mh == NULL) 2735 mh = mt = m; 2736 else { 2737 mt->m_nextpkt = m; 2738 mt = m; 2739 } 2740 } 2741 /* make sure that we can refill faster than drain */ 2742 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2743 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2744 2745 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2746 if (lro_enabled) 2747 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2748 mt = mf = NULL; 2749 while (mh != NULL) { 2750 m = mh; 2751 mh = mh->m_nextpkt; 2752 m->m_nextpkt = NULL; 2753 #ifndef __NO_STRICT_ALIGNMENT 2754 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2755 continue; 2756 #endif 2757 rx_bytes += m->m_pkthdr.len; 2758 rx_pkts++; 2759 #if defined(INET6) || defined(INET) 2760 if (lro_enabled) { 2761 if (!lro_possible) { 2762 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2763 if (lro_possible && mf != NULL) { 2764 ifp->if_input(ifp, mf); 2765 DBG_COUNTER_INC(rx_if_input); 2766 mt = mf = NULL; 2767 } 2768 } 2769 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2770 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2771 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2772 continue; 2773 } 2774 } 2775 #endif 2776 if (lro_possible) { 2777 ifp->if_input(ifp, m); 2778 DBG_COUNTER_INC(rx_if_input); 2779 continue; 2780 } 2781 2782 if (mf == NULL) 2783 mf = m; 2784 if (mt != NULL) 2785 mt->m_nextpkt = m; 2786 mt = m; 2787 } 2788 if (mf != NULL) { 2789 ifp->if_input(ifp, mf); 2790 DBG_COUNTER_INC(rx_if_input); 2791 } 2792 2793 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2794 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2795 2796 /* 2797 * Flush any outstanding LRO work 2798 */ 2799 #if defined(INET6) || defined(INET) 2800 tcp_lro_flush_all(&rxq->ifr_lc); 2801 #endif 2802 if (avail) 2803 return true; 2804 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2805 err: 2806 STATE_LOCK(ctx); 2807 ctx->ifc_flags |= IFC_DO_RESET; 2808 iflib_admin_intr_deferred(ctx); 2809 STATE_UNLOCK(ctx); 2810 return (false); 2811 } 2812 2813 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2814 static inline qidx_t 2815 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2816 { 2817 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2818 qidx_t minthresh = txq->ift_size / 8; 2819 if (in_use > 4*minthresh) 2820 return (notify_count); 2821 if (in_use > 2*minthresh) 2822 return (notify_count >> 1); 2823 if (in_use > minthresh) 2824 return (notify_count >> 3); 2825 return (0); 2826 } 2827 2828 static inline qidx_t 2829 txq_max_rs_deferred(iflib_txq_t txq) 2830 { 2831 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2832 qidx_t minthresh = txq->ift_size / 8; 2833 if (txq->ift_in_use > 4*minthresh) 2834 return (notify_count); 2835 if (txq->ift_in_use > 2*minthresh) 2836 return (notify_count >> 1); 2837 if (txq->ift_in_use > minthresh) 2838 return (notify_count >> 2); 2839 return (2); 2840 } 2841 2842 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2843 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2844 2845 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2846 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2847 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2848 2849 /* forward compatibility for cxgb */ 2850 #define FIRST_QSET(ctx) 0 2851 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2852 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2853 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2854 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2855 2856 /* XXX we should be setting this to something other than zero */ 2857 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2858 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2859 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2860 2861 static inline bool 2862 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2863 { 2864 qidx_t dbval, max; 2865 bool rang; 2866 2867 rang = false; 2868 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2869 if (ring || txq->ift_db_pending >= max) { 2870 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2871 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2872 txq->ift_db_pending = txq->ift_npending = 0; 2873 rang = true; 2874 } 2875 return (rang); 2876 } 2877 2878 #ifdef PKT_DEBUG 2879 static void 2880 print_pkt(if_pkt_info_t pi) 2881 { 2882 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2883 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2884 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2885 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2886 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2887 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2888 } 2889 #endif 2890 2891 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2892 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2893 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2894 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2895 2896 static int 2897 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2898 { 2899 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2900 struct ether_vlan_header *eh; 2901 struct mbuf *m; 2902 2903 m = *mp; 2904 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2905 M_WRITABLE(m) == 0) { 2906 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2907 return (ENOMEM); 2908 } else { 2909 m_freem(*mp); 2910 DBG_COUNTER_INC(tx_frees); 2911 *mp = m; 2912 } 2913 } 2914 2915 /* 2916 * Determine where frame payload starts. 2917 * Jump over vlan headers if already present, 2918 * helpful for QinQ too. 2919 */ 2920 if (__predict_false(m->m_len < sizeof(*eh))) { 2921 txq->ift_pullups++; 2922 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2923 return (ENOMEM); 2924 } 2925 eh = mtod(m, struct ether_vlan_header *); 2926 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2927 pi->ipi_etype = ntohs(eh->evl_proto); 2928 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2929 } else { 2930 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2931 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2932 } 2933 2934 switch (pi->ipi_etype) { 2935 #ifdef INET 2936 case ETHERTYPE_IP: 2937 { 2938 struct mbuf *n; 2939 struct ip *ip = NULL; 2940 struct tcphdr *th = NULL; 2941 int minthlen; 2942 2943 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2944 if (__predict_false(m->m_len < minthlen)) { 2945 /* 2946 * if this code bloat is causing too much of a hit 2947 * move it to a separate function and mark it noinline 2948 */ 2949 if (m->m_len == pi->ipi_ehdrlen) { 2950 n = m->m_next; 2951 MPASS(n); 2952 if (n->m_len >= sizeof(*ip)) { 2953 ip = (struct ip *)n->m_data; 2954 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2955 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2956 } else { 2957 txq->ift_pullups++; 2958 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2959 return (ENOMEM); 2960 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2961 } 2962 } else { 2963 txq->ift_pullups++; 2964 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2965 return (ENOMEM); 2966 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2967 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2968 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2969 } 2970 } else { 2971 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2972 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2973 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2974 } 2975 pi->ipi_ip_hlen = ip->ip_hl << 2; 2976 pi->ipi_ipproto = ip->ip_p; 2977 pi->ipi_flags |= IPI_TX_IPV4; 2978 2979 /* TCP checksum offload may require TCP header length */ 2980 if (IS_TX_OFFLOAD4(pi)) { 2981 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 2982 if (__predict_false(th == NULL)) { 2983 txq->ift_pullups++; 2984 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2985 return (ENOMEM); 2986 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2987 } 2988 pi->ipi_tcp_hflags = th->th_flags; 2989 pi->ipi_tcp_hlen = th->th_off << 2; 2990 pi->ipi_tcp_seq = th->th_seq; 2991 } 2992 if (IS_TSO4(pi)) { 2993 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2994 return (ENXIO); 2995 /* 2996 * TSO always requires hardware checksum offload. 2997 */ 2998 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 2999 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3000 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3001 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3002 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3003 ip->ip_sum = 0; 3004 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3005 } 3006 } 3007 } 3008 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3009 ip->ip_sum = 0; 3010 3011 break; 3012 } 3013 #endif 3014 #ifdef INET6 3015 case ETHERTYPE_IPV6: 3016 { 3017 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3018 struct tcphdr *th; 3019 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3020 3021 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3022 txq->ift_pullups++; 3023 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3024 return (ENOMEM); 3025 } 3026 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3027 3028 /* XXX-BZ this will go badly in case of ext hdrs. */ 3029 pi->ipi_ipproto = ip6->ip6_nxt; 3030 pi->ipi_flags |= IPI_TX_IPV6; 3031 3032 /* TCP checksum offload may require TCP header length */ 3033 if (IS_TX_OFFLOAD6(pi)) { 3034 if (pi->ipi_ipproto == IPPROTO_TCP) { 3035 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3036 txq->ift_pullups++; 3037 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3038 return (ENOMEM); 3039 } 3040 pi->ipi_tcp_hflags = th->th_flags; 3041 pi->ipi_tcp_hlen = th->th_off << 2; 3042 pi->ipi_tcp_seq = th->th_seq; 3043 } 3044 if (IS_TSO6(pi)) { 3045 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3046 return (ENXIO); 3047 /* 3048 * TSO always requires hardware checksum offload. 3049 */ 3050 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3051 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3052 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3053 } 3054 } 3055 break; 3056 } 3057 #endif 3058 default: 3059 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3060 pi->ipi_ip_hlen = 0; 3061 break; 3062 } 3063 *mp = m; 3064 3065 return (0); 3066 } 3067 3068 /* 3069 * If dodgy hardware rejects the scatter gather chain we've handed it 3070 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3071 * m_defrag'd mbufs 3072 */ 3073 static __noinline struct mbuf * 3074 iflib_remove_mbuf(iflib_txq_t txq) 3075 { 3076 int ntxd, pidx; 3077 struct mbuf *m, **ifsd_m; 3078 3079 ifsd_m = txq->ift_sds.ifsd_m; 3080 ntxd = txq->ift_size; 3081 pidx = txq->ift_pidx & (ntxd - 1); 3082 ifsd_m = txq->ift_sds.ifsd_m; 3083 m = ifsd_m[pidx]; 3084 ifsd_m[pidx] = NULL; 3085 bus_dmamap_unload(txq->ift_desc_tag, txq->ift_sds.ifsd_map[pidx]); 3086 if (txq->ift_sds.ifsd_tso_map != NULL) 3087 bus_dmamap_unload(txq->ift_tso_desc_tag, 3088 txq->ift_sds.ifsd_tso_map[pidx]); 3089 #if MEMORY_LOGGING 3090 txq->ift_dequeued++; 3091 #endif 3092 return (m); 3093 } 3094 3095 static inline caddr_t 3096 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3097 { 3098 qidx_t size; 3099 int ntxd; 3100 caddr_t start, end, cur, next; 3101 3102 ntxd = txq->ift_size; 3103 size = txq->ift_txd_size[qid]; 3104 start = txq->ift_ifdi[qid].idi_vaddr; 3105 3106 if (__predict_false(size == 0)) 3107 return (start); 3108 cur = start + size*cidx; 3109 end = start + size*ntxd; 3110 next = CACHE_PTR_NEXT(cur); 3111 return (next < end ? next : start); 3112 } 3113 3114 /* 3115 * Pad an mbuf to ensure a minimum ethernet frame size. 3116 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3117 */ 3118 static __noinline int 3119 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3120 { 3121 /* 3122 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3123 * and ARP message is the smallest common payload I can think of 3124 */ 3125 static char pad[18]; /* just zeros */ 3126 int n; 3127 struct mbuf *new_head; 3128 3129 if (!M_WRITABLE(*m_head)) { 3130 new_head = m_dup(*m_head, M_NOWAIT); 3131 if (new_head == NULL) { 3132 m_freem(*m_head); 3133 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3134 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3135 DBG_COUNTER_INC(tx_frees); 3136 return ENOMEM; 3137 } 3138 m_freem(*m_head); 3139 *m_head = new_head; 3140 } 3141 3142 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3143 n > 0; n -= sizeof(pad)) 3144 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3145 break; 3146 3147 if (n > 0) { 3148 m_freem(*m_head); 3149 device_printf(dev, "cannot pad short frame\n"); 3150 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3151 DBG_COUNTER_INC(tx_frees); 3152 return (ENOBUFS); 3153 } 3154 3155 return 0; 3156 } 3157 3158 static int 3159 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3160 { 3161 if_ctx_t ctx; 3162 if_shared_ctx_t sctx; 3163 if_softc_ctx_t scctx; 3164 bus_dma_segment_t *segs; 3165 struct mbuf *m_head, **ifsd_m; 3166 void *next_txd; 3167 bus_dmamap_t map; 3168 struct if_pkt_info pi; 3169 int remap = 0; 3170 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3171 bus_dma_tag_t desc_tag; 3172 3173 ctx = txq->ift_ctx; 3174 sctx = ctx->ifc_sctx; 3175 scctx = &ctx->ifc_softc_ctx; 3176 segs = txq->ift_segs; 3177 ntxd = txq->ift_size; 3178 m_head = *m_headp; 3179 map = NULL; 3180 3181 /* 3182 * If we're doing TSO the next descriptor to clean may be quite far ahead 3183 */ 3184 cidx = txq->ift_cidx; 3185 pidx = txq->ift_pidx; 3186 if (ctx->ifc_flags & IFC_PREFETCH) { 3187 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3188 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3189 next_txd = calc_next_txd(txq, cidx, 0); 3190 prefetch(next_txd); 3191 } 3192 3193 /* prefetch the next cache line of mbuf pointers and flags */ 3194 prefetch(&txq->ift_sds.ifsd_m[next]); 3195 prefetch(&txq->ift_sds.ifsd_map[next]); 3196 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3197 } 3198 map = txq->ift_sds.ifsd_map[pidx]; 3199 ifsd_m = txq->ift_sds.ifsd_m; 3200 3201 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3202 desc_tag = txq->ift_tso_desc_tag; 3203 max_segs = scctx->isc_tx_tso_segments_max; 3204 map = txq->ift_sds.ifsd_tso_map[pidx]; 3205 MPASS(desc_tag != NULL); 3206 MPASS(max_segs > 0); 3207 } else { 3208 desc_tag = txq->ift_desc_tag; 3209 max_segs = scctx->isc_tx_nsegments; 3210 map = txq->ift_sds.ifsd_map[pidx]; 3211 } 3212 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3213 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3214 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3215 if (err) { 3216 DBG_COUNTER_INC(encap_txd_encap_fail); 3217 return err; 3218 } 3219 } 3220 m_head = *m_headp; 3221 3222 pkt_info_zero(&pi); 3223 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3224 pi.ipi_pidx = pidx; 3225 pi.ipi_qsidx = txq->ift_id; 3226 pi.ipi_len = m_head->m_pkthdr.len; 3227 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3228 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3229 3230 /* deliberate bitwise OR to make one condition */ 3231 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3232 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3233 DBG_COUNTER_INC(encap_txd_encap_fail); 3234 return (err); 3235 } 3236 m_head = *m_headp; 3237 } 3238 3239 retry: 3240 err = bus_dmamap_load_mbuf_sg(desc_tag, map, m_head, segs, &nsegs, 3241 BUS_DMA_NOWAIT); 3242 defrag: 3243 if (__predict_false(err)) { 3244 switch (err) { 3245 case EFBIG: 3246 /* try collapse once and defrag once */ 3247 if (remap == 0) { 3248 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3249 /* try defrag if collapsing fails */ 3250 if (m_head == NULL) 3251 remap++; 3252 } 3253 if (remap == 1) { 3254 txq->ift_mbuf_defrag++; 3255 m_head = m_defrag(*m_headp, M_NOWAIT); 3256 } 3257 remap++; 3258 if (__predict_false(m_head == NULL)) 3259 goto defrag_failed; 3260 *m_headp = m_head; 3261 goto retry; 3262 break; 3263 case ENOMEM: 3264 txq->ift_no_tx_dma_setup++; 3265 break; 3266 default: 3267 txq->ift_no_tx_dma_setup++; 3268 m_freem(*m_headp); 3269 DBG_COUNTER_INC(tx_frees); 3270 *m_headp = NULL; 3271 break; 3272 } 3273 txq->ift_map_failed++; 3274 DBG_COUNTER_INC(encap_load_mbuf_fail); 3275 DBG_COUNTER_INC(encap_txd_encap_fail); 3276 return (err); 3277 } 3278 ifsd_m[pidx] = m_head; 3279 /* 3280 * XXX assumes a 1 to 1 relationship between segments and 3281 * descriptors - this does not hold true on all drivers, e.g. 3282 * cxgb 3283 */ 3284 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3285 txq->ift_no_desc_avail++; 3286 bus_dmamap_unload(desc_tag, map); 3287 DBG_COUNTER_INC(encap_txq_avail_fail); 3288 DBG_COUNTER_INC(encap_txd_encap_fail); 3289 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3290 GROUPTASK_ENQUEUE(&txq->ift_task); 3291 return (ENOBUFS); 3292 } 3293 /* 3294 * On Intel cards we can greatly reduce the number of TX interrupts 3295 * we see by only setting report status on every Nth descriptor. 3296 * However, this also means that the driver will need to keep track 3297 * of the descriptors that RS was set on to check them for the DD bit. 3298 */ 3299 txq->ift_rs_pending += nsegs + 1; 3300 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3301 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3302 pi.ipi_flags |= IPI_TX_INTR; 3303 txq->ift_rs_pending = 0; 3304 } 3305 3306 pi.ipi_segs = segs; 3307 pi.ipi_nsegs = nsegs; 3308 3309 MPASS(pidx >= 0 && pidx < txq->ift_size); 3310 #ifdef PKT_DEBUG 3311 print_pkt(&pi); 3312 #endif 3313 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3314 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3315 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3316 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3317 DBG_COUNTER_INC(tx_encap); 3318 MPASS(pi.ipi_new_pidx < txq->ift_size); 3319 3320 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3321 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3322 ndesc += txq->ift_size; 3323 txq->ift_gen = 1; 3324 } 3325 /* 3326 * drivers can need as many as 3327 * two sentinels 3328 */ 3329 MPASS(ndesc <= pi.ipi_nsegs + 2); 3330 MPASS(pi.ipi_new_pidx != pidx); 3331 MPASS(ndesc > 0); 3332 txq->ift_in_use += ndesc; 3333 3334 /* 3335 * We update the last software descriptor again here because there may 3336 * be a sentinel and/or there may be more mbufs than segments 3337 */ 3338 txq->ift_pidx = pi.ipi_new_pidx; 3339 txq->ift_npending += pi.ipi_ndescs; 3340 } else { 3341 *m_headp = m_head = iflib_remove_mbuf(txq); 3342 if (err == EFBIG) { 3343 txq->ift_txd_encap_efbig++; 3344 if (remap < 2) { 3345 remap = 1; 3346 goto defrag; 3347 } 3348 } 3349 goto defrag_failed; 3350 } 3351 /* 3352 * err can't possibly be non-zero here, so we don't neet to test it 3353 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3354 */ 3355 return (err); 3356 3357 defrag_failed: 3358 txq->ift_mbuf_defrag_failed++; 3359 txq->ift_map_failed++; 3360 m_freem(*m_headp); 3361 DBG_COUNTER_INC(tx_frees); 3362 *m_headp = NULL; 3363 DBG_COUNTER_INC(encap_txd_encap_fail); 3364 return (ENOMEM); 3365 } 3366 3367 static void 3368 iflib_tx_desc_free(iflib_txq_t txq, int n) 3369 { 3370 uint32_t qsize, cidx, mask, gen; 3371 struct mbuf *m, **ifsd_m; 3372 bool do_prefetch; 3373 3374 cidx = txq->ift_cidx; 3375 gen = txq->ift_gen; 3376 qsize = txq->ift_size; 3377 mask = qsize-1; 3378 ifsd_m = txq->ift_sds.ifsd_m; 3379 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3380 3381 while (n-- > 0) { 3382 if (do_prefetch) { 3383 prefetch(ifsd_m[(cidx + 3) & mask]); 3384 prefetch(ifsd_m[(cidx + 4) & mask]); 3385 } 3386 if ((m = ifsd_m[cidx]) != NULL) { 3387 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3388 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3389 bus_dmamap_sync(txq->ift_tso_desc_tag, 3390 txq->ift_sds.ifsd_tso_map[cidx], 3391 BUS_DMASYNC_POSTWRITE); 3392 bus_dmamap_unload(txq->ift_tso_desc_tag, 3393 txq->ift_sds.ifsd_tso_map[cidx]); 3394 } else { 3395 bus_dmamap_sync(txq->ift_desc_tag, 3396 txq->ift_sds.ifsd_map[cidx], 3397 BUS_DMASYNC_POSTWRITE); 3398 bus_dmamap_unload(txq->ift_desc_tag, 3399 txq->ift_sds.ifsd_map[cidx]); 3400 } 3401 /* XXX we don't support any drivers that batch packets yet */ 3402 MPASS(m->m_nextpkt == NULL); 3403 m_freem(m); 3404 ifsd_m[cidx] = NULL; 3405 #if MEMORY_LOGGING 3406 txq->ift_dequeued++; 3407 #endif 3408 DBG_COUNTER_INC(tx_frees); 3409 } 3410 if (__predict_false(++cidx == qsize)) { 3411 cidx = 0; 3412 gen = 0; 3413 } 3414 } 3415 txq->ift_cidx = cidx; 3416 txq->ift_gen = gen; 3417 } 3418 3419 static __inline int 3420 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3421 { 3422 int reclaim; 3423 if_ctx_t ctx = txq->ift_ctx; 3424 3425 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3426 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3427 3428 /* 3429 * Need a rate-limiting check so that this isn't called every time 3430 */ 3431 iflib_tx_credits_update(ctx, txq); 3432 reclaim = DESC_RECLAIMABLE(txq); 3433 3434 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3435 #ifdef INVARIANTS 3436 if (iflib_verbose_debug) { 3437 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3438 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3439 reclaim, thresh); 3440 3441 } 3442 #endif 3443 return (0); 3444 } 3445 iflib_tx_desc_free(txq, reclaim); 3446 txq->ift_cleaned += reclaim; 3447 txq->ift_in_use -= reclaim; 3448 3449 return (reclaim); 3450 } 3451 3452 static struct mbuf ** 3453 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3454 { 3455 int next, size; 3456 struct mbuf **items; 3457 3458 size = r->size; 3459 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3460 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3461 3462 prefetch(items[(cidx + offset) & (size-1)]); 3463 if (remaining > 1) { 3464 prefetch2cachelines(&items[next]); 3465 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3466 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3467 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3468 } 3469 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3470 } 3471 3472 static void 3473 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3474 { 3475 3476 ifmp_ring_check_drainage(txq->ift_br, budget); 3477 } 3478 3479 static uint32_t 3480 iflib_txq_can_drain(struct ifmp_ring *r) 3481 { 3482 iflib_txq_t txq = r->cookie; 3483 if_ctx_t ctx = txq->ift_ctx; 3484 3485 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3486 BUS_DMASYNC_POSTREAD); 3487 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3488 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3489 } 3490 3491 static uint32_t 3492 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3493 { 3494 iflib_txq_t txq = r->cookie; 3495 if_ctx_t ctx = txq->ift_ctx; 3496 struct ifnet *ifp = ctx->ifc_ifp; 3497 struct mbuf **mp, *m; 3498 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3499 int reclaimed, err, in_use_prev, desc_used; 3500 bool do_prefetch, ring, rang; 3501 3502 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3503 !LINK_ACTIVE(ctx))) { 3504 DBG_COUNTER_INC(txq_drain_notready); 3505 return (0); 3506 } 3507 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3508 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3509 avail = IDXDIFF(pidx, cidx, r->size); 3510 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3511 DBG_COUNTER_INC(txq_drain_flushing); 3512 for (i = 0; i < avail; i++) { 3513 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3514 m_free(r->items[(cidx + i) & (r->size-1)]); 3515 r->items[(cidx + i) & (r->size-1)] = NULL; 3516 } 3517 return (avail); 3518 } 3519 3520 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3521 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3522 CALLOUT_LOCK(txq); 3523 callout_stop(&txq->ift_timer); 3524 CALLOUT_UNLOCK(txq); 3525 DBG_COUNTER_INC(txq_drain_oactive); 3526 return (0); 3527 } 3528 if (reclaimed) 3529 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3530 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3531 count = MIN(avail, TX_BATCH_SIZE); 3532 #ifdef INVARIANTS 3533 if (iflib_verbose_debug) 3534 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3535 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3536 #endif 3537 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3538 avail = TXQ_AVAIL(txq); 3539 err = 0; 3540 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3541 int rem = do_prefetch ? count - i : 0; 3542 3543 mp = _ring_peek_one(r, cidx, i, rem); 3544 MPASS(mp != NULL && *mp != NULL); 3545 if (__predict_false(*mp == (struct mbuf *)txq)) { 3546 consumed++; 3547 reclaimed++; 3548 continue; 3549 } 3550 in_use_prev = txq->ift_in_use; 3551 err = iflib_encap(txq, mp); 3552 if (__predict_false(err)) { 3553 /* no room - bail out */ 3554 if (err == ENOBUFS) 3555 break; 3556 consumed++; 3557 /* we can't send this packet - skip it */ 3558 continue; 3559 } 3560 consumed++; 3561 pkt_sent++; 3562 m = *mp; 3563 DBG_COUNTER_INC(tx_sent); 3564 bytes_sent += m->m_pkthdr.len; 3565 mcast_sent += !!(m->m_flags & M_MCAST); 3566 avail = TXQ_AVAIL(txq); 3567 3568 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3569 desc_used += (txq->ift_in_use - in_use_prev); 3570 ETHER_BPF_MTAP(ifp, m); 3571 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3572 break; 3573 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3574 } 3575 3576 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3577 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3578 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3579 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3580 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3581 if (mcast_sent) 3582 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3583 #ifdef INVARIANTS 3584 if (iflib_verbose_debug) 3585 printf("consumed=%d\n", consumed); 3586 #endif 3587 return (consumed); 3588 } 3589 3590 static uint32_t 3591 iflib_txq_drain_always(struct ifmp_ring *r) 3592 { 3593 return (1); 3594 } 3595 3596 static uint32_t 3597 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3598 { 3599 int i, avail; 3600 struct mbuf **mp; 3601 iflib_txq_t txq; 3602 3603 txq = r->cookie; 3604 3605 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3606 CALLOUT_LOCK(txq); 3607 callout_stop(&txq->ift_timer); 3608 CALLOUT_UNLOCK(txq); 3609 3610 avail = IDXDIFF(pidx, cidx, r->size); 3611 for (i = 0; i < avail; i++) { 3612 mp = _ring_peek_one(r, cidx, i, avail - i); 3613 if (__predict_false(*mp == (struct mbuf *)txq)) 3614 continue; 3615 m_freem(*mp); 3616 DBG_COUNTER_INC(tx_frees); 3617 } 3618 MPASS(ifmp_ring_is_stalled(r) == 0); 3619 return (avail); 3620 } 3621 3622 static void 3623 iflib_ifmp_purge(iflib_txq_t txq) 3624 { 3625 struct ifmp_ring *r; 3626 3627 r = txq->ift_br; 3628 r->drain = iflib_txq_drain_free; 3629 r->can_drain = iflib_txq_drain_always; 3630 3631 ifmp_ring_check_drainage(r, r->size); 3632 3633 r->drain = iflib_txq_drain; 3634 r->can_drain = iflib_txq_can_drain; 3635 } 3636 3637 static void 3638 _task_fn_tx(void *context) 3639 { 3640 iflib_txq_t txq = context; 3641 if_ctx_t ctx = txq->ift_ctx; 3642 struct ifnet *ifp = ctx->ifc_ifp; 3643 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3644 3645 #ifdef IFLIB_DIAGNOSTICS 3646 txq->ift_cpu_exec_count[curcpu]++; 3647 #endif 3648 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3649 return; 3650 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3651 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3652 BUS_DMASYNC_POSTREAD); 3653 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3654 netmap_tx_irq(ifp, txq->ift_id); 3655 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3656 return; 3657 } 3658 #ifdef ALTQ 3659 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3660 iflib_altq_if_start(ifp); 3661 #endif 3662 if (txq->ift_db_pending) 3663 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3664 else if (!abdicate) 3665 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3666 /* 3667 * When abdicating, we always need to check drainage, not just when we don't enqueue 3668 */ 3669 if (abdicate) 3670 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3671 if (ctx->ifc_flags & IFC_LEGACY) 3672 IFDI_INTR_ENABLE(ctx); 3673 else { 3674 #ifdef INVARIANTS 3675 int rc = 3676 #endif 3677 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3678 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3679 } 3680 } 3681 3682 static void 3683 _task_fn_rx(void *context) 3684 { 3685 iflib_rxq_t rxq = context; 3686 if_ctx_t ctx = rxq->ifr_ctx; 3687 bool more; 3688 uint16_t budget; 3689 3690 #ifdef IFLIB_DIAGNOSTICS 3691 rxq->ifr_cpu_exec_count[curcpu]++; 3692 #endif 3693 DBG_COUNTER_INC(task_fn_rxs); 3694 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3695 return; 3696 more = true; 3697 #ifdef DEV_NETMAP 3698 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3699 u_int work = 0; 3700 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3701 more = false; 3702 } 3703 } 3704 #endif 3705 budget = ctx->ifc_sysctl_rx_budget; 3706 if (budget == 0) 3707 budget = 16; /* XXX */ 3708 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3709 if (ctx->ifc_flags & IFC_LEGACY) 3710 IFDI_INTR_ENABLE(ctx); 3711 else { 3712 #ifdef INVARIANTS 3713 int rc = 3714 #endif 3715 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3716 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3717 DBG_COUNTER_INC(rx_intr_enables); 3718 } 3719 } 3720 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3721 return; 3722 if (more) 3723 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3724 } 3725 3726 static void 3727 _task_fn_admin(void *context) 3728 { 3729 if_ctx_t ctx = context; 3730 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3731 iflib_txq_t txq; 3732 int i; 3733 bool oactive, running, do_reset, do_watchdog, in_detach; 3734 uint32_t reset_on = hz / 2; 3735 3736 STATE_LOCK(ctx); 3737 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3738 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3739 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3740 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3741 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3742 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3743 STATE_UNLOCK(ctx); 3744 3745 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3746 return; 3747 if (in_detach) 3748 return; 3749 3750 CTX_LOCK(ctx); 3751 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3752 CALLOUT_LOCK(txq); 3753 callout_stop(&txq->ift_timer); 3754 CALLOUT_UNLOCK(txq); 3755 } 3756 if (do_watchdog) { 3757 ctx->ifc_watchdog_events++; 3758 IFDI_WATCHDOG_RESET(ctx); 3759 } 3760 IFDI_UPDATE_ADMIN_STATUS(ctx); 3761 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3762 #ifdef DEV_NETMAP 3763 reset_on = hz / 2; 3764 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3765 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on); 3766 #endif 3767 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3768 } 3769 IFDI_LINK_INTR_ENABLE(ctx); 3770 if (do_reset) 3771 iflib_if_init_locked(ctx); 3772 CTX_UNLOCK(ctx); 3773 3774 if (LINK_ACTIVE(ctx) == 0) 3775 return; 3776 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3777 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3778 } 3779 3780 3781 static void 3782 _task_fn_iov(void *context) 3783 { 3784 if_ctx_t ctx = context; 3785 3786 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3787 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3788 return; 3789 3790 CTX_LOCK(ctx); 3791 IFDI_VFLR_HANDLE(ctx); 3792 CTX_UNLOCK(ctx); 3793 } 3794 3795 static int 3796 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3797 { 3798 int err; 3799 if_int_delay_info_t info; 3800 if_ctx_t ctx; 3801 3802 info = (if_int_delay_info_t)arg1; 3803 ctx = info->iidi_ctx; 3804 info->iidi_req = req; 3805 info->iidi_oidp = oidp; 3806 CTX_LOCK(ctx); 3807 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3808 CTX_UNLOCK(ctx); 3809 return (err); 3810 } 3811 3812 /********************************************************************* 3813 * 3814 * IFNET FUNCTIONS 3815 * 3816 **********************************************************************/ 3817 3818 static void 3819 iflib_if_init_locked(if_ctx_t ctx) 3820 { 3821 iflib_stop(ctx); 3822 iflib_init_locked(ctx); 3823 } 3824 3825 3826 static void 3827 iflib_if_init(void *arg) 3828 { 3829 if_ctx_t ctx = arg; 3830 3831 CTX_LOCK(ctx); 3832 iflib_if_init_locked(ctx); 3833 CTX_UNLOCK(ctx); 3834 } 3835 3836 static int 3837 iflib_if_transmit(if_t ifp, struct mbuf *m) 3838 { 3839 if_ctx_t ctx = if_getsoftc(ifp); 3840 3841 iflib_txq_t txq; 3842 int err, qidx; 3843 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3844 3845 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3846 DBG_COUNTER_INC(tx_frees); 3847 m_freem(m); 3848 return (ENOBUFS); 3849 } 3850 3851 MPASS(m->m_nextpkt == NULL); 3852 /* ALTQ-enabled interfaces always use queue 0. */ 3853 qidx = 0; 3854 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3855 qidx = QIDX(ctx, m); 3856 /* 3857 * XXX calculate buf_ring based on flowid (divvy up bits?) 3858 */ 3859 txq = &ctx->ifc_txqs[qidx]; 3860 3861 #ifdef DRIVER_BACKPRESSURE 3862 if (txq->ift_closed) { 3863 while (m != NULL) { 3864 next = m->m_nextpkt; 3865 m->m_nextpkt = NULL; 3866 m_freem(m); 3867 DBG_COUNTER_INC(tx_frees); 3868 m = next; 3869 } 3870 return (ENOBUFS); 3871 } 3872 #endif 3873 #ifdef notyet 3874 qidx = count = 0; 3875 mp = marr; 3876 next = m; 3877 do { 3878 count++; 3879 next = next->m_nextpkt; 3880 } while (next != NULL); 3881 3882 if (count > nitems(marr)) 3883 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3884 /* XXX check nextpkt */ 3885 m_freem(m); 3886 /* XXX simplify for now */ 3887 DBG_COUNTER_INC(tx_frees); 3888 return (ENOBUFS); 3889 } 3890 for (next = m, i = 0; next != NULL; i++) { 3891 mp[i] = next; 3892 next = next->m_nextpkt; 3893 mp[i]->m_nextpkt = NULL; 3894 } 3895 #endif 3896 DBG_COUNTER_INC(tx_seen); 3897 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3898 3899 if (abdicate) 3900 GROUPTASK_ENQUEUE(&txq->ift_task); 3901 if (err) { 3902 if (!abdicate) 3903 GROUPTASK_ENQUEUE(&txq->ift_task); 3904 /* support forthcoming later */ 3905 #ifdef DRIVER_BACKPRESSURE 3906 txq->ift_closed = TRUE; 3907 #endif 3908 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3909 m_freem(m); 3910 DBG_COUNTER_INC(tx_frees); 3911 } 3912 3913 return (err); 3914 } 3915 3916 #ifdef ALTQ 3917 /* 3918 * The overall approach to integrating iflib with ALTQ is to continue to use 3919 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 3920 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 3921 * is redundant/unnecessary, but doing so minimizes the amount of 3922 * ALTQ-specific code required in iflib. It is assumed that the overhead of 3923 * redundantly queueing to an intermediate mp_ring is swamped by the 3924 * performance limitations inherent in using ALTQ. 3925 * 3926 * When ALTQ support is compiled in, all iflib drivers will use a transmit 3927 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 3928 * given interface. If ALTQ is enabled for an interface, then all 3929 * transmitted packets for that interface will be submitted to the ALTQ 3930 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 3931 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 3932 * update stats that the iflib machinery handles, and which is sensitve to 3933 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 3934 * will be installed as the start routine for use by ALTQ facilities that 3935 * need to trigger queue drains on a scheduled basis. 3936 * 3937 */ 3938 static void 3939 iflib_altq_if_start(if_t ifp) 3940 { 3941 struct ifaltq *ifq = &ifp->if_snd; 3942 struct mbuf *m; 3943 3944 IFQ_LOCK(ifq); 3945 IFQ_DEQUEUE_NOLOCK(ifq, m); 3946 while (m != NULL) { 3947 iflib_if_transmit(ifp, m); 3948 IFQ_DEQUEUE_NOLOCK(ifq, m); 3949 } 3950 IFQ_UNLOCK(ifq); 3951 } 3952 3953 static int 3954 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 3955 { 3956 int err; 3957 3958 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 3959 IFQ_ENQUEUE(&ifp->if_snd, m, err); 3960 if (err == 0) 3961 iflib_altq_if_start(ifp); 3962 } else 3963 err = iflib_if_transmit(ifp, m); 3964 3965 return (err); 3966 } 3967 #endif /* ALTQ */ 3968 3969 static void 3970 iflib_if_qflush(if_t ifp) 3971 { 3972 if_ctx_t ctx = if_getsoftc(ifp); 3973 iflib_txq_t txq = ctx->ifc_txqs; 3974 int i; 3975 3976 STATE_LOCK(ctx); 3977 ctx->ifc_flags |= IFC_QFLUSH; 3978 STATE_UNLOCK(ctx); 3979 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3980 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3981 iflib_txq_check_drain(txq, 0); 3982 STATE_LOCK(ctx); 3983 ctx->ifc_flags &= ~IFC_QFLUSH; 3984 STATE_UNLOCK(ctx); 3985 3986 /* 3987 * When ALTQ is enabled, this will also take care of purging the 3988 * ALTQ queue(s). 3989 */ 3990 if_qflush(ifp); 3991 } 3992 3993 3994 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3995 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3996 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 3997 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM) 3998 3999 static int 4000 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4001 { 4002 if_ctx_t ctx = if_getsoftc(ifp); 4003 struct ifreq *ifr = (struct ifreq *)data; 4004 #if defined(INET) || defined(INET6) 4005 struct ifaddr *ifa = (struct ifaddr *)data; 4006 #endif 4007 bool avoid_reset = FALSE; 4008 int err = 0, reinit = 0, bits; 4009 4010 switch (command) { 4011 case SIOCSIFADDR: 4012 #ifdef INET 4013 if (ifa->ifa_addr->sa_family == AF_INET) 4014 avoid_reset = TRUE; 4015 #endif 4016 #ifdef INET6 4017 if (ifa->ifa_addr->sa_family == AF_INET6) 4018 avoid_reset = TRUE; 4019 #endif 4020 /* 4021 ** Calling init results in link renegotiation, 4022 ** so we avoid doing it when possible. 4023 */ 4024 if (avoid_reset) { 4025 if_setflagbits(ifp, IFF_UP,0); 4026 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4027 reinit = 1; 4028 #ifdef INET 4029 if (!(if_getflags(ifp) & IFF_NOARP)) 4030 arp_ifinit(ifp, ifa); 4031 #endif 4032 } else 4033 err = ether_ioctl(ifp, command, data); 4034 break; 4035 case SIOCSIFMTU: 4036 CTX_LOCK(ctx); 4037 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4038 CTX_UNLOCK(ctx); 4039 break; 4040 } 4041 bits = if_getdrvflags(ifp); 4042 /* stop the driver and free any clusters before proceeding */ 4043 iflib_stop(ctx); 4044 4045 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4046 STATE_LOCK(ctx); 4047 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4048 ctx->ifc_flags |= IFC_MULTISEG; 4049 else 4050 ctx->ifc_flags &= ~IFC_MULTISEG; 4051 STATE_UNLOCK(ctx); 4052 err = if_setmtu(ifp, ifr->ifr_mtu); 4053 } 4054 iflib_init_locked(ctx); 4055 STATE_LOCK(ctx); 4056 if_setdrvflags(ifp, bits); 4057 STATE_UNLOCK(ctx); 4058 CTX_UNLOCK(ctx); 4059 break; 4060 case SIOCSIFFLAGS: 4061 CTX_LOCK(ctx); 4062 if (if_getflags(ifp) & IFF_UP) { 4063 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4064 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4065 (IFF_PROMISC | IFF_ALLMULTI)) { 4066 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4067 } 4068 } else 4069 reinit = 1; 4070 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4071 iflib_stop(ctx); 4072 } 4073 ctx->ifc_if_flags = if_getflags(ifp); 4074 CTX_UNLOCK(ctx); 4075 break; 4076 case SIOCADDMULTI: 4077 case SIOCDELMULTI: 4078 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4079 CTX_LOCK(ctx); 4080 IFDI_INTR_DISABLE(ctx); 4081 IFDI_MULTI_SET(ctx); 4082 IFDI_INTR_ENABLE(ctx); 4083 CTX_UNLOCK(ctx); 4084 } 4085 break; 4086 case SIOCSIFMEDIA: 4087 CTX_LOCK(ctx); 4088 IFDI_MEDIA_SET(ctx); 4089 CTX_UNLOCK(ctx); 4090 /* falls thru */ 4091 case SIOCGIFMEDIA: 4092 case SIOCGIFXMEDIA: 4093 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4094 break; 4095 case SIOCGI2C: 4096 { 4097 struct ifi2creq i2c; 4098 4099 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4100 if (err != 0) 4101 break; 4102 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4103 err = EINVAL; 4104 break; 4105 } 4106 if (i2c.len > sizeof(i2c.data)) { 4107 err = EINVAL; 4108 break; 4109 } 4110 4111 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4112 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4113 sizeof(i2c)); 4114 break; 4115 } 4116 case SIOCSIFCAP: 4117 { 4118 int mask, setmask, oldmask; 4119 4120 oldmask = if_getcapenable(ifp); 4121 mask = ifr->ifr_reqcap ^ oldmask; 4122 mask &= ctx->ifc_softc_ctx.isc_capabilities; 4123 setmask = 0; 4124 #ifdef TCP_OFFLOAD 4125 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4126 #endif 4127 setmask |= (mask & IFCAP_FLAGS); 4128 setmask |= (mask & IFCAP_WOL); 4129 4130 /* 4131 * If any RX csum has changed, change all the ones that 4132 * are supported by the driver. 4133 */ 4134 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4135 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4136 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4137 } 4138 4139 /* 4140 * want to ensure that traffic has stopped before we change any of the flags 4141 */ 4142 if (setmask) { 4143 CTX_LOCK(ctx); 4144 bits = if_getdrvflags(ifp); 4145 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4146 iflib_stop(ctx); 4147 STATE_LOCK(ctx); 4148 if_togglecapenable(ifp, setmask); 4149 STATE_UNLOCK(ctx); 4150 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4151 iflib_init_locked(ctx); 4152 STATE_LOCK(ctx); 4153 if_setdrvflags(ifp, bits); 4154 STATE_UNLOCK(ctx); 4155 CTX_UNLOCK(ctx); 4156 } 4157 if_vlancap(ifp); 4158 break; 4159 } 4160 case SIOCGPRIVATE_0: 4161 case SIOCSDRVSPEC: 4162 case SIOCGDRVSPEC: 4163 CTX_LOCK(ctx); 4164 err = IFDI_PRIV_IOCTL(ctx, command, data); 4165 CTX_UNLOCK(ctx); 4166 break; 4167 default: 4168 err = ether_ioctl(ifp, command, data); 4169 break; 4170 } 4171 if (reinit) 4172 iflib_if_init(ctx); 4173 return (err); 4174 } 4175 4176 static uint64_t 4177 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4178 { 4179 if_ctx_t ctx = if_getsoftc(ifp); 4180 4181 return (IFDI_GET_COUNTER(ctx, cnt)); 4182 } 4183 4184 /********************************************************************* 4185 * 4186 * OTHER FUNCTIONS EXPORTED TO THE STACK 4187 * 4188 **********************************************************************/ 4189 4190 static void 4191 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4192 { 4193 if_ctx_t ctx = if_getsoftc(ifp); 4194 4195 if ((void *)ctx != arg) 4196 return; 4197 4198 if ((vtag == 0) || (vtag > 4095)) 4199 return; 4200 4201 CTX_LOCK(ctx); 4202 IFDI_VLAN_REGISTER(ctx, vtag); 4203 /* Re-init to load the changes */ 4204 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4205 iflib_if_init_locked(ctx); 4206 CTX_UNLOCK(ctx); 4207 } 4208 4209 static void 4210 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4211 { 4212 if_ctx_t ctx = if_getsoftc(ifp); 4213 4214 if ((void *)ctx != arg) 4215 return; 4216 4217 if ((vtag == 0) || (vtag > 4095)) 4218 return; 4219 4220 CTX_LOCK(ctx); 4221 IFDI_VLAN_UNREGISTER(ctx, vtag); 4222 /* Re-init to load the changes */ 4223 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4224 iflib_if_init_locked(ctx); 4225 CTX_UNLOCK(ctx); 4226 } 4227 4228 static void 4229 iflib_led_func(void *arg, int onoff) 4230 { 4231 if_ctx_t ctx = arg; 4232 4233 CTX_LOCK(ctx); 4234 IFDI_LED_FUNC(ctx, onoff); 4235 CTX_UNLOCK(ctx); 4236 } 4237 4238 /********************************************************************* 4239 * 4240 * BUS FUNCTION DEFINITIONS 4241 * 4242 **********************************************************************/ 4243 4244 int 4245 iflib_device_probe(device_t dev) 4246 { 4247 pci_vendor_info_t *ent; 4248 4249 uint16_t pci_vendor_id, pci_device_id; 4250 uint16_t pci_subvendor_id, pci_subdevice_id; 4251 uint16_t pci_rev_id; 4252 if_shared_ctx_t sctx; 4253 4254 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4255 return (ENOTSUP); 4256 4257 pci_vendor_id = pci_get_vendor(dev); 4258 pci_device_id = pci_get_device(dev); 4259 pci_subvendor_id = pci_get_subvendor(dev); 4260 pci_subdevice_id = pci_get_subdevice(dev); 4261 pci_rev_id = pci_get_revid(dev); 4262 if (sctx->isc_parse_devinfo != NULL) 4263 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4264 4265 ent = sctx->isc_vendor_info; 4266 while (ent->pvi_vendor_id != 0) { 4267 if (pci_vendor_id != ent->pvi_vendor_id) { 4268 ent++; 4269 continue; 4270 } 4271 if ((pci_device_id == ent->pvi_device_id) && 4272 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4273 (ent->pvi_subvendor_id == 0)) && 4274 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4275 (ent->pvi_subdevice_id == 0)) && 4276 ((pci_rev_id == ent->pvi_rev_id) || 4277 (ent->pvi_rev_id == 0))) { 4278 4279 device_set_desc_copy(dev, ent->pvi_name); 4280 /* this needs to be changed to zero if the bus probing code 4281 * ever stops re-probing on best match because the sctx 4282 * may have its values over written by register calls 4283 * in subsequent probes 4284 */ 4285 return (BUS_PROBE_DEFAULT); 4286 } 4287 ent++; 4288 } 4289 return (ENXIO); 4290 } 4291 4292 static void 4293 iflib_reset_qvalues(if_ctx_t ctx) 4294 { 4295 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4296 if_shared_ctx_t sctx = ctx->ifc_sctx; 4297 device_t dev = ctx->ifc_dev; 4298 int i; 4299 4300 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4301 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4302 /* 4303 * XXX sanity check that ntxd & nrxd are a power of 2 4304 */ 4305 if (ctx->ifc_sysctl_ntxqs != 0) 4306 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4307 if (ctx->ifc_sysctl_nrxqs != 0) 4308 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4309 4310 for (i = 0; i < sctx->isc_ntxqs; i++) { 4311 if (ctx->ifc_sysctl_ntxds[i] != 0) 4312 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4313 else 4314 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4315 } 4316 4317 for (i = 0; i < sctx->isc_nrxqs; i++) { 4318 if (ctx->ifc_sysctl_nrxds[i] != 0) 4319 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4320 else 4321 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4322 } 4323 4324 for (i = 0; i < sctx->isc_nrxqs; i++) { 4325 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4326 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4327 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4328 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4329 } 4330 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4331 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4332 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4333 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4334 } 4335 } 4336 4337 for (i = 0; i < sctx->isc_ntxqs; i++) { 4338 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4339 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4340 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4341 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4342 } 4343 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4344 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4345 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4346 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4347 } 4348 } 4349 } 4350 4351 int 4352 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4353 { 4354 int err, rid, msix; 4355 if_ctx_t ctx; 4356 if_t ifp; 4357 if_softc_ctx_t scctx; 4358 int i; 4359 uint16_t main_txq; 4360 uint16_t main_rxq; 4361 4362 4363 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4364 4365 if (sc == NULL) { 4366 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4367 device_set_softc(dev, ctx); 4368 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4369 } 4370 4371 ctx->ifc_sctx = sctx; 4372 ctx->ifc_dev = dev; 4373 ctx->ifc_softc = sc; 4374 4375 if ((err = iflib_register(ctx)) != 0) { 4376 device_printf(dev, "iflib_register failed %d\n", err); 4377 goto fail_ctx_free; 4378 } 4379 iflib_add_device_sysctl_pre(ctx); 4380 4381 scctx = &ctx->ifc_softc_ctx; 4382 ifp = ctx->ifc_ifp; 4383 4384 iflib_reset_qvalues(ctx); 4385 CTX_LOCK(ctx); 4386 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4387 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4388 goto fail_unlock; 4389 } 4390 _iflib_pre_assert(scctx); 4391 ctx->ifc_txrx = *scctx->isc_txrx; 4392 4393 #ifdef INVARIANTS 4394 MPASS(scctx->isc_capabilities); 4395 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4396 MPASS(scctx->isc_tx_csum_flags); 4397 #endif 4398 4399 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4400 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4401 4402 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4403 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4404 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4405 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4406 4407 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4408 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4409 4410 /* XXX change for per-queue sizes */ 4411 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4412 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4413 for (i = 0; i < sctx->isc_nrxqs; i++) { 4414 if (!powerof2(scctx->isc_nrxd[i])) { 4415 /* round down instead? */ 4416 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4417 err = EINVAL; 4418 goto fail_iflib_detach; 4419 } 4420 } 4421 for (i = 0; i < sctx->isc_ntxqs; i++) { 4422 if (!powerof2(scctx->isc_ntxd[i])) { 4423 device_printf(dev, 4424 "# tx descriptors must be a power of 2"); 4425 err = EINVAL; 4426 goto fail_iflib_detach; 4427 } 4428 } 4429 4430 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4431 MAX_SINGLE_PACKET_FRACTION) 4432 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4433 MAX_SINGLE_PACKET_FRACTION); 4434 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4435 MAX_SINGLE_PACKET_FRACTION) 4436 scctx->isc_tx_tso_segments_max = max(1, 4437 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4438 4439 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4440 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4441 /* 4442 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4443 * but some MACs do. 4444 */ 4445 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4446 IP_MAXPACKET)); 4447 /* 4448 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4449 * into account. In the worst case, each of these calls will 4450 * add another mbuf and, thus, the requirement for another DMA 4451 * segment. So for best performance, it doesn't make sense to 4452 * advertize a maximum of TSO segments that typically will 4453 * require defragmentation in iflib_encap(). 4454 */ 4455 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4456 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4457 } 4458 if (scctx->isc_rss_table_size == 0) 4459 scctx->isc_rss_table_size = 64; 4460 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4461 4462 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4463 /* XXX format name */ 4464 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4465 4466 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4467 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4468 device_printf(dev, "Unable to fetch CPU list\n"); 4469 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4470 } 4471 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4472 4473 /* 4474 ** Now setup MSI or MSI/X, should 4475 ** return us the number of supported 4476 ** vectors. (Will be 1 for MSI) 4477 */ 4478 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4479 msix = scctx->isc_vectors; 4480 } else if (scctx->isc_msix_bar != 0) 4481 /* 4482 * The simple fact that isc_msix_bar is not 0 does not mean we 4483 * we have a good value there that is known to work. 4484 */ 4485 msix = iflib_msix_init(ctx); 4486 else { 4487 scctx->isc_vectors = 1; 4488 scctx->isc_ntxqsets = 1; 4489 scctx->isc_nrxqsets = 1; 4490 scctx->isc_intr = IFLIB_INTR_LEGACY; 4491 msix = 0; 4492 } 4493 /* Get memory for the station queues */ 4494 if ((err = iflib_queues_alloc(ctx))) { 4495 device_printf(dev, "Unable to allocate queue memory\n"); 4496 goto fail_intr_free; 4497 } 4498 4499 if ((err = iflib_qset_structures_setup(ctx))) 4500 goto fail_queues; 4501 4502 /* 4503 * Group taskqueues aren't properly set up until SMP is started, 4504 * so we disable interrupts until we can handle them post 4505 * SI_SUB_SMP. 4506 * 4507 * XXX: disabling interrupts doesn't actually work, at least for 4508 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4509 * we do null handling and depend on this not causing too large an 4510 * interrupt storm. 4511 */ 4512 IFDI_INTR_DISABLE(ctx); 4513 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4514 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4515 goto fail_queues; 4516 } 4517 if (msix <= 1) { 4518 rid = 0; 4519 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4520 MPASS(msix == 1); 4521 rid = 1; 4522 } 4523 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4524 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4525 goto fail_queues; 4526 } 4527 } 4528 4529 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4530 4531 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4532 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4533 goto fail_detach; 4534 } 4535 4536 /* 4537 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4538 * This must appear after the call to ether_ifattach() because 4539 * ether_ifattach() sets if_hdrlen to the default value. 4540 */ 4541 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4542 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4543 4544 if ((err = iflib_netmap_attach(ctx))) { 4545 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4546 goto fail_detach; 4547 } 4548 *ctxp = ctx; 4549 4550 NETDUMP_SET(ctx->ifc_ifp, iflib); 4551 4552 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4553 iflib_add_device_sysctl_post(ctx); 4554 ctx->ifc_flags |= IFC_INIT_DONE; 4555 CTX_UNLOCK(ctx); 4556 return (0); 4557 4558 fail_detach: 4559 ether_ifdetach(ctx->ifc_ifp); 4560 fail_intr_free: 4561 iflib_free_intr_mem(ctx); 4562 fail_queues: 4563 iflib_tx_structures_free(ctx); 4564 iflib_rx_structures_free(ctx); 4565 fail_iflib_detach: 4566 IFDI_DETACH(ctx); 4567 fail_unlock: 4568 CTX_UNLOCK(ctx); 4569 fail_ctx_free: 4570 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4571 free(ctx->ifc_softc, M_IFLIB); 4572 free(ctx, M_IFLIB); 4573 return (err); 4574 } 4575 4576 int 4577 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4578 struct iflib_cloneattach_ctx *clctx) 4579 { 4580 int err; 4581 if_ctx_t ctx; 4582 if_t ifp; 4583 if_softc_ctx_t scctx; 4584 int i; 4585 void *sc; 4586 uint16_t main_txq; 4587 uint16_t main_rxq; 4588 4589 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4590 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4591 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4592 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4593 ctx->ifc_flags |= IFC_PSEUDO; 4594 4595 ctx->ifc_sctx = sctx; 4596 ctx->ifc_softc = sc; 4597 ctx->ifc_dev = dev; 4598 4599 if ((err = iflib_register(ctx)) != 0) { 4600 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4601 goto fail_ctx_free; 4602 } 4603 iflib_add_device_sysctl_pre(ctx); 4604 4605 scctx = &ctx->ifc_softc_ctx; 4606 ifp = ctx->ifc_ifp; 4607 4608 /* 4609 * XXX sanity check that ntxd & nrxd are a power of 2 4610 */ 4611 iflib_reset_qvalues(ctx); 4612 4613 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4614 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4615 goto fail_ctx_free; 4616 } 4617 if (sctx->isc_flags & IFLIB_GEN_MAC) 4618 iflib_gen_mac(ctx); 4619 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4620 clctx->cc_params)) != 0) { 4621 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4622 goto fail_ctx_free; 4623 } 4624 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4625 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4626 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4627 4628 #ifdef INVARIANTS 4629 MPASS(scctx->isc_capabilities); 4630 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4631 MPASS(scctx->isc_tx_csum_flags); 4632 #endif 4633 4634 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4635 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4636 4637 ifp->if_flags |= IFF_NOGROUP; 4638 if (sctx->isc_flags & IFLIB_PSEUDO) { 4639 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4640 4641 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4642 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4643 goto fail_detach; 4644 } 4645 *ctxp = ctx; 4646 4647 /* 4648 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4649 * This must appear after the call to ether_ifattach() because 4650 * ether_ifattach() sets if_hdrlen to the default value. 4651 */ 4652 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4653 if_setifheaderlen(ifp, 4654 sizeof(struct ether_vlan_header)); 4655 4656 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4657 iflib_add_device_sysctl_post(ctx); 4658 ctx->ifc_flags |= IFC_INIT_DONE; 4659 return (0); 4660 } 4661 _iflib_pre_assert(scctx); 4662 ctx->ifc_txrx = *scctx->isc_txrx; 4663 4664 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4665 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4666 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4667 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4668 4669 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4670 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4671 4672 /* XXX change for per-queue sizes */ 4673 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4674 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4675 for (i = 0; i < sctx->isc_nrxqs; i++) { 4676 if (!powerof2(scctx->isc_nrxd[i])) { 4677 /* round down instead? */ 4678 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4679 err = EINVAL; 4680 goto fail_iflib_detach; 4681 } 4682 } 4683 for (i = 0; i < sctx->isc_ntxqs; i++) { 4684 if (!powerof2(scctx->isc_ntxd[i])) { 4685 device_printf(dev, 4686 "# tx descriptors must be a power of 2"); 4687 err = EINVAL; 4688 goto fail_iflib_detach; 4689 } 4690 } 4691 4692 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4693 MAX_SINGLE_PACKET_FRACTION) 4694 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4695 MAX_SINGLE_PACKET_FRACTION); 4696 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4697 MAX_SINGLE_PACKET_FRACTION) 4698 scctx->isc_tx_tso_segments_max = max(1, 4699 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4700 4701 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4702 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4703 /* 4704 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4705 * but some MACs do. 4706 */ 4707 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4708 IP_MAXPACKET)); 4709 /* 4710 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4711 * into account. In the worst case, each of these calls will 4712 * add another mbuf and, thus, the requirement for another DMA 4713 * segment. So for best performance, it doesn't make sense to 4714 * advertize a maximum of TSO segments that typically will 4715 * require defragmentation in iflib_encap(). 4716 */ 4717 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4718 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4719 } 4720 if (scctx->isc_rss_table_size == 0) 4721 scctx->isc_rss_table_size = 64; 4722 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4723 4724 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4725 /* XXX format name */ 4726 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4727 4728 /* XXX --- can support > 1 -- but keep it simple for now */ 4729 scctx->isc_intr = IFLIB_INTR_LEGACY; 4730 4731 /* Get memory for the station queues */ 4732 if ((err = iflib_queues_alloc(ctx))) { 4733 device_printf(dev, "Unable to allocate queue memory\n"); 4734 goto fail_iflib_detach; 4735 } 4736 4737 if ((err = iflib_qset_structures_setup(ctx))) { 4738 device_printf(dev, "qset structure setup failed %d\n", err); 4739 goto fail_queues; 4740 } 4741 4742 /* 4743 * XXX What if anything do we want to do about interrupts? 4744 */ 4745 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4746 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4747 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4748 goto fail_detach; 4749 } 4750 4751 /* 4752 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4753 * This must appear after the call to ether_ifattach() because 4754 * ether_ifattach() sets if_hdrlen to the default value. 4755 */ 4756 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4757 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4758 4759 /* XXX handle more than one queue */ 4760 for (i = 0; i < scctx->isc_nrxqsets; i++) 4761 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4762 4763 *ctxp = ctx; 4764 4765 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4766 iflib_add_device_sysctl_post(ctx); 4767 ctx->ifc_flags |= IFC_INIT_DONE; 4768 return (0); 4769 fail_detach: 4770 ether_ifdetach(ctx->ifc_ifp); 4771 fail_queues: 4772 iflib_tx_structures_free(ctx); 4773 iflib_rx_structures_free(ctx); 4774 fail_iflib_detach: 4775 IFDI_DETACH(ctx); 4776 fail_ctx_free: 4777 free(ctx->ifc_softc, M_IFLIB); 4778 free(ctx, M_IFLIB); 4779 return (err); 4780 } 4781 4782 int 4783 iflib_pseudo_deregister(if_ctx_t ctx) 4784 { 4785 if_t ifp = ctx->ifc_ifp; 4786 iflib_txq_t txq; 4787 iflib_rxq_t rxq; 4788 int i, j; 4789 struct taskqgroup *tqg; 4790 iflib_fl_t fl; 4791 4792 /* Unregister VLAN events */ 4793 if (ctx->ifc_vlan_attach_event != NULL) 4794 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4795 if (ctx->ifc_vlan_detach_event != NULL) 4796 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4797 4798 ether_ifdetach(ifp); 4799 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4800 CTX_LOCK_DESTROY(ctx); 4801 /* XXX drain any dependent tasks */ 4802 tqg = qgroup_if_io_tqg; 4803 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4804 callout_drain(&txq->ift_timer); 4805 if (txq->ift_task.gt_uniq != NULL) 4806 taskqgroup_detach(tqg, &txq->ift_task); 4807 } 4808 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4809 if (rxq->ifr_task.gt_uniq != NULL) 4810 taskqgroup_detach(tqg, &rxq->ifr_task); 4811 4812 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4813 free(fl->ifl_rx_bitmap, M_IFLIB); 4814 } 4815 tqg = qgroup_if_config_tqg; 4816 if (ctx->ifc_admin_task.gt_uniq != NULL) 4817 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4818 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4819 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4820 4821 if_free(ifp); 4822 4823 iflib_tx_structures_free(ctx); 4824 iflib_rx_structures_free(ctx); 4825 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4826 free(ctx->ifc_softc, M_IFLIB); 4827 free(ctx, M_IFLIB); 4828 return (0); 4829 } 4830 4831 int 4832 iflib_device_attach(device_t dev) 4833 { 4834 if_ctx_t ctx; 4835 if_shared_ctx_t sctx; 4836 4837 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4838 return (ENOTSUP); 4839 4840 pci_enable_busmaster(dev); 4841 4842 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4843 } 4844 4845 int 4846 iflib_device_deregister(if_ctx_t ctx) 4847 { 4848 if_t ifp = ctx->ifc_ifp; 4849 iflib_txq_t txq; 4850 iflib_rxq_t rxq; 4851 device_t dev = ctx->ifc_dev; 4852 int i, j; 4853 struct taskqgroup *tqg; 4854 iflib_fl_t fl; 4855 4856 /* Make sure VLANS are not using driver */ 4857 if (if_vlantrunkinuse(ifp)) { 4858 device_printf(dev, "Vlan in use, detach first\n"); 4859 return (EBUSY); 4860 } 4861 #ifdef PCI_IOV 4862 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 4863 device_printf(dev, "SR-IOV in use; detach first.\n"); 4864 return (EBUSY); 4865 } 4866 #endif 4867 4868 STATE_LOCK(ctx); 4869 ctx->ifc_flags |= IFC_IN_DETACH; 4870 STATE_UNLOCK(ctx); 4871 4872 CTX_LOCK(ctx); 4873 iflib_stop(ctx); 4874 CTX_UNLOCK(ctx); 4875 4876 /* Unregister VLAN events */ 4877 if (ctx->ifc_vlan_attach_event != NULL) 4878 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4879 if (ctx->ifc_vlan_detach_event != NULL) 4880 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4881 4882 iflib_netmap_detach(ifp); 4883 ether_ifdetach(ifp); 4884 if (ctx->ifc_led_dev != NULL) 4885 led_destroy(ctx->ifc_led_dev); 4886 /* XXX drain any dependent tasks */ 4887 tqg = qgroup_if_io_tqg; 4888 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4889 callout_drain(&txq->ift_timer); 4890 if (txq->ift_task.gt_uniq != NULL) 4891 taskqgroup_detach(tqg, &txq->ift_task); 4892 } 4893 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4894 if (rxq->ifr_task.gt_uniq != NULL) 4895 taskqgroup_detach(tqg, &rxq->ifr_task); 4896 4897 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4898 free(fl->ifl_rx_bitmap, M_IFLIB); 4899 4900 } 4901 tqg = qgroup_if_config_tqg; 4902 if (ctx->ifc_admin_task.gt_uniq != NULL) 4903 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4904 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4905 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4906 CTX_LOCK(ctx); 4907 IFDI_DETACH(ctx); 4908 CTX_UNLOCK(ctx); 4909 4910 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4911 CTX_LOCK_DESTROY(ctx); 4912 device_set_softc(ctx->ifc_dev, NULL); 4913 iflib_free_intr_mem(ctx); 4914 4915 bus_generic_detach(dev); 4916 if_free(ifp); 4917 4918 iflib_tx_structures_free(ctx); 4919 iflib_rx_structures_free(ctx); 4920 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4921 free(ctx->ifc_softc, M_IFLIB); 4922 STATE_LOCK_DESTROY(ctx); 4923 free(ctx, M_IFLIB); 4924 return (0); 4925 } 4926 4927 static void 4928 iflib_free_intr_mem(if_ctx_t ctx) 4929 { 4930 4931 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4932 pci_release_msi(ctx->ifc_dev); 4933 } 4934 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4935 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4936 } 4937 if (ctx->ifc_msix_mem != NULL) { 4938 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4939 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4940 ctx->ifc_msix_mem = NULL; 4941 } 4942 } 4943 4944 int 4945 iflib_device_detach(device_t dev) 4946 { 4947 if_ctx_t ctx = device_get_softc(dev); 4948 4949 return (iflib_device_deregister(ctx)); 4950 } 4951 4952 int 4953 iflib_device_suspend(device_t dev) 4954 { 4955 if_ctx_t ctx = device_get_softc(dev); 4956 4957 CTX_LOCK(ctx); 4958 IFDI_SUSPEND(ctx); 4959 CTX_UNLOCK(ctx); 4960 4961 return bus_generic_suspend(dev); 4962 } 4963 int 4964 iflib_device_shutdown(device_t dev) 4965 { 4966 if_ctx_t ctx = device_get_softc(dev); 4967 4968 CTX_LOCK(ctx); 4969 IFDI_SHUTDOWN(ctx); 4970 CTX_UNLOCK(ctx); 4971 4972 return bus_generic_suspend(dev); 4973 } 4974 4975 4976 int 4977 iflib_device_resume(device_t dev) 4978 { 4979 if_ctx_t ctx = device_get_softc(dev); 4980 iflib_txq_t txq = ctx->ifc_txqs; 4981 4982 CTX_LOCK(ctx); 4983 IFDI_RESUME(ctx); 4984 iflib_if_init_locked(ctx); 4985 CTX_UNLOCK(ctx); 4986 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4987 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4988 4989 return (bus_generic_resume(dev)); 4990 } 4991 4992 int 4993 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4994 { 4995 int error; 4996 if_ctx_t ctx = device_get_softc(dev); 4997 4998 CTX_LOCK(ctx); 4999 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5000 CTX_UNLOCK(ctx); 5001 5002 return (error); 5003 } 5004 5005 void 5006 iflib_device_iov_uninit(device_t dev) 5007 { 5008 if_ctx_t ctx = device_get_softc(dev); 5009 5010 CTX_LOCK(ctx); 5011 IFDI_IOV_UNINIT(ctx); 5012 CTX_UNLOCK(ctx); 5013 } 5014 5015 int 5016 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5017 { 5018 int error; 5019 if_ctx_t ctx = device_get_softc(dev); 5020 5021 CTX_LOCK(ctx); 5022 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5023 CTX_UNLOCK(ctx); 5024 5025 return (error); 5026 } 5027 5028 /********************************************************************* 5029 * 5030 * MODULE FUNCTION DEFINITIONS 5031 * 5032 **********************************************************************/ 5033 5034 /* 5035 * - Start a fast taskqueue thread for each core 5036 * - Start a taskqueue for control operations 5037 */ 5038 static int 5039 iflib_module_init(void) 5040 { 5041 return (0); 5042 } 5043 5044 static int 5045 iflib_module_event_handler(module_t mod, int what, void *arg) 5046 { 5047 int err; 5048 5049 switch (what) { 5050 case MOD_LOAD: 5051 if ((err = iflib_module_init()) != 0) 5052 return (err); 5053 break; 5054 case MOD_UNLOAD: 5055 return (EBUSY); 5056 default: 5057 return (EOPNOTSUPP); 5058 } 5059 5060 return (0); 5061 } 5062 5063 /********************************************************************* 5064 * 5065 * PUBLIC FUNCTION DEFINITIONS 5066 * ordered as in iflib.h 5067 * 5068 **********************************************************************/ 5069 5070 5071 static void 5072 _iflib_assert(if_shared_ctx_t sctx) 5073 { 5074 MPASS(sctx->isc_tx_maxsize); 5075 MPASS(sctx->isc_tx_maxsegsize); 5076 5077 MPASS(sctx->isc_rx_maxsize); 5078 MPASS(sctx->isc_rx_nsegments); 5079 MPASS(sctx->isc_rx_maxsegsize); 5080 5081 MPASS(sctx->isc_nrxd_min[0]); 5082 MPASS(sctx->isc_nrxd_max[0]); 5083 MPASS(sctx->isc_nrxd_default[0]); 5084 MPASS(sctx->isc_ntxd_min[0]); 5085 MPASS(sctx->isc_ntxd_max[0]); 5086 MPASS(sctx->isc_ntxd_default[0]); 5087 } 5088 5089 static void 5090 _iflib_pre_assert(if_softc_ctx_t scctx) 5091 { 5092 5093 MPASS(scctx->isc_txrx->ift_txd_encap); 5094 MPASS(scctx->isc_txrx->ift_txd_flush); 5095 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5096 MPASS(scctx->isc_txrx->ift_rxd_available); 5097 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5098 MPASS(scctx->isc_txrx->ift_rxd_refill); 5099 MPASS(scctx->isc_txrx->ift_rxd_flush); 5100 } 5101 5102 static int 5103 iflib_register(if_ctx_t ctx) 5104 { 5105 if_shared_ctx_t sctx = ctx->ifc_sctx; 5106 driver_t *driver = sctx->isc_driver; 5107 device_t dev = ctx->ifc_dev; 5108 if_t ifp; 5109 5110 _iflib_assert(sctx); 5111 5112 CTX_LOCK_INIT(ctx); 5113 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5114 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5115 if (ifp == NULL) { 5116 device_printf(dev, "can not allocate ifnet structure\n"); 5117 return (ENOMEM); 5118 } 5119 5120 /* 5121 * Initialize our context's device specific methods 5122 */ 5123 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5124 kobj_class_compile((kobj_class_t) driver); 5125 driver->refs++; 5126 5127 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5128 if_setsoftc(ifp, ctx); 5129 if_setdev(ifp, dev); 5130 if_setinitfn(ifp, iflib_if_init); 5131 if_setioctlfn(ifp, iflib_if_ioctl); 5132 #ifdef ALTQ 5133 if_setstartfn(ifp, iflib_altq_if_start); 5134 if_settransmitfn(ifp, iflib_altq_if_transmit); 5135 if_setsendqready(ifp); 5136 #else 5137 if_settransmitfn(ifp, iflib_if_transmit); 5138 #endif 5139 if_setqflushfn(ifp, iflib_if_qflush); 5140 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5141 5142 ctx->ifc_vlan_attach_event = 5143 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5144 EVENTHANDLER_PRI_FIRST); 5145 ctx->ifc_vlan_detach_event = 5146 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5147 EVENTHANDLER_PRI_FIRST); 5148 5149 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5150 iflib_media_change, iflib_media_status); 5151 5152 return (0); 5153 } 5154 5155 5156 static int 5157 iflib_queues_alloc(if_ctx_t ctx) 5158 { 5159 if_shared_ctx_t sctx = ctx->ifc_sctx; 5160 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5161 device_t dev = ctx->ifc_dev; 5162 int nrxqsets = scctx->isc_nrxqsets; 5163 int ntxqsets = scctx->isc_ntxqsets; 5164 iflib_txq_t txq; 5165 iflib_rxq_t rxq; 5166 iflib_fl_t fl = NULL; 5167 int i, j, cpu, err, txconf, rxconf; 5168 iflib_dma_info_t ifdip; 5169 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5170 uint32_t *txqsizes = scctx->isc_txqsizes; 5171 uint8_t nrxqs = sctx->isc_nrxqs; 5172 uint8_t ntxqs = sctx->isc_ntxqs; 5173 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5174 caddr_t *vaddrs; 5175 uint64_t *paddrs; 5176 5177 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5178 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5179 5180 /* Allocate the TX ring struct memory */ 5181 if (!(ctx->ifc_txqs = 5182 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5183 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5184 device_printf(dev, "Unable to allocate TX ring memory\n"); 5185 err = ENOMEM; 5186 goto fail; 5187 } 5188 5189 /* Now allocate the RX */ 5190 if (!(ctx->ifc_rxqs = 5191 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5192 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5193 device_printf(dev, "Unable to allocate RX ring memory\n"); 5194 err = ENOMEM; 5195 goto rx_fail; 5196 } 5197 5198 txq = ctx->ifc_txqs; 5199 rxq = ctx->ifc_rxqs; 5200 5201 /* 5202 * XXX handle allocation failure 5203 */ 5204 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5205 /* Set up some basics */ 5206 5207 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5208 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5209 err = ENOMEM; 5210 goto err_tx_desc; 5211 } 5212 txq->ift_ifdi = ifdip; 5213 for (j = 0; j < ntxqs; j++, ifdip++) { 5214 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5215 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5216 err = ENOMEM; 5217 goto err_tx_desc; 5218 } 5219 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5220 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5221 } 5222 txq->ift_ctx = ctx; 5223 txq->ift_id = i; 5224 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5225 txq->ift_br_offset = 1; 5226 } else { 5227 txq->ift_br_offset = 0; 5228 } 5229 /* XXX fix this */ 5230 txq->ift_timer.c_cpu = cpu; 5231 5232 if (iflib_txsd_alloc(txq)) { 5233 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5234 err = ENOMEM; 5235 goto err_tx_desc; 5236 } 5237 5238 /* Initialize the TX lock */ 5239 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5240 device_get_nameunit(dev), txq->ift_id); 5241 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5242 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5243 5244 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5245 device_get_nameunit(dev), txq->ift_id); 5246 5247 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5248 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5249 if (err) { 5250 /* XXX free any allocated rings */ 5251 device_printf(dev, "Unable to allocate buf_ring\n"); 5252 goto err_tx_desc; 5253 } 5254 } 5255 5256 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5257 /* Set up some basics */ 5258 5259 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5260 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5261 err = ENOMEM; 5262 goto err_tx_desc; 5263 } 5264 5265 rxq->ifr_ifdi = ifdip; 5266 /* XXX this needs to be changed if #rx queues != #tx queues */ 5267 rxq->ifr_ntxqirq = 1; 5268 rxq->ifr_txqid[0] = i; 5269 for (j = 0; j < nrxqs; j++, ifdip++) { 5270 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5271 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5272 err = ENOMEM; 5273 goto err_tx_desc; 5274 } 5275 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5276 } 5277 rxq->ifr_ctx = ctx; 5278 rxq->ifr_id = i; 5279 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5280 rxq->ifr_fl_offset = 1; 5281 } else { 5282 rxq->ifr_fl_offset = 0; 5283 } 5284 rxq->ifr_nfl = nfree_lists; 5285 if (!(fl = 5286 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5287 device_printf(dev, "Unable to allocate free list memory\n"); 5288 err = ENOMEM; 5289 goto err_tx_desc; 5290 } 5291 rxq->ifr_fl = fl; 5292 for (j = 0; j < nfree_lists; j++) { 5293 fl[j].ifl_rxq = rxq; 5294 fl[j].ifl_id = j; 5295 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5296 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5297 } 5298 /* Allocate receive buffers for the ring */ 5299 if (iflib_rxsd_alloc(rxq)) { 5300 device_printf(dev, 5301 "Critical Failure setting up receive buffers\n"); 5302 err = ENOMEM; 5303 goto err_rx_desc; 5304 } 5305 5306 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5307 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 5308 } 5309 5310 /* TXQs */ 5311 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5312 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5313 for (i = 0; i < ntxqsets; i++) { 5314 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5315 5316 for (j = 0; j < ntxqs; j++, di++) { 5317 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5318 paddrs[i*ntxqs + j] = di->idi_paddr; 5319 } 5320 } 5321 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5322 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5323 iflib_tx_structures_free(ctx); 5324 free(vaddrs, M_IFLIB); 5325 free(paddrs, M_IFLIB); 5326 goto err_rx_desc; 5327 } 5328 free(vaddrs, M_IFLIB); 5329 free(paddrs, M_IFLIB); 5330 5331 /* RXQs */ 5332 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5333 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5334 for (i = 0; i < nrxqsets; i++) { 5335 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5336 5337 for (j = 0; j < nrxqs; j++, di++) { 5338 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5339 paddrs[i*nrxqs + j] = di->idi_paddr; 5340 } 5341 } 5342 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5343 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5344 iflib_tx_structures_free(ctx); 5345 free(vaddrs, M_IFLIB); 5346 free(paddrs, M_IFLIB); 5347 goto err_rx_desc; 5348 } 5349 free(vaddrs, M_IFLIB); 5350 free(paddrs, M_IFLIB); 5351 5352 return (0); 5353 5354 /* XXX handle allocation failure changes */ 5355 err_rx_desc: 5356 err_tx_desc: 5357 rx_fail: 5358 if (ctx->ifc_rxqs != NULL) 5359 free(ctx->ifc_rxqs, M_IFLIB); 5360 ctx->ifc_rxqs = NULL; 5361 if (ctx->ifc_txqs != NULL) 5362 free(ctx->ifc_txqs, M_IFLIB); 5363 ctx->ifc_txqs = NULL; 5364 fail: 5365 return (err); 5366 } 5367 5368 static int 5369 iflib_tx_structures_setup(if_ctx_t ctx) 5370 { 5371 iflib_txq_t txq = ctx->ifc_txqs; 5372 int i; 5373 5374 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5375 iflib_txq_setup(txq); 5376 5377 return (0); 5378 } 5379 5380 static void 5381 iflib_tx_structures_free(if_ctx_t ctx) 5382 { 5383 iflib_txq_t txq = ctx->ifc_txqs; 5384 if_shared_ctx_t sctx = ctx->ifc_sctx; 5385 int i, j; 5386 5387 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5388 iflib_txq_destroy(txq); 5389 for (j = 0; j < sctx->isc_ntxqs; j++) 5390 iflib_dma_free(&txq->ift_ifdi[j]); 5391 } 5392 free(ctx->ifc_txqs, M_IFLIB); 5393 ctx->ifc_txqs = NULL; 5394 IFDI_QUEUES_FREE(ctx); 5395 } 5396 5397 /********************************************************************* 5398 * 5399 * Initialize all receive rings. 5400 * 5401 **********************************************************************/ 5402 static int 5403 iflib_rx_structures_setup(if_ctx_t ctx) 5404 { 5405 iflib_rxq_t rxq = ctx->ifc_rxqs; 5406 int q; 5407 #if defined(INET6) || defined(INET) 5408 int i, err; 5409 #endif 5410 5411 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5412 #if defined(INET6) || defined(INET) 5413 tcp_lro_free(&rxq->ifr_lc); 5414 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5415 TCP_LRO_ENTRIES, min(1024, 5416 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5417 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5418 goto fail; 5419 } 5420 rxq->ifr_lro_enabled = TRUE; 5421 #endif 5422 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5423 } 5424 return (0); 5425 #if defined(INET6) || defined(INET) 5426 fail: 5427 /* 5428 * Free RX software descriptors allocated so far, we will only handle 5429 * the rings that completed, the failing case will have 5430 * cleaned up for itself. 'q' failed, so its the terminus. 5431 */ 5432 rxq = ctx->ifc_rxqs; 5433 for (i = 0; i < q; ++i, rxq++) { 5434 iflib_rx_sds_free(rxq); 5435 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5436 } 5437 return (err); 5438 #endif 5439 } 5440 5441 /********************************************************************* 5442 * 5443 * Free all receive rings. 5444 * 5445 **********************************************************************/ 5446 static void 5447 iflib_rx_structures_free(if_ctx_t ctx) 5448 { 5449 iflib_rxq_t rxq = ctx->ifc_rxqs; 5450 5451 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5452 iflib_rx_sds_free(rxq); 5453 } 5454 free(ctx->ifc_rxqs, M_IFLIB); 5455 ctx->ifc_rxqs = NULL; 5456 } 5457 5458 static int 5459 iflib_qset_structures_setup(if_ctx_t ctx) 5460 { 5461 int err; 5462 5463 /* 5464 * It is expected that the caller takes care of freeing queues if this 5465 * fails. 5466 */ 5467 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5468 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5469 return (err); 5470 } 5471 5472 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5473 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5474 5475 return (err); 5476 } 5477 5478 int 5479 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5480 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5481 { 5482 5483 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5484 } 5485 5486 #ifdef SMP 5487 static int 5488 find_nth(if_ctx_t ctx, int qid) 5489 { 5490 cpuset_t cpus; 5491 int i, cpuid, eqid, count; 5492 5493 CPU_COPY(&ctx->ifc_cpus, &cpus); 5494 count = CPU_COUNT(&cpus); 5495 eqid = qid % count; 5496 /* clear up to the qid'th bit */ 5497 for (i = 0; i < eqid; i++) { 5498 cpuid = CPU_FFS(&cpus); 5499 MPASS(cpuid != 0); 5500 CPU_CLR(cpuid-1, &cpus); 5501 } 5502 cpuid = CPU_FFS(&cpus); 5503 MPASS(cpuid != 0); 5504 return (cpuid-1); 5505 } 5506 5507 #ifdef SCHED_ULE 5508 extern struct cpu_group *cpu_top; /* CPU topology */ 5509 5510 static int 5511 find_child_with_core(int cpu, struct cpu_group *grp) 5512 { 5513 int i; 5514 5515 if (grp->cg_children == 0) 5516 return -1; 5517 5518 MPASS(grp->cg_child); 5519 for (i = 0; i < grp->cg_children; i++) { 5520 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5521 return i; 5522 } 5523 5524 return -1; 5525 } 5526 5527 /* 5528 * Find the nth "close" core to the specified core 5529 * "close" is defined as the deepest level that shares 5530 * at least an L2 cache. With threads, this will be 5531 * threads on the same core. If the sahred cache is L3 5532 * or higher, simply returns the same core. 5533 */ 5534 static int 5535 find_close_core(int cpu, int core_offset) 5536 { 5537 struct cpu_group *grp; 5538 int i; 5539 int fcpu; 5540 cpuset_t cs; 5541 5542 grp = cpu_top; 5543 if (grp == NULL) 5544 return cpu; 5545 i = 0; 5546 while ((i = find_child_with_core(cpu, grp)) != -1) { 5547 /* If the child only has one cpu, don't descend */ 5548 if (grp->cg_child[i].cg_count <= 1) 5549 break; 5550 grp = &grp->cg_child[i]; 5551 } 5552 5553 /* If they don't share at least an L2 cache, use the same CPU */ 5554 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5555 return cpu; 5556 5557 /* Now pick one */ 5558 CPU_COPY(&grp->cg_mask, &cs); 5559 5560 /* Add the selected CPU offset to core offset. */ 5561 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5562 if (fcpu - 1 == cpu) 5563 break; 5564 CPU_CLR(fcpu - 1, &cs); 5565 } 5566 MPASS(fcpu); 5567 5568 core_offset += i; 5569 5570 CPU_COPY(&grp->cg_mask, &cs); 5571 for (i = core_offset % grp->cg_count; i > 0; i--) { 5572 MPASS(CPU_FFS(&cs)); 5573 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5574 } 5575 MPASS(CPU_FFS(&cs)); 5576 return CPU_FFS(&cs) - 1; 5577 } 5578 #else 5579 static int 5580 find_close_core(int cpu, int core_offset __unused) 5581 { 5582 return cpu; 5583 } 5584 #endif 5585 5586 static int 5587 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5588 { 5589 switch (type) { 5590 case IFLIB_INTR_TX: 5591 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5592 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5593 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5594 case IFLIB_INTR_RX: 5595 case IFLIB_INTR_RXTX: 5596 /* RX queues get the specified core */ 5597 return qid / CPU_COUNT(&ctx->ifc_cpus); 5598 default: 5599 return -1; 5600 } 5601 } 5602 #else 5603 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5604 #define find_close_core(cpuid, tid) CPU_FIRST() 5605 #define find_nth(ctx, gid) CPU_FIRST() 5606 #endif 5607 5608 /* Just to avoid copy/paste */ 5609 static inline int 5610 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5611 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name) 5612 { 5613 int cpuid; 5614 int err, tid; 5615 5616 cpuid = find_nth(ctx, qid); 5617 tid = get_core_offset(ctx, type, qid); 5618 MPASS(tid >= 0); 5619 cpuid = find_close_core(cpuid, tid); 5620 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5621 if (err) { 5622 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5623 return (err); 5624 } 5625 #ifdef notyet 5626 if (cpuid > ctx->ifc_cpuid_highest) 5627 ctx->ifc_cpuid_highest = cpuid; 5628 #endif 5629 return 0; 5630 } 5631 5632 int 5633 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5634 iflib_intr_type_t type, driver_filter_t *filter, 5635 void *filter_arg, int qid, const char *name) 5636 { 5637 struct grouptask *gtask; 5638 struct taskqgroup *tqg; 5639 iflib_filter_info_t info; 5640 gtask_fn_t *fn; 5641 int tqrid, err; 5642 driver_filter_t *intr_fast; 5643 void *q; 5644 5645 info = &ctx->ifc_filter_info; 5646 tqrid = rid; 5647 5648 switch (type) { 5649 /* XXX merge tx/rx for netmap? */ 5650 case IFLIB_INTR_TX: 5651 q = &ctx->ifc_txqs[qid]; 5652 info = &ctx->ifc_txqs[qid].ift_filter_info; 5653 gtask = &ctx->ifc_txqs[qid].ift_task; 5654 tqg = qgroup_if_io_tqg; 5655 fn = _task_fn_tx; 5656 intr_fast = iflib_fast_intr; 5657 GROUPTASK_INIT(gtask, 0, fn, q); 5658 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5659 break; 5660 case IFLIB_INTR_RX: 5661 q = &ctx->ifc_rxqs[qid]; 5662 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5663 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5664 tqg = qgroup_if_io_tqg; 5665 fn = _task_fn_rx; 5666 intr_fast = iflib_fast_intr; 5667 GROUPTASK_INIT(gtask, 0, fn, q); 5668 break; 5669 case IFLIB_INTR_RXTX: 5670 q = &ctx->ifc_rxqs[qid]; 5671 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5672 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5673 tqg = qgroup_if_io_tqg; 5674 fn = _task_fn_rx; 5675 intr_fast = iflib_fast_intr_rxtx; 5676 GROUPTASK_INIT(gtask, 0, fn, q); 5677 break; 5678 case IFLIB_INTR_ADMIN: 5679 q = ctx; 5680 tqrid = -1; 5681 info = &ctx->ifc_filter_info; 5682 gtask = &ctx->ifc_admin_task; 5683 tqg = qgroup_if_config_tqg; 5684 fn = _task_fn_admin; 5685 intr_fast = iflib_fast_intr_ctx; 5686 break; 5687 default: 5688 panic("unknown net intr type"); 5689 } 5690 5691 info->ifi_filter = filter; 5692 info->ifi_filter_arg = filter_arg; 5693 info->ifi_task = gtask; 5694 info->ifi_ctx = q; 5695 5696 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5697 if (err != 0) { 5698 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5699 return (err); 5700 } 5701 if (type == IFLIB_INTR_ADMIN) 5702 return (0); 5703 5704 if (tqrid != -1) { 5705 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5706 if (err) 5707 return (err); 5708 } else { 5709 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5710 } 5711 5712 return (0); 5713 } 5714 5715 void 5716 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5717 { 5718 struct grouptask *gtask; 5719 struct taskqgroup *tqg; 5720 gtask_fn_t *fn; 5721 void *q; 5722 int irq_num = -1; 5723 int err; 5724 5725 switch (type) { 5726 case IFLIB_INTR_TX: 5727 q = &ctx->ifc_txqs[qid]; 5728 gtask = &ctx->ifc_txqs[qid].ift_task; 5729 tqg = qgroup_if_io_tqg; 5730 fn = _task_fn_tx; 5731 if (irq != NULL) 5732 irq_num = rman_get_start(irq->ii_res); 5733 break; 5734 case IFLIB_INTR_RX: 5735 q = &ctx->ifc_rxqs[qid]; 5736 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5737 tqg = qgroup_if_io_tqg; 5738 fn = _task_fn_rx; 5739 if (irq != NULL) 5740 irq_num = rman_get_start(irq->ii_res); 5741 break; 5742 case IFLIB_INTR_IOV: 5743 q = ctx; 5744 gtask = &ctx->ifc_vflr_task; 5745 tqg = qgroup_if_config_tqg; 5746 fn = _task_fn_iov; 5747 break; 5748 default: 5749 panic("unknown net intr type"); 5750 } 5751 GROUPTASK_INIT(gtask, 0, fn, q); 5752 if (irq_num != -1) { 5753 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5754 if (err) 5755 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5756 } 5757 else { 5758 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5759 } 5760 } 5761 5762 void 5763 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5764 { 5765 if (irq->ii_tag) 5766 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5767 5768 if (irq->ii_res) 5769 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5770 } 5771 5772 static int 5773 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5774 { 5775 iflib_txq_t txq = ctx->ifc_txqs; 5776 iflib_rxq_t rxq = ctx->ifc_rxqs; 5777 if_irq_t irq = &ctx->ifc_legacy_irq; 5778 iflib_filter_info_t info; 5779 struct grouptask *gtask; 5780 struct taskqgroup *tqg; 5781 gtask_fn_t *fn; 5782 int tqrid; 5783 void *q; 5784 int err; 5785 5786 q = &ctx->ifc_rxqs[0]; 5787 info = &rxq[0].ifr_filter_info; 5788 gtask = &rxq[0].ifr_task; 5789 tqg = qgroup_if_io_tqg; 5790 tqrid = irq->ii_rid = *rid; 5791 fn = _task_fn_rx; 5792 5793 ctx->ifc_flags |= IFC_LEGACY; 5794 info->ifi_filter = filter; 5795 info->ifi_filter_arg = filter_arg; 5796 info->ifi_task = gtask; 5797 info->ifi_ctx = ctx; 5798 5799 /* We allocate a single interrupt resource */ 5800 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5801 return (err); 5802 GROUPTASK_INIT(gtask, 0, fn, q); 5803 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5804 5805 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5806 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5807 return (0); 5808 } 5809 5810 void 5811 iflib_led_create(if_ctx_t ctx) 5812 { 5813 5814 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5815 device_get_nameunit(ctx->ifc_dev)); 5816 } 5817 5818 void 5819 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5820 { 5821 5822 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5823 } 5824 5825 void 5826 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5827 { 5828 5829 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5830 } 5831 5832 void 5833 iflib_admin_intr_deferred(if_ctx_t ctx) 5834 { 5835 #ifdef INVARIANTS 5836 struct grouptask *gtask; 5837 5838 gtask = &ctx->ifc_admin_task; 5839 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5840 #endif 5841 5842 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5843 } 5844 5845 void 5846 iflib_iov_intr_deferred(if_ctx_t ctx) 5847 { 5848 5849 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5850 } 5851 5852 void 5853 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5854 { 5855 5856 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5857 } 5858 5859 void 5860 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5861 const char *name) 5862 { 5863 5864 GROUPTASK_INIT(gtask, 0, fn, ctx); 5865 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5866 } 5867 5868 void 5869 iflib_config_gtask_deinit(struct grouptask *gtask) 5870 { 5871 5872 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5873 } 5874 5875 void 5876 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5877 { 5878 if_t ifp = ctx->ifc_ifp; 5879 iflib_txq_t txq = ctx->ifc_txqs; 5880 5881 if_setbaudrate(ifp, baudrate); 5882 if (baudrate >= IF_Gbps(10)) { 5883 STATE_LOCK(ctx); 5884 ctx->ifc_flags |= IFC_PREFETCH; 5885 STATE_UNLOCK(ctx); 5886 } 5887 /* If link down, disable watchdog */ 5888 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5889 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5890 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5891 } 5892 ctx->ifc_link_state = link_state; 5893 if_link_state_change(ifp, link_state); 5894 } 5895 5896 static int 5897 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5898 { 5899 int credits; 5900 #ifdef INVARIANTS 5901 int credits_pre = txq->ift_cidx_processed; 5902 #endif 5903 5904 if (ctx->isc_txd_credits_update == NULL) 5905 return (0); 5906 5907 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 5908 BUS_DMASYNC_POSTREAD); 5909 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5910 return (0); 5911 5912 txq->ift_processed += credits; 5913 txq->ift_cidx_processed += credits; 5914 5915 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5916 if (txq->ift_cidx_processed >= txq->ift_size) 5917 txq->ift_cidx_processed -= txq->ift_size; 5918 return (credits); 5919 } 5920 5921 static int 5922 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5923 { 5924 5925 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5926 budget)); 5927 } 5928 5929 void 5930 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5931 const char *description, if_int_delay_info_t info, 5932 int offset, int value) 5933 { 5934 info->iidi_ctx = ctx; 5935 info->iidi_offset = offset; 5936 info->iidi_value = value; 5937 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5938 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5939 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5940 info, 0, iflib_sysctl_int_delay, "I", description); 5941 } 5942 5943 struct sx * 5944 iflib_ctx_lock_get(if_ctx_t ctx) 5945 { 5946 5947 return (&ctx->ifc_ctx_sx); 5948 } 5949 5950 static int 5951 iflib_msix_init(if_ctx_t ctx) 5952 { 5953 device_t dev = ctx->ifc_dev; 5954 if_shared_ctx_t sctx = ctx->ifc_sctx; 5955 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5956 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5957 int iflib_num_tx_queues, iflib_num_rx_queues; 5958 int err, admincnt, bar; 5959 5960 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5961 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5962 5963 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5964 5965 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5966 admincnt = sctx->isc_admin_intrcnt; 5967 /* Override by tuneable */ 5968 if (scctx->isc_disable_msix) 5969 goto msi; 5970 5971 /* 5972 * bar == -1 => "trust me I know what I'm doing" 5973 * Some drivers are for hardware that is so shoddily 5974 * documented that no one knows which bars are which 5975 * so the developer has to map all bars. This hack 5976 * allows shoddy garbage to use msix in this framework. 5977 */ 5978 if (bar != -1) { 5979 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5980 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5981 if (ctx->ifc_msix_mem == NULL) { 5982 /* May not be enabled */ 5983 device_printf(dev, "Unable to map MSIX table \n"); 5984 goto msi; 5985 } 5986 } 5987 /* First try MSI/X */ 5988 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5989 device_printf(dev, "System has MSIX disabled \n"); 5990 bus_release_resource(dev, SYS_RES_MEMORY, 5991 bar, ctx->ifc_msix_mem); 5992 ctx->ifc_msix_mem = NULL; 5993 goto msi; 5994 } 5995 #if IFLIB_DEBUG 5996 /* use only 1 qset in debug mode */ 5997 queuemsgs = min(msgs - admincnt, 1); 5998 #else 5999 queuemsgs = msgs - admincnt; 6000 #endif 6001 #ifdef RSS 6002 queues = imin(queuemsgs, rss_getnumbuckets()); 6003 #else 6004 queues = queuemsgs; 6005 #endif 6006 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6007 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 6008 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6009 #ifdef RSS 6010 /* If we're doing RSS, clamp at the number of RSS buckets */ 6011 if (queues > rss_getnumbuckets()) 6012 queues = rss_getnumbuckets(); 6013 #endif 6014 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6015 rx_queues = iflib_num_rx_queues; 6016 else 6017 rx_queues = queues; 6018 6019 if (rx_queues > scctx->isc_nrxqsets) 6020 rx_queues = scctx->isc_nrxqsets; 6021 6022 /* 6023 * We want this to be all logical CPUs by default 6024 */ 6025 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6026 tx_queues = iflib_num_tx_queues; 6027 else 6028 tx_queues = mp_ncpus; 6029 6030 if (tx_queues > scctx->isc_ntxqsets) 6031 tx_queues = scctx->isc_ntxqsets; 6032 6033 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6034 #ifdef INVARIANTS 6035 if (tx_queues != rx_queues) 6036 device_printf(dev, 6037 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6038 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6039 #endif 6040 tx_queues = min(rx_queues, tx_queues); 6041 rx_queues = min(rx_queues, tx_queues); 6042 } 6043 6044 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 6045 6046 vectors = rx_queues + admincnt; 6047 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6048 device_printf(dev, "Using MSIX interrupts with %d vectors\n", vectors); 6049 scctx->isc_vectors = vectors; 6050 scctx->isc_nrxqsets = rx_queues; 6051 scctx->isc_ntxqsets = tx_queues; 6052 scctx->isc_intr = IFLIB_INTR_MSIX; 6053 6054 return (vectors); 6055 } else { 6056 device_printf(dev, 6057 "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 6058 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6059 ctx->ifc_msix_mem); 6060 ctx->ifc_msix_mem = NULL; 6061 } 6062 msi: 6063 vectors = pci_msi_count(dev); 6064 scctx->isc_nrxqsets = 1; 6065 scctx->isc_ntxqsets = 1; 6066 scctx->isc_vectors = vectors; 6067 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6068 device_printf(dev,"Using an MSI interrupt\n"); 6069 scctx->isc_intr = IFLIB_INTR_MSI; 6070 } else { 6071 scctx->isc_vectors = 1; 6072 device_printf(dev,"Using a Legacy interrupt\n"); 6073 scctx->isc_intr = IFLIB_INTR_LEGACY; 6074 } 6075 6076 return (vectors); 6077 } 6078 6079 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6080 6081 static int 6082 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6083 { 6084 int rc; 6085 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6086 struct sbuf *sb; 6087 const char *ring_state = "UNKNOWN"; 6088 6089 /* XXX needed ? */ 6090 rc = sysctl_wire_old_buffer(req, 0); 6091 MPASS(rc == 0); 6092 if (rc != 0) 6093 return (rc); 6094 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6095 MPASS(sb != NULL); 6096 if (sb == NULL) 6097 return (ENOMEM); 6098 if (state[3] <= 3) 6099 ring_state = ring_states[state[3]]; 6100 6101 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6102 state[0], state[1], state[2], ring_state); 6103 rc = sbuf_finish(sb); 6104 sbuf_delete(sb); 6105 return(rc); 6106 } 6107 6108 enum iflib_ndesc_handler { 6109 IFLIB_NTXD_HANDLER, 6110 IFLIB_NRXD_HANDLER, 6111 }; 6112 6113 static int 6114 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6115 { 6116 if_ctx_t ctx = (void *)arg1; 6117 enum iflib_ndesc_handler type = arg2; 6118 char buf[256] = {0}; 6119 qidx_t *ndesc; 6120 char *p, *next; 6121 int nqs, rc, i; 6122 6123 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6124 6125 nqs = 8; 6126 switch(type) { 6127 case IFLIB_NTXD_HANDLER: 6128 ndesc = ctx->ifc_sysctl_ntxds; 6129 if (ctx->ifc_sctx) 6130 nqs = ctx->ifc_sctx->isc_ntxqs; 6131 break; 6132 case IFLIB_NRXD_HANDLER: 6133 ndesc = ctx->ifc_sysctl_nrxds; 6134 if (ctx->ifc_sctx) 6135 nqs = ctx->ifc_sctx->isc_nrxqs; 6136 break; 6137 default: 6138 panic("unhandled type"); 6139 } 6140 if (nqs == 0) 6141 nqs = 8; 6142 6143 for (i=0; i<8; i++) { 6144 if (i >= nqs) 6145 break; 6146 if (i) 6147 strcat(buf, ","); 6148 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6149 } 6150 6151 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6152 if (rc || req->newptr == NULL) 6153 return rc; 6154 6155 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6156 i++, p = strsep(&next, " ,")) { 6157 ndesc[i] = strtoul(p, NULL, 10); 6158 } 6159 6160 return(rc); 6161 } 6162 6163 #define NAME_BUFLEN 32 6164 static void 6165 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6166 { 6167 device_t dev = iflib_get_dev(ctx); 6168 struct sysctl_oid_list *child, *oid_list; 6169 struct sysctl_ctx_list *ctx_list; 6170 struct sysctl_oid *node; 6171 6172 ctx_list = device_get_sysctl_ctx(dev); 6173 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6174 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6175 CTLFLAG_RD, NULL, "IFLIB fields"); 6176 oid_list = SYSCTL_CHILDREN(node); 6177 6178 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6179 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 6180 "driver version"); 6181 6182 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6183 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6184 "# of txqs to use, 0 => use default #"); 6185 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6186 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6187 "# of rxqs to use, 0 => use default #"); 6188 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6189 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6190 "permit #txq != #rxq"); 6191 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6192 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6193 "disable MSIX (default 0)"); 6194 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6195 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6196 "set the rx budget"); 6197 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6198 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6199 "cause tx to abdicate instead of running to completion"); 6200 6201 /* XXX change for per-queue sizes */ 6202 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6203 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6204 mp_ndesc_handler, "A", 6205 "list of # of tx descriptors to use, 0 = use default #"); 6206 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6207 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6208 mp_ndesc_handler, "A", 6209 "list of # of rx descriptors to use, 0 = use default #"); 6210 } 6211 6212 static void 6213 iflib_add_device_sysctl_post(if_ctx_t ctx) 6214 { 6215 if_shared_ctx_t sctx = ctx->ifc_sctx; 6216 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6217 device_t dev = iflib_get_dev(ctx); 6218 struct sysctl_oid_list *child; 6219 struct sysctl_ctx_list *ctx_list; 6220 iflib_fl_t fl; 6221 iflib_txq_t txq; 6222 iflib_rxq_t rxq; 6223 int i, j; 6224 char namebuf[NAME_BUFLEN]; 6225 char *qfmt; 6226 struct sysctl_oid *queue_node, *fl_node, *node; 6227 struct sysctl_oid_list *queue_list, *fl_list; 6228 ctx_list = device_get_sysctl_ctx(dev); 6229 6230 node = ctx->ifc_sysctl_node; 6231 child = SYSCTL_CHILDREN(node); 6232 6233 if (scctx->isc_ntxqsets > 100) 6234 qfmt = "txq%03d"; 6235 else if (scctx->isc_ntxqsets > 10) 6236 qfmt = "txq%02d"; 6237 else 6238 qfmt = "txq%d"; 6239 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6240 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6241 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6242 CTLFLAG_RD, NULL, "Queue Name"); 6243 queue_list = SYSCTL_CHILDREN(queue_node); 6244 #if MEMORY_LOGGING 6245 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6246 CTLFLAG_RD, 6247 &txq->ift_dequeued, "total mbufs freed"); 6248 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6249 CTLFLAG_RD, 6250 &txq->ift_enqueued, "total mbufs enqueued"); 6251 #endif 6252 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6253 CTLFLAG_RD, 6254 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6255 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6256 CTLFLAG_RD, 6257 &txq->ift_pullups, "# of times m_pullup was called"); 6258 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6259 CTLFLAG_RD, 6260 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6261 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6262 CTLFLAG_RD, 6263 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6264 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6265 CTLFLAG_RD, 6266 &txq->ift_map_failed, "# of times dma map failed"); 6267 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6268 CTLFLAG_RD, 6269 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6270 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6271 CTLFLAG_RD, 6272 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6273 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6274 CTLFLAG_RD, 6275 &txq->ift_pidx, 1, "Producer Index"); 6276 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6277 CTLFLAG_RD, 6278 &txq->ift_cidx, 1, "Consumer Index"); 6279 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6280 CTLFLAG_RD, 6281 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6282 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6283 CTLFLAG_RD, 6284 &txq->ift_in_use, 1, "descriptors in use"); 6285 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6286 CTLFLAG_RD, 6287 &txq->ift_processed, "descriptors procesed for clean"); 6288 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6289 CTLFLAG_RD, 6290 &txq->ift_cleaned, "total cleaned"); 6291 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6292 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6293 0, mp_ring_state_handler, "A", "soft ring state"); 6294 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6295 CTLFLAG_RD, &txq->ift_br->enqueues, 6296 "# of enqueues to the mp_ring for this queue"); 6297 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6298 CTLFLAG_RD, &txq->ift_br->drops, 6299 "# of drops in the mp_ring for this queue"); 6300 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6301 CTLFLAG_RD, &txq->ift_br->starts, 6302 "# of normal consumer starts in the mp_ring for this queue"); 6303 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6304 CTLFLAG_RD, &txq->ift_br->stalls, 6305 "# of consumer stalls in the mp_ring for this queue"); 6306 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6307 CTLFLAG_RD, &txq->ift_br->restarts, 6308 "# of consumer restarts in the mp_ring for this queue"); 6309 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6310 CTLFLAG_RD, &txq->ift_br->abdications, 6311 "# of consumer abdications in the mp_ring for this queue"); 6312 } 6313 6314 if (scctx->isc_nrxqsets > 100) 6315 qfmt = "rxq%03d"; 6316 else if (scctx->isc_nrxqsets > 10) 6317 qfmt = "rxq%02d"; 6318 else 6319 qfmt = "rxq%d"; 6320 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6321 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6322 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6323 CTLFLAG_RD, NULL, "Queue Name"); 6324 queue_list = SYSCTL_CHILDREN(queue_node); 6325 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6326 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6327 CTLFLAG_RD, 6328 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6329 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6330 CTLFLAG_RD, 6331 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6332 } 6333 6334 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6335 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6336 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6337 CTLFLAG_RD, NULL, "freelist Name"); 6338 fl_list = SYSCTL_CHILDREN(fl_node); 6339 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6340 CTLFLAG_RD, 6341 &fl->ifl_pidx, 1, "Producer Index"); 6342 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6343 CTLFLAG_RD, 6344 &fl->ifl_cidx, 1, "Consumer Index"); 6345 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6346 CTLFLAG_RD, 6347 &fl->ifl_credits, 1, "credits available"); 6348 #if MEMORY_LOGGING 6349 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6350 CTLFLAG_RD, 6351 &fl->ifl_m_enqueued, "mbufs allocated"); 6352 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6353 CTLFLAG_RD, 6354 &fl->ifl_m_dequeued, "mbufs freed"); 6355 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6356 CTLFLAG_RD, 6357 &fl->ifl_cl_enqueued, "clusters allocated"); 6358 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6359 CTLFLAG_RD, 6360 &fl->ifl_cl_dequeued, "clusters freed"); 6361 #endif 6362 6363 } 6364 } 6365 6366 } 6367 6368 void 6369 iflib_request_reset(if_ctx_t ctx) 6370 { 6371 6372 STATE_LOCK(ctx); 6373 ctx->ifc_flags |= IFC_DO_RESET; 6374 STATE_UNLOCK(ctx); 6375 } 6376 6377 #ifndef __NO_STRICT_ALIGNMENT 6378 static struct mbuf * 6379 iflib_fixup_rx(struct mbuf *m) 6380 { 6381 struct mbuf *n; 6382 6383 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6384 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6385 m->m_data += ETHER_HDR_LEN; 6386 n = m; 6387 } else { 6388 MGETHDR(n, M_NOWAIT, MT_DATA); 6389 if (n == NULL) { 6390 m_freem(m); 6391 return (NULL); 6392 } 6393 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6394 m->m_data += ETHER_HDR_LEN; 6395 m->m_len -= ETHER_HDR_LEN; 6396 n->m_len = ETHER_HDR_LEN; 6397 M_MOVE_PKTHDR(n, m); 6398 n->m_next = m; 6399 } 6400 return (n); 6401 } 6402 #endif 6403 6404 #ifdef NETDUMP 6405 static void 6406 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6407 { 6408 if_ctx_t ctx; 6409 6410 ctx = if_getsoftc(ifp); 6411 CTX_LOCK(ctx); 6412 *nrxr = NRXQSETS(ctx); 6413 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6414 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6415 CTX_UNLOCK(ctx); 6416 } 6417 6418 static void 6419 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6420 { 6421 if_ctx_t ctx; 6422 if_softc_ctx_t scctx; 6423 iflib_fl_t fl; 6424 iflib_rxq_t rxq; 6425 int i, j; 6426 6427 ctx = if_getsoftc(ifp); 6428 scctx = &ctx->ifc_softc_ctx; 6429 6430 switch (event) { 6431 case NETDUMP_START: 6432 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6433 rxq = &ctx->ifc_rxqs[i]; 6434 for (j = 0; j < rxq->ifr_nfl; j++) { 6435 fl = rxq->ifr_fl; 6436 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6437 } 6438 } 6439 iflib_no_tx_batch = 1; 6440 break; 6441 default: 6442 break; 6443 } 6444 } 6445 6446 static int 6447 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6448 { 6449 if_ctx_t ctx; 6450 iflib_txq_t txq; 6451 int error; 6452 6453 ctx = if_getsoftc(ifp); 6454 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6455 IFF_DRV_RUNNING) 6456 return (EBUSY); 6457 6458 txq = &ctx->ifc_txqs[0]; 6459 error = iflib_encap(txq, &m); 6460 if (error == 0) 6461 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6462 return (error); 6463 } 6464 6465 static int 6466 iflib_netdump_poll(struct ifnet *ifp, int count) 6467 { 6468 if_ctx_t ctx; 6469 if_softc_ctx_t scctx; 6470 iflib_txq_t txq; 6471 int i; 6472 6473 ctx = if_getsoftc(ifp); 6474 scctx = &ctx->ifc_softc_ctx; 6475 6476 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6477 IFF_DRV_RUNNING) 6478 return (EBUSY); 6479 6480 txq = &ctx->ifc_txqs[0]; 6481 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6482 6483 for (i = 0; i < scctx->isc_nrxqsets; i++) 6484 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6485 return (0); 6486 } 6487 #endif /* NETDUMP */ 6488