1 /*- 2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 35 #include <sys/param.h> 36 #include <sys/types.h> 37 #include <sys/bus.h> 38 #include <sys/eventhandler.h> 39 #include <sys/sockio.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sysctl.h> 50 #include <sys/syslog.h> 51 #include <sys/taskqueue.h> 52 #include <sys/limits.h> 53 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_pcb.h> 65 #include <netinet/tcp_lro.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/if_ether.h> 68 #include <netinet/ip.h> 69 #include <netinet/ip6.h> 70 #include <netinet/tcp.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <vm/vm.h> 76 #include <vm/pmap.h> 77 78 #include <dev/led/led.h> 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pci_private.h> 82 83 #include <net/iflib.h> 84 85 #include "ifdi_if.h" 86 87 #if defined(__i386__) || defined(__amd64__) 88 #include <sys/memdesc.h> 89 #include <machine/bus.h> 90 #include <machine/md_var.h> 91 #include <machine/specialreg.h> 92 #include <x86/include/busdma_impl.h> 93 #include <x86/iommu/busdma_dmar.h> 94 #endif 95 96 #include <sys/bitstring.h> 97 /* 98 * enable accounting of every mbuf as it comes in to and goes out of 99 * iflib's software descriptor references 100 */ 101 #define MEMORY_LOGGING 0 102 /* 103 * Enable mbuf vectors for compressing long mbuf chains 104 */ 105 106 /* 107 * NB: 108 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 109 * we prefetch needs to be determined by the time spent in m_free vis a vis 110 * the cost of a prefetch. This will of course vary based on the workload: 111 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 112 * is quite expensive, thus suggesting very little prefetch. 113 * - small packet forwarding which is just returning a single mbuf to 114 * UMA will typically be very fast vis a vis the cost of a memory 115 * access. 116 */ 117 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 struct iflib_txq; 132 typedef struct iflib_txq *iflib_txq_t; 133 struct iflib_rxq; 134 typedef struct iflib_rxq *iflib_rxq_t; 135 struct iflib_fl; 136 typedef struct iflib_fl *iflib_fl_t; 137 138 struct iflib_ctx; 139 140 typedef struct iflib_filter_info { 141 driver_filter_t *ifi_filter; 142 void *ifi_filter_arg; 143 struct grouptask *ifi_task; 144 void *ifi_ctx; 145 } *iflib_filter_info_t; 146 147 struct iflib_ctx { 148 KOBJ_FIELDS; 149 /* 150 * Pointer to hardware driver's softc 151 */ 152 void *ifc_softc; 153 device_t ifc_dev; 154 if_t ifc_ifp; 155 156 cpuset_t ifc_cpus; 157 if_shared_ctx_t ifc_sctx; 158 struct if_softc_ctx ifc_softc_ctx; 159 160 struct mtx ifc_mtx; 161 162 uint16_t ifc_nhwtxqs; 163 uint16_t ifc_nhwrxqs; 164 165 iflib_txq_t ifc_txqs; 166 iflib_rxq_t ifc_rxqs; 167 uint32_t ifc_if_flags; 168 uint32_t ifc_flags; 169 uint32_t ifc_max_fl_buf_size; 170 int ifc_in_detach; 171 172 int ifc_link_state; 173 int ifc_link_irq; 174 int ifc_watchdog_events; 175 struct cdev *ifc_led_dev; 176 struct resource *ifc_msix_mem; 177 178 struct if_irq ifc_legacy_irq; 179 struct grouptask ifc_admin_task; 180 struct grouptask ifc_vflr_task; 181 struct iflib_filter_info ifc_filter_info; 182 struct ifmedia ifc_media; 183 184 struct sysctl_oid *ifc_sysctl_node; 185 uint16_t ifc_sysctl_ntxqs; 186 uint16_t ifc_sysctl_nrxqs; 187 uint16_t ifc_sysctl_qs_eq_override; 188 189 qidx_t ifc_sysctl_ntxds[8]; 190 qidx_t ifc_sysctl_nrxds[8]; 191 struct if_txrx ifc_txrx; 192 #define isc_txd_encap ifc_txrx.ift_txd_encap 193 #define isc_txd_flush ifc_txrx.ift_txd_flush 194 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 195 #define isc_rxd_available ifc_txrx.ift_rxd_available 196 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 197 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 198 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 199 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 200 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 201 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 202 eventhandler_tag ifc_vlan_attach_event; 203 eventhandler_tag ifc_vlan_detach_event; 204 uint8_t ifc_mac[ETHER_ADDR_LEN]; 205 char ifc_mtx_name[16]; 206 }; 207 208 209 void * 210 iflib_get_softc(if_ctx_t ctx) 211 { 212 213 return (ctx->ifc_softc); 214 } 215 216 device_t 217 iflib_get_dev(if_ctx_t ctx) 218 { 219 220 return (ctx->ifc_dev); 221 } 222 223 if_t 224 iflib_get_ifp(if_ctx_t ctx) 225 { 226 227 return (ctx->ifc_ifp); 228 } 229 230 struct ifmedia * 231 iflib_get_media(if_ctx_t ctx) 232 { 233 234 return (&ctx->ifc_media); 235 } 236 237 void 238 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 239 { 240 241 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 242 } 243 244 if_softc_ctx_t 245 iflib_get_softc_ctx(if_ctx_t ctx) 246 { 247 248 return (&ctx->ifc_softc_ctx); 249 } 250 251 if_shared_ctx_t 252 iflib_get_sctx(if_ctx_t ctx) 253 { 254 255 return (ctx->ifc_sctx); 256 } 257 258 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 259 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 260 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 261 262 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 263 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 264 265 #define RX_SW_DESC_MAP_CREATED (1 << 0) 266 #define TX_SW_DESC_MAP_CREATED (1 << 1) 267 #define RX_SW_DESC_INUSE (1 << 3) 268 #define TX_SW_DESC_MAPPED (1 << 4) 269 270 typedef struct iflib_sw_rx_desc_array { 271 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 272 struct mbuf **ifsd_m; /* pkthdr mbufs */ 273 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 274 uint8_t *ifsd_flags; 275 } iflib_rxsd_array_t; 276 277 typedef struct iflib_sw_tx_desc_array { 278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 279 struct mbuf **ifsd_m; /* pkthdr mbufs */ 280 uint8_t *ifsd_flags; 281 } if_txsd_vec_t; 282 283 284 /* magic number that should be high enough for any hardware */ 285 #define IFLIB_MAX_TX_SEGS 128 286 #define IFLIB_MAX_RX_SEGS 32 287 #define IFLIB_RX_COPY_THRESH 128 288 #define IFLIB_MAX_RX_REFRESH 32 289 /* The minimum descriptors per second before we start coalescing */ 290 #define IFLIB_MIN_DESC_SEC 16384 291 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 292 #define IFLIB_QUEUE_IDLE 0 293 #define IFLIB_QUEUE_HUNG 1 294 #define IFLIB_QUEUE_WORKING 2 295 /* maximum number of txqs that can share an rx interrupt */ 296 #define IFLIB_MAX_TX_SHARED_INTR 4 297 298 /* this should really scale with ring size - this is a fairly arbitrary value */ 299 #define TX_BATCH_SIZE 32 300 301 #define IFLIB_RESTART_BUDGET 8 302 303 #define IFC_LEGACY 0x001 304 #define IFC_QFLUSH 0x002 305 #define IFC_MULTISEG 0x004 306 #define IFC_DMAR 0x008 307 #define IFC_SC_ALLOCATED 0x010 308 #define IFC_INIT_DONE 0x020 309 #define IFC_PREFETCH 0x040 310 #define IFC_DO_RESET 0x080 311 #define IFC_CHECK_HUNG 0x100 312 313 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 314 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 315 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 316 struct iflib_txq { 317 qidx_t ift_in_use; 318 qidx_t ift_cidx; 319 qidx_t ift_cidx_processed; 320 qidx_t ift_pidx; 321 uint8_t ift_gen; 322 uint8_t ift_br_offset; 323 uint16_t ift_npending; 324 uint16_t ift_db_pending; 325 uint16_t ift_rs_pending; 326 /* implicit pad */ 327 uint8_t ift_txd_size[8]; 328 uint64_t ift_processed; 329 uint64_t ift_cleaned; 330 uint64_t ift_cleaned_prev; 331 #if MEMORY_LOGGING 332 uint64_t ift_enqueued; 333 uint64_t ift_dequeued; 334 #endif 335 uint64_t ift_no_tx_dma_setup; 336 uint64_t ift_no_desc_avail; 337 uint64_t ift_mbuf_defrag_failed; 338 uint64_t ift_mbuf_defrag; 339 uint64_t ift_map_failed; 340 uint64_t ift_txd_encap_efbig; 341 uint64_t ift_pullups; 342 343 struct mtx ift_mtx; 344 struct mtx ift_db_mtx; 345 346 /* constant values */ 347 if_ctx_t ift_ctx; 348 struct ifmp_ring *ift_br; 349 struct grouptask ift_task; 350 qidx_t ift_size; 351 uint16_t ift_id; 352 struct callout ift_timer; 353 354 if_txsd_vec_t ift_sds; 355 uint8_t ift_qstatus; 356 uint8_t ift_closed; 357 uint8_t ift_update_freq; 358 struct iflib_filter_info ift_filter_info; 359 bus_dma_tag_t ift_desc_tag; 360 bus_dma_tag_t ift_tso_desc_tag; 361 iflib_dma_info_t ift_ifdi; 362 #define MTX_NAME_LEN 16 363 char ift_mtx_name[MTX_NAME_LEN]; 364 char ift_db_mtx_name[MTX_NAME_LEN]; 365 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 366 #ifdef IFLIB_DIAGNOSTICS 367 uint64_t ift_cpu_exec_count[256]; 368 #endif 369 } __aligned(CACHE_LINE_SIZE); 370 371 struct iflib_fl { 372 qidx_t ifl_cidx; 373 qidx_t ifl_pidx; 374 qidx_t ifl_credits; 375 uint8_t ifl_gen; 376 uint8_t ifl_rxd_size; 377 #if MEMORY_LOGGING 378 uint64_t ifl_m_enqueued; 379 uint64_t ifl_m_dequeued; 380 uint64_t ifl_cl_enqueued; 381 uint64_t ifl_cl_dequeued; 382 #endif 383 /* implicit pad */ 384 385 bitstr_t *ifl_rx_bitmap;; 386 qidx_t ifl_fragidx; 387 /* constant */ 388 qidx_t ifl_size; 389 uint16_t ifl_buf_size; 390 uint16_t ifl_cltype; 391 uma_zone_t ifl_zone; 392 iflib_rxsd_array_t ifl_sds; 393 iflib_rxq_t ifl_rxq; 394 uint8_t ifl_id; 395 bus_dma_tag_t ifl_desc_tag; 396 iflib_dma_info_t ifl_ifdi; 397 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 398 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 399 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 400 } __aligned(CACHE_LINE_SIZE); 401 402 static inline qidx_t 403 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 404 { 405 qidx_t used; 406 407 if (pidx > cidx) 408 used = pidx - cidx; 409 else if (pidx < cidx) 410 used = size - cidx + pidx; 411 else if (gen == 0 && pidx == cidx) 412 used = 0; 413 else if (gen == 1 && pidx == cidx) 414 used = size; 415 else 416 panic("bad state"); 417 418 return (used); 419 } 420 421 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 422 423 #define IDXDIFF(head, tail, wrap) \ 424 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 425 426 struct iflib_rxq { 427 /* If there is a separate completion queue - 428 * these are the cq cidx and pidx. Otherwise 429 * these are unused. 430 */ 431 qidx_t ifr_size; 432 qidx_t ifr_cq_cidx; 433 qidx_t ifr_cq_pidx; 434 uint8_t ifr_cq_gen; 435 uint8_t ifr_fl_offset; 436 437 if_ctx_t ifr_ctx; 438 iflib_fl_t ifr_fl; 439 uint64_t ifr_rx_irq; 440 uint16_t ifr_id; 441 uint8_t ifr_lro_enabled; 442 uint8_t ifr_nfl; 443 uint8_t ifr_ntxqirq; 444 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 445 struct lro_ctrl ifr_lc; 446 struct grouptask ifr_task; 447 struct iflib_filter_info ifr_filter_info; 448 iflib_dma_info_t ifr_ifdi; 449 450 /* dynamically allocate if any drivers need a value substantially larger than this */ 451 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 452 #ifdef IFLIB_DIAGNOSTICS 453 uint64_t ifr_cpu_exec_count[256]; 454 #endif 455 } __aligned(CACHE_LINE_SIZE); 456 457 typedef struct if_rxsd { 458 caddr_t *ifsd_cl; 459 struct mbuf **ifsd_m; 460 iflib_fl_t ifsd_fl; 461 qidx_t ifsd_cidx; 462 } *if_rxsd_t; 463 464 /* multiple of word size */ 465 #ifdef __LP64__ 466 #define PKT_INFO_SIZE 6 467 #define RXD_INFO_SIZE 5 468 #define PKT_TYPE uint64_t 469 #else 470 #define PKT_INFO_SIZE 11 471 #define RXD_INFO_SIZE 8 472 #define PKT_TYPE uint32_t 473 #endif 474 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 475 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 476 477 typedef struct if_pkt_info_pad { 478 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 479 } *if_pkt_info_pad_t; 480 typedef struct if_rxd_info_pad { 481 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 482 } *if_rxd_info_pad_t; 483 484 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 485 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 486 487 488 static inline void 489 pkt_info_zero(if_pkt_info_t pi) 490 { 491 if_pkt_info_pad_t pi_pad; 492 493 pi_pad = (if_pkt_info_pad_t)pi; 494 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 495 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 496 #ifndef __LP64__ 497 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 498 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 499 #endif 500 } 501 502 static inline void 503 rxd_info_zero(if_rxd_info_t ri) 504 { 505 if_rxd_info_pad_t ri_pad; 506 int i; 507 508 ri_pad = (if_rxd_info_pad_t)ri; 509 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 510 ri_pad->rxd_val[i] = 0; 511 ri_pad->rxd_val[i+1] = 0; 512 ri_pad->rxd_val[i+2] = 0; 513 ri_pad->rxd_val[i+3] = 0; 514 } 515 #ifdef __LP64__ 516 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 517 #endif 518 } 519 520 /* 521 * Only allow a single packet to take up most 1/nth of the tx ring 522 */ 523 #define MAX_SINGLE_PACKET_FRACTION 12 524 #define IF_BAD_DMA (bus_addr_t)-1 525 526 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 527 528 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) 529 530 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) 531 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) 532 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) 533 534 535 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 536 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 537 538 539 /* Our boot-time initialization hook */ 540 static int iflib_module_event_handler(module_t, int, void *); 541 542 static moduledata_t iflib_moduledata = { 543 "iflib", 544 iflib_module_event_handler, 545 NULL 546 }; 547 548 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 549 MODULE_VERSION(iflib, 1); 550 551 MODULE_DEPEND(iflib, pci, 1, 1, 1); 552 MODULE_DEPEND(iflib, ether, 1, 1, 1); 553 554 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 555 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 556 557 #ifndef IFLIB_DEBUG_COUNTERS 558 #ifdef INVARIANTS 559 #define IFLIB_DEBUG_COUNTERS 1 560 #else 561 #define IFLIB_DEBUG_COUNTERS 0 562 #endif /* !INVARIANTS */ 563 #endif 564 565 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 566 "iflib driver parameters"); 567 568 /* 569 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 570 */ 571 static int iflib_min_tx_latency = 0; 572 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 573 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 574 static int iflib_no_tx_batch = 0; 575 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 576 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 577 578 579 #if IFLIB_DEBUG_COUNTERS 580 581 static int iflib_tx_seen; 582 static int iflib_tx_sent; 583 static int iflib_tx_encap; 584 static int iflib_rx_allocs; 585 static int iflib_fl_refills; 586 static int iflib_fl_refills_large; 587 static int iflib_tx_frees; 588 589 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 590 &iflib_tx_seen, 0, "# tx mbufs seen"); 591 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 592 &iflib_tx_sent, 0, "# tx mbufs sent"); 593 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 594 &iflib_tx_encap, 0, "# tx mbufs encapped"); 595 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 596 &iflib_tx_frees, 0, "# tx frees"); 597 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 598 &iflib_rx_allocs, 0, "# rx allocations"); 599 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 600 &iflib_fl_refills, 0, "# refills"); 601 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 602 &iflib_fl_refills_large, 0, "# large refills"); 603 604 605 static int iflib_txq_drain_flushing; 606 static int iflib_txq_drain_oactive; 607 static int iflib_txq_drain_notready; 608 static int iflib_txq_drain_encapfail; 609 610 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 611 &iflib_txq_drain_flushing, 0, "# drain flushes"); 612 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 613 &iflib_txq_drain_oactive, 0, "# drain oactives"); 614 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 615 &iflib_txq_drain_notready, 0, "# drain notready"); 616 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 617 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 618 619 620 static int iflib_encap_load_mbuf_fail; 621 static int iflib_encap_txq_avail_fail; 622 static int iflib_encap_txd_encap_fail; 623 624 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 625 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 627 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 629 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 630 631 static int iflib_task_fn_rxs; 632 static int iflib_rx_intr_enables; 633 static int iflib_fast_intrs; 634 static int iflib_intr_link; 635 static int iflib_intr_msix; 636 static int iflib_rx_unavail; 637 static int iflib_rx_ctx_inactive; 638 static int iflib_rx_zero_len; 639 static int iflib_rx_if_input; 640 static int iflib_rx_mbuf_null; 641 static int iflib_rxd_flush; 642 643 static int iflib_verbose_debug; 644 645 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 646 &iflib_intr_link, 0, "# intr link calls"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 648 &iflib_intr_msix, 0, "# intr msix calls"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 650 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 651 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 652 &iflib_rx_intr_enables, 0, "# rx intr enables"); 653 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 654 &iflib_fast_intrs, 0, "# fast_intr calls"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 656 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 658 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 660 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 662 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 664 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 666 &iflib_rxd_flush, 0, "# times rxd_flush called"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 668 &iflib_verbose_debug, 0, "enable verbose debugging"); 669 670 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 671 static void 672 iflib_debug_reset(void) 673 { 674 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 675 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 676 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 677 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 678 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail = 679 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables = 680 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 681 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 682 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 683 } 684 685 #else 686 #define DBG_COUNTER_INC(name) 687 static void iflib_debug_reset(void) {} 688 #endif 689 690 691 692 #define IFLIB_DEBUG 0 693 694 static void iflib_tx_structures_free(if_ctx_t ctx); 695 static void iflib_rx_structures_free(if_ctx_t ctx); 696 static int iflib_queues_alloc(if_ctx_t ctx); 697 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 698 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 699 static int iflib_qset_structures_setup(if_ctx_t ctx); 700 static int iflib_msix_init(if_ctx_t ctx); 701 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 702 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 703 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 704 static int iflib_register(if_ctx_t); 705 static void iflib_init_locked(if_ctx_t ctx); 706 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 707 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 708 static void iflib_ifmp_purge(iflib_txq_t txq); 709 static void _iflib_pre_assert(if_softc_ctx_t scctx); 710 static void iflib_stop(if_ctx_t ctx); 711 static void iflib_if_init_locked(if_ctx_t ctx); 712 #ifndef __NO_STRICT_ALIGNMENT 713 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 714 #endif 715 716 #ifdef DEV_NETMAP 717 #include <sys/selinfo.h> 718 #include <net/netmap.h> 719 #include <dev/netmap/netmap_kern.h> 720 721 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 722 723 /* 724 * device-specific sysctl variables: 725 * 726 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 727 * During regular operations the CRC is stripped, but on some 728 * hardware reception of frames not multiple of 64 is slower, 729 * so using crcstrip=0 helps in benchmarks. 730 * 731 * iflib_rx_miss, iflib_rx_miss_bufs: 732 * count packets that might be missed due to lost interrupts. 733 */ 734 SYSCTL_DECL(_dev_netmap); 735 /* 736 * The xl driver by default strips CRCs and we do not override it. 737 */ 738 739 int iflib_crcstrip = 1; 740 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 741 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 742 743 int iflib_rx_miss, iflib_rx_miss_bufs; 744 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 745 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 746 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 747 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 748 749 /* 750 * Register/unregister. We are already under netmap lock. 751 * Only called on the first register or the last unregister. 752 */ 753 static int 754 iflib_netmap_register(struct netmap_adapter *na, int onoff) 755 { 756 struct ifnet *ifp = na->ifp; 757 if_ctx_t ctx = ifp->if_softc; 758 int status; 759 760 CTX_LOCK(ctx); 761 IFDI_INTR_DISABLE(ctx); 762 763 /* Tell the stack that the interface is no longer active */ 764 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 765 766 if (!CTX_IS_VF(ctx)) 767 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 768 769 /* enable or disable flags and callbacks in na and ifp */ 770 if (onoff) { 771 nm_set_native_flags(na); 772 } else { 773 nm_clear_native_flags(na); 774 } 775 iflib_stop(ctx); 776 iflib_init_locked(ctx); 777 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 778 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 779 if (status) 780 nm_clear_native_flags(na); 781 CTX_UNLOCK(ctx); 782 return (status); 783 } 784 785 /* 786 * Reconcile kernel and user view of the transmit ring. 787 * 788 * All information is in the kring. 789 * Userspace wants to send packets up to the one before kring->rhead, 790 * kernel knows kring->nr_hwcur is the first unsent packet. 791 * 792 * Here we push packets out (as many as possible), and possibly 793 * reclaim buffers from previously completed transmission. 794 * 795 * The caller (netmap) guarantees that there is only one instance 796 * running at any time. Any interference with other driver 797 * methods should be handled by the individual drivers. 798 */ 799 static int 800 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 801 { 802 struct netmap_adapter *na = kring->na; 803 struct ifnet *ifp = na->ifp; 804 struct netmap_ring *ring = kring->ring; 805 u_int nm_i; /* index into the netmap ring */ 806 u_int nic_i; /* index into the NIC ring */ 807 u_int n; 808 u_int const lim = kring->nkr_num_slots - 1; 809 u_int const head = kring->rhead; 810 struct if_pkt_info pi; 811 812 /* 813 * interrupts on every tx packet are expensive so request 814 * them every half ring, or where NS_REPORT is set 815 */ 816 u_int report_frequency = kring->nkr_num_slots >> 1; 817 /* device-specific */ 818 if_ctx_t ctx = ifp->if_softc; 819 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 820 821 if (txq->ift_sds.ifsd_map) 822 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 823 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 824 825 826 /* 827 * First part: process new packets to send. 828 * nm_i is the current index in the netmap ring, 829 * nic_i is the corresponding index in the NIC ring. 830 * 831 * If we have packets to send (nm_i != head) 832 * iterate over the netmap ring, fetch length and update 833 * the corresponding slot in the NIC ring. Some drivers also 834 * need to update the buffer's physical address in the NIC slot 835 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 836 * 837 * The netmap_reload_map() calls is especially expensive, 838 * even when (as in this case) the tag is 0, so do only 839 * when the buffer has actually changed. 840 * 841 * If possible do not set the report/intr bit on all slots, 842 * but only a few times per ring or when NS_REPORT is set. 843 * 844 * Finally, on 10G and faster drivers, it might be useful 845 * to prefetch the next slot and txr entry. 846 */ 847 848 nm_i = kring->nr_hwcur; 849 pkt_info_zero(&pi); 850 pi.ipi_segs = txq->ift_segs; 851 pi.ipi_qsidx = kring->ring_id; 852 if (nm_i != head) { /* we have new packets to send */ 853 nic_i = netmap_idx_k2n(kring, nm_i); 854 855 __builtin_prefetch(&ring->slot[nm_i]); 856 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 857 if (txq->ift_sds.ifsd_map) 858 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 859 860 for (n = 0; nm_i != head; n++) { 861 struct netmap_slot *slot = &ring->slot[nm_i]; 862 u_int len = slot->len; 863 uint64_t paddr; 864 void *addr = PNMB(na, slot, &paddr); 865 int flags = (slot->flags & NS_REPORT || 866 nic_i == 0 || nic_i == report_frequency) ? 867 IPI_TX_INTR : 0; 868 869 /* device-specific */ 870 pi.ipi_len = len; 871 pi.ipi_segs[0].ds_addr = paddr; 872 pi.ipi_segs[0].ds_len = len; 873 pi.ipi_nsegs = 1; 874 pi.ipi_ndescs = 0; 875 pi.ipi_pidx = nic_i; 876 pi.ipi_flags = flags; 877 878 /* Fill the slot in the NIC ring. */ 879 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 880 881 /* prefetch for next round */ 882 __builtin_prefetch(&ring->slot[nm_i + 1]); 883 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 884 if (txq->ift_sds.ifsd_map) { 885 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 886 887 NM_CHECK_ADDR_LEN(na, addr, len); 888 889 if (slot->flags & NS_BUF_CHANGED) { 890 /* buffer has changed, reload map */ 891 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 892 } 893 /* make sure changes to the buffer are synced */ 894 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 895 BUS_DMASYNC_PREWRITE); 896 } 897 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 898 nm_i = nm_next(nm_i, lim); 899 nic_i = nm_next(nic_i, lim); 900 } 901 kring->nr_hwcur = head; 902 903 /* synchronize the NIC ring */ 904 if (txq->ift_sds.ifsd_map) 905 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 906 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 907 908 /* (re)start the tx unit up to slot nic_i (excluded) */ 909 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 910 } 911 912 /* 913 * Second part: reclaim buffers for completed transmissions. 914 */ 915 if (iflib_tx_credits_update(ctx, txq)) { 916 /* some tx completed, increment avail */ 917 nic_i = txq->ift_cidx_processed; 918 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 919 } 920 return (0); 921 } 922 923 /* 924 * Reconcile kernel and user view of the receive ring. 925 * Same as for the txsync, this routine must be efficient. 926 * The caller guarantees a single invocations, but races against 927 * the rest of the driver should be handled here. 928 * 929 * On call, kring->rhead is the first packet that userspace wants 930 * to keep, and kring->rcur is the wakeup point. 931 * The kernel has previously reported packets up to kring->rtail. 932 * 933 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 934 * of whether or not we received an interrupt. 935 */ 936 static int 937 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 938 { 939 struct netmap_adapter *na = kring->na; 940 struct netmap_ring *ring = kring->ring; 941 uint32_t nm_i; /* index into the netmap ring */ 942 uint32_t nic_i, nic_i_start; /* index into the NIC ring */ 943 u_int i, n; 944 u_int const lim = kring->nkr_num_slots - 1; 945 u_int const head = kring->rhead; 946 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 947 struct if_rxd_info ri; 948 struct if_rxd_update iru; 949 950 struct ifnet *ifp = na->ifp; 951 if_ctx_t ctx = ifp->if_softc; 952 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 953 iflib_fl_t fl = rxq->ifr_fl; 954 if (head > lim) 955 return netmap_ring_reinit(kring); 956 957 /* XXX check sync modes */ 958 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 959 if (fl->ifl_sds.ifsd_map == NULL) 960 continue; 961 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 962 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 963 } 964 /* 965 * First part: import newly received packets. 966 * 967 * nm_i is the index of the next free slot in the netmap ring, 968 * nic_i is the index of the next received packet in the NIC ring, 969 * and they may differ in case if_init() has been called while 970 * in netmap mode. For the receive ring we have 971 * 972 * nic_i = rxr->next_check; 973 * nm_i = kring->nr_hwtail (previous) 974 * and 975 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 976 * 977 * rxr->next_check is set to 0 on a ring reinit 978 */ 979 if (netmap_no_pendintr || force_update) { 980 int crclen = iflib_crcstrip ? 0 : 4; 981 int error, avail; 982 uint16_t slot_flags = kring->nkr_slot_flags; 983 984 for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) { 985 nic_i = fl->ifl_cidx; 986 nm_i = netmap_idx_n2k(kring, nic_i); 987 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 988 for (n = 0; avail > 0; n++, avail--) { 989 rxd_info_zero(&ri); 990 ri.iri_frags = rxq->ifr_frags; 991 ri.iri_qsidx = kring->ring_id; 992 ri.iri_ifp = ctx->ifc_ifp; 993 ri.iri_cidx = nic_i; 994 995 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 996 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 997 ring->slot[nm_i].flags = slot_flags; 998 if (fl->ifl_sds.ifsd_map) 999 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1000 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1001 nm_i = nm_next(nm_i, lim); 1002 nic_i = nm_next(nic_i, lim); 1003 } 1004 if (n) { /* update the state variables */ 1005 if (netmap_no_pendintr && !force_update) { 1006 /* diagnostics */ 1007 iflib_rx_miss ++; 1008 iflib_rx_miss_bufs += n; 1009 } 1010 fl->ifl_cidx = nic_i; 1011 kring->nr_hwtail = nm_i; 1012 } 1013 kring->nr_kflags &= ~NKR_PENDINTR; 1014 } 1015 } 1016 /* 1017 * Second part: skip past packets that userspace has released. 1018 * (kring->nr_hwcur to head excluded), 1019 * and make the buffers available for reception. 1020 * As usual nm_i is the index in the netmap ring, 1021 * nic_i is the index in the NIC ring, and 1022 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1023 */ 1024 /* XXX not sure how this will work with multiple free lists */ 1025 nm_i = kring->nr_hwcur; 1026 if (nm_i == head) 1027 return (0); 1028 1029 iru.iru_paddrs = fl->ifl_bus_addrs; 1030 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1031 iru.iru_idxs = fl->ifl_rxd_idxs; 1032 iru.iru_qsidx = rxq->ifr_id; 1033 iru.iru_buf_size = fl->ifl_buf_size; 1034 iru.iru_flidx = fl->ifl_id; 1035 nic_i_start = nic_i = netmap_idx_k2n(kring, nm_i); 1036 for (i = 0; nm_i != head; i++) { 1037 struct netmap_slot *slot = &ring->slot[nm_i]; 1038 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 1039 1040 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 1041 goto ring_reset; 1042 1043 fl->ifl_vm_addrs[i] = addr; 1044 if (fl->ifl_sds.ifsd_map && (slot->flags & NS_BUF_CHANGED)) { 1045 /* buffer has changed, reload map */ 1046 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], addr); 1047 } 1048 slot->flags &= ~NS_BUF_CHANGED; 1049 1050 nm_i = nm_next(nm_i, lim); 1051 fl->ifl_rxd_idxs[i] = nic_i = nm_next(nic_i, lim); 1052 if (nm_i != head && i < IFLIB_MAX_RX_REFRESH) 1053 continue; 1054 1055 iru.iru_pidx = nic_i_start; 1056 iru.iru_count = i; 1057 i = 0; 1058 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1059 if (fl->ifl_sds.ifsd_map == NULL) { 1060 nic_i_start = nic_i; 1061 continue; 1062 } 1063 nic_i = nic_i_start; 1064 for (n = 0; n < iru.iru_count; n++) { 1065 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], 1066 BUS_DMASYNC_PREREAD); 1067 nic_i = nm_next(nic_i, lim); 1068 } 1069 nic_i_start = nic_i; 1070 } 1071 kring->nr_hwcur = head; 1072 1073 if (fl->ifl_sds.ifsd_map) 1074 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1075 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1076 /* 1077 * IMPORTANT: we must leave one free slot in the ring, 1078 * so move nic_i back by one unit 1079 */ 1080 nic_i = nm_prev(nic_i, lim); 1081 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 1082 return 0; 1083 1084 ring_reset: 1085 return netmap_ring_reinit(kring); 1086 } 1087 1088 static void 1089 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1090 { 1091 struct ifnet *ifp = na->ifp; 1092 if_ctx_t ctx = ifp->if_softc; 1093 1094 CTX_LOCK(ctx); 1095 if (onoff) { 1096 IFDI_INTR_ENABLE(ctx); 1097 } else { 1098 IFDI_INTR_DISABLE(ctx); 1099 } 1100 CTX_UNLOCK(ctx); 1101 } 1102 1103 1104 static int 1105 iflib_netmap_attach(if_ctx_t ctx) 1106 { 1107 struct netmap_adapter na; 1108 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1109 1110 bzero(&na, sizeof(na)); 1111 1112 na.ifp = ctx->ifc_ifp; 1113 na.na_flags = NAF_BDG_MAYSLEEP; 1114 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1115 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1116 1117 na.num_tx_desc = scctx->isc_ntxd[0]; 1118 na.num_rx_desc = scctx->isc_nrxd[0]; 1119 na.nm_txsync = iflib_netmap_txsync; 1120 na.nm_rxsync = iflib_netmap_rxsync; 1121 na.nm_register = iflib_netmap_register; 1122 na.nm_intr = iflib_netmap_intr; 1123 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1124 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1125 return (netmap_attach(&na)); 1126 } 1127 1128 static void 1129 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1130 { 1131 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1132 struct netmap_slot *slot; 1133 1134 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1135 if (slot == NULL) 1136 return; 1137 if (txq->ift_sds.ifsd_map == NULL) 1138 return; 1139 1140 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1141 1142 /* 1143 * In netmap mode, set the map for the packet buffer. 1144 * NOTE: Some drivers (not this one) also need to set 1145 * the physical buffer address in the NIC ring. 1146 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1147 * netmap slot index, si 1148 */ 1149 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); 1150 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1151 } 1152 } 1153 static void 1154 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1155 { 1156 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1157 struct netmap_slot *slot; 1158 struct if_rxd_update iru; 1159 iflib_fl_t fl; 1160 bus_dmamap_t *map; 1161 int nrxd; 1162 uint32_t i, j, pidx_start; 1163 1164 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1165 if (slot == NULL) 1166 return; 1167 fl = &rxq->ifr_fl[0]; 1168 map = fl->ifl_sds.ifsd_map; 1169 nrxd = ctx->ifc_softc_ctx.isc_nrxd[0]; 1170 iru.iru_paddrs = fl->ifl_bus_addrs; 1171 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1172 iru.iru_idxs = fl->ifl_rxd_idxs; 1173 iru.iru_qsidx = rxq->ifr_id; 1174 iru.iru_buf_size = rxq->ifr_fl[0].ifl_buf_size; 1175 iru.iru_flidx = 0; 1176 1177 for (pidx_start = i = j = 0; i < nrxd; i++, j++) { 1178 int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i); 1179 void *addr; 1180 1181 fl->ifl_rxd_idxs[j] = i; 1182 addr = fl->ifl_vm_addrs[j] = PNMB(na, slot + sj, &fl->ifl_bus_addrs[j]); 1183 if (map) { 1184 netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, *map, addr); 1185 map++; 1186 } 1187 1188 if (j < IFLIB_MAX_RX_REFRESH && i < nrxd - 1) 1189 continue; 1190 1191 iru.iru_pidx = pidx_start; 1192 pidx_start = i; 1193 iru.iru_count = j; 1194 j = 0; 1195 MPASS(pidx_start + j <= nrxd); 1196 /* Update descriptors and the cached value */ 1197 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1198 } 1199 /* preserve queue */ 1200 if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) { 1201 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; 1202 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); 1203 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t); 1204 } else 1205 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1); 1206 } 1207 1208 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1209 1210 #else 1211 #define iflib_netmap_txq_init(ctx, txq) 1212 #define iflib_netmap_rxq_init(ctx, rxq) 1213 #define iflib_netmap_detach(ifp) 1214 1215 #define iflib_netmap_attach(ctx) (0) 1216 #define netmap_rx_irq(ifp, qid, budget) (0) 1217 #define netmap_tx_irq(ifp, qid) do {} while (0) 1218 1219 #endif 1220 1221 #if defined(__i386__) || defined(__amd64__) 1222 static __inline void 1223 prefetch(void *x) 1224 { 1225 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1226 } 1227 #else 1228 #define prefetch(x) 1229 #endif 1230 1231 static void 1232 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1233 { 1234 if (err) 1235 return; 1236 *(bus_addr_t *) arg = segs[0].ds_addr; 1237 } 1238 1239 int 1240 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1241 { 1242 int err; 1243 if_shared_ctx_t sctx = ctx->ifc_sctx; 1244 device_t dev = ctx->ifc_dev; 1245 1246 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1247 1248 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1249 sctx->isc_q_align, 0, /* alignment, bounds */ 1250 BUS_SPACE_MAXADDR, /* lowaddr */ 1251 BUS_SPACE_MAXADDR, /* highaddr */ 1252 NULL, NULL, /* filter, filterarg */ 1253 size, /* maxsize */ 1254 1, /* nsegments */ 1255 size, /* maxsegsize */ 1256 BUS_DMA_ALLOCNOW, /* flags */ 1257 NULL, /* lockfunc */ 1258 NULL, /* lockarg */ 1259 &dma->idi_tag); 1260 if (err) { 1261 device_printf(dev, 1262 "%s: bus_dma_tag_create failed: %d\n", 1263 __func__, err); 1264 goto fail_0; 1265 } 1266 1267 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1268 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1269 if (err) { 1270 device_printf(dev, 1271 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1272 __func__, (uintmax_t)size, err); 1273 goto fail_1; 1274 } 1275 1276 dma->idi_paddr = IF_BAD_DMA; 1277 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1278 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1279 if (err || dma->idi_paddr == IF_BAD_DMA) { 1280 device_printf(dev, 1281 "%s: bus_dmamap_load failed: %d\n", 1282 __func__, err); 1283 goto fail_2; 1284 } 1285 1286 dma->idi_size = size; 1287 return (0); 1288 1289 fail_2: 1290 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1291 fail_1: 1292 bus_dma_tag_destroy(dma->idi_tag); 1293 fail_0: 1294 dma->idi_tag = NULL; 1295 1296 return (err); 1297 } 1298 1299 int 1300 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1301 { 1302 int i, err; 1303 iflib_dma_info_t *dmaiter; 1304 1305 dmaiter = dmalist; 1306 for (i = 0; i < count; i++, dmaiter++) { 1307 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1308 break; 1309 } 1310 if (err) 1311 iflib_dma_free_multi(dmalist, i); 1312 return (err); 1313 } 1314 1315 void 1316 iflib_dma_free(iflib_dma_info_t dma) 1317 { 1318 if (dma->idi_tag == NULL) 1319 return; 1320 if (dma->idi_paddr != IF_BAD_DMA) { 1321 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1322 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1323 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1324 dma->idi_paddr = IF_BAD_DMA; 1325 } 1326 if (dma->idi_vaddr != NULL) { 1327 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1328 dma->idi_vaddr = NULL; 1329 } 1330 bus_dma_tag_destroy(dma->idi_tag); 1331 dma->idi_tag = NULL; 1332 } 1333 1334 void 1335 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1336 { 1337 int i; 1338 iflib_dma_info_t *dmaiter = dmalist; 1339 1340 for (i = 0; i < count; i++, dmaiter++) 1341 iflib_dma_free(*dmaiter); 1342 } 1343 1344 #ifdef EARLY_AP_STARTUP 1345 static const int iflib_started = 1; 1346 #else 1347 /* 1348 * We used to abuse the smp_started flag to decide if the queues have been 1349 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1350 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1351 * is set. Run a SYSINIT() strictly after that to just set a usable 1352 * completion flag. 1353 */ 1354 1355 static int iflib_started; 1356 1357 static void 1358 iflib_record_started(void *arg) 1359 { 1360 iflib_started = 1; 1361 } 1362 1363 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1364 iflib_record_started, NULL); 1365 #endif 1366 1367 static int 1368 iflib_fast_intr(void *arg) 1369 { 1370 iflib_filter_info_t info = arg; 1371 struct grouptask *gtask = info->ifi_task; 1372 if (!iflib_started) 1373 return (FILTER_HANDLED); 1374 1375 DBG_COUNTER_INC(fast_intrs); 1376 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1377 return (FILTER_HANDLED); 1378 1379 GROUPTASK_ENQUEUE(gtask); 1380 return (FILTER_HANDLED); 1381 } 1382 1383 static int 1384 iflib_fast_intr_rxtx(void *arg) 1385 { 1386 iflib_filter_info_t info = arg; 1387 struct grouptask *gtask = info->ifi_task; 1388 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1389 if_ctx_t ctx; 1390 int i, cidx; 1391 1392 if (!iflib_started) 1393 return (FILTER_HANDLED); 1394 1395 DBG_COUNTER_INC(fast_intrs); 1396 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1397 return (FILTER_HANDLED); 1398 1399 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1400 qidx_t txqid = rxq->ifr_txqid[i]; 1401 1402 ctx = rxq->ifr_ctx; 1403 1404 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1405 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1406 continue; 1407 } 1408 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1409 } 1410 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1411 cidx = rxq->ifr_cq_cidx; 1412 else 1413 cidx = rxq->ifr_fl[0].ifl_cidx; 1414 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1415 GROUPTASK_ENQUEUE(gtask); 1416 else 1417 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1418 return (FILTER_HANDLED); 1419 } 1420 1421 1422 static int 1423 iflib_fast_intr_ctx(void *arg) 1424 { 1425 iflib_filter_info_t info = arg; 1426 struct grouptask *gtask = info->ifi_task; 1427 1428 if (!iflib_started) 1429 return (FILTER_HANDLED); 1430 1431 DBG_COUNTER_INC(fast_intrs); 1432 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1433 return (FILTER_HANDLED); 1434 1435 GROUPTASK_ENQUEUE(gtask); 1436 return (FILTER_HANDLED); 1437 } 1438 1439 static int 1440 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1441 driver_filter_t filter, driver_intr_t handler, void *arg, 1442 char *name) 1443 { 1444 int rc, flags; 1445 struct resource *res; 1446 void *tag = NULL; 1447 device_t dev = ctx->ifc_dev; 1448 1449 flags = RF_ACTIVE; 1450 if (ctx->ifc_flags & IFC_LEGACY) 1451 flags |= RF_SHAREABLE; 1452 MPASS(rid < 512); 1453 irq->ii_rid = rid; 1454 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1455 if (res == NULL) { 1456 device_printf(dev, 1457 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1458 return (ENOMEM); 1459 } 1460 irq->ii_res = res; 1461 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1462 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1463 filter, handler, arg, &tag); 1464 if (rc != 0) { 1465 device_printf(dev, 1466 "failed to setup interrupt for rid %d, name %s: %d\n", 1467 rid, name ? name : "unknown", rc); 1468 return (rc); 1469 } else if (name) 1470 bus_describe_intr(dev, res, tag, "%s", name); 1471 1472 irq->ii_tag = tag; 1473 return (0); 1474 } 1475 1476 1477 /********************************************************************* 1478 * 1479 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1480 * the information needed to transmit a packet on the wire. This is 1481 * called only once at attach, setup is done every reset. 1482 * 1483 **********************************************************************/ 1484 1485 static int 1486 iflib_txsd_alloc(iflib_txq_t txq) 1487 { 1488 if_ctx_t ctx = txq->ift_ctx; 1489 if_shared_ctx_t sctx = ctx->ifc_sctx; 1490 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1491 device_t dev = ctx->ifc_dev; 1492 int err, nsegments, ntsosegments; 1493 1494 nsegments = scctx->isc_tx_nsegments; 1495 ntsosegments = scctx->isc_tx_tso_segments_max; 1496 MPASS(scctx->isc_ntxd[0] > 0); 1497 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1498 MPASS(nsegments > 0); 1499 MPASS(ntsosegments > 0); 1500 /* 1501 * Setup DMA descriptor areas. 1502 */ 1503 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1504 1, 0, /* alignment, bounds */ 1505 BUS_SPACE_MAXADDR, /* lowaddr */ 1506 BUS_SPACE_MAXADDR, /* highaddr */ 1507 NULL, NULL, /* filter, filterarg */ 1508 sctx->isc_tx_maxsize, /* maxsize */ 1509 nsegments, /* nsegments */ 1510 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1511 0, /* flags */ 1512 NULL, /* lockfunc */ 1513 NULL, /* lockfuncarg */ 1514 &txq->ift_desc_tag))) { 1515 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1516 device_printf(dev,"maxsize: %zd nsegments: %d maxsegsize: %zd\n", 1517 sctx->isc_tx_maxsize, nsegments, sctx->isc_tx_maxsegsize); 1518 goto fail; 1519 } 1520 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1521 1, 0, /* alignment, bounds */ 1522 BUS_SPACE_MAXADDR, /* lowaddr */ 1523 BUS_SPACE_MAXADDR, /* highaddr */ 1524 NULL, NULL, /* filter, filterarg */ 1525 scctx->isc_tx_tso_size_max, /* maxsize */ 1526 ntsosegments, /* nsegments */ 1527 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1528 0, /* flags */ 1529 NULL, /* lockfunc */ 1530 NULL, /* lockfuncarg */ 1531 &txq->ift_tso_desc_tag))) { 1532 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1533 1534 goto fail; 1535 } 1536 if (!(txq->ift_sds.ifsd_flags = 1537 (uint8_t *) malloc(sizeof(uint8_t) * 1538 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1539 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1540 err = ENOMEM; 1541 goto fail; 1542 } 1543 if (!(txq->ift_sds.ifsd_m = 1544 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1545 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1546 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1547 err = ENOMEM; 1548 goto fail; 1549 } 1550 1551 /* Create the descriptor buffer dma maps */ 1552 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1553 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1554 return (0); 1555 1556 if (!(txq->ift_sds.ifsd_map = 1557 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1558 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1559 err = ENOMEM; 1560 goto fail; 1561 } 1562 1563 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1564 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1565 if (err != 0) { 1566 device_printf(dev, "Unable to create TX DMA map\n"); 1567 goto fail; 1568 } 1569 } 1570 #endif 1571 return (0); 1572 fail: 1573 /* We free all, it handles case where we are in the middle */ 1574 iflib_tx_structures_free(ctx); 1575 return (err); 1576 } 1577 1578 static void 1579 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1580 { 1581 bus_dmamap_t map; 1582 1583 map = NULL; 1584 if (txq->ift_sds.ifsd_map != NULL) 1585 map = txq->ift_sds.ifsd_map[i]; 1586 if (map != NULL) { 1587 bus_dmamap_unload(txq->ift_desc_tag, map); 1588 bus_dmamap_destroy(txq->ift_desc_tag, map); 1589 txq->ift_sds.ifsd_map[i] = NULL; 1590 } 1591 } 1592 1593 static void 1594 iflib_txq_destroy(iflib_txq_t txq) 1595 { 1596 if_ctx_t ctx = txq->ift_ctx; 1597 1598 for (int i = 0; i < txq->ift_size; i++) 1599 iflib_txsd_destroy(ctx, txq, i); 1600 if (txq->ift_sds.ifsd_map != NULL) { 1601 free(txq->ift_sds.ifsd_map, M_IFLIB); 1602 txq->ift_sds.ifsd_map = NULL; 1603 } 1604 if (txq->ift_sds.ifsd_m != NULL) { 1605 free(txq->ift_sds.ifsd_m, M_IFLIB); 1606 txq->ift_sds.ifsd_m = NULL; 1607 } 1608 if (txq->ift_sds.ifsd_flags != NULL) { 1609 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1610 txq->ift_sds.ifsd_flags = NULL; 1611 } 1612 if (txq->ift_desc_tag != NULL) { 1613 bus_dma_tag_destroy(txq->ift_desc_tag); 1614 txq->ift_desc_tag = NULL; 1615 } 1616 if (txq->ift_tso_desc_tag != NULL) { 1617 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1618 txq->ift_tso_desc_tag = NULL; 1619 } 1620 } 1621 1622 static void 1623 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1624 { 1625 struct mbuf **mp; 1626 1627 mp = &txq->ift_sds.ifsd_m[i]; 1628 if (*mp == NULL) 1629 return; 1630 1631 if (txq->ift_sds.ifsd_map != NULL) { 1632 bus_dmamap_sync(txq->ift_desc_tag, 1633 txq->ift_sds.ifsd_map[i], 1634 BUS_DMASYNC_POSTWRITE); 1635 bus_dmamap_unload(txq->ift_desc_tag, 1636 txq->ift_sds.ifsd_map[i]); 1637 } 1638 m_free(*mp); 1639 DBG_COUNTER_INC(tx_frees); 1640 *mp = NULL; 1641 } 1642 1643 static int 1644 iflib_txq_setup(iflib_txq_t txq) 1645 { 1646 if_ctx_t ctx = txq->ift_ctx; 1647 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1648 iflib_dma_info_t di; 1649 int i; 1650 1651 /* Set number of descriptors available */ 1652 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1653 /* XXX make configurable */ 1654 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1655 1656 /* Reset indices */ 1657 txq->ift_cidx_processed = 0; 1658 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1659 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1660 1661 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1662 bzero((void *)di->idi_vaddr, di->idi_size); 1663 1664 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1665 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1666 bus_dmamap_sync(di->idi_tag, di->idi_map, 1667 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1668 return (0); 1669 } 1670 1671 /********************************************************************* 1672 * 1673 * Allocate memory for rx_buffer structures. Since we use one 1674 * rx_buffer per received packet, the maximum number of rx_buffer's 1675 * that we'll need is equal to the number of receive descriptors 1676 * that we've allocated. 1677 * 1678 **********************************************************************/ 1679 static int 1680 iflib_rxsd_alloc(iflib_rxq_t rxq) 1681 { 1682 if_ctx_t ctx = rxq->ifr_ctx; 1683 if_shared_ctx_t sctx = ctx->ifc_sctx; 1684 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1685 device_t dev = ctx->ifc_dev; 1686 iflib_fl_t fl; 1687 int err; 1688 1689 MPASS(scctx->isc_nrxd[0] > 0); 1690 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1691 1692 fl = rxq->ifr_fl; 1693 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1694 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1695 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1696 1, 0, /* alignment, bounds */ 1697 BUS_SPACE_MAXADDR, /* lowaddr */ 1698 BUS_SPACE_MAXADDR, /* highaddr */ 1699 NULL, NULL, /* filter, filterarg */ 1700 sctx->isc_rx_maxsize, /* maxsize */ 1701 sctx->isc_rx_nsegments, /* nsegments */ 1702 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1703 0, /* flags */ 1704 NULL, /* lockfunc */ 1705 NULL, /* lockarg */ 1706 &fl->ifl_desc_tag); 1707 if (err) { 1708 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1709 __func__, err); 1710 goto fail; 1711 } 1712 if (!(fl->ifl_sds.ifsd_flags = 1713 (uint8_t *) malloc(sizeof(uint8_t) * 1714 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1715 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1716 err = ENOMEM; 1717 goto fail; 1718 } 1719 if (!(fl->ifl_sds.ifsd_m = 1720 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1721 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1722 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1723 err = ENOMEM; 1724 goto fail; 1725 } 1726 if (!(fl->ifl_sds.ifsd_cl = 1727 (caddr_t *) malloc(sizeof(caddr_t) * 1728 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1729 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1730 err = ENOMEM; 1731 goto fail; 1732 } 1733 1734 /* Create the descriptor buffer dma maps */ 1735 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1736 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1737 continue; 1738 1739 if (!(fl->ifl_sds.ifsd_map = 1740 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1741 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1742 err = ENOMEM; 1743 goto fail; 1744 } 1745 1746 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1747 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1748 if (err != 0) { 1749 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1750 goto fail; 1751 } 1752 } 1753 #endif 1754 } 1755 return (0); 1756 1757 fail: 1758 iflib_rx_structures_free(ctx); 1759 return (err); 1760 } 1761 1762 1763 /* 1764 * Internal service routines 1765 */ 1766 1767 struct rxq_refill_cb_arg { 1768 int error; 1769 bus_dma_segment_t seg; 1770 int nseg; 1771 }; 1772 1773 static void 1774 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1775 { 1776 struct rxq_refill_cb_arg *cb_arg = arg; 1777 1778 cb_arg->error = error; 1779 cb_arg->seg = segs[0]; 1780 cb_arg->nseg = nseg; 1781 } 1782 1783 1784 #ifdef ACPI_DMAR 1785 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1786 #else 1787 #define IS_DMAR(ctx) (0) 1788 #endif 1789 1790 /** 1791 * rxq_refill - refill an rxq free-buffer list 1792 * @ctx: the iflib context 1793 * @rxq: the free-list to refill 1794 * @n: the number of new buffers to allocate 1795 * 1796 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1797 * The caller must assure that @n does not exceed the queue's capacity. 1798 */ 1799 static void 1800 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1801 { 1802 struct mbuf *m; 1803 int idx, frag_idx = fl->ifl_fragidx, pidx = fl->ifl_pidx; 1804 caddr_t cl, *sd_cl; 1805 struct mbuf **sd_m; 1806 uint8_t *sd_flags; 1807 struct if_rxd_update iru; 1808 bus_dmamap_t *sd_map; 1809 int n, i = 0; 1810 uint64_t bus_addr; 1811 int err; 1812 1813 sd_m = fl->ifl_sds.ifsd_m; 1814 sd_map = fl->ifl_sds.ifsd_map; 1815 sd_cl = fl->ifl_sds.ifsd_cl; 1816 sd_flags = fl->ifl_sds.ifsd_flags; 1817 idx = pidx; 1818 1819 n = count; 1820 MPASS(n > 0); 1821 MPASS(fl->ifl_credits + n <= fl->ifl_size); 1822 1823 if (pidx < fl->ifl_cidx) 1824 MPASS(pidx + n <= fl->ifl_cidx); 1825 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size)) 1826 MPASS(fl->ifl_gen == 0); 1827 if (pidx > fl->ifl_cidx) 1828 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1829 1830 DBG_COUNTER_INC(fl_refills); 1831 if (n > 8) 1832 DBG_COUNTER_INC(fl_refills_large); 1833 iru.iru_paddrs = fl->ifl_bus_addrs; 1834 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1835 iru.iru_idxs = fl->ifl_rxd_idxs; 1836 iru.iru_qsidx = fl->ifl_rxq->ifr_id; 1837 iru.iru_buf_size = fl->ifl_buf_size; 1838 iru.iru_flidx = fl->ifl_id; 1839 while (n--) { 1840 /* 1841 * We allocate an uninitialized mbuf + cluster, mbuf is 1842 * initialized after rx. 1843 * 1844 * If the cluster is still set then we know a minimum sized packet was received 1845 */ 1846 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1847 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1848 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1849 if ((cl = sd_cl[frag_idx]) == NULL) { 1850 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1851 break; 1852 #if MEMORY_LOGGING 1853 fl->ifl_cl_enqueued++; 1854 #endif 1855 } 1856 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1857 break; 1858 } 1859 #if MEMORY_LOGGING 1860 fl->ifl_m_enqueued++; 1861 #endif 1862 1863 DBG_COUNTER_INC(rx_allocs); 1864 #if defined(__i386__) || defined(__amd64__) 1865 if (!IS_DMAR(ctx)) { 1866 bus_addr = pmap_kextract((vm_offset_t)cl); 1867 } else 1868 #endif 1869 { 1870 struct rxq_refill_cb_arg cb_arg; 1871 iflib_rxq_t q; 1872 1873 cb_arg.error = 0; 1874 q = fl->ifl_rxq; 1875 MPASS(sd_map != NULL); 1876 MPASS(sd_map[frag_idx] != NULL); 1877 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1878 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1879 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1880 BUS_DMASYNC_PREREAD); 1881 1882 if (err != 0 || cb_arg.error) { 1883 /* 1884 * !zone_pack ? 1885 */ 1886 if (fl->ifl_zone == zone_pack) 1887 uma_zfree(fl->ifl_zone, cl); 1888 m_free(m); 1889 n = 0; 1890 goto done; 1891 } 1892 bus_addr = cb_arg.seg.ds_addr; 1893 } 1894 bit_set(fl->ifl_rx_bitmap, frag_idx); 1895 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1896 1897 MPASS(sd_m[frag_idx] == NULL); 1898 sd_cl[frag_idx] = cl; 1899 sd_m[frag_idx] = m; 1900 fl->ifl_rxd_idxs[i] = frag_idx; 1901 fl->ifl_bus_addrs[i] = bus_addr; 1902 fl->ifl_vm_addrs[i] = cl; 1903 fl->ifl_credits++; 1904 i++; 1905 MPASS(fl->ifl_credits <= fl->ifl_size); 1906 if (++idx == fl->ifl_size) { 1907 fl->ifl_gen = 1; 1908 idx = 0; 1909 } 1910 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1911 iru.iru_pidx = pidx; 1912 iru.iru_count = i; 1913 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1914 i = 0; 1915 pidx = idx; 1916 fl->ifl_pidx = idx; 1917 } 1918 1919 } 1920 done: 1921 DBG_COUNTER_INC(rxd_flush); 1922 if (fl->ifl_pidx == 0) 1923 pidx = fl->ifl_size - 1; 1924 else 1925 pidx = fl->ifl_pidx - 1; 1926 1927 if (sd_map) 1928 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1929 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1930 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1931 fl->ifl_fragidx = frag_idx; 1932 } 1933 1934 static __inline void 1935 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1936 { 1937 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1938 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1939 #ifdef INVARIANTS 1940 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1941 #endif 1942 1943 MPASS(fl->ifl_credits <= fl->ifl_size); 1944 MPASS(reclaimable == delta); 1945 1946 if (reclaimable > 0) 1947 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1948 } 1949 1950 static void 1951 iflib_fl_bufs_free(iflib_fl_t fl) 1952 { 1953 iflib_dma_info_t idi = fl->ifl_ifdi; 1954 uint32_t i; 1955 1956 for (i = 0; i < fl->ifl_size; i++) { 1957 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1958 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1959 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1960 1961 if (*sd_flags & RX_SW_DESC_INUSE) { 1962 if (fl->ifl_sds.ifsd_map != NULL) { 1963 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1964 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1965 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1966 } 1967 if (*sd_m != NULL) { 1968 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 1969 uma_zfree(zone_mbuf, *sd_m); 1970 } 1971 if (*sd_cl != NULL) 1972 uma_zfree(fl->ifl_zone, *sd_cl); 1973 *sd_flags = 0; 1974 } else { 1975 MPASS(*sd_cl == NULL); 1976 MPASS(*sd_m == NULL); 1977 } 1978 #if MEMORY_LOGGING 1979 fl->ifl_m_dequeued++; 1980 fl->ifl_cl_dequeued++; 1981 #endif 1982 *sd_cl = NULL; 1983 *sd_m = NULL; 1984 } 1985 #ifdef INVARIANTS 1986 for (i = 0; i < fl->ifl_size; i++) { 1987 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 1988 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 1989 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 1990 } 1991 #endif 1992 /* 1993 * Reset free list values 1994 */ 1995 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = 0;; 1996 bzero(idi->idi_vaddr, idi->idi_size); 1997 } 1998 1999 /********************************************************************* 2000 * 2001 * Initialize a receive ring and its buffers. 2002 * 2003 **********************************************************************/ 2004 static int 2005 iflib_fl_setup(iflib_fl_t fl) 2006 { 2007 iflib_rxq_t rxq = fl->ifl_rxq; 2008 if_ctx_t ctx = rxq->ifr_ctx; 2009 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2010 2011 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 2012 /* 2013 ** Free current RX buffer structs and their mbufs 2014 */ 2015 iflib_fl_bufs_free(fl); 2016 /* Now replenish the mbufs */ 2017 MPASS(fl->ifl_credits == 0); 2018 /* 2019 * XXX don't set the max_frame_size to larger 2020 * than the hardware can handle 2021 */ 2022 if (sctx->isc_max_frame_size <= 2048) 2023 fl->ifl_buf_size = MCLBYTES; 2024 #ifndef CONTIGMALLOC_WORKS 2025 else 2026 fl->ifl_buf_size = MJUMPAGESIZE; 2027 #else 2028 else if (sctx->isc_max_frame_size <= 4096) 2029 fl->ifl_buf_size = MJUMPAGESIZE; 2030 else if (sctx->isc_max_frame_size <= 9216) 2031 fl->ifl_buf_size = MJUM9BYTES; 2032 else 2033 fl->ifl_buf_size = MJUM16BYTES; 2034 #endif 2035 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2036 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2037 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2038 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2039 2040 2041 /* avoid pre-allocating zillions of clusters to an idle card 2042 * potentially speeding up attach 2043 */ 2044 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2045 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2046 if (min(128, fl->ifl_size) != fl->ifl_credits) 2047 return (ENOBUFS); 2048 /* 2049 * handle failure 2050 */ 2051 MPASS(rxq != NULL); 2052 MPASS(fl->ifl_ifdi != NULL); 2053 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2054 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2055 return (0); 2056 } 2057 2058 /********************************************************************* 2059 * 2060 * Free receive ring data structures 2061 * 2062 **********************************************************************/ 2063 static void 2064 iflib_rx_sds_free(iflib_rxq_t rxq) 2065 { 2066 iflib_fl_t fl; 2067 int i; 2068 2069 if (rxq->ifr_fl != NULL) { 2070 for (i = 0; i < rxq->ifr_nfl; i++) { 2071 fl = &rxq->ifr_fl[i]; 2072 if (fl->ifl_desc_tag != NULL) { 2073 bus_dma_tag_destroy(fl->ifl_desc_tag); 2074 fl->ifl_desc_tag = NULL; 2075 } 2076 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2077 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2078 /* XXX destroy maps first */ 2079 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2080 fl->ifl_sds.ifsd_m = NULL; 2081 fl->ifl_sds.ifsd_cl = NULL; 2082 fl->ifl_sds.ifsd_map = NULL; 2083 } 2084 free(rxq->ifr_fl, M_IFLIB); 2085 rxq->ifr_fl = NULL; 2086 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2087 } 2088 } 2089 2090 /* 2091 * MI independent logic 2092 * 2093 */ 2094 static void 2095 iflib_timer(void *arg) 2096 { 2097 iflib_txq_t txq = arg; 2098 if_ctx_t ctx = txq->ift_ctx; 2099 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2100 2101 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2102 return; 2103 /* 2104 ** Check on the state of the TX queue(s), this 2105 ** can be done without the lock because its RO 2106 ** and the HUNG state will be static if set. 2107 */ 2108 IFDI_TIMER(ctx, txq->ift_id); 2109 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2110 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2111 (sctx->isc_pause_frames == 0))) 2112 goto hung; 2113 2114 if (ifmp_ring_is_stalled(txq->ift_br)) 2115 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2116 txq->ift_cleaned_prev = txq->ift_cleaned; 2117 /* handle any laggards */ 2118 if (txq->ift_db_pending) 2119 GROUPTASK_ENQUEUE(&txq->ift_task); 2120 2121 sctx->isc_pause_frames = 0; 2122 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2123 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2124 return; 2125 hung: 2126 CTX_LOCK(ctx); 2127 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2128 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2129 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2130 2131 IFDI_WATCHDOG_RESET(ctx); 2132 ctx->ifc_watchdog_events++; 2133 2134 ctx->ifc_flags |= IFC_DO_RESET; 2135 iflib_admin_intr_deferred(ctx); 2136 CTX_UNLOCK(ctx); 2137 } 2138 2139 static void 2140 iflib_init_locked(if_ctx_t ctx) 2141 { 2142 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2143 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2144 if_t ifp = ctx->ifc_ifp; 2145 iflib_fl_t fl; 2146 iflib_txq_t txq; 2147 iflib_rxq_t rxq; 2148 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2149 2150 2151 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2152 IFDI_INTR_DISABLE(ctx); 2153 2154 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2155 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2156 /* Set hardware offload abilities */ 2157 if_clearhwassist(ifp); 2158 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2159 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2160 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2161 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2162 if (if_getcapenable(ifp) & IFCAP_TSO4) 2163 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2164 if (if_getcapenable(ifp) & IFCAP_TSO6) 2165 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2166 2167 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2168 CALLOUT_LOCK(txq); 2169 callout_stop(&txq->ift_timer); 2170 CALLOUT_UNLOCK(txq); 2171 iflib_netmap_txq_init(ctx, txq); 2172 } 2173 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2174 MPASS(rxq->ifr_id == i); 2175 iflib_netmap_rxq_init(ctx, rxq); 2176 } 2177 #ifdef INVARIANTS 2178 i = if_getdrvflags(ifp); 2179 #endif 2180 IFDI_INIT(ctx); 2181 MPASS(if_getdrvflags(ifp) == i); 2182 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2183 /* XXX this should really be done on a per-queue basis */ 2184 if (if_getcapenable(ifp) & IFCAP_NETMAP) 2185 continue; 2186 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2187 if (iflib_fl_setup(fl)) { 2188 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2189 goto done; 2190 } 2191 } 2192 } 2193 done: 2194 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2195 IFDI_INTR_ENABLE(ctx); 2196 txq = ctx->ifc_txqs; 2197 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2198 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2199 txq->ift_timer.c_cpu); 2200 } 2201 2202 static int 2203 iflib_media_change(if_t ifp) 2204 { 2205 if_ctx_t ctx = if_getsoftc(ifp); 2206 int err; 2207 2208 CTX_LOCK(ctx); 2209 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2210 iflib_init_locked(ctx); 2211 CTX_UNLOCK(ctx); 2212 return (err); 2213 } 2214 2215 static void 2216 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2217 { 2218 if_ctx_t ctx = if_getsoftc(ifp); 2219 2220 CTX_LOCK(ctx); 2221 IFDI_UPDATE_ADMIN_STATUS(ctx); 2222 IFDI_MEDIA_STATUS(ctx, ifmr); 2223 CTX_UNLOCK(ctx); 2224 } 2225 2226 static void 2227 iflib_stop(if_ctx_t ctx) 2228 { 2229 iflib_txq_t txq = ctx->ifc_txqs; 2230 iflib_rxq_t rxq = ctx->ifc_rxqs; 2231 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2232 iflib_dma_info_t di; 2233 iflib_fl_t fl; 2234 int i, j; 2235 2236 /* Tell the stack that the interface is no longer active */ 2237 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2238 2239 IFDI_INTR_DISABLE(ctx); 2240 DELAY(1000); 2241 IFDI_STOP(ctx); 2242 DELAY(1000); 2243 2244 iflib_debug_reset(); 2245 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2246 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2247 /* make sure all transmitters have completed before proceeding XXX */ 2248 2249 /* clean any enqueued buffers */ 2250 iflib_ifmp_purge(txq); 2251 /* Free any existing tx buffers. */ 2252 for (j = 0; j < txq->ift_size; j++) { 2253 iflib_txsd_free(ctx, txq, j); 2254 } 2255 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2256 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2257 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2258 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2259 txq->ift_pullups = 0; 2260 ifmp_ring_reset_stats(txq->ift_br); 2261 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2262 bzero((void *)di->idi_vaddr, di->idi_size); 2263 } 2264 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2265 /* make sure all transmitters have completed before proceeding XXX */ 2266 2267 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) 2268 bzero((void *)di->idi_vaddr, di->idi_size); 2269 /* also resets the free lists pidx/cidx */ 2270 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2271 iflib_fl_bufs_free(fl); 2272 } 2273 } 2274 2275 static inline caddr_t 2276 calc_next_rxd(iflib_fl_t fl, int cidx) 2277 { 2278 qidx_t size; 2279 int nrxd; 2280 caddr_t start, end, cur, next; 2281 2282 nrxd = fl->ifl_size; 2283 size = fl->ifl_rxd_size; 2284 start = fl->ifl_ifdi->idi_vaddr; 2285 2286 if (__predict_false(size == 0)) 2287 return (start); 2288 cur = start + size*cidx; 2289 end = start + size*nrxd; 2290 next = CACHE_PTR_NEXT(cur); 2291 return (next < end ? next : start); 2292 } 2293 2294 static inline void 2295 prefetch_pkts(iflib_fl_t fl, int cidx) 2296 { 2297 int nextptr; 2298 int nrxd = fl->ifl_size; 2299 caddr_t next_rxd; 2300 2301 2302 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2303 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2304 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2305 next_rxd = calc_next_rxd(fl, cidx); 2306 prefetch(next_rxd); 2307 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2308 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2309 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2310 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2311 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2312 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2313 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2314 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2315 } 2316 2317 static void 2318 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2319 { 2320 int flid, cidx; 2321 bus_dmamap_t map; 2322 iflib_fl_t fl; 2323 iflib_dma_info_t di; 2324 int next; 2325 2326 map = NULL; 2327 flid = irf->irf_flid; 2328 cidx = irf->irf_idx; 2329 fl = &rxq->ifr_fl[flid]; 2330 sd->ifsd_fl = fl; 2331 sd->ifsd_cidx = cidx; 2332 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2333 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2334 fl->ifl_credits--; 2335 #if MEMORY_LOGGING 2336 fl->ifl_m_dequeued++; 2337 #endif 2338 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2339 prefetch_pkts(fl, cidx); 2340 if (fl->ifl_sds.ifsd_map != NULL) { 2341 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2342 prefetch(&fl->ifl_sds.ifsd_map[next]); 2343 map = fl->ifl_sds.ifsd_map[cidx]; 2344 di = fl->ifl_ifdi; 2345 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2346 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2347 bus_dmamap_sync(di->idi_tag, di->idi_map, 2348 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2349 2350 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2351 MPASS(fl->ifl_cidx == cidx); 2352 if (unload) 2353 bus_dmamap_unload(fl->ifl_desc_tag, map); 2354 } 2355 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2356 if (__predict_false(fl->ifl_cidx == 0)) 2357 fl->ifl_gen = 0; 2358 if (map != NULL) 2359 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2360 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2361 bit_clear(fl->ifl_rx_bitmap, cidx); 2362 } 2363 2364 static struct mbuf * 2365 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2366 { 2367 int i, padlen , flags; 2368 struct mbuf *m, *mh, *mt; 2369 caddr_t cl; 2370 2371 i = 0; 2372 mh = NULL; 2373 do { 2374 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2375 2376 MPASS(*sd->ifsd_cl != NULL); 2377 MPASS(*sd->ifsd_m != NULL); 2378 2379 /* Don't include zero-length frags */ 2380 if (ri->iri_frags[i].irf_len == 0) { 2381 /* XXX we can save the cluster here, but not the mbuf */ 2382 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2383 m_free(*sd->ifsd_m); 2384 *sd->ifsd_m = NULL; 2385 continue; 2386 } 2387 m = *sd->ifsd_m; 2388 *sd->ifsd_m = NULL; 2389 if (mh == NULL) { 2390 flags = M_PKTHDR|M_EXT; 2391 mh = mt = m; 2392 padlen = ri->iri_pad; 2393 } else { 2394 flags = M_EXT; 2395 mt->m_next = m; 2396 mt = m; 2397 /* assuming padding is only on the first fragment */ 2398 padlen = 0; 2399 } 2400 cl = *sd->ifsd_cl; 2401 *sd->ifsd_cl = NULL; 2402 2403 /* Can these two be made one ? */ 2404 m_init(m, M_NOWAIT, MT_DATA, flags); 2405 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2406 /* 2407 * These must follow m_init and m_cljset 2408 */ 2409 m->m_data += padlen; 2410 ri->iri_len -= padlen; 2411 m->m_len = ri->iri_frags[i].irf_len; 2412 } while (++i < ri->iri_nfrags); 2413 2414 return (mh); 2415 } 2416 2417 /* 2418 * Process one software descriptor 2419 */ 2420 static struct mbuf * 2421 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2422 { 2423 struct if_rxsd sd; 2424 struct mbuf *m; 2425 2426 /* should I merge this back in now that the two paths are basically duplicated? */ 2427 if (ri->iri_nfrags == 1 && 2428 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) { 2429 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2430 m = *sd.ifsd_m; 2431 *sd.ifsd_m = NULL; 2432 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2433 #ifndef __NO_STRICT_ALIGNMENT 2434 if (!IP_ALIGNED(m)) 2435 m->m_data += 2; 2436 #endif 2437 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2438 m->m_len = ri->iri_frags[0].irf_len; 2439 } else { 2440 m = assemble_segments(rxq, ri, &sd); 2441 } 2442 m->m_pkthdr.len = ri->iri_len; 2443 m->m_pkthdr.rcvif = ri->iri_ifp; 2444 m->m_flags |= ri->iri_flags; 2445 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2446 m->m_pkthdr.flowid = ri->iri_flowid; 2447 M_HASHTYPE_SET(m, ri->iri_rsstype); 2448 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2449 m->m_pkthdr.csum_data = ri->iri_csum_data; 2450 return (m); 2451 } 2452 2453 static bool 2454 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2455 { 2456 if_ctx_t ctx = rxq->ifr_ctx; 2457 if_shared_ctx_t sctx = ctx->ifc_sctx; 2458 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2459 int avail, i; 2460 qidx_t *cidxp; 2461 struct if_rxd_info ri; 2462 int err, budget_left, rx_bytes, rx_pkts; 2463 iflib_fl_t fl; 2464 struct ifnet *ifp; 2465 int lro_enabled; 2466 2467 /* 2468 * XXX early demux data packets so that if_input processing only handles 2469 * acks in interrupt context 2470 */ 2471 struct mbuf *m, *mh, *mt; 2472 2473 ifp = ctx->ifc_ifp; 2474 #ifdef DEV_NETMAP 2475 if (ifp->if_capenable & IFCAP_NETMAP) { 2476 u_int work = 0; 2477 if (netmap_rx_irq(ifp, rxq->ifr_id, &work)) 2478 return (FALSE); 2479 } 2480 #endif 2481 2482 mh = mt = NULL; 2483 MPASS(budget > 0); 2484 rx_pkts = rx_bytes = 0; 2485 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2486 cidxp = &rxq->ifr_cq_cidx; 2487 else 2488 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2489 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2490 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2491 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2492 DBG_COUNTER_INC(rx_unavail); 2493 return (false); 2494 } 2495 2496 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2497 if (__predict_false(!CTX_ACTIVE(ctx))) { 2498 DBG_COUNTER_INC(rx_ctx_inactive); 2499 break; 2500 } 2501 /* 2502 * Reset client set fields to their default values 2503 */ 2504 rxd_info_zero(&ri); 2505 ri.iri_qsidx = rxq->ifr_id; 2506 ri.iri_cidx = *cidxp; 2507 ri.iri_ifp = ifp; 2508 ri.iri_frags = rxq->ifr_frags; 2509 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2510 2511 if (err) 2512 goto err; 2513 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2514 *cidxp = ri.iri_cidx; 2515 /* Update our consumer index */ 2516 /* XXX NB: shurd - check if this is still safe */ 2517 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2518 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2519 rxq->ifr_cq_gen = 0; 2520 } 2521 /* was this only a completion queue message? */ 2522 if (__predict_false(ri.iri_nfrags == 0)) 2523 continue; 2524 } 2525 MPASS(ri.iri_nfrags != 0); 2526 MPASS(ri.iri_len != 0); 2527 2528 /* will advance the cidx on the corresponding free lists */ 2529 m = iflib_rxd_pkt_get(rxq, &ri); 2530 if (avail == 0 && budget_left) 2531 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2532 2533 if (__predict_false(m == NULL)) { 2534 DBG_COUNTER_INC(rx_mbuf_null); 2535 continue; 2536 } 2537 /* imm_pkt: -- cxgb */ 2538 if (mh == NULL) 2539 mh = mt = m; 2540 else { 2541 mt->m_nextpkt = m; 2542 mt = m; 2543 } 2544 } 2545 /* make sure that we can refill faster than drain */ 2546 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2547 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2548 2549 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2550 while (mh != NULL) { 2551 m = mh; 2552 mh = mh->m_nextpkt; 2553 m->m_nextpkt = NULL; 2554 #ifndef __NO_STRICT_ALIGNMENT 2555 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2556 continue; 2557 #endif 2558 rx_bytes += m->m_pkthdr.len; 2559 rx_pkts++; 2560 #if defined(INET6) || defined(INET) 2561 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2562 continue; 2563 #endif 2564 DBG_COUNTER_INC(rx_if_input); 2565 ifp->if_input(ifp, m); 2566 } 2567 2568 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2569 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2570 2571 /* 2572 * Flush any outstanding LRO work 2573 */ 2574 #if defined(INET6) || defined(INET) 2575 tcp_lro_flush_all(&rxq->ifr_lc); 2576 #endif 2577 if (avail) 2578 return true; 2579 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2580 err: 2581 CTX_LOCK(ctx); 2582 ctx->ifc_flags |= IFC_DO_RESET; 2583 iflib_admin_intr_deferred(ctx); 2584 CTX_UNLOCK(ctx); 2585 return (false); 2586 } 2587 2588 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2589 static inline qidx_t 2590 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2591 { 2592 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2593 qidx_t minthresh = txq->ift_size / 8; 2594 if (in_use > 4*minthresh) 2595 return (notify_count); 2596 if (in_use > 2*minthresh) 2597 return (notify_count >> 1); 2598 if (in_use > minthresh) 2599 return (notify_count >> 3); 2600 return (0); 2601 } 2602 2603 static inline qidx_t 2604 txq_max_rs_deferred(iflib_txq_t txq) 2605 { 2606 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2607 qidx_t minthresh = txq->ift_size / 8; 2608 if (txq->ift_in_use > 4*minthresh) 2609 return (notify_count); 2610 if (txq->ift_in_use > 2*minthresh) 2611 return (notify_count >> 1); 2612 if (txq->ift_in_use > minthresh) 2613 return (notify_count >> 2); 2614 return (2); 2615 } 2616 2617 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2618 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2619 2620 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2621 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2622 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2623 2624 /* forward compatibility for cxgb */ 2625 #define FIRST_QSET(ctx) 0 2626 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2627 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2628 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2629 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2630 2631 /* XXX we should be setting this to something other than zero */ 2632 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2633 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2634 2635 static inline bool 2636 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2637 { 2638 qidx_t dbval, max; 2639 bool rang; 2640 2641 rang = false; 2642 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2643 if (ring || txq->ift_db_pending >= max) { 2644 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2645 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2646 txq->ift_db_pending = txq->ift_npending = 0; 2647 rang = true; 2648 } 2649 return (rang); 2650 } 2651 2652 #ifdef PKT_DEBUG 2653 static void 2654 print_pkt(if_pkt_info_t pi) 2655 { 2656 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2657 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2658 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2659 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2660 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2661 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2662 } 2663 #endif 2664 2665 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2666 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2667 2668 static int 2669 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2670 { 2671 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2672 struct ether_vlan_header *eh; 2673 struct mbuf *m, *n; 2674 2675 n = m = *mp; 2676 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2677 M_WRITABLE(m) == 0) { 2678 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2679 return (ENOMEM); 2680 } else { 2681 m_freem(*mp); 2682 n = *mp = m; 2683 } 2684 } 2685 2686 /* 2687 * Determine where frame payload starts. 2688 * Jump over vlan headers if already present, 2689 * helpful for QinQ too. 2690 */ 2691 if (__predict_false(m->m_len < sizeof(*eh))) { 2692 txq->ift_pullups++; 2693 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2694 return (ENOMEM); 2695 } 2696 eh = mtod(m, struct ether_vlan_header *); 2697 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2698 pi->ipi_etype = ntohs(eh->evl_proto); 2699 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2700 } else { 2701 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2702 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2703 } 2704 2705 switch (pi->ipi_etype) { 2706 #ifdef INET 2707 case ETHERTYPE_IP: 2708 { 2709 struct ip *ip = NULL; 2710 struct tcphdr *th = NULL; 2711 int minthlen; 2712 2713 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2714 if (__predict_false(m->m_len < minthlen)) { 2715 /* 2716 * if this code bloat is causing too much of a hit 2717 * move it to a separate function and mark it noinline 2718 */ 2719 if (m->m_len == pi->ipi_ehdrlen) { 2720 n = m->m_next; 2721 MPASS(n); 2722 if (n->m_len >= sizeof(*ip)) { 2723 ip = (struct ip *)n->m_data; 2724 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2725 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2726 } else { 2727 txq->ift_pullups++; 2728 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2729 return (ENOMEM); 2730 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2731 } 2732 } else { 2733 txq->ift_pullups++; 2734 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2735 return (ENOMEM); 2736 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2737 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2738 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2739 } 2740 } else { 2741 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2742 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2743 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2744 } 2745 pi->ipi_ip_hlen = ip->ip_hl << 2; 2746 pi->ipi_ipproto = ip->ip_p; 2747 pi->ipi_flags |= IPI_TX_IPV4; 2748 2749 if (pi->ipi_csum_flags & CSUM_IP) 2750 ip->ip_sum = 0; 2751 2752 if (pi->ipi_ipproto == IPPROTO_TCP) { 2753 if (__predict_false(th == NULL)) { 2754 txq->ift_pullups++; 2755 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2756 return (ENOMEM); 2757 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2758 } 2759 pi->ipi_tcp_hflags = th->th_flags; 2760 pi->ipi_tcp_hlen = th->th_off << 2; 2761 pi->ipi_tcp_seq = th->th_seq; 2762 } 2763 if (IS_TSO4(pi)) { 2764 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2765 return (ENXIO); 2766 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2767 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2768 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2769 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2770 ip->ip_sum = 0; 2771 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2772 } 2773 } 2774 break; 2775 } 2776 #endif 2777 #ifdef INET6 2778 case ETHERTYPE_IPV6: 2779 { 2780 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2781 struct tcphdr *th; 2782 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2783 2784 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2785 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2786 return (ENOMEM); 2787 } 2788 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2789 2790 /* XXX-BZ this will go badly in case of ext hdrs. */ 2791 pi->ipi_ipproto = ip6->ip6_nxt; 2792 pi->ipi_flags |= IPI_TX_IPV6; 2793 2794 if (pi->ipi_ipproto == IPPROTO_TCP) { 2795 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2796 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2797 return (ENOMEM); 2798 } 2799 pi->ipi_tcp_hflags = th->th_flags; 2800 pi->ipi_tcp_hlen = th->th_off << 2; 2801 } 2802 if (IS_TSO6(pi)) { 2803 2804 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2805 return (ENXIO); 2806 /* 2807 * The corresponding flag is set by the stack in the IPv4 2808 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2809 * So, set it here because the rest of the flow requires it. 2810 */ 2811 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2812 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2813 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2814 } 2815 break; 2816 } 2817 #endif 2818 default: 2819 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2820 pi->ipi_ip_hlen = 0; 2821 break; 2822 } 2823 *mp = m; 2824 2825 return (0); 2826 } 2827 2828 static __noinline struct mbuf * 2829 collapse_pkthdr(struct mbuf *m0) 2830 { 2831 struct mbuf *m, *m_next, *tmp; 2832 2833 m = m0; 2834 m_next = m->m_next; 2835 while (m_next != NULL && m_next->m_len == 0) { 2836 m = m_next; 2837 m->m_next = NULL; 2838 m_free(m); 2839 m_next = m_next->m_next; 2840 } 2841 m = m0; 2842 m->m_next = m_next; 2843 if ((m_next->m_flags & M_EXT) == 0) { 2844 m = m_defrag(m, M_NOWAIT); 2845 } else { 2846 tmp = m_next->m_next; 2847 memcpy(m_next, m, MPKTHSIZE); 2848 m = m_next; 2849 m->m_next = tmp; 2850 } 2851 return (m); 2852 } 2853 2854 /* 2855 * If dodgy hardware rejects the scatter gather chain we've handed it 2856 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2857 * m_defrag'd mbufs 2858 */ 2859 static __noinline struct mbuf * 2860 iflib_remove_mbuf(iflib_txq_t txq) 2861 { 2862 int ntxd, i, pidx; 2863 struct mbuf *m, *mh, **ifsd_m; 2864 2865 pidx = txq->ift_pidx; 2866 ifsd_m = txq->ift_sds.ifsd_m; 2867 ntxd = txq->ift_size; 2868 mh = m = ifsd_m[pidx]; 2869 ifsd_m[pidx] = NULL; 2870 #if MEMORY_LOGGING 2871 txq->ift_dequeued++; 2872 #endif 2873 i = 1; 2874 2875 while (m) { 2876 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2877 #if MEMORY_LOGGING 2878 txq->ift_dequeued++; 2879 #endif 2880 m = m->m_next; 2881 i++; 2882 } 2883 return (mh); 2884 } 2885 2886 static int 2887 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2888 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2889 int max_segs, int flags) 2890 { 2891 if_ctx_t ctx; 2892 if_shared_ctx_t sctx; 2893 if_softc_ctx_t scctx; 2894 int i, next, pidx, err, maxsegsz, ntxd, count; 2895 struct mbuf *m, *tmp, **ifsd_m; 2896 2897 m = *m0; 2898 2899 /* 2900 * Please don't ever do this 2901 */ 2902 if (__predict_false(m->m_len == 0)) 2903 *m0 = m = collapse_pkthdr(m); 2904 2905 ctx = txq->ift_ctx; 2906 sctx = ctx->ifc_sctx; 2907 scctx = &ctx->ifc_softc_ctx; 2908 ifsd_m = txq->ift_sds.ifsd_m; 2909 ntxd = txq->ift_size; 2910 pidx = txq->ift_pidx; 2911 if (map != NULL) { 2912 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 2913 2914 err = bus_dmamap_load_mbuf_sg(tag, map, 2915 *m0, segs, nsegs, BUS_DMA_NOWAIT); 2916 if (err) 2917 return (err); 2918 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 2919 count = 0; 2920 m = *m0; 2921 do { 2922 if (__predict_false(m->m_len <= 0)) { 2923 tmp = m; 2924 m = m->m_next; 2925 tmp->m_next = NULL; 2926 m_free(tmp); 2927 continue; 2928 } 2929 next = (pidx + count) & (ntxd-1); 2930 MPASS(ifsd_m[next] == NULL); 2931 ifsd_m[next] = m; 2932 count++; 2933 tmp = m; 2934 m = m->m_next; 2935 } while (m != NULL); 2936 } else { 2937 int buflen, sgsize, max_sgsize; 2938 vm_offset_t vaddr; 2939 vm_paddr_t curaddr; 2940 2941 count = i = 0; 2942 maxsegsz = sctx->isc_tx_maxsize; 2943 m = *m0; 2944 do { 2945 if (__predict_false(m->m_len <= 0)) { 2946 tmp = m; 2947 m = m->m_next; 2948 tmp->m_next = NULL; 2949 m_free(tmp); 2950 continue; 2951 } 2952 buflen = m->m_len; 2953 vaddr = (vm_offset_t)m->m_data; 2954 /* 2955 * see if we can't be smarter about physically 2956 * contiguous mappings 2957 */ 2958 next = (pidx + count) & (ntxd-1); 2959 MPASS(ifsd_m[next] == NULL); 2960 #if MEMORY_LOGGING 2961 txq->ift_enqueued++; 2962 #endif 2963 ifsd_m[next] = m; 2964 while (buflen > 0) { 2965 max_sgsize = MIN(buflen, maxsegsz); 2966 curaddr = pmap_kextract(vaddr); 2967 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 2968 sgsize = MIN(sgsize, max_sgsize); 2969 segs[i].ds_addr = curaddr; 2970 segs[i].ds_len = sgsize; 2971 vaddr += sgsize; 2972 buflen -= sgsize; 2973 i++; 2974 if (i >= max_segs) 2975 goto err; 2976 } 2977 count++; 2978 tmp = m; 2979 m = m->m_next; 2980 } while (m != NULL); 2981 *nsegs = i; 2982 } 2983 return (0); 2984 err: 2985 *m0 = iflib_remove_mbuf(txq); 2986 return (EFBIG); 2987 } 2988 2989 static inline caddr_t 2990 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 2991 { 2992 qidx_t size; 2993 int ntxd; 2994 caddr_t start, end, cur, next; 2995 2996 ntxd = txq->ift_size; 2997 size = txq->ift_txd_size[qid]; 2998 start = txq->ift_ifdi[qid].idi_vaddr; 2999 3000 if (__predict_false(size == 0)) 3001 return (start); 3002 cur = start + size*cidx; 3003 end = start + size*ntxd; 3004 next = CACHE_PTR_NEXT(cur); 3005 return (next < end ? next : start); 3006 } 3007 3008 static int 3009 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3010 { 3011 if_ctx_t ctx; 3012 if_shared_ctx_t sctx; 3013 if_softc_ctx_t scctx; 3014 bus_dma_segment_t *segs; 3015 struct mbuf *m_head; 3016 void *next_txd; 3017 bus_dmamap_t map; 3018 struct if_pkt_info pi; 3019 int remap = 0; 3020 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3021 bus_dma_tag_t desc_tag; 3022 3023 segs = txq->ift_segs; 3024 ctx = txq->ift_ctx; 3025 sctx = ctx->ifc_sctx; 3026 scctx = &ctx->ifc_softc_ctx; 3027 segs = txq->ift_segs; 3028 ntxd = txq->ift_size; 3029 m_head = *m_headp; 3030 map = NULL; 3031 3032 /* 3033 * If we're doing TSO the next descriptor to clean may be quite far ahead 3034 */ 3035 cidx = txq->ift_cidx; 3036 pidx = txq->ift_pidx; 3037 if (ctx->ifc_flags & IFC_PREFETCH) { 3038 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3039 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3040 next_txd = calc_next_txd(txq, cidx, 0); 3041 prefetch(next_txd); 3042 } 3043 3044 /* prefetch the next cache line of mbuf pointers and flags */ 3045 prefetch(&txq->ift_sds.ifsd_m[next]); 3046 if (txq->ift_sds.ifsd_map != NULL) { 3047 prefetch(&txq->ift_sds.ifsd_map[next]); 3048 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3049 prefetch(&txq->ift_sds.ifsd_flags[next]); 3050 } 3051 } else if (txq->ift_sds.ifsd_map != NULL) 3052 map = txq->ift_sds.ifsd_map[pidx]; 3053 3054 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3055 desc_tag = txq->ift_tso_desc_tag; 3056 max_segs = scctx->isc_tx_tso_segments_max; 3057 } else { 3058 desc_tag = txq->ift_desc_tag; 3059 max_segs = scctx->isc_tx_nsegments; 3060 } 3061 m_head = *m_headp; 3062 3063 pkt_info_zero(&pi); 3064 pi.ipi_len = m_head->m_pkthdr.len; 3065 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3066 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3067 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3068 pi.ipi_pidx = pidx; 3069 pi.ipi_qsidx = txq->ift_id; 3070 3071 /* deliberate bitwise OR to make one condition */ 3072 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3073 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3074 return (err); 3075 m_head = *m_headp; 3076 } 3077 3078 retry: 3079 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3080 defrag: 3081 if (__predict_false(err)) { 3082 switch (err) { 3083 case EFBIG: 3084 /* try collapse once and defrag once */ 3085 if (remap == 0) 3086 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3087 if (remap == 1) 3088 m_head = m_defrag(*m_headp, M_NOWAIT); 3089 remap++; 3090 if (__predict_false(m_head == NULL)) 3091 goto defrag_failed; 3092 txq->ift_mbuf_defrag++; 3093 *m_headp = m_head; 3094 goto retry; 3095 break; 3096 case ENOMEM: 3097 txq->ift_no_tx_dma_setup++; 3098 break; 3099 default: 3100 txq->ift_no_tx_dma_setup++; 3101 m_freem(*m_headp); 3102 DBG_COUNTER_INC(tx_frees); 3103 *m_headp = NULL; 3104 break; 3105 } 3106 txq->ift_map_failed++; 3107 DBG_COUNTER_INC(encap_load_mbuf_fail); 3108 return (err); 3109 } 3110 3111 /* 3112 * XXX assumes a 1 to 1 relationship between segments and 3113 * descriptors - this does not hold true on all drivers, e.g. 3114 * cxgb 3115 */ 3116 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3117 txq->ift_no_desc_avail++; 3118 if (map != NULL) 3119 bus_dmamap_unload(desc_tag, map); 3120 DBG_COUNTER_INC(encap_txq_avail_fail); 3121 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3122 GROUPTASK_ENQUEUE(&txq->ift_task); 3123 return (ENOBUFS); 3124 } 3125 /* 3126 * On Intel cards we can greatly reduce the number of TX interrupts 3127 * we see by only setting report status on every Nth descriptor. 3128 * However, this also means that the driver will need to keep track 3129 * of the descriptors that RS was set on to check them for the DD bit. 3130 */ 3131 txq->ift_rs_pending += nsegs + 1; 3132 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3133 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3134 pi.ipi_flags |= IPI_TX_INTR; 3135 txq->ift_rs_pending = 0; 3136 } 3137 3138 pi.ipi_segs = segs; 3139 pi.ipi_nsegs = nsegs; 3140 3141 MPASS(pidx >= 0 && pidx < txq->ift_size); 3142 #ifdef PKT_DEBUG 3143 print_pkt(&pi); 3144 #endif 3145 if (map != NULL) 3146 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3147 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3148 if (map != NULL) 3149 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3150 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3151 DBG_COUNTER_INC(tx_encap); 3152 MPASS(pi.ipi_new_pidx < txq->ift_size); 3153 3154 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3155 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3156 ndesc += txq->ift_size; 3157 txq->ift_gen = 1; 3158 } 3159 /* 3160 * drivers can need as many as 3161 * two sentinels 3162 */ 3163 MPASS(ndesc <= pi.ipi_nsegs + 2); 3164 MPASS(pi.ipi_new_pidx != pidx); 3165 MPASS(ndesc > 0); 3166 txq->ift_in_use += ndesc; 3167 3168 /* 3169 * We update the last software descriptor again here because there may 3170 * be a sentinel and/or there may be more mbufs than segments 3171 */ 3172 txq->ift_pidx = pi.ipi_new_pidx; 3173 txq->ift_npending += pi.ipi_ndescs; 3174 } else if (__predict_false(err == EFBIG && remap < 2)) { 3175 *m_headp = m_head = iflib_remove_mbuf(txq); 3176 remap = 1; 3177 txq->ift_txd_encap_efbig++; 3178 goto defrag; 3179 } else 3180 DBG_COUNTER_INC(encap_txd_encap_fail); 3181 return (err); 3182 3183 defrag_failed: 3184 txq->ift_mbuf_defrag_failed++; 3185 txq->ift_map_failed++; 3186 m_freem(*m_headp); 3187 DBG_COUNTER_INC(tx_frees); 3188 *m_headp = NULL; 3189 return (ENOMEM); 3190 } 3191 3192 static void 3193 iflib_tx_desc_free(iflib_txq_t txq, int n) 3194 { 3195 int hasmap; 3196 uint32_t qsize, cidx, mask, gen; 3197 struct mbuf *m, **ifsd_m; 3198 uint8_t *ifsd_flags; 3199 bus_dmamap_t *ifsd_map; 3200 bool do_prefetch; 3201 3202 cidx = txq->ift_cidx; 3203 gen = txq->ift_gen; 3204 qsize = txq->ift_size; 3205 mask = qsize-1; 3206 hasmap = txq->ift_sds.ifsd_map != NULL; 3207 ifsd_flags = txq->ift_sds.ifsd_flags; 3208 ifsd_m = txq->ift_sds.ifsd_m; 3209 ifsd_map = txq->ift_sds.ifsd_map; 3210 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3211 3212 while (n--) { 3213 if (do_prefetch) { 3214 prefetch(ifsd_m[(cidx + 3) & mask]); 3215 prefetch(ifsd_m[(cidx + 4) & mask]); 3216 } 3217 if (ifsd_m[cidx] != NULL) { 3218 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3219 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3220 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3221 /* 3222 * does it matter if it's not the TSO tag? If so we'll 3223 * have to add the type to flags 3224 */ 3225 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3226 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3227 } 3228 if ((m = ifsd_m[cidx]) != NULL) { 3229 /* XXX we don't support any drivers that batch packets yet */ 3230 MPASS(m->m_nextpkt == NULL); 3231 3232 m_free(m); 3233 ifsd_m[cidx] = NULL; 3234 #if MEMORY_LOGGING 3235 txq->ift_dequeued++; 3236 #endif 3237 DBG_COUNTER_INC(tx_frees); 3238 } 3239 } 3240 if (__predict_false(++cidx == qsize)) { 3241 cidx = 0; 3242 gen = 0; 3243 } 3244 } 3245 txq->ift_cidx = cidx; 3246 txq->ift_gen = gen; 3247 } 3248 3249 static __inline int 3250 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3251 { 3252 int reclaim; 3253 if_ctx_t ctx = txq->ift_ctx; 3254 3255 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3256 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3257 3258 /* 3259 * Need a rate-limiting check so that this isn't called every time 3260 */ 3261 iflib_tx_credits_update(ctx, txq); 3262 reclaim = DESC_RECLAIMABLE(txq); 3263 3264 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3265 #ifdef INVARIANTS 3266 if (iflib_verbose_debug) { 3267 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3268 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3269 reclaim, thresh); 3270 3271 } 3272 #endif 3273 return (0); 3274 } 3275 iflib_tx_desc_free(txq, reclaim); 3276 txq->ift_cleaned += reclaim; 3277 txq->ift_in_use -= reclaim; 3278 3279 return (reclaim); 3280 } 3281 3282 static struct mbuf ** 3283 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3284 { 3285 int next, size; 3286 struct mbuf **items; 3287 3288 size = r->size; 3289 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3290 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3291 3292 prefetch(items[(cidx + offset) & (size-1)]); 3293 if (remaining > 1) { 3294 prefetch(&items[next]); 3295 prefetch(items[(cidx + offset + 1) & (size-1)]); 3296 prefetch(items[(cidx + offset + 2) & (size-1)]); 3297 prefetch(items[(cidx + offset + 3) & (size-1)]); 3298 } 3299 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3300 } 3301 3302 static void 3303 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3304 { 3305 3306 ifmp_ring_check_drainage(txq->ift_br, budget); 3307 } 3308 3309 static uint32_t 3310 iflib_txq_can_drain(struct ifmp_ring *r) 3311 { 3312 iflib_txq_t txq = r->cookie; 3313 if_ctx_t ctx = txq->ift_ctx; 3314 3315 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3316 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3317 } 3318 3319 static uint32_t 3320 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3321 { 3322 iflib_txq_t txq = r->cookie; 3323 if_ctx_t ctx = txq->ift_ctx; 3324 struct ifnet *ifp = ctx->ifc_ifp; 3325 struct mbuf **mp, *m; 3326 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3327 int reclaimed, err, in_use_prev, desc_used; 3328 bool do_prefetch, ring, rang; 3329 3330 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3331 !LINK_ACTIVE(ctx))) { 3332 DBG_COUNTER_INC(txq_drain_notready); 3333 return (0); 3334 } 3335 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3336 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3337 avail = IDXDIFF(pidx, cidx, r->size); 3338 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3339 DBG_COUNTER_INC(txq_drain_flushing); 3340 for (i = 0; i < avail; i++) { 3341 m_free(r->items[(cidx + i) & (r->size-1)]); 3342 r->items[(cidx + i) & (r->size-1)] = NULL; 3343 } 3344 return (avail); 3345 } 3346 3347 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3348 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3349 CALLOUT_LOCK(txq); 3350 callout_stop(&txq->ift_timer); 3351 CALLOUT_UNLOCK(txq); 3352 DBG_COUNTER_INC(txq_drain_oactive); 3353 return (0); 3354 } 3355 if (reclaimed) 3356 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3357 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3358 count = MIN(avail, TX_BATCH_SIZE); 3359 #ifdef INVARIANTS 3360 if (iflib_verbose_debug) 3361 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3362 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3363 #endif 3364 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3365 avail = TXQ_AVAIL(txq); 3366 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3367 int pidx_prev, rem = do_prefetch ? count - i : 0; 3368 3369 mp = _ring_peek_one(r, cidx, i, rem); 3370 MPASS(mp != NULL && *mp != NULL); 3371 if (__predict_false(*mp == (struct mbuf *)txq)) { 3372 consumed++; 3373 reclaimed++; 3374 continue; 3375 } 3376 in_use_prev = txq->ift_in_use; 3377 pidx_prev = txq->ift_pidx; 3378 err = iflib_encap(txq, mp); 3379 if (__predict_false(err)) { 3380 DBG_COUNTER_INC(txq_drain_encapfail); 3381 /* no room - bail out */ 3382 if (err == ENOBUFS) 3383 break; 3384 consumed++; 3385 DBG_COUNTER_INC(txq_drain_encapfail); 3386 /* we can't send this packet - skip it */ 3387 continue; 3388 } 3389 consumed++; 3390 pkt_sent++; 3391 m = *mp; 3392 DBG_COUNTER_INC(tx_sent); 3393 bytes_sent += m->m_pkthdr.len; 3394 mcast_sent += !!(m->m_flags & M_MCAST); 3395 avail = TXQ_AVAIL(txq); 3396 3397 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3398 desc_used += (txq->ift_in_use - in_use_prev); 3399 ETHER_BPF_MTAP(ifp, m); 3400 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3401 break; 3402 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3403 } 3404 3405 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3406 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3407 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3408 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3409 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3410 if (mcast_sent) 3411 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3412 #ifdef INVARIANTS 3413 if (iflib_verbose_debug) 3414 printf("consumed=%d\n", consumed); 3415 #endif 3416 return (consumed); 3417 } 3418 3419 static uint32_t 3420 iflib_txq_drain_always(struct ifmp_ring *r) 3421 { 3422 return (1); 3423 } 3424 3425 static uint32_t 3426 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3427 { 3428 int i, avail; 3429 struct mbuf **mp; 3430 iflib_txq_t txq; 3431 3432 txq = r->cookie; 3433 3434 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3435 CALLOUT_LOCK(txq); 3436 callout_stop(&txq->ift_timer); 3437 CALLOUT_UNLOCK(txq); 3438 3439 avail = IDXDIFF(pidx, cidx, r->size); 3440 for (i = 0; i < avail; i++) { 3441 mp = _ring_peek_one(r, cidx, i, avail - i); 3442 if (__predict_false(*mp == (struct mbuf *)txq)) 3443 continue; 3444 m_freem(*mp); 3445 } 3446 MPASS(ifmp_ring_is_stalled(r) == 0); 3447 return (avail); 3448 } 3449 3450 static void 3451 iflib_ifmp_purge(iflib_txq_t txq) 3452 { 3453 struct ifmp_ring *r; 3454 3455 r = txq->ift_br; 3456 r->drain = iflib_txq_drain_free; 3457 r->can_drain = iflib_txq_drain_always; 3458 3459 ifmp_ring_check_drainage(r, r->size); 3460 3461 r->drain = iflib_txq_drain; 3462 r->can_drain = iflib_txq_can_drain; 3463 } 3464 3465 static void 3466 _task_fn_tx(void *context) 3467 { 3468 iflib_txq_t txq = context; 3469 if_ctx_t ctx = txq->ift_ctx; 3470 struct ifnet *ifp = ctx->ifc_ifp; 3471 int rc; 3472 3473 #ifdef IFLIB_DIAGNOSTICS 3474 txq->ift_cpu_exec_count[curcpu]++; 3475 #endif 3476 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3477 return; 3478 if ((ifp->if_capenable & IFCAP_NETMAP)) { 3479 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3480 netmap_tx_irq(ifp, txq->ift_id); 3481 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3482 return; 3483 } 3484 if (txq->ift_db_pending) 3485 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3486 else 3487 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3488 if (ctx->ifc_flags & IFC_LEGACY) 3489 IFDI_INTR_ENABLE(ctx); 3490 else { 3491 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3492 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3493 } 3494 } 3495 3496 static void 3497 _task_fn_rx(void *context) 3498 { 3499 iflib_rxq_t rxq = context; 3500 if_ctx_t ctx = rxq->ifr_ctx; 3501 bool more; 3502 int rc; 3503 3504 #ifdef IFLIB_DIAGNOSTICS 3505 rxq->ifr_cpu_exec_count[curcpu]++; 3506 #endif 3507 DBG_COUNTER_INC(task_fn_rxs); 3508 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3509 return; 3510 if ((more = iflib_rxeof(rxq, 16 /* XXX */)) == false) { 3511 if (ctx->ifc_flags & IFC_LEGACY) 3512 IFDI_INTR_ENABLE(ctx); 3513 else { 3514 DBG_COUNTER_INC(rx_intr_enables); 3515 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3516 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3517 } 3518 } 3519 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3520 return; 3521 if (more) 3522 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3523 } 3524 3525 static void 3526 _task_fn_admin(void *context) 3527 { 3528 if_ctx_t ctx = context; 3529 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3530 iflib_txq_t txq; 3531 int i; 3532 3533 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) { 3534 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3535 return; 3536 } 3537 } 3538 3539 CTX_LOCK(ctx); 3540 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3541 CALLOUT_LOCK(txq); 3542 callout_stop(&txq->ift_timer); 3543 CALLOUT_UNLOCK(txq); 3544 } 3545 IFDI_UPDATE_ADMIN_STATUS(ctx); 3546 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3547 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3548 IFDI_LINK_INTR_ENABLE(ctx); 3549 if (ctx->ifc_flags & IFC_DO_RESET) { 3550 ctx->ifc_flags &= ~IFC_DO_RESET; 3551 iflib_if_init_locked(ctx); 3552 } 3553 CTX_UNLOCK(ctx); 3554 3555 if (LINK_ACTIVE(ctx) == 0) 3556 return; 3557 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3558 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3559 } 3560 3561 3562 static void 3563 _task_fn_iov(void *context) 3564 { 3565 if_ctx_t ctx = context; 3566 3567 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3568 return; 3569 3570 CTX_LOCK(ctx); 3571 IFDI_VFLR_HANDLE(ctx); 3572 CTX_UNLOCK(ctx); 3573 } 3574 3575 static int 3576 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3577 { 3578 int err; 3579 if_int_delay_info_t info; 3580 if_ctx_t ctx; 3581 3582 info = (if_int_delay_info_t)arg1; 3583 ctx = info->iidi_ctx; 3584 info->iidi_req = req; 3585 info->iidi_oidp = oidp; 3586 CTX_LOCK(ctx); 3587 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3588 CTX_UNLOCK(ctx); 3589 return (err); 3590 } 3591 3592 /********************************************************************* 3593 * 3594 * IFNET FUNCTIONS 3595 * 3596 **********************************************************************/ 3597 3598 static void 3599 iflib_if_init_locked(if_ctx_t ctx) 3600 { 3601 iflib_stop(ctx); 3602 iflib_init_locked(ctx); 3603 } 3604 3605 3606 static void 3607 iflib_if_init(void *arg) 3608 { 3609 if_ctx_t ctx = arg; 3610 3611 CTX_LOCK(ctx); 3612 iflib_if_init_locked(ctx); 3613 CTX_UNLOCK(ctx); 3614 } 3615 3616 static int 3617 iflib_if_transmit(if_t ifp, struct mbuf *m) 3618 { 3619 if_ctx_t ctx = if_getsoftc(ifp); 3620 3621 iflib_txq_t txq; 3622 int err, qidx; 3623 3624 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3625 DBG_COUNTER_INC(tx_frees); 3626 m_freem(m); 3627 return (ENOBUFS); 3628 } 3629 3630 MPASS(m->m_nextpkt == NULL); 3631 qidx = 0; 3632 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3633 qidx = QIDX(ctx, m); 3634 /* 3635 * XXX calculate buf_ring based on flowid (divvy up bits?) 3636 */ 3637 txq = &ctx->ifc_txqs[qidx]; 3638 3639 #ifdef DRIVER_BACKPRESSURE 3640 if (txq->ift_closed) { 3641 while (m != NULL) { 3642 next = m->m_nextpkt; 3643 m->m_nextpkt = NULL; 3644 m_freem(m); 3645 m = next; 3646 } 3647 return (ENOBUFS); 3648 } 3649 #endif 3650 #ifdef notyet 3651 qidx = count = 0; 3652 mp = marr; 3653 next = m; 3654 do { 3655 count++; 3656 next = next->m_nextpkt; 3657 } while (next != NULL); 3658 3659 if (count > nitems(marr)) 3660 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3661 /* XXX check nextpkt */ 3662 m_freem(m); 3663 /* XXX simplify for now */ 3664 DBG_COUNTER_INC(tx_frees); 3665 return (ENOBUFS); 3666 } 3667 for (next = m, i = 0; next != NULL; i++) { 3668 mp[i] = next; 3669 next = next->m_nextpkt; 3670 mp[i]->m_nextpkt = NULL; 3671 } 3672 #endif 3673 DBG_COUNTER_INC(tx_seen); 3674 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3675 3676 if (err) { 3677 GROUPTASK_ENQUEUE(&txq->ift_task); 3678 /* support forthcoming later */ 3679 #ifdef DRIVER_BACKPRESSURE 3680 txq->ift_closed = TRUE; 3681 #endif 3682 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3683 m_freem(m); 3684 } else if (TXQ_AVAIL(txq) < (txq->ift_size >> 1)) { 3685 GROUPTASK_ENQUEUE(&txq->ift_task); 3686 } 3687 3688 return (err); 3689 } 3690 3691 static void 3692 iflib_if_qflush(if_t ifp) 3693 { 3694 if_ctx_t ctx = if_getsoftc(ifp); 3695 iflib_txq_t txq = ctx->ifc_txqs; 3696 int i; 3697 3698 CTX_LOCK(ctx); 3699 ctx->ifc_flags |= IFC_QFLUSH; 3700 CTX_UNLOCK(ctx); 3701 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3702 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3703 iflib_txq_check_drain(txq, 0); 3704 CTX_LOCK(ctx); 3705 ctx->ifc_flags &= ~IFC_QFLUSH; 3706 CTX_UNLOCK(ctx); 3707 3708 if_qflush(ifp); 3709 } 3710 3711 3712 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3713 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | \ 3714 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3715 3716 static int 3717 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3718 { 3719 if_ctx_t ctx = if_getsoftc(ifp); 3720 struct ifreq *ifr = (struct ifreq *)data; 3721 #if defined(INET) || defined(INET6) 3722 struct ifaddr *ifa = (struct ifaddr *)data; 3723 #endif 3724 bool avoid_reset = FALSE; 3725 int err = 0, reinit = 0, bits; 3726 3727 switch (command) { 3728 case SIOCSIFADDR: 3729 #ifdef INET 3730 if (ifa->ifa_addr->sa_family == AF_INET) 3731 avoid_reset = TRUE; 3732 #endif 3733 #ifdef INET6 3734 if (ifa->ifa_addr->sa_family == AF_INET6) 3735 avoid_reset = TRUE; 3736 #endif 3737 /* 3738 ** Calling init results in link renegotiation, 3739 ** so we avoid doing it when possible. 3740 */ 3741 if (avoid_reset) { 3742 if_setflagbits(ifp, IFF_UP,0); 3743 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3744 reinit = 1; 3745 #ifdef INET 3746 if (!(if_getflags(ifp) & IFF_NOARP)) 3747 arp_ifinit(ifp, ifa); 3748 #endif 3749 } else 3750 err = ether_ioctl(ifp, command, data); 3751 break; 3752 case SIOCSIFMTU: 3753 CTX_LOCK(ctx); 3754 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3755 CTX_UNLOCK(ctx); 3756 break; 3757 } 3758 bits = if_getdrvflags(ifp); 3759 /* stop the driver and free any clusters before proceeding */ 3760 iflib_stop(ctx); 3761 3762 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3763 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3764 ctx->ifc_flags |= IFC_MULTISEG; 3765 else 3766 ctx->ifc_flags &= ~IFC_MULTISEG; 3767 err = if_setmtu(ifp, ifr->ifr_mtu); 3768 } 3769 iflib_init_locked(ctx); 3770 if_setdrvflags(ifp, bits); 3771 CTX_UNLOCK(ctx); 3772 break; 3773 case SIOCSIFFLAGS: 3774 CTX_LOCK(ctx); 3775 if (if_getflags(ifp) & IFF_UP) { 3776 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3777 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3778 (IFF_PROMISC | IFF_ALLMULTI)) { 3779 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3780 } 3781 } else 3782 reinit = 1; 3783 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3784 iflib_stop(ctx); 3785 } 3786 ctx->ifc_if_flags = if_getflags(ifp); 3787 CTX_UNLOCK(ctx); 3788 break; 3789 case SIOCADDMULTI: 3790 case SIOCDELMULTI: 3791 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3792 CTX_LOCK(ctx); 3793 IFDI_INTR_DISABLE(ctx); 3794 IFDI_MULTI_SET(ctx); 3795 IFDI_INTR_ENABLE(ctx); 3796 CTX_UNLOCK(ctx); 3797 } 3798 break; 3799 case SIOCSIFMEDIA: 3800 CTX_LOCK(ctx); 3801 IFDI_MEDIA_SET(ctx); 3802 CTX_UNLOCK(ctx); 3803 /* falls thru */ 3804 case SIOCGIFMEDIA: 3805 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3806 break; 3807 case SIOCGI2C: 3808 { 3809 struct ifi2creq i2c; 3810 3811 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 3812 if (err != 0) 3813 break; 3814 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3815 err = EINVAL; 3816 break; 3817 } 3818 if (i2c.len > sizeof(i2c.data)) { 3819 err = EINVAL; 3820 break; 3821 } 3822 3823 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 3824 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 3825 break; 3826 } 3827 case SIOCSIFCAP: 3828 { 3829 int mask, setmask; 3830 3831 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3832 setmask = 0; 3833 #ifdef TCP_OFFLOAD 3834 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 3835 #endif 3836 setmask |= (mask & IFCAP_FLAGS); 3837 3838 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 3839 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 3840 if ((mask & IFCAP_WOL) && 3841 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 3842 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 3843 if_vlancap(ifp); 3844 /* 3845 * want to ensure that traffic has stopped before we change any of the flags 3846 */ 3847 if (setmask) { 3848 CTX_LOCK(ctx); 3849 bits = if_getdrvflags(ifp); 3850 if (bits & IFF_DRV_RUNNING) 3851 iflib_stop(ctx); 3852 if_togglecapenable(ifp, setmask); 3853 if (bits & IFF_DRV_RUNNING) 3854 iflib_init_locked(ctx); 3855 if_setdrvflags(ifp, bits); 3856 CTX_UNLOCK(ctx); 3857 } 3858 break; 3859 } 3860 case SIOCGPRIVATE_0: 3861 case SIOCSDRVSPEC: 3862 case SIOCGDRVSPEC: 3863 CTX_LOCK(ctx); 3864 err = IFDI_PRIV_IOCTL(ctx, command, data); 3865 CTX_UNLOCK(ctx); 3866 break; 3867 default: 3868 err = ether_ioctl(ifp, command, data); 3869 break; 3870 } 3871 if (reinit) 3872 iflib_if_init(ctx); 3873 return (err); 3874 } 3875 3876 static uint64_t 3877 iflib_if_get_counter(if_t ifp, ift_counter cnt) 3878 { 3879 if_ctx_t ctx = if_getsoftc(ifp); 3880 3881 return (IFDI_GET_COUNTER(ctx, cnt)); 3882 } 3883 3884 /********************************************************************* 3885 * 3886 * OTHER FUNCTIONS EXPORTED TO THE STACK 3887 * 3888 **********************************************************************/ 3889 3890 static void 3891 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 3892 { 3893 if_ctx_t ctx = if_getsoftc(ifp); 3894 3895 if ((void *)ctx != arg) 3896 return; 3897 3898 if ((vtag == 0) || (vtag > 4095)) 3899 return; 3900 3901 CTX_LOCK(ctx); 3902 IFDI_VLAN_REGISTER(ctx, vtag); 3903 /* Re-init to load the changes */ 3904 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3905 iflib_init_locked(ctx); 3906 CTX_UNLOCK(ctx); 3907 } 3908 3909 static void 3910 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 3911 { 3912 if_ctx_t ctx = if_getsoftc(ifp); 3913 3914 if ((void *)ctx != arg) 3915 return; 3916 3917 if ((vtag == 0) || (vtag > 4095)) 3918 return; 3919 3920 CTX_LOCK(ctx); 3921 IFDI_VLAN_UNREGISTER(ctx, vtag); 3922 /* Re-init to load the changes */ 3923 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3924 iflib_init_locked(ctx); 3925 CTX_UNLOCK(ctx); 3926 } 3927 3928 static void 3929 iflib_led_func(void *arg, int onoff) 3930 { 3931 if_ctx_t ctx = arg; 3932 3933 CTX_LOCK(ctx); 3934 IFDI_LED_FUNC(ctx, onoff); 3935 CTX_UNLOCK(ctx); 3936 } 3937 3938 /********************************************************************* 3939 * 3940 * BUS FUNCTION DEFINITIONS 3941 * 3942 **********************************************************************/ 3943 3944 int 3945 iflib_device_probe(device_t dev) 3946 { 3947 pci_vendor_info_t *ent; 3948 3949 uint16_t pci_vendor_id, pci_device_id; 3950 uint16_t pci_subvendor_id, pci_subdevice_id; 3951 uint16_t pci_rev_id; 3952 if_shared_ctx_t sctx; 3953 3954 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 3955 return (ENOTSUP); 3956 3957 pci_vendor_id = pci_get_vendor(dev); 3958 pci_device_id = pci_get_device(dev); 3959 pci_subvendor_id = pci_get_subvendor(dev); 3960 pci_subdevice_id = pci_get_subdevice(dev); 3961 pci_rev_id = pci_get_revid(dev); 3962 if (sctx->isc_parse_devinfo != NULL) 3963 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 3964 3965 ent = sctx->isc_vendor_info; 3966 while (ent->pvi_vendor_id != 0) { 3967 if (pci_vendor_id != ent->pvi_vendor_id) { 3968 ent++; 3969 continue; 3970 } 3971 if ((pci_device_id == ent->pvi_device_id) && 3972 ((pci_subvendor_id == ent->pvi_subvendor_id) || 3973 (ent->pvi_subvendor_id == 0)) && 3974 ((pci_subdevice_id == ent->pvi_subdevice_id) || 3975 (ent->pvi_subdevice_id == 0)) && 3976 ((pci_rev_id == ent->pvi_rev_id) || 3977 (ent->pvi_rev_id == 0))) { 3978 3979 device_set_desc_copy(dev, ent->pvi_name); 3980 /* this needs to be changed to zero if the bus probing code 3981 * ever stops re-probing on best match because the sctx 3982 * may have its values over written by register calls 3983 * in subsequent probes 3984 */ 3985 return (BUS_PROBE_DEFAULT); 3986 } 3987 ent++; 3988 } 3989 return (ENXIO); 3990 } 3991 3992 int 3993 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 3994 { 3995 int err, rid, msix, msix_bar; 3996 if_ctx_t ctx; 3997 if_t ifp; 3998 if_softc_ctx_t scctx; 3999 int i; 4000 uint16_t main_txq; 4001 uint16_t main_rxq; 4002 4003 4004 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4005 4006 if (sc == NULL) { 4007 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4008 device_set_softc(dev, ctx); 4009 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4010 } 4011 4012 ctx->ifc_sctx = sctx; 4013 ctx->ifc_dev = dev; 4014 ctx->ifc_softc = sc; 4015 4016 if ((err = iflib_register(ctx)) != 0) { 4017 device_printf(dev, "iflib_register failed %d\n", err); 4018 return (err); 4019 } 4020 iflib_add_device_sysctl_pre(ctx); 4021 4022 scctx = &ctx->ifc_softc_ctx; 4023 ifp = ctx->ifc_ifp; 4024 4025 /* 4026 * XXX sanity check that ntxd & nrxd are a power of 2 4027 */ 4028 if (ctx->ifc_sysctl_ntxqs != 0) 4029 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4030 if (ctx->ifc_sysctl_nrxqs != 0) 4031 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4032 4033 for (i = 0; i < sctx->isc_ntxqs; i++) { 4034 if (ctx->ifc_sysctl_ntxds[i] != 0) 4035 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4036 else 4037 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4038 } 4039 4040 for (i = 0; i < sctx->isc_nrxqs; i++) { 4041 if (ctx->ifc_sysctl_nrxds[i] != 0) 4042 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4043 else 4044 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4045 } 4046 4047 for (i = 0; i < sctx->isc_nrxqs; i++) { 4048 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4049 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4050 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4051 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4052 } 4053 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4054 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4055 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4056 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4057 } 4058 } 4059 4060 for (i = 0; i < sctx->isc_ntxqs; i++) { 4061 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4062 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4063 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4064 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4065 } 4066 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4067 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4068 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4069 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4070 } 4071 } 4072 4073 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4074 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4075 return (err); 4076 } 4077 _iflib_pre_assert(scctx); 4078 ctx->ifc_txrx = *scctx->isc_txrx; 4079 4080 #ifdef INVARIANTS 4081 MPASS(scctx->isc_capenable); 4082 if (scctx->isc_capenable & IFCAP_TXCSUM) 4083 MPASS(scctx->isc_tx_csum_flags); 4084 #endif 4085 4086 if_setcapabilities(ifp, scctx->isc_capenable); 4087 if_setcapenable(ifp, scctx->isc_capenable); 4088 4089 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4090 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4091 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4092 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4093 4094 #ifdef ACPI_DMAR 4095 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4096 ctx->ifc_flags |= IFC_DMAR; 4097 #elif !(defined(__i386__) || defined(__amd64__)) 4098 /* set unconditionally for !x86 */ 4099 ctx->ifc_flags |= IFC_DMAR; 4100 #endif 4101 4102 msix_bar = scctx->isc_msix_bar; 4103 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4104 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4105 4106 /* XXX change for per-queue sizes */ 4107 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4108 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4109 for (i = 0; i < sctx->isc_nrxqs; i++) { 4110 if (!powerof2(scctx->isc_nrxd[i])) { 4111 /* round down instead? */ 4112 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4113 err = EINVAL; 4114 goto fail; 4115 } 4116 } 4117 for (i = 0; i < sctx->isc_ntxqs; i++) { 4118 if (!powerof2(scctx->isc_ntxd[i])) { 4119 device_printf(dev, 4120 "# tx descriptors must be a power of 2"); 4121 err = EINVAL; 4122 goto fail; 4123 } 4124 } 4125 4126 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4127 MAX_SINGLE_PACKET_FRACTION) 4128 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4129 MAX_SINGLE_PACKET_FRACTION); 4130 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4131 MAX_SINGLE_PACKET_FRACTION) 4132 scctx->isc_tx_tso_segments_max = max(1, 4133 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4134 4135 /* 4136 * Protect the stack against modern hardware 4137 */ 4138 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4139 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4140 4141 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4142 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4143 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4144 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4145 if (scctx->isc_rss_table_size == 0) 4146 scctx->isc_rss_table_size = 64; 4147 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4148 4149 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4150 /* XXX format name */ 4151 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4152 /* 4153 ** Now setup MSI or MSI/X, should 4154 ** return us the number of supported 4155 ** vectors. (Will be 1 for MSI) 4156 */ 4157 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4158 msix = scctx->isc_vectors; 4159 } else if (scctx->isc_msix_bar != 0) 4160 /* 4161 * The simple fact that isc_msix_bar is not 0 does not mean we 4162 * we have a good value there that is known to work. 4163 */ 4164 msix = iflib_msix_init(ctx); 4165 else { 4166 scctx->isc_vectors = 1; 4167 scctx->isc_ntxqsets = 1; 4168 scctx->isc_nrxqsets = 1; 4169 scctx->isc_intr = IFLIB_INTR_LEGACY; 4170 msix = 0; 4171 } 4172 /* Get memory for the station queues */ 4173 if ((err = iflib_queues_alloc(ctx))) { 4174 device_printf(dev, "Unable to allocate queue memory\n"); 4175 goto fail; 4176 } 4177 4178 if ((err = iflib_qset_structures_setup(ctx))) { 4179 device_printf(dev, "qset structure setup failed %d\n", err); 4180 goto fail_queues; 4181 } 4182 4183 /* 4184 * Group taskqueues aren't properly set up until SMP is started, 4185 * so we disable interrupts until we can handle them post 4186 * SI_SUB_SMP. 4187 * 4188 * XXX: disabling interrupts doesn't actually work, at least for 4189 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4190 * we do null handling and depend on this not causing too large an 4191 * interrupt storm. 4192 */ 4193 IFDI_INTR_DISABLE(ctx); 4194 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4195 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4196 goto fail_intr_free; 4197 } 4198 if (msix <= 1) { 4199 rid = 0; 4200 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4201 MPASS(msix == 1); 4202 rid = 1; 4203 } 4204 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4205 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4206 goto fail_intr_free; 4207 } 4208 } 4209 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4210 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4211 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4212 goto fail_detach; 4213 } 4214 if ((err = iflib_netmap_attach(ctx))) { 4215 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4216 goto fail_detach; 4217 } 4218 *ctxp = ctx; 4219 4220 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4221 iflib_add_device_sysctl_post(ctx); 4222 ctx->ifc_flags |= IFC_INIT_DONE; 4223 return (0); 4224 fail_detach: 4225 ether_ifdetach(ctx->ifc_ifp); 4226 fail_intr_free: 4227 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4228 pci_release_msi(ctx->ifc_dev); 4229 fail_queues: 4230 /* XXX free queues */ 4231 fail: 4232 IFDI_DETACH(ctx); 4233 return (err); 4234 } 4235 4236 int 4237 iflib_device_attach(device_t dev) 4238 { 4239 if_ctx_t ctx; 4240 if_shared_ctx_t sctx; 4241 4242 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4243 return (ENOTSUP); 4244 4245 pci_enable_busmaster(dev); 4246 4247 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4248 } 4249 4250 int 4251 iflib_device_deregister(if_ctx_t ctx) 4252 { 4253 if_t ifp = ctx->ifc_ifp; 4254 iflib_txq_t txq; 4255 iflib_rxq_t rxq; 4256 device_t dev = ctx->ifc_dev; 4257 int i, j; 4258 struct taskqgroup *tqg; 4259 iflib_fl_t fl; 4260 4261 /* Make sure VLANS are not using driver */ 4262 if (if_vlantrunkinuse(ifp)) { 4263 device_printf(dev,"Vlan in use, detach first\n"); 4264 return (EBUSY); 4265 } 4266 4267 CTX_LOCK(ctx); 4268 ctx->ifc_in_detach = 1; 4269 iflib_stop(ctx); 4270 CTX_UNLOCK(ctx); 4271 4272 /* Unregister VLAN events */ 4273 if (ctx->ifc_vlan_attach_event != NULL) 4274 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4275 if (ctx->ifc_vlan_detach_event != NULL) 4276 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4277 4278 iflib_netmap_detach(ifp); 4279 ether_ifdetach(ifp); 4280 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4281 CTX_LOCK_DESTROY(ctx); 4282 if (ctx->ifc_led_dev != NULL) 4283 led_destroy(ctx->ifc_led_dev); 4284 /* XXX drain any dependent tasks */ 4285 tqg = qgroup_if_io_tqg; 4286 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4287 callout_drain(&txq->ift_timer); 4288 if (txq->ift_task.gt_uniq != NULL) 4289 taskqgroup_detach(tqg, &txq->ift_task); 4290 } 4291 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4292 if (rxq->ifr_task.gt_uniq != NULL) 4293 taskqgroup_detach(tqg, &rxq->ifr_task); 4294 4295 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4296 free(fl->ifl_rx_bitmap, M_IFLIB); 4297 4298 } 4299 tqg = qgroup_if_config_tqg; 4300 if (ctx->ifc_admin_task.gt_uniq != NULL) 4301 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4302 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4303 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4304 4305 IFDI_DETACH(ctx); 4306 device_set_softc(ctx->ifc_dev, NULL); 4307 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4308 pci_release_msi(dev); 4309 } 4310 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4311 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4312 } 4313 if (ctx->ifc_msix_mem != NULL) { 4314 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4315 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4316 ctx->ifc_msix_mem = NULL; 4317 } 4318 4319 bus_generic_detach(dev); 4320 if_free(ifp); 4321 4322 iflib_tx_structures_free(ctx); 4323 iflib_rx_structures_free(ctx); 4324 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4325 free(ctx->ifc_softc, M_IFLIB); 4326 free(ctx, M_IFLIB); 4327 return (0); 4328 } 4329 4330 4331 int 4332 iflib_device_detach(device_t dev) 4333 { 4334 if_ctx_t ctx = device_get_softc(dev); 4335 4336 return (iflib_device_deregister(ctx)); 4337 } 4338 4339 int 4340 iflib_device_suspend(device_t dev) 4341 { 4342 if_ctx_t ctx = device_get_softc(dev); 4343 4344 CTX_LOCK(ctx); 4345 IFDI_SUSPEND(ctx); 4346 CTX_UNLOCK(ctx); 4347 4348 return bus_generic_suspend(dev); 4349 } 4350 int 4351 iflib_device_shutdown(device_t dev) 4352 { 4353 if_ctx_t ctx = device_get_softc(dev); 4354 4355 CTX_LOCK(ctx); 4356 IFDI_SHUTDOWN(ctx); 4357 CTX_UNLOCK(ctx); 4358 4359 return bus_generic_suspend(dev); 4360 } 4361 4362 4363 int 4364 iflib_device_resume(device_t dev) 4365 { 4366 if_ctx_t ctx = device_get_softc(dev); 4367 iflib_txq_t txq = ctx->ifc_txqs; 4368 4369 CTX_LOCK(ctx); 4370 IFDI_RESUME(ctx); 4371 iflib_init_locked(ctx); 4372 CTX_UNLOCK(ctx); 4373 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4374 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4375 4376 return (bus_generic_resume(dev)); 4377 } 4378 4379 int 4380 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4381 { 4382 int error; 4383 if_ctx_t ctx = device_get_softc(dev); 4384 4385 CTX_LOCK(ctx); 4386 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4387 CTX_UNLOCK(ctx); 4388 4389 return (error); 4390 } 4391 4392 void 4393 iflib_device_iov_uninit(device_t dev) 4394 { 4395 if_ctx_t ctx = device_get_softc(dev); 4396 4397 CTX_LOCK(ctx); 4398 IFDI_IOV_UNINIT(ctx); 4399 CTX_UNLOCK(ctx); 4400 } 4401 4402 int 4403 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4404 { 4405 int error; 4406 if_ctx_t ctx = device_get_softc(dev); 4407 4408 CTX_LOCK(ctx); 4409 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4410 CTX_UNLOCK(ctx); 4411 4412 return (error); 4413 } 4414 4415 /********************************************************************* 4416 * 4417 * MODULE FUNCTION DEFINITIONS 4418 * 4419 **********************************************************************/ 4420 4421 /* 4422 * - Start a fast taskqueue thread for each core 4423 * - Start a taskqueue for control operations 4424 */ 4425 static int 4426 iflib_module_init(void) 4427 { 4428 return (0); 4429 } 4430 4431 static int 4432 iflib_module_event_handler(module_t mod, int what, void *arg) 4433 { 4434 int err; 4435 4436 switch (what) { 4437 case MOD_LOAD: 4438 if ((err = iflib_module_init()) != 0) 4439 return (err); 4440 break; 4441 case MOD_UNLOAD: 4442 return (EBUSY); 4443 default: 4444 return (EOPNOTSUPP); 4445 } 4446 4447 return (0); 4448 } 4449 4450 /********************************************************************* 4451 * 4452 * PUBLIC FUNCTION DEFINITIONS 4453 * ordered as in iflib.h 4454 * 4455 **********************************************************************/ 4456 4457 4458 static void 4459 _iflib_assert(if_shared_ctx_t sctx) 4460 { 4461 MPASS(sctx->isc_tx_maxsize); 4462 MPASS(sctx->isc_tx_maxsegsize); 4463 4464 MPASS(sctx->isc_rx_maxsize); 4465 MPASS(sctx->isc_rx_nsegments); 4466 MPASS(sctx->isc_rx_maxsegsize); 4467 4468 MPASS(sctx->isc_nrxd_min[0]); 4469 MPASS(sctx->isc_nrxd_max[0]); 4470 MPASS(sctx->isc_nrxd_default[0]); 4471 MPASS(sctx->isc_ntxd_min[0]); 4472 MPASS(sctx->isc_ntxd_max[0]); 4473 MPASS(sctx->isc_ntxd_default[0]); 4474 } 4475 4476 static void 4477 _iflib_pre_assert(if_softc_ctx_t scctx) 4478 { 4479 4480 MPASS(scctx->isc_txrx->ift_txd_encap); 4481 MPASS(scctx->isc_txrx->ift_txd_flush); 4482 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4483 MPASS(scctx->isc_txrx->ift_rxd_available); 4484 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4485 MPASS(scctx->isc_txrx->ift_rxd_refill); 4486 MPASS(scctx->isc_txrx->ift_rxd_flush); 4487 } 4488 4489 static int 4490 iflib_register(if_ctx_t ctx) 4491 { 4492 if_shared_ctx_t sctx = ctx->ifc_sctx; 4493 driver_t *driver = sctx->isc_driver; 4494 device_t dev = ctx->ifc_dev; 4495 if_t ifp; 4496 4497 _iflib_assert(sctx); 4498 4499 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4500 4501 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4502 if (ifp == NULL) { 4503 device_printf(dev, "can not allocate ifnet structure\n"); 4504 return (ENOMEM); 4505 } 4506 4507 /* 4508 * Initialize our context's device specific methods 4509 */ 4510 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4511 kobj_class_compile((kobj_class_t) driver); 4512 driver->refs++; 4513 4514 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4515 if_setsoftc(ifp, ctx); 4516 if_setdev(ifp, dev); 4517 if_setinitfn(ifp, iflib_if_init); 4518 if_setioctlfn(ifp, iflib_if_ioctl); 4519 if_settransmitfn(ifp, iflib_if_transmit); 4520 if_setqflushfn(ifp, iflib_if_qflush); 4521 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4522 4523 ctx->ifc_vlan_attach_event = 4524 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4525 EVENTHANDLER_PRI_FIRST); 4526 ctx->ifc_vlan_detach_event = 4527 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4528 EVENTHANDLER_PRI_FIRST); 4529 4530 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4531 iflib_media_change, iflib_media_status); 4532 4533 return (0); 4534 } 4535 4536 4537 static int 4538 iflib_queues_alloc(if_ctx_t ctx) 4539 { 4540 if_shared_ctx_t sctx = ctx->ifc_sctx; 4541 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4542 device_t dev = ctx->ifc_dev; 4543 int nrxqsets = scctx->isc_nrxqsets; 4544 int ntxqsets = scctx->isc_ntxqsets; 4545 iflib_txq_t txq; 4546 iflib_rxq_t rxq; 4547 iflib_fl_t fl = NULL; 4548 int i, j, cpu, err, txconf, rxconf; 4549 iflib_dma_info_t ifdip; 4550 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4551 uint32_t *txqsizes = scctx->isc_txqsizes; 4552 uint8_t nrxqs = sctx->isc_nrxqs; 4553 uint8_t ntxqs = sctx->isc_ntxqs; 4554 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4555 caddr_t *vaddrs; 4556 uint64_t *paddrs; 4557 struct ifmp_ring **brscp; 4558 4559 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4560 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4561 4562 brscp = NULL; 4563 txq = NULL; 4564 rxq = NULL; 4565 4566 /* Allocate the TX ring struct memory */ 4567 if (!(txq = 4568 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4569 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4570 device_printf(dev, "Unable to allocate TX ring memory\n"); 4571 err = ENOMEM; 4572 goto fail; 4573 } 4574 4575 /* Now allocate the RX */ 4576 if (!(rxq = 4577 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4578 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4579 device_printf(dev, "Unable to allocate RX ring memory\n"); 4580 err = ENOMEM; 4581 goto rx_fail; 4582 } 4583 4584 ctx->ifc_txqs = txq; 4585 ctx->ifc_rxqs = rxq; 4586 4587 /* 4588 * XXX handle allocation failure 4589 */ 4590 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4591 /* Set up some basics */ 4592 4593 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4594 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4595 err = ENOMEM; 4596 goto err_tx_desc; 4597 } 4598 txq->ift_ifdi = ifdip; 4599 for (j = 0; j < ntxqs; j++, ifdip++) { 4600 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4601 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4602 err = ENOMEM; 4603 goto err_tx_desc; 4604 } 4605 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4606 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4607 } 4608 txq->ift_ctx = ctx; 4609 txq->ift_id = i; 4610 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4611 txq->ift_br_offset = 1; 4612 } else { 4613 txq->ift_br_offset = 0; 4614 } 4615 /* XXX fix this */ 4616 txq->ift_timer.c_cpu = cpu; 4617 4618 if (iflib_txsd_alloc(txq)) { 4619 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4620 err = ENOMEM; 4621 goto err_tx_desc; 4622 } 4623 4624 /* Initialize the TX lock */ 4625 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4626 device_get_nameunit(dev), txq->ift_id); 4627 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4628 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4629 4630 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4631 device_get_nameunit(dev), txq->ift_id); 4632 4633 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4634 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4635 if (err) { 4636 /* XXX free any allocated rings */ 4637 device_printf(dev, "Unable to allocate buf_ring\n"); 4638 goto err_tx_desc; 4639 } 4640 } 4641 4642 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4643 /* Set up some basics */ 4644 4645 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4646 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4647 err = ENOMEM; 4648 goto err_tx_desc; 4649 } 4650 4651 rxq->ifr_ifdi = ifdip; 4652 /* XXX this needs to be changed if #rx queues != #tx queues */ 4653 rxq->ifr_ntxqirq = 1; 4654 rxq->ifr_txqid[0] = i; 4655 for (j = 0; j < nrxqs; j++, ifdip++) { 4656 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4657 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4658 err = ENOMEM; 4659 goto err_tx_desc; 4660 } 4661 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4662 } 4663 rxq->ifr_ctx = ctx; 4664 rxq->ifr_id = i; 4665 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4666 rxq->ifr_fl_offset = 1; 4667 } else { 4668 rxq->ifr_fl_offset = 0; 4669 } 4670 rxq->ifr_nfl = nfree_lists; 4671 if (!(fl = 4672 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4673 device_printf(dev, "Unable to allocate free list memory\n"); 4674 err = ENOMEM; 4675 goto err_tx_desc; 4676 } 4677 rxq->ifr_fl = fl; 4678 for (j = 0; j < nfree_lists; j++) { 4679 fl[j].ifl_rxq = rxq; 4680 fl[j].ifl_id = j; 4681 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4682 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4683 } 4684 /* Allocate receive buffers for the ring*/ 4685 if (iflib_rxsd_alloc(rxq)) { 4686 device_printf(dev, 4687 "Critical Failure setting up receive buffers\n"); 4688 err = ENOMEM; 4689 goto err_rx_desc; 4690 } 4691 } 4692 4693 /* TXQs */ 4694 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4695 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4696 for (i = 0; i < ntxqsets; i++) { 4697 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4698 4699 for (j = 0; j < ntxqs; j++, di++) { 4700 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4701 paddrs[i*ntxqs + j] = di->idi_paddr; 4702 } 4703 } 4704 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4705 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4706 iflib_tx_structures_free(ctx); 4707 free(vaddrs, M_IFLIB); 4708 free(paddrs, M_IFLIB); 4709 goto err_rx_desc; 4710 } 4711 free(vaddrs, M_IFLIB); 4712 free(paddrs, M_IFLIB); 4713 4714 /* RXQs */ 4715 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4716 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4717 for (i = 0; i < nrxqsets; i++) { 4718 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4719 4720 for (j = 0; j < nrxqs; j++, di++) { 4721 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4722 paddrs[i*nrxqs + j] = di->idi_paddr; 4723 } 4724 } 4725 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4726 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4727 iflib_tx_structures_free(ctx); 4728 free(vaddrs, M_IFLIB); 4729 free(paddrs, M_IFLIB); 4730 goto err_rx_desc; 4731 } 4732 free(vaddrs, M_IFLIB); 4733 free(paddrs, M_IFLIB); 4734 4735 return (0); 4736 4737 /* XXX handle allocation failure changes */ 4738 err_rx_desc: 4739 err_tx_desc: 4740 if (ctx->ifc_rxqs != NULL) 4741 free(ctx->ifc_rxqs, M_IFLIB); 4742 ctx->ifc_rxqs = NULL; 4743 if (ctx->ifc_txqs != NULL) 4744 free(ctx->ifc_txqs, M_IFLIB); 4745 ctx->ifc_txqs = NULL; 4746 rx_fail: 4747 if (brscp != NULL) 4748 free(brscp, M_IFLIB); 4749 if (rxq != NULL) 4750 free(rxq, M_IFLIB); 4751 if (txq != NULL) 4752 free(txq, M_IFLIB); 4753 fail: 4754 return (err); 4755 } 4756 4757 static int 4758 iflib_tx_structures_setup(if_ctx_t ctx) 4759 { 4760 iflib_txq_t txq = ctx->ifc_txqs; 4761 int i; 4762 4763 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4764 iflib_txq_setup(txq); 4765 4766 return (0); 4767 } 4768 4769 static void 4770 iflib_tx_structures_free(if_ctx_t ctx) 4771 { 4772 iflib_txq_t txq = ctx->ifc_txqs; 4773 int i, j; 4774 4775 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4776 iflib_txq_destroy(txq); 4777 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4778 iflib_dma_free(&txq->ift_ifdi[j]); 4779 } 4780 free(ctx->ifc_txqs, M_IFLIB); 4781 ctx->ifc_txqs = NULL; 4782 IFDI_QUEUES_FREE(ctx); 4783 } 4784 4785 /********************************************************************* 4786 * 4787 * Initialize all receive rings. 4788 * 4789 **********************************************************************/ 4790 static int 4791 iflib_rx_structures_setup(if_ctx_t ctx) 4792 { 4793 iflib_rxq_t rxq = ctx->ifc_rxqs; 4794 int q; 4795 #if defined(INET6) || defined(INET) 4796 int i, err; 4797 #endif 4798 4799 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 4800 #if defined(INET6) || defined(INET) 4801 tcp_lro_free(&rxq->ifr_lc); 4802 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 4803 TCP_LRO_ENTRIES, min(1024, 4804 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 4805 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 4806 goto fail; 4807 } 4808 rxq->ifr_lro_enabled = TRUE; 4809 #endif 4810 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 4811 } 4812 return (0); 4813 #if defined(INET6) || defined(INET) 4814 fail: 4815 /* 4816 * Free RX software descriptors allocated so far, we will only handle 4817 * the rings that completed, the failing case will have 4818 * cleaned up for itself. 'q' failed, so its the terminus. 4819 */ 4820 rxq = ctx->ifc_rxqs; 4821 for (i = 0; i < q; ++i, rxq++) { 4822 iflib_rx_sds_free(rxq); 4823 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 4824 } 4825 return (err); 4826 #endif 4827 } 4828 4829 /********************************************************************* 4830 * 4831 * Free all receive rings. 4832 * 4833 **********************************************************************/ 4834 static void 4835 iflib_rx_structures_free(if_ctx_t ctx) 4836 { 4837 iflib_rxq_t rxq = ctx->ifc_rxqs; 4838 4839 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 4840 iflib_rx_sds_free(rxq); 4841 } 4842 } 4843 4844 static int 4845 iflib_qset_structures_setup(if_ctx_t ctx) 4846 { 4847 int err; 4848 4849 if ((err = iflib_tx_structures_setup(ctx)) != 0) 4850 return (err); 4851 4852 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 4853 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 4854 iflib_tx_structures_free(ctx); 4855 iflib_rx_structures_free(ctx); 4856 } 4857 return (err); 4858 } 4859 4860 int 4861 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 4862 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 4863 { 4864 4865 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 4866 } 4867 4868 static int 4869 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid) 4870 { 4871 int i, cpuid, eqid, count; 4872 4873 CPU_COPY(&ctx->ifc_cpus, cpus); 4874 count = CPU_COUNT(&ctx->ifc_cpus); 4875 eqid = qid % count; 4876 /* clear up to the qid'th bit */ 4877 for (i = 0; i < eqid; i++) { 4878 cpuid = CPU_FFS(cpus); 4879 MPASS(cpuid != 0); 4880 CPU_CLR(cpuid-1, cpus); 4881 } 4882 cpuid = CPU_FFS(cpus); 4883 MPASS(cpuid != 0); 4884 return (cpuid-1); 4885 } 4886 4887 int 4888 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 4889 iflib_intr_type_t type, driver_filter_t *filter, 4890 void *filter_arg, int qid, char *name) 4891 { 4892 struct grouptask *gtask; 4893 struct taskqgroup *tqg; 4894 iflib_filter_info_t info; 4895 cpuset_t cpus; 4896 gtask_fn_t *fn; 4897 int tqrid, err, cpuid; 4898 driver_filter_t *intr_fast; 4899 void *q; 4900 4901 info = &ctx->ifc_filter_info; 4902 tqrid = rid; 4903 4904 switch (type) { 4905 /* XXX merge tx/rx for netmap? */ 4906 case IFLIB_INTR_TX: 4907 q = &ctx->ifc_txqs[qid]; 4908 info = &ctx->ifc_txqs[qid].ift_filter_info; 4909 gtask = &ctx->ifc_txqs[qid].ift_task; 4910 tqg = qgroup_if_io_tqg; 4911 fn = _task_fn_tx; 4912 intr_fast = iflib_fast_intr; 4913 GROUPTASK_INIT(gtask, 0, fn, q); 4914 break; 4915 case IFLIB_INTR_RX: 4916 q = &ctx->ifc_rxqs[qid]; 4917 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4918 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4919 tqg = qgroup_if_io_tqg; 4920 fn = _task_fn_rx; 4921 intr_fast = iflib_fast_intr; 4922 GROUPTASK_INIT(gtask, 0, fn, q); 4923 break; 4924 case IFLIB_INTR_RXTX: 4925 q = &ctx->ifc_rxqs[qid]; 4926 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4927 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4928 tqg = qgroup_if_io_tqg; 4929 fn = _task_fn_rx; 4930 intr_fast = iflib_fast_intr_rxtx; 4931 GROUPTASK_INIT(gtask, 0, fn, q); 4932 break; 4933 case IFLIB_INTR_ADMIN: 4934 q = ctx; 4935 tqrid = -1; 4936 info = &ctx->ifc_filter_info; 4937 gtask = &ctx->ifc_admin_task; 4938 tqg = qgroup_if_config_tqg; 4939 fn = _task_fn_admin; 4940 intr_fast = iflib_fast_intr_ctx; 4941 break; 4942 default: 4943 panic("unknown net intr type"); 4944 } 4945 4946 info->ifi_filter = filter; 4947 info->ifi_filter_arg = filter_arg; 4948 info->ifi_task = gtask; 4949 info->ifi_ctx = q; 4950 4951 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 4952 if (err != 0) { 4953 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 4954 return (err); 4955 } 4956 if (type == IFLIB_INTR_ADMIN) 4957 return (0); 4958 4959 if (tqrid != -1) { 4960 cpuid = find_nth(ctx, &cpus, qid); 4961 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, irq->ii_rid, name); 4962 } else { 4963 taskqgroup_attach(tqg, gtask, q, tqrid, name); 4964 } 4965 4966 return (0); 4967 } 4968 4969 void 4970 iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name) 4971 { 4972 struct grouptask *gtask; 4973 struct taskqgroup *tqg; 4974 gtask_fn_t *fn; 4975 void *q; 4976 4977 switch (type) { 4978 case IFLIB_INTR_TX: 4979 q = &ctx->ifc_txqs[qid]; 4980 gtask = &ctx->ifc_txqs[qid].ift_task; 4981 tqg = qgroup_if_io_tqg; 4982 fn = _task_fn_tx; 4983 break; 4984 case IFLIB_INTR_RX: 4985 q = &ctx->ifc_rxqs[qid]; 4986 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4987 tqg = qgroup_if_io_tqg; 4988 fn = _task_fn_rx; 4989 break; 4990 case IFLIB_INTR_IOV: 4991 q = ctx; 4992 gtask = &ctx->ifc_vflr_task; 4993 tqg = qgroup_if_config_tqg; 4994 rid = -1; 4995 fn = _task_fn_iov; 4996 break; 4997 default: 4998 panic("unknown net intr type"); 4999 } 5000 GROUPTASK_INIT(gtask, 0, fn, q); 5001 taskqgroup_attach(tqg, gtask, q, rid, name); 5002 } 5003 5004 void 5005 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5006 { 5007 if (irq->ii_tag) 5008 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5009 5010 if (irq->ii_res) 5011 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5012 } 5013 5014 static int 5015 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5016 { 5017 iflib_txq_t txq = ctx->ifc_txqs; 5018 iflib_rxq_t rxq = ctx->ifc_rxqs; 5019 if_irq_t irq = &ctx->ifc_legacy_irq; 5020 iflib_filter_info_t info; 5021 struct grouptask *gtask; 5022 struct taskqgroup *tqg; 5023 gtask_fn_t *fn; 5024 int tqrid; 5025 void *q; 5026 int err; 5027 5028 q = &ctx->ifc_rxqs[0]; 5029 info = &rxq[0].ifr_filter_info; 5030 gtask = &rxq[0].ifr_task; 5031 tqg = qgroup_if_io_tqg; 5032 tqrid = irq->ii_rid = *rid; 5033 fn = _task_fn_rx; 5034 5035 ctx->ifc_flags |= IFC_LEGACY; 5036 info->ifi_filter = filter; 5037 info->ifi_filter_arg = filter_arg; 5038 info->ifi_task = gtask; 5039 info->ifi_ctx = ctx; 5040 5041 /* We allocate a single interrupt resource */ 5042 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5043 return (err); 5044 GROUPTASK_INIT(gtask, 0, fn, q); 5045 taskqgroup_attach(tqg, gtask, q, tqrid, name); 5046 5047 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5048 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx"); 5049 return (0); 5050 } 5051 5052 void 5053 iflib_led_create(if_ctx_t ctx) 5054 { 5055 5056 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5057 device_get_nameunit(ctx->ifc_dev)); 5058 } 5059 5060 void 5061 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5062 { 5063 5064 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5065 } 5066 5067 void 5068 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5069 { 5070 5071 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5072 } 5073 5074 void 5075 iflib_admin_intr_deferred(if_ctx_t ctx) 5076 { 5077 #ifdef INVARIANTS 5078 struct grouptask *gtask; 5079 5080 gtask = &ctx->ifc_admin_task; 5081 MPASS(gtask->gt_taskqueue != NULL); 5082 #endif 5083 5084 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5085 } 5086 5087 void 5088 iflib_iov_intr_deferred(if_ctx_t ctx) 5089 { 5090 5091 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5092 } 5093 5094 void 5095 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5096 { 5097 5098 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5099 } 5100 5101 void 5102 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5103 char *name) 5104 { 5105 5106 GROUPTASK_INIT(gtask, 0, fn, ctx); 5107 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5108 } 5109 5110 void 5111 iflib_config_gtask_deinit(struct grouptask *gtask) 5112 { 5113 5114 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5115 } 5116 5117 void 5118 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5119 { 5120 if_t ifp = ctx->ifc_ifp; 5121 iflib_txq_t txq = ctx->ifc_txqs; 5122 5123 if_setbaudrate(ifp, baudrate); 5124 if (baudrate >= IF_Gbps(10)) 5125 ctx->ifc_flags |= IFC_PREFETCH; 5126 5127 /* If link down, disable watchdog */ 5128 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5129 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5130 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5131 } 5132 ctx->ifc_link_state = link_state; 5133 if_link_state_change(ifp, link_state); 5134 } 5135 5136 static int 5137 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5138 { 5139 int credits; 5140 #ifdef INVARIANTS 5141 int credits_pre = txq->ift_cidx_processed; 5142 #endif 5143 5144 if (ctx->isc_txd_credits_update == NULL) 5145 return (0); 5146 5147 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5148 return (0); 5149 5150 txq->ift_processed += credits; 5151 txq->ift_cidx_processed += credits; 5152 5153 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5154 if (txq->ift_cidx_processed >= txq->ift_size) 5155 txq->ift_cidx_processed -= txq->ift_size; 5156 return (credits); 5157 } 5158 5159 static int 5160 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5161 { 5162 5163 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5164 budget)); 5165 } 5166 5167 void 5168 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5169 const char *description, if_int_delay_info_t info, 5170 int offset, int value) 5171 { 5172 info->iidi_ctx = ctx; 5173 info->iidi_offset = offset; 5174 info->iidi_value = value; 5175 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5176 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5177 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5178 info, 0, iflib_sysctl_int_delay, "I", description); 5179 } 5180 5181 struct mtx * 5182 iflib_ctx_lock_get(if_ctx_t ctx) 5183 { 5184 5185 return (&ctx->ifc_mtx); 5186 } 5187 5188 static int 5189 iflib_msix_init(if_ctx_t ctx) 5190 { 5191 device_t dev = ctx->ifc_dev; 5192 if_shared_ctx_t sctx = ctx->ifc_sctx; 5193 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5194 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5195 int iflib_num_tx_queues, iflib_num_rx_queues; 5196 int err, admincnt, bar; 5197 5198 iflib_num_tx_queues = scctx->isc_ntxqsets; 5199 iflib_num_rx_queues = scctx->isc_nrxqsets; 5200 5201 device_printf(dev, "msix_init qsets capped at %d\n", iflib_num_tx_queues); 5202 5203 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5204 admincnt = sctx->isc_admin_intrcnt; 5205 /* Override by tuneable */ 5206 if (scctx->isc_disable_msix) 5207 goto msi; 5208 5209 /* 5210 ** When used in a virtualized environment 5211 ** PCI BUSMASTER capability may not be set 5212 ** so explicity set it here and rewrite 5213 ** the ENABLE in the MSIX control register 5214 ** at this point to cause the host to 5215 ** successfully initialize us. 5216 */ 5217 { 5218 int msix_ctrl, rid; 5219 5220 pci_enable_busmaster(dev); 5221 rid = 0; 5222 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5223 rid += PCIR_MSIX_CTRL; 5224 msix_ctrl = pci_read_config(dev, rid, 2); 5225 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5226 pci_write_config(dev, rid, msix_ctrl, 2); 5227 } else { 5228 device_printf(dev, "PCIY_MSIX capability not found; " 5229 "or rid %d == 0.\n", rid); 5230 goto msi; 5231 } 5232 } 5233 5234 /* 5235 * bar == -1 => "trust me I know what I'm doing" 5236 * Some drivers are for hardware that is so shoddily 5237 * documented that no one knows which bars are which 5238 * so the developer has to map all bars. This hack 5239 * allows shoddy garbage to use msix in this framework. 5240 */ 5241 if (bar != -1) { 5242 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5243 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5244 if (ctx->ifc_msix_mem == NULL) { 5245 /* May not be enabled */ 5246 device_printf(dev, "Unable to map MSIX table \n"); 5247 goto msi; 5248 } 5249 } 5250 /* First try MSI/X */ 5251 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5252 device_printf(dev, "System has MSIX disabled \n"); 5253 bus_release_resource(dev, SYS_RES_MEMORY, 5254 bar, ctx->ifc_msix_mem); 5255 ctx->ifc_msix_mem = NULL; 5256 goto msi; 5257 } 5258 #if IFLIB_DEBUG 5259 /* use only 1 qset in debug mode */ 5260 queuemsgs = min(msgs - admincnt, 1); 5261 #else 5262 queuemsgs = msgs - admincnt; 5263 #endif 5264 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) { 5265 #ifdef RSS 5266 queues = imin(queuemsgs, rss_getnumbuckets()); 5267 #else 5268 queues = queuemsgs; 5269 #endif 5270 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5271 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5272 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5273 } else { 5274 device_printf(dev, "Unable to fetch CPU list\n"); 5275 /* Figure out a reasonable auto config value */ 5276 queues = min(queuemsgs, mp_ncpus); 5277 } 5278 #ifdef RSS 5279 /* If we're doing RSS, clamp at the number of RSS buckets */ 5280 if (queues > rss_getnumbuckets()) 5281 queues = rss_getnumbuckets(); 5282 #endif 5283 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5284 rx_queues = iflib_num_rx_queues; 5285 else 5286 rx_queues = queues; 5287 /* 5288 * We want this to be all logical CPUs by default 5289 */ 5290 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5291 tx_queues = iflib_num_tx_queues; 5292 else 5293 tx_queues = mp_ncpus; 5294 5295 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5296 #ifdef INVARIANTS 5297 if (tx_queues != rx_queues) 5298 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5299 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5300 #endif 5301 tx_queues = min(rx_queues, tx_queues); 5302 rx_queues = min(rx_queues, tx_queues); 5303 } 5304 5305 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5306 5307 vectors = rx_queues + admincnt; 5308 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5309 device_printf(dev, 5310 "Using MSIX interrupts with %d vectors\n", vectors); 5311 scctx->isc_vectors = vectors; 5312 scctx->isc_nrxqsets = rx_queues; 5313 scctx->isc_ntxqsets = tx_queues; 5314 scctx->isc_intr = IFLIB_INTR_MSIX; 5315 5316 return (vectors); 5317 } else { 5318 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5319 } 5320 msi: 5321 vectors = pci_msi_count(dev); 5322 scctx->isc_nrxqsets = 1; 5323 scctx->isc_ntxqsets = 1; 5324 scctx->isc_vectors = vectors; 5325 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5326 device_printf(dev,"Using an MSI interrupt\n"); 5327 scctx->isc_intr = IFLIB_INTR_MSI; 5328 } else { 5329 device_printf(dev,"Using a Legacy interrupt\n"); 5330 scctx->isc_intr = IFLIB_INTR_LEGACY; 5331 } 5332 5333 return (vectors); 5334 } 5335 5336 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5337 5338 static int 5339 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5340 { 5341 int rc; 5342 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5343 struct sbuf *sb; 5344 char *ring_state = "UNKNOWN"; 5345 5346 /* XXX needed ? */ 5347 rc = sysctl_wire_old_buffer(req, 0); 5348 MPASS(rc == 0); 5349 if (rc != 0) 5350 return (rc); 5351 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5352 MPASS(sb != NULL); 5353 if (sb == NULL) 5354 return (ENOMEM); 5355 if (state[3] <= 3) 5356 ring_state = ring_states[state[3]]; 5357 5358 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5359 state[0], state[1], state[2], ring_state); 5360 rc = sbuf_finish(sb); 5361 sbuf_delete(sb); 5362 return(rc); 5363 } 5364 5365 enum iflib_ndesc_handler { 5366 IFLIB_NTXD_HANDLER, 5367 IFLIB_NRXD_HANDLER, 5368 }; 5369 5370 static int 5371 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5372 { 5373 if_ctx_t ctx = (void *)arg1; 5374 enum iflib_ndesc_handler type = arg2; 5375 char buf[256] = {0}; 5376 qidx_t *ndesc; 5377 char *p, *next; 5378 int nqs, rc, i; 5379 5380 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5381 5382 nqs = 8; 5383 switch(type) { 5384 case IFLIB_NTXD_HANDLER: 5385 ndesc = ctx->ifc_sysctl_ntxds; 5386 if (ctx->ifc_sctx) 5387 nqs = ctx->ifc_sctx->isc_ntxqs; 5388 break; 5389 case IFLIB_NRXD_HANDLER: 5390 ndesc = ctx->ifc_sysctl_nrxds; 5391 if (ctx->ifc_sctx) 5392 nqs = ctx->ifc_sctx->isc_nrxqs; 5393 break; 5394 } 5395 if (nqs == 0) 5396 nqs = 8; 5397 5398 for (i=0; i<8; i++) { 5399 if (i >= nqs) 5400 break; 5401 if (i) 5402 strcat(buf, ","); 5403 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5404 } 5405 5406 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5407 if (rc || req->newptr == NULL) 5408 return rc; 5409 5410 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5411 i++, p = strsep(&next, " ,")) { 5412 ndesc[i] = strtoul(p, NULL, 10); 5413 } 5414 5415 return(rc); 5416 } 5417 5418 #define NAME_BUFLEN 32 5419 static void 5420 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5421 { 5422 device_t dev = iflib_get_dev(ctx); 5423 struct sysctl_oid_list *child, *oid_list; 5424 struct sysctl_ctx_list *ctx_list; 5425 struct sysctl_oid *node; 5426 5427 ctx_list = device_get_sysctl_ctx(dev); 5428 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5429 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5430 CTLFLAG_RD, NULL, "IFLIB fields"); 5431 oid_list = SYSCTL_CHILDREN(node); 5432 5433 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5434 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5435 "driver version"); 5436 5437 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5438 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5439 "# of txqs to use, 0 => use default #"); 5440 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5441 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5442 "# of rxqs to use, 0 => use default #"); 5443 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5444 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5445 "permit #txq != #rxq"); 5446 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5447 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5448 "disable MSIX (default 0)"); 5449 5450 /* XXX change for per-queue sizes */ 5451 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5452 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5453 mp_ndesc_handler, "A", 5454 "list of # of tx descriptors to use, 0 = use default #"); 5455 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5456 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5457 mp_ndesc_handler, "A", 5458 "list of # of rx descriptors to use, 0 = use default #"); 5459 } 5460 5461 static void 5462 iflib_add_device_sysctl_post(if_ctx_t ctx) 5463 { 5464 if_shared_ctx_t sctx = ctx->ifc_sctx; 5465 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5466 device_t dev = iflib_get_dev(ctx); 5467 struct sysctl_oid_list *child; 5468 struct sysctl_ctx_list *ctx_list; 5469 iflib_fl_t fl; 5470 iflib_txq_t txq; 5471 iflib_rxq_t rxq; 5472 int i, j; 5473 char namebuf[NAME_BUFLEN]; 5474 char *qfmt; 5475 struct sysctl_oid *queue_node, *fl_node, *node; 5476 struct sysctl_oid_list *queue_list, *fl_list; 5477 ctx_list = device_get_sysctl_ctx(dev); 5478 5479 node = ctx->ifc_sysctl_node; 5480 child = SYSCTL_CHILDREN(node); 5481 5482 if (scctx->isc_ntxqsets > 100) 5483 qfmt = "txq%03d"; 5484 else if (scctx->isc_ntxqsets > 10) 5485 qfmt = "txq%02d"; 5486 else 5487 qfmt = "txq%d"; 5488 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5489 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5490 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5491 CTLFLAG_RD, NULL, "Queue Name"); 5492 queue_list = SYSCTL_CHILDREN(queue_node); 5493 #if MEMORY_LOGGING 5494 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5495 CTLFLAG_RD, 5496 &txq->ift_dequeued, "total mbufs freed"); 5497 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5498 CTLFLAG_RD, 5499 &txq->ift_enqueued, "total mbufs enqueued"); 5500 #endif 5501 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5502 CTLFLAG_RD, 5503 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5504 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5505 CTLFLAG_RD, 5506 &txq->ift_pullups, "# of times m_pullup was called"); 5507 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5508 CTLFLAG_RD, 5509 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5510 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5511 CTLFLAG_RD, 5512 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5513 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5514 CTLFLAG_RD, 5515 &txq->ift_map_failed, "# of times dma map failed"); 5516 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5517 CTLFLAG_RD, 5518 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5519 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5520 CTLFLAG_RD, 5521 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5522 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5523 CTLFLAG_RD, 5524 &txq->ift_pidx, 1, "Producer Index"); 5525 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5526 CTLFLAG_RD, 5527 &txq->ift_cidx, 1, "Consumer Index"); 5528 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5529 CTLFLAG_RD, 5530 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5531 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5532 CTLFLAG_RD, 5533 &txq->ift_in_use, 1, "descriptors in use"); 5534 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5535 CTLFLAG_RD, 5536 &txq->ift_processed, "descriptors procesed for clean"); 5537 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5538 CTLFLAG_RD, 5539 &txq->ift_cleaned, "total cleaned"); 5540 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5541 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5542 0, mp_ring_state_handler, "A", "soft ring state"); 5543 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5544 CTLFLAG_RD, &txq->ift_br->enqueues, 5545 "# of enqueues to the mp_ring for this queue"); 5546 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5547 CTLFLAG_RD, &txq->ift_br->drops, 5548 "# of drops in the mp_ring for this queue"); 5549 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5550 CTLFLAG_RD, &txq->ift_br->starts, 5551 "# of normal consumer starts in the mp_ring for this queue"); 5552 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5553 CTLFLAG_RD, &txq->ift_br->stalls, 5554 "# of consumer stalls in the mp_ring for this queue"); 5555 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5556 CTLFLAG_RD, &txq->ift_br->restarts, 5557 "# of consumer restarts in the mp_ring for this queue"); 5558 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5559 CTLFLAG_RD, &txq->ift_br->abdications, 5560 "# of consumer abdications in the mp_ring for this queue"); 5561 } 5562 5563 if (scctx->isc_nrxqsets > 100) 5564 qfmt = "rxq%03d"; 5565 else if (scctx->isc_nrxqsets > 10) 5566 qfmt = "rxq%02d"; 5567 else 5568 qfmt = "rxq%d"; 5569 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5570 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5571 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5572 CTLFLAG_RD, NULL, "Queue Name"); 5573 queue_list = SYSCTL_CHILDREN(queue_node); 5574 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5575 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5576 CTLFLAG_RD, 5577 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5578 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5579 CTLFLAG_RD, 5580 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5581 } 5582 5583 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5584 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5585 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5586 CTLFLAG_RD, NULL, "freelist Name"); 5587 fl_list = SYSCTL_CHILDREN(fl_node); 5588 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5589 CTLFLAG_RD, 5590 &fl->ifl_pidx, 1, "Producer Index"); 5591 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5592 CTLFLAG_RD, 5593 &fl->ifl_cidx, 1, "Consumer Index"); 5594 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5595 CTLFLAG_RD, 5596 &fl->ifl_credits, 1, "credits available"); 5597 #if MEMORY_LOGGING 5598 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5599 CTLFLAG_RD, 5600 &fl->ifl_m_enqueued, "mbufs allocated"); 5601 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5602 CTLFLAG_RD, 5603 &fl->ifl_m_dequeued, "mbufs freed"); 5604 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5605 CTLFLAG_RD, 5606 &fl->ifl_cl_enqueued, "clusters allocated"); 5607 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5608 CTLFLAG_RD, 5609 &fl->ifl_cl_dequeued, "clusters freed"); 5610 #endif 5611 5612 } 5613 } 5614 5615 } 5616 5617 #ifndef __NO_STRICT_ALIGNMENT 5618 static struct mbuf * 5619 iflib_fixup_rx(struct mbuf *m) 5620 { 5621 struct mbuf *n; 5622 5623 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5624 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 5625 m->m_data += ETHER_HDR_LEN; 5626 n = m; 5627 } else { 5628 MGETHDR(n, M_NOWAIT, MT_DATA); 5629 if (n == NULL) { 5630 m_freem(m); 5631 return (NULL); 5632 } 5633 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 5634 m->m_data += ETHER_HDR_LEN; 5635 m->m_len -= ETHER_HDR_LEN; 5636 n->m_len = ETHER_HDR_LEN; 5637 M_MOVE_PKTHDR(n, m); 5638 n->m_next = m; 5639 } 5640 return (n); 5641 } 5642 #endif 5643