1 /*- 2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/sockio.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/module.h> 45 #include <sys/kobj.h> 46 #include <sys/rman.h> 47 #include <sys/sbuf.h> 48 #include <sys/smp.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 56 #include <net/if.h> 57 #include <net/if_var.h> 58 #include <net/if_types.h> 59 #include <net/if_media.h> 60 #include <net/bpf.h> 61 #include <net/ethernet.h> 62 #include <net/mp_ring.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/ip_var.h> 74 #include <netinet6/ip6_var.h> 75 76 #include <machine/bus.h> 77 #include <machine/in_cksum.h> 78 79 #include <vm/vm.h> 80 #include <vm/pmap.h> 81 82 #include <dev/led/led.h> 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pci_private.h> 86 87 #include <net/iflib.h> 88 89 #include "ifdi_if.h" 90 91 #if defined(__i386__) || defined(__amd64__) 92 #include <sys/memdesc.h> 93 #include <machine/bus.h> 94 #include <machine/md_var.h> 95 #include <machine/specialreg.h> 96 #include <x86/include/busdma_impl.h> 97 #include <x86/iommu/busdma_dmar.h> 98 #endif 99 100 #include <sys/bitstring.h> 101 /* 102 * enable accounting of every mbuf as it comes in to and goes out of 103 * iflib's software descriptor references 104 */ 105 #define MEMORY_LOGGING 0 106 /* 107 * Enable mbuf vectors for compressing long mbuf chains 108 */ 109 110 /* 111 * NB: 112 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 113 * we prefetch needs to be determined by the time spent in m_free vis a vis 114 * the cost of a prefetch. This will of course vary based on the workload: 115 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 116 * is quite expensive, thus suggesting very little prefetch. 117 * - small packet forwarding which is just returning a single mbuf to 118 * UMA will typically be very fast vis a vis the cost of a memory 119 * access. 120 */ 121 122 123 /* 124 * File organization: 125 * - private structures 126 * - iflib private utility functions 127 * - ifnet functions 128 * - vlan registry and other exported functions 129 * - iflib public core functions 130 * 131 * 132 */ 133 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct mtx ifc_mtx; 167 168 uint16_t ifc_nhwtxqs; 169 uint16_t ifc_nhwrxqs; 170 171 iflib_txq_t ifc_txqs; 172 iflib_rxq_t ifc_rxqs; 173 uint32_t ifc_if_flags; 174 uint32_t ifc_flags; 175 uint32_t ifc_max_fl_buf_size; 176 int ifc_in_detach; 177 178 int ifc_link_state; 179 int ifc_link_irq; 180 int ifc_watchdog_events; 181 struct cdev *ifc_led_dev; 182 struct resource *ifc_msix_mem; 183 184 struct if_irq ifc_legacy_irq; 185 struct grouptask ifc_admin_task; 186 struct grouptask ifc_vflr_task; 187 struct iflib_filter_info ifc_filter_info; 188 struct ifmedia ifc_media; 189 190 struct sysctl_oid *ifc_sysctl_node; 191 uint16_t ifc_sysctl_ntxqs; 192 uint16_t ifc_sysctl_nrxqs; 193 uint16_t ifc_sysctl_qs_eq_override; 194 uint16_t ifc_sysctl_rx_budget; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 uint8_t ifc_mac[ETHER_ADDR_LEN]; 212 char ifc_mtx_name[16]; 213 }; 214 215 216 void * 217 iflib_get_softc(if_ctx_t ctx) 218 { 219 220 return (ctx->ifc_softc); 221 } 222 223 device_t 224 iflib_get_dev(if_ctx_t ctx) 225 { 226 227 return (ctx->ifc_dev); 228 } 229 230 if_t 231 iflib_get_ifp(if_ctx_t ctx) 232 { 233 234 return (ctx->ifc_ifp); 235 } 236 237 struct ifmedia * 238 iflib_get_media(if_ctx_t ctx) 239 { 240 241 return (&ctx->ifc_media); 242 } 243 244 void 245 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 246 { 247 248 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 249 } 250 251 if_softc_ctx_t 252 iflib_get_softc_ctx(if_ctx_t ctx) 253 { 254 255 return (&ctx->ifc_softc_ctx); 256 } 257 258 if_shared_ctx_t 259 iflib_get_sctx(if_ctx_t ctx) 260 { 261 262 return (ctx->ifc_sctx); 263 } 264 265 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 266 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 267 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 268 269 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 270 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 271 272 #define RX_SW_DESC_MAP_CREATED (1 << 0) 273 #define TX_SW_DESC_MAP_CREATED (1 << 1) 274 #define RX_SW_DESC_INUSE (1 << 3) 275 #define TX_SW_DESC_MAPPED (1 << 4) 276 277 #define M_TOOBIG M_PROTO1 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 uint8_t *ifsd_flags; 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 struct mbuf **ifsd_m; /* pkthdr mbufs */ 289 uint8_t *ifsd_flags; 290 } if_txsd_vec_t; 291 292 293 /* magic number that should be high enough for any hardware */ 294 #define IFLIB_MAX_TX_SEGS 128 295 /* bnxt supports 64 with hardware LRO enabled */ 296 #define IFLIB_MAX_RX_SEGS 64 297 #define IFLIB_RX_COPY_THRESH 128 298 #define IFLIB_MAX_RX_REFRESH 32 299 /* The minimum descriptors per second before we start coalescing */ 300 #define IFLIB_MIN_DESC_SEC 16384 301 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 302 #define IFLIB_QUEUE_IDLE 0 303 #define IFLIB_QUEUE_HUNG 1 304 #define IFLIB_QUEUE_WORKING 2 305 /* maximum number of txqs that can share an rx interrupt */ 306 #define IFLIB_MAX_TX_SHARED_INTR 4 307 308 /* this should really scale with ring size - this is a fairly arbitrary value */ 309 #define TX_BATCH_SIZE 32 310 311 #define IFLIB_RESTART_BUDGET 8 312 313 #define IFC_LEGACY 0x001 314 #define IFC_QFLUSH 0x002 315 #define IFC_MULTISEG 0x004 316 #define IFC_DMAR 0x008 317 #define IFC_SC_ALLOCATED 0x010 318 #define IFC_INIT_DONE 0x020 319 #define IFC_PREFETCH 0x040 320 #define IFC_DO_RESET 0x080 321 #define IFC_CHECK_HUNG 0x100 322 323 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 324 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 325 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 326 struct iflib_txq { 327 qidx_t ift_in_use; 328 qidx_t ift_cidx; 329 qidx_t ift_cidx_processed; 330 qidx_t ift_pidx; 331 uint8_t ift_gen; 332 uint8_t ift_br_offset; 333 uint16_t ift_npending; 334 uint16_t ift_db_pending; 335 uint16_t ift_rs_pending; 336 /* implicit pad */ 337 uint8_t ift_txd_size[8]; 338 uint64_t ift_processed; 339 uint64_t ift_cleaned; 340 uint64_t ift_cleaned_prev; 341 #if MEMORY_LOGGING 342 uint64_t ift_enqueued; 343 uint64_t ift_dequeued; 344 #endif 345 uint64_t ift_no_tx_dma_setup; 346 uint64_t ift_no_desc_avail; 347 uint64_t ift_mbuf_defrag_failed; 348 uint64_t ift_mbuf_defrag; 349 uint64_t ift_map_failed; 350 uint64_t ift_txd_encap_efbig; 351 uint64_t ift_pullups; 352 353 struct mtx ift_mtx; 354 struct mtx ift_db_mtx; 355 356 /* constant values */ 357 if_ctx_t ift_ctx; 358 struct ifmp_ring *ift_br; 359 struct grouptask ift_task; 360 qidx_t ift_size; 361 uint16_t ift_id; 362 struct callout ift_timer; 363 364 if_txsd_vec_t ift_sds; 365 uint8_t ift_qstatus; 366 uint8_t ift_closed; 367 uint8_t ift_update_freq; 368 struct iflib_filter_info ift_filter_info; 369 bus_dma_tag_t ift_desc_tag; 370 bus_dma_tag_t ift_tso_desc_tag; 371 iflib_dma_info_t ift_ifdi; 372 #define MTX_NAME_LEN 16 373 char ift_mtx_name[MTX_NAME_LEN]; 374 char ift_db_mtx_name[MTX_NAME_LEN]; 375 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 376 #ifdef IFLIB_DIAGNOSTICS 377 uint64_t ift_cpu_exec_count[256]; 378 #endif 379 } __aligned(CACHE_LINE_SIZE); 380 381 struct iflib_fl { 382 qidx_t ifl_cidx; 383 qidx_t ifl_pidx; 384 qidx_t ifl_credits; 385 uint8_t ifl_gen; 386 uint8_t ifl_rxd_size; 387 #if MEMORY_LOGGING 388 uint64_t ifl_m_enqueued; 389 uint64_t ifl_m_dequeued; 390 uint64_t ifl_cl_enqueued; 391 uint64_t ifl_cl_dequeued; 392 #endif 393 /* implicit pad */ 394 395 bitstr_t *ifl_rx_bitmap; 396 qidx_t ifl_fragidx; 397 /* constant */ 398 qidx_t ifl_size; 399 uint16_t ifl_buf_size; 400 uint16_t ifl_cltype; 401 uma_zone_t ifl_zone; 402 iflib_rxsd_array_t ifl_sds; 403 iflib_rxq_t ifl_rxq; 404 uint8_t ifl_id; 405 bus_dma_tag_t ifl_desc_tag; 406 iflib_dma_info_t ifl_ifdi; 407 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 408 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 409 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 410 } __aligned(CACHE_LINE_SIZE); 411 412 static inline qidx_t 413 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 414 { 415 qidx_t used; 416 417 if (pidx > cidx) 418 used = pidx - cidx; 419 else if (pidx < cidx) 420 used = size - cidx + pidx; 421 else if (gen == 0 && pidx == cidx) 422 used = 0; 423 else if (gen == 1 && pidx == cidx) 424 used = size; 425 else 426 panic("bad state"); 427 428 return (used); 429 } 430 431 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 432 433 #define IDXDIFF(head, tail, wrap) \ 434 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 435 436 struct iflib_rxq { 437 /* If there is a separate completion queue - 438 * these are the cq cidx and pidx. Otherwise 439 * these are unused. 440 */ 441 qidx_t ifr_size; 442 qidx_t ifr_cq_cidx; 443 qidx_t ifr_cq_pidx; 444 uint8_t ifr_cq_gen; 445 uint8_t ifr_fl_offset; 446 447 if_ctx_t ifr_ctx; 448 iflib_fl_t ifr_fl; 449 uint64_t ifr_rx_irq; 450 uint16_t ifr_id; 451 uint8_t ifr_lro_enabled; 452 uint8_t ifr_nfl; 453 uint8_t ifr_ntxqirq; 454 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 455 struct lro_ctrl ifr_lc; 456 struct grouptask ifr_task; 457 struct iflib_filter_info ifr_filter_info; 458 iflib_dma_info_t ifr_ifdi; 459 460 /* dynamically allocate if any drivers need a value substantially larger than this */ 461 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 462 #ifdef IFLIB_DIAGNOSTICS 463 uint64_t ifr_cpu_exec_count[256]; 464 #endif 465 } __aligned(CACHE_LINE_SIZE); 466 467 typedef struct if_rxsd { 468 caddr_t *ifsd_cl; 469 struct mbuf **ifsd_m; 470 iflib_fl_t ifsd_fl; 471 qidx_t ifsd_cidx; 472 } *if_rxsd_t; 473 474 /* multiple of word size */ 475 #ifdef __LP64__ 476 #define PKT_INFO_SIZE 6 477 #define RXD_INFO_SIZE 5 478 #define PKT_TYPE uint64_t 479 #else 480 #define PKT_INFO_SIZE 11 481 #define RXD_INFO_SIZE 8 482 #define PKT_TYPE uint32_t 483 #endif 484 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 485 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 486 487 typedef struct if_pkt_info_pad { 488 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 489 } *if_pkt_info_pad_t; 490 typedef struct if_rxd_info_pad { 491 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 492 } *if_rxd_info_pad_t; 493 494 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 495 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 496 497 498 static inline void 499 pkt_info_zero(if_pkt_info_t pi) 500 { 501 if_pkt_info_pad_t pi_pad; 502 503 pi_pad = (if_pkt_info_pad_t)pi; 504 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 505 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 506 #ifndef __LP64__ 507 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 508 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 509 #endif 510 } 511 512 static inline void 513 rxd_info_zero(if_rxd_info_t ri) 514 { 515 if_rxd_info_pad_t ri_pad; 516 int i; 517 518 ri_pad = (if_rxd_info_pad_t)ri; 519 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 520 ri_pad->rxd_val[i] = 0; 521 ri_pad->rxd_val[i+1] = 0; 522 ri_pad->rxd_val[i+2] = 0; 523 ri_pad->rxd_val[i+3] = 0; 524 } 525 #ifdef __LP64__ 526 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 527 #endif 528 } 529 530 /* 531 * Only allow a single packet to take up most 1/nth of the tx ring 532 */ 533 #define MAX_SINGLE_PACKET_FRACTION 12 534 #define IF_BAD_DMA (bus_addr_t)-1 535 536 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 537 538 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) 539 540 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) 541 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) 542 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) 543 544 545 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 546 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 547 548 549 /* Our boot-time initialization hook */ 550 static int iflib_module_event_handler(module_t, int, void *); 551 552 static moduledata_t iflib_moduledata = { 553 "iflib", 554 iflib_module_event_handler, 555 NULL 556 }; 557 558 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 559 MODULE_VERSION(iflib, 1); 560 561 MODULE_DEPEND(iflib, pci, 1, 1, 1); 562 MODULE_DEPEND(iflib, ether, 1, 1, 1); 563 564 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 565 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 566 567 #ifndef IFLIB_DEBUG_COUNTERS 568 #ifdef INVARIANTS 569 #define IFLIB_DEBUG_COUNTERS 1 570 #else 571 #define IFLIB_DEBUG_COUNTERS 0 572 #endif /* !INVARIANTS */ 573 #endif 574 575 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 576 "iflib driver parameters"); 577 578 /* 579 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 580 */ 581 static int iflib_min_tx_latency = 0; 582 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 583 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 584 static int iflib_no_tx_batch = 0; 585 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 586 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 587 588 589 #if IFLIB_DEBUG_COUNTERS 590 591 static int iflib_tx_seen; 592 static int iflib_tx_sent; 593 static int iflib_tx_encap; 594 static int iflib_rx_allocs; 595 static int iflib_fl_refills; 596 static int iflib_fl_refills_large; 597 static int iflib_tx_frees; 598 599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 600 &iflib_tx_seen, 0, "# tx mbufs seen"); 601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 602 &iflib_tx_sent, 0, "# tx mbufs sent"); 603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 604 &iflib_tx_encap, 0, "# tx mbufs encapped"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 606 &iflib_tx_frees, 0, "# tx frees"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 608 &iflib_rx_allocs, 0, "# rx allocations"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 610 &iflib_fl_refills, 0, "# refills"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 612 &iflib_fl_refills_large, 0, "# large refills"); 613 614 615 static int iflib_txq_drain_flushing; 616 static int iflib_txq_drain_oactive; 617 static int iflib_txq_drain_notready; 618 static int iflib_txq_drain_encapfail; 619 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 621 &iflib_txq_drain_flushing, 0, "# drain flushes"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 623 &iflib_txq_drain_oactive, 0, "# drain oactives"); 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 625 &iflib_txq_drain_notready, 0, "# drain notready"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 627 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 628 629 630 static int iflib_encap_load_mbuf_fail; 631 static int iflib_encap_pad_mbuf_fail; 632 static int iflib_encap_txq_avail_fail; 633 static int iflib_encap_txd_encap_fail; 634 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 636 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 638 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 639 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 640 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 641 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 642 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 643 644 static int iflib_task_fn_rxs; 645 static int iflib_rx_intr_enables; 646 static int iflib_fast_intrs; 647 static int iflib_intr_link; 648 static int iflib_intr_msix; 649 static int iflib_rx_unavail; 650 static int iflib_rx_ctx_inactive; 651 static int iflib_rx_zero_len; 652 static int iflib_rx_if_input; 653 static int iflib_rx_mbuf_null; 654 static int iflib_rxd_flush; 655 656 static int iflib_verbose_debug; 657 658 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 659 &iflib_intr_link, 0, "# intr link calls"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 661 &iflib_intr_msix, 0, "# intr msix calls"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 663 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 665 &iflib_rx_intr_enables, 0, "# rx intr enables"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 667 &iflib_fast_intrs, 0, "# fast_intr calls"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 669 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 671 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 673 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 675 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 677 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 678 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 679 &iflib_rxd_flush, 0, "# times rxd_flush called"); 680 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 681 &iflib_verbose_debug, 0, "enable verbose debugging"); 682 683 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 684 static void 685 iflib_debug_reset(void) 686 { 687 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 688 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 689 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 690 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 691 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 692 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 693 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 694 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 695 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 696 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 697 } 698 699 #else 700 #define DBG_COUNTER_INC(name) 701 static void iflib_debug_reset(void) {} 702 #endif 703 704 705 706 #define IFLIB_DEBUG 0 707 708 static void iflib_tx_structures_free(if_ctx_t ctx); 709 static void iflib_rx_structures_free(if_ctx_t ctx); 710 static int iflib_queues_alloc(if_ctx_t ctx); 711 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 712 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 713 static int iflib_qset_structures_setup(if_ctx_t ctx); 714 static int iflib_msix_init(if_ctx_t ctx); 715 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 716 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 717 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 718 static int iflib_register(if_ctx_t); 719 static void iflib_init_locked(if_ctx_t ctx); 720 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 721 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 722 static void iflib_ifmp_purge(iflib_txq_t txq); 723 static void _iflib_pre_assert(if_softc_ctx_t scctx); 724 static void iflib_stop(if_ctx_t ctx); 725 static void iflib_if_init_locked(if_ctx_t ctx); 726 #ifndef __NO_STRICT_ALIGNMENT 727 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 728 #endif 729 730 #ifdef DEV_NETMAP 731 #include <sys/selinfo.h> 732 #include <net/netmap.h> 733 #include <dev/netmap/netmap_kern.h> 734 735 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 736 737 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 738 739 /* 740 * device-specific sysctl variables: 741 * 742 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 743 * During regular operations the CRC is stripped, but on some 744 * hardware reception of frames not multiple of 64 is slower, 745 * so using crcstrip=0 helps in benchmarks. 746 * 747 * iflib_rx_miss, iflib_rx_miss_bufs: 748 * count packets that might be missed due to lost interrupts. 749 */ 750 SYSCTL_DECL(_dev_netmap); 751 /* 752 * The xl driver by default strips CRCs and we do not override it. 753 */ 754 755 int iflib_crcstrip = 1; 756 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 757 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 758 759 int iflib_rx_miss, iflib_rx_miss_bufs; 760 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 761 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 763 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 764 765 /* 766 * Register/unregister. We are already under netmap lock. 767 * Only called on the first register or the last unregister. 768 */ 769 static int 770 iflib_netmap_register(struct netmap_adapter *na, int onoff) 771 { 772 struct ifnet *ifp = na->ifp; 773 if_ctx_t ctx = ifp->if_softc; 774 int status; 775 776 CTX_LOCK(ctx); 777 IFDI_INTR_DISABLE(ctx); 778 779 /* Tell the stack that the interface is no longer active */ 780 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 781 782 if (!CTX_IS_VF(ctx)) 783 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 784 785 /* enable or disable flags and callbacks in na and ifp */ 786 if (onoff) { 787 nm_set_native_flags(na); 788 } else { 789 nm_clear_native_flags(na); 790 } 791 iflib_stop(ctx); 792 iflib_init_locked(ctx); 793 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 794 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 795 if (status) 796 nm_clear_native_flags(na); 797 CTX_UNLOCK(ctx); 798 return (status); 799 } 800 801 static int 802 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 803 { 804 struct netmap_adapter *na = kring->na; 805 u_int const lim = kring->nkr_num_slots - 1; 806 u_int head = kring->rhead; 807 struct netmap_ring *ring = kring->ring; 808 bus_dmamap_t *map; 809 struct if_rxd_update iru; 810 if_ctx_t ctx = rxq->ifr_ctx; 811 iflib_fl_t fl = &rxq->ifr_fl[0]; 812 uint32_t refill_pidx, nic_i; 813 814 if (nm_i == head && __predict_true(!init)) 815 return 0; 816 iru_init(&iru, rxq, 0 /* flid */); 817 map = fl->ifl_sds.ifsd_map; 818 refill_pidx = netmap_idx_k2n(kring, nm_i); 819 /* 820 * IMPORTANT: we must leave one free slot in the ring, 821 * so move head back by one unit 822 */ 823 head = nm_prev(head, lim); 824 while (nm_i != head) { 825 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 826 struct netmap_slot *slot = &ring->slot[nm_i]; 827 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 828 uint32_t nic_i_dma = refill_pidx; 829 nic_i = netmap_idx_k2n(kring, nm_i); 830 831 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 832 833 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 834 return netmap_ring_reinit(kring); 835 836 fl->ifl_vm_addrs[tmp_pidx] = addr; 837 if (__predict_false(init) && map) { 838 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 839 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 840 /* buffer has changed, reload map */ 841 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 842 } 843 slot->flags &= ~NS_BUF_CHANGED; 844 845 nm_i = nm_next(nm_i, lim); 846 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 847 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 848 continue; 849 850 iru.iru_pidx = refill_pidx; 851 iru.iru_count = tmp_pidx+1; 852 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 853 854 refill_pidx = nic_i; 855 if (map == NULL) 856 continue; 857 858 for (int n = 0; n < iru.iru_count; n++) { 859 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 860 BUS_DMASYNC_PREREAD); 861 /* XXX - change this to not use the netmap func*/ 862 nic_i_dma = nm_next(nic_i_dma, lim); 863 } 864 } 865 } 866 kring->nr_hwcur = head; 867 868 if (map) 869 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 870 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 871 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 872 return (0); 873 } 874 875 /* 876 * Reconcile kernel and user view of the transmit ring. 877 * 878 * All information is in the kring. 879 * Userspace wants to send packets up to the one before kring->rhead, 880 * kernel knows kring->nr_hwcur is the first unsent packet. 881 * 882 * Here we push packets out (as many as possible), and possibly 883 * reclaim buffers from previously completed transmission. 884 * 885 * The caller (netmap) guarantees that there is only one instance 886 * running at any time. Any interference with other driver 887 * methods should be handled by the individual drivers. 888 */ 889 static int 890 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 891 { 892 struct netmap_adapter *na = kring->na; 893 struct ifnet *ifp = na->ifp; 894 struct netmap_ring *ring = kring->ring; 895 u_int nm_i; /* index into the netmap ring */ 896 u_int nic_i; /* index into the NIC ring */ 897 u_int n; 898 u_int const lim = kring->nkr_num_slots - 1; 899 u_int const head = kring->rhead; 900 struct if_pkt_info pi; 901 902 /* 903 * interrupts on every tx packet are expensive so request 904 * them every half ring, or where NS_REPORT is set 905 */ 906 u_int report_frequency = kring->nkr_num_slots >> 1; 907 /* device-specific */ 908 if_ctx_t ctx = ifp->if_softc; 909 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 910 911 if (txq->ift_sds.ifsd_map) 912 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 913 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 914 915 916 /* 917 * First part: process new packets to send. 918 * nm_i is the current index in the netmap ring, 919 * nic_i is the corresponding index in the NIC ring. 920 * 921 * If we have packets to send (nm_i != head) 922 * iterate over the netmap ring, fetch length and update 923 * the corresponding slot in the NIC ring. Some drivers also 924 * need to update the buffer's physical address in the NIC slot 925 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 926 * 927 * The netmap_reload_map() calls is especially expensive, 928 * even when (as in this case) the tag is 0, so do only 929 * when the buffer has actually changed. 930 * 931 * If possible do not set the report/intr bit on all slots, 932 * but only a few times per ring or when NS_REPORT is set. 933 * 934 * Finally, on 10G and faster drivers, it might be useful 935 * to prefetch the next slot and txr entry. 936 */ 937 938 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 939 pkt_info_zero(&pi); 940 pi.ipi_segs = txq->ift_segs; 941 pi.ipi_qsidx = kring->ring_id; 942 if (nm_i != head) { /* we have new packets to send */ 943 nic_i = netmap_idx_k2n(kring, nm_i); 944 945 __builtin_prefetch(&ring->slot[nm_i]); 946 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 947 if (txq->ift_sds.ifsd_map) 948 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 949 950 for (n = 0; nm_i != head; n++) { 951 struct netmap_slot *slot = &ring->slot[nm_i]; 952 u_int len = slot->len; 953 uint64_t paddr; 954 void *addr = PNMB(na, slot, &paddr); 955 int flags = (slot->flags & NS_REPORT || 956 nic_i == 0 || nic_i == report_frequency) ? 957 IPI_TX_INTR : 0; 958 959 /* device-specific */ 960 pi.ipi_len = len; 961 pi.ipi_segs[0].ds_addr = paddr; 962 pi.ipi_segs[0].ds_len = len; 963 pi.ipi_nsegs = 1; 964 pi.ipi_ndescs = 0; 965 pi.ipi_pidx = nic_i; 966 pi.ipi_flags = flags; 967 968 /* Fill the slot in the NIC ring. */ 969 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 970 971 /* prefetch for next round */ 972 __builtin_prefetch(&ring->slot[nm_i + 1]); 973 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 974 if (txq->ift_sds.ifsd_map) { 975 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 976 977 NM_CHECK_ADDR_LEN(na, addr, len); 978 979 if (slot->flags & NS_BUF_CHANGED) { 980 /* buffer has changed, reload map */ 981 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 982 } 983 /* make sure changes to the buffer are synced */ 984 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 985 BUS_DMASYNC_PREWRITE); 986 } 987 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 988 nm_i = nm_next(nm_i, lim); 989 nic_i = nm_next(nic_i, lim); 990 } 991 kring->nr_hwcur = head; 992 993 /* synchronize the NIC ring */ 994 if (txq->ift_sds.ifsd_map) 995 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 996 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 997 998 /* (re)start the tx unit up to slot nic_i (excluded) */ 999 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1000 } 1001 1002 /* 1003 * Second part: reclaim buffers for completed transmissions. 1004 */ 1005 if (iflib_tx_credits_update(ctx, txq)) { 1006 /* some tx completed, increment avail */ 1007 nic_i = txq->ift_cidx_processed; 1008 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1009 } 1010 return (0); 1011 } 1012 1013 /* 1014 * Reconcile kernel and user view of the receive ring. 1015 * Same as for the txsync, this routine must be efficient. 1016 * The caller guarantees a single invocations, but races against 1017 * the rest of the driver should be handled here. 1018 * 1019 * On call, kring->rhead is the first packet that userspace wants 1020 * to keep, and kring->rcur is the wakeup point. 1021 * The kernel has previously reported packets up to kring->rtail. 1022 * 1023 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1024 * of whether or not we received an interrupt. 1025 */ 1026 static int 1027 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1028 { 1029 struct netmap_adapter *na = kring->na; 1030 struct netmap_ring *ring = kring->ring; 1031 uint32_t nm_i; /* index into the netmap ring */ 1032 uint32_t nic_i; /* index into the NIC ring */ 1033 u_int i, n; 1034 u_int const lim = kring->nkr_num_slots - 1; 1035 u_int const head = netmap_idx_n2k(kring, kring->rhead); 1036 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1037 struct if_rxd_info ri; 1038 1039 struct ifnet *ifp = na->ifp; 1040 if_ctx_t ctx = ifp->if_softc; 1041 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1042 iflib_fl_t fl = rxq->ifr_fl; 1043 if (head > lim) 1044 return netmap_ring_reinit(kring); 1045 1046 /* XXX check sync modes */ 1047 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1048 if (fl->ifl_sds.ifsd_map == NULL) 1049 continue; 1050 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1051 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1052 } 1053 /* 1054 * First part: import newly received packets. 1055 * 1056 * nm_i is the index of the next free slot in the netmap ring, 1057 * nic_i is the index of the next received packet in the NIC ring, 1058 * and they may differ in case if_init() has been called while 1059 * in netmap mode. For the receive ring we have 1060 * 1061 * nic_i = rxr->next_check; 1062 * nm_i = kring->nr_hwtail (previous) 1063 * and 1064 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1065 * 1066 * rxr->next_check is set to 0 on a ring reinit 1067 */ 1068 if (netmap_no_pendintr || force_update) { 1069 int crclen = iflib_crcstrip ? 0 : 4; 1070 int error, avail; 1071 1072 for (i = 0; i < rxq->ifr_nfl; i++) { 1073 fl = &rxq->ifr_fl[i]; 1074 nic_i = fl->ifl_cidx; 1075 nm_i = netmap_idx_n2k(kring, nic_i); 1076 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1077 for (n = 0; avail > 0; n++, avail--) { 1078 rxd_info_zero(&ri); 1079 ri.iri_frags = rxq->ifr_frags; 1080 ri.iri_qsidx = kring->ring_id; 1081 ri.iri_ifp = ctx->ifc_ifp; 1082 ri.iri_cidx = nic_i; 1083 1084 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1085 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1086 ring->slot[nm_i].flags = 0; 1087 if (fl->ifl_sds.ifsd_map) 1088 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1089 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1090 nm_i = nm_next(nm_i, lim); 1091 nic_i = nm_next(nic_i, lim); 1092 } 1093 if (n) { /* update the state variables */ 1094 if (netmap_no_pendintr && !force_update) { 1095 /* diagnostics */ 1096 iflib_rx_miss ++; 1097 iflib_rx_miss_bufs += n; 1098 } 1099 fl->ifl_cidx = nic_i; 1100 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); 1101 } 1102 kring->nr_kflags &= ~NKR_PENDINTR; 1103 } 1104 } 1105 /* 1106 * Second part: skip past packets that userspace has released. 1107 * (kring->nr_hwcur to head excluded), 1108 * and make the buffers available for reception. 1109 * As usual nm_i is the index in the netmap ring, 1110 * nic_i is the index in the NIC ring, and 1111 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1112 */ 1113 /* XXX not sure how this will work with multiple free lists */ 1114 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 1115 1116 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1117 } 1118 1119 static void 1120 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1121 { 1122 struct ifnet *ifp = na->ifp; 1123 if_ctx_t ctx = ifp->if_softc; 1124 1125 CTX_LOCK(ctx); 1126 if (onoff) { 1127 IFDI_INTR_ENABLE(ctx); 1128 } else { 1129 IFDI_INTR_DISABLE(ctx); 1130 } 1131 CTX_UNLOCK(ctx); 1132 } 1133 1134 1135 static int 1136 iflib_netmap_attach(if_ctx_t ctx) 1137 { 1138 struct netmap_adapter na; 1139 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1140 1141 bzero(&na, sizeof(na)); 1142 1143 na.ifp = ctx->ifc_ifp; 1144 na.na_flags = NAF_BDG_MAYSLEEP; 1145 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1146 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1147 1148 na.num_tx_desc = scctx->isc_ntxd[0]; 1149 na.num_rx_desc = scctx->isc_nrxd[0]; 1150 na.nm_txsync = iflib_netmap_txsync; 1151 na.nm_rxsync = iflib_netmap_rxsync; 1152 na.nm_register = iflib_netmap_register; 1153 na.nm_intr = iflib_netmap_intr; 1154 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1155 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1156 return (netmap_attach(&na)); 1157 } 1158 1159 static void 1160 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1161 { 1162 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1163 struct netmap_slot *slot; 1164 1165 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1166 if (slot == NULL) 1167 return; 1168 if (txq->ift_sds.ifsd_map == NULL) 1169 return; 1170 1171 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1172 1173 /* 1174 * In netmap mode, set the map for the packet buffer. 1175 * NOTE: Some drivers (not this one) also need to set 1176 * the physical buffer address in the NIC ring. 1177 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1178 * netmap slot index, si 1179 */ 1180 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); 1181 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1182 } 1183 } 1184 1185 static void 1186 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1187 { 1188 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1189 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; 1190 struct netmap_slot *slot; 1191 uint32_t nm_i; 1192 1193 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1194 if (slot == NULL) 1195 return; 1196 nm_i = netmap_idx_n2k(kring, 0); 1197 netmap_fl_refill(rxq, kring, nm_i, true); 1198 } 1199 1200 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1201 1202 #else 1203 #define iflib_netmap_txq_init(ctx, txq) 1204 #define iflib_netmap_rxq_init(ctx, rxq) 1205 #define iflib_netmap_detach(ifp) 1206 1207 #define iflib_netmap_attach(ctx) (0) 1208 #define netmap_rx_irq(ifp, qid, budget) (0) 1209 #define netmap_tx_irq(ifp, qid) do {} while (0) 1210 1211 #endif 1212 1213 #if defined(__i386__) || defined(__amd64__) 1214 static __inline void 1215 prefetch(void *x) 1216 { 1217 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1218 } 1219 static __inline void 1220 prefetch2cachelines(void *x) 1221 { 1222 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1223 #if (CACHE_LINE_SIZE < 128) 1224 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1225 #endif 1226 } 1227 #else 1228 #define prefetch(x) 1229 #define prefetch2cachelines(x) 1230 #endif 1231 1232 static void 1233 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1234 { 1235 iflib_fl_t fl; 1236 1237 fl = &rxq->ifr_fl[flid]; 1238 iru->iru_paddrs = fl->ifl_bus_addrs; 1239 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1240 iru->iru_idxs = fl->ifl_rxd_idxs; 1241 iru->iru_qsidx = rxq->ifr_id; 1242 iru->iru_buf_size = fl->ifl_buf_size; 1243 iru->iru_flidx = fl->ifl_id; 1244 } 1245 1246 static void 1247 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1248 { 1249 if (err) 1250 return; 1251 *(bus_addr_t *) arg = segs[0].ds_addr; 1252 } 1253 1254 int 1255 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1256 { 1257 int err; 1258 if_shared_ctx_t sctx = ctx->ifc_sctx; 1259 device_t dev = ctx->ifc_dev; 1260 1261 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1262 1263 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1264 sctx->isc_q_align, 0, /* alignment, bounds */ 1265 BUS_SPACE_MAXADDR, /* lowaddr */ 1266 BUS_SPACE_MAXADDR, /* highaddr */ 1267 NULL, NULL, /* filter, filterarg */ 1268 size, /* maxsize */ 1269 1, /* nsegments */ 1270 size, /* maxsegsize */ 1271 BUS_DMA_ALLOCNOW, /* flags */ 1272 NULL, /* lockfunc */ 1273 NULL, /* lockarg */ 1274 &dma->idi_tag); 1275 if (err) { 1276 device_printf(dev, 1277 "%s: bus_dma_tag_create failed: %d\n", 1278 __func__, err); 1279 goto fail_0; 1280 } 1281 1282 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1283 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1284 if (err) { 1285 device_printf(dev, 1286 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1287 __func__, (uintmax_t)size, err); 1288 goto fail_1; 1289 } 1290 1291 dma->idi_paddr = IF_BAD_DMA; 1292 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1293 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1294 if (err || dma->idi_paddr == IF_BAD_DMA) { 1295 device_printf(dev, 1296 "%s: bus_dmamap_load failed: %d\n", 1297 __func__, err); 1298 goto fail_2; 1299 } 1300 1301 dma->idi_size = size; 1302 return (0); 1303 1304 fail_2: 1305 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1306 fail_1: 1307 bus_dma_tag_destroy(dma->idi_tag); 1308 fail_0: 1309 dma->idi_tag = NULL; 1310 1311 return (err); 1312 } 1313 1314 int 1315 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1316 { 1317 int i, err; 1318 iflib_dma_info_t *dmaiter; 1319 1320 dmaiter = dmalist; 1321 for (i = 0; i < count; i++, dmaiter++) { 1322 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1323 break; 1324 } 1325 if (err) 1326 iflib_dma_free_multi(dmalist, i); 1327 return (err); 1328 } 1329 1330 void 1331 iflib_dma_free(iflib_dma_info_t dma) 1332 { 1333 if (dma->idi_tag == NULL) 1334 return; 1335 if (dma->idi_paddr != IF_BAD_DMA) { 1336 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1337 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1338 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1339 dma->idi_paddr = IF_BAD_DMA; 1340 } 1341 if (dma->idi_vaddr != NULL) { 1342 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1343 dma->idi_vaddr = NULL; 1344 } 1345 bus_dma_tag_destroy(dma->idi_tag); 1346 dma->idi_tag = NULL; 1347 } 1348 1349 void 1350 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1351 { 1352 int i; 1353 iflib_dma_info_t *dmaiter = dmalist; 1354 1355 for (i = 0; i < count; i++, dmaiter++) 1356 iflib_dma_free(*dmaiter); 1357 } 1358 1359 #ifdef EARLY_AP_STARTUP 1360 static const int iflib_started = 1; 1361 #else 1362 /* 1363 * We used to abuse the smp_started flag to decide if the queues have been 1364 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1365 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1366 * is set. Run a SYSINIT() strictly after that to just set a usable 1367 * completion flag. 1368 */ 1369 1370 static int iflib_started; 1371 1372 static void 1373 iflib_record_started(void *arg) 1374 { 1375 iflib_started = 1; 1376 } 1377 1378 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1379 iflib_record_started, NULL); 1380 #endif 1381 1382 static int 1383 iflib_fast_intr(void *arg) 1384 { 1385 iflib_filter_info_t info = arg; 1386 struct grouptask *gtask = info->ifi_task; 1387 if (!iflib_started) 1388 return (FILTER_HANDLED); 1389 1390 DBG_COUNTER_INC(fast_intrs); 1391 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1392 return (FILTER_HANDLED); 1393 1394 GROUPTASK_ENQUEUE(gtask); 1395 return (FILTER_HANDLED); 1396 } 1397 1398 static int 1399 iflib_fast_intr_rxtx(void *arg) 1400 { 1401 iflib_filter_info_t info = arg; 1402 struct grouptask *gtask = info->ifi_task; 1403 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1404 if_ctx_t ctx; 1405 int i, cidx; 1406 1407 if (!iflib_started) 1408 return (FILTER_HANDLED); 1409 1410 DBG_COUNTER_INC(fast_intrs); 1411 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1412 return (FILTER_HANDLED); 1413 1414 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1415 qidx_t txqid = rxq->ifr_txqid[i]; 1416 1417 ctx = rxq->ifr_ctx; 1418 1419 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1420 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1421 continue; 1422 } 1423 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1424 } 1425 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1426 cidx = rxq->ifr_cq_cidx; 1427 else 1428 cidx = rxq->ifr_fl[0].ifl_cidx; 1429 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1430 GROUPTASK_ENQUEUE(gtask); 1431 else 1432 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1433 return (FILTER_HANDLED); 1434 } 1435 1436 1437 static int 1438 iflib_fast_intr_ctx(void *arg) 1439 { 1440 iflib_filter_info_t info = arg; 1441 struct grouptask *gtask = info->ifi_task; 1442 1443 if (!iflib_started) 1444 return (FILTER_HANDLED); 1445 1446 DBG_COUNTER_INC(fast_intrs); 1447 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1448 return (FILTER_HANDLED); 1449 1450 GROUPTASK_ENQUEUE(gtask); 1451 return (FILTER_HANDLED); 1452 } 1453 1454 static int 1455 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1456 driver_filter_t filter, driver_intr_t handler, void *arg, 1457 char *name) 1458 { 1459 int rc, flags; 1460 struct resource *res; 1461 void *tag = NULL; 1462 device_t dev = ctx->ifc_dev; 1463 1464 flags = RF_ACTIVE; 1465 if (ctx->ifc_flags & IFC_LEGACY) 1466 flags |= RF_SHAREABLE; 1467 MPASS(rid < 512); 1468 irq->ii_rid = rid; 1469 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1470 if (res == NULL) { 1471 device_printf(dev, 1472 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1473 return (ENOMEM); 1474 } 1475 irq->ii_res = res; 1476 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1477 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1478 filter, handler, arg, &tag); 1479 if (rc != 0) { 1480 device_printf(dev, 1481 "failed to setup interrupt for rid %d, name %s: %d\n", 1482 rid, name ? name : "unknown", rc); 1483 return (rc); 1484 } else if (name) 1485 bus_describe_intr(dev, res, tag, "%s", name); 1486 1487 irq->ii_tag = tag; 1488 return (0); 1489 } 1490 1491 1492 /********************************************************************* 1493 * 1494 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1495 * the information needed to transmit a packet on the wire. This is 1496 * called only once at attach, setup is done every reset. 1497 * 1498 **********************************************************************/ 1499 1500 static int 1501 iflib_txsd_alloc(iflib_txq_t txq) 1502 { 1503 if_ctx_t ctx = txq->ift_ctx; 1504 if_shared_ctx_t sctx = ctx->ifc_sctx; 1505 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1506 device_t dev = ctx->ifc_dev; 1507 int err, nsegments, ntsosegments; 1508 1509 nsegments = scctx->isc_tx_nsegments; 1510 ntsosegments = scctx->isc_tx_tso_segments_max; 1511 MPASS(scctx->isc_ntxd[0] > 0); 1512 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1513 MPASS(nsegments > 0); 1514 MPASS(ntsosegments > 0); 1515 /* 1516 * Setup DMA descriptor areas. 1517 */ 1518 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1519 1, 0, /* alignment, bounds */ 1520 BUS_SPACE_MAXADDR, /* lowaddr */ 1521 BUS_SPACE_MAXADDR, /* highaddr */ 1522 NULL, NULL, /* filter, filterarg */ 1523 sctx->isc_tx_maxsize, /* maxsize */ 1524 nsegments, /* nsegments */ 1525 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1526 0, /* flags */ 1527 NULL, /* lockfunc */ 1528 NULL, /* lockfuncarg */ 1529 &txq->ift_desc_tag))) { 1530 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1531 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1532 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1533 goto fail; 1534 } 1535 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1536 1, 0, /* alignment, bounds */ 1537 BUS_SPACE_MAXADDR, /* lowaddr */ 1538 BUS_SPACE_MAXADDR, /* highaddr */ 1539 NULL, NULL, /* filter, filterarg */ 1540 scctx->isc_tx_tso_size_max, /* maxsize */ 1541 ntsosegments, /* nsegments */ 1542 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1543 0, /* flags */ 1544 NULL, /* lockfunc */ 1545 NULL, /* lockfuncarg */ 1546 &txq->ift_tso_desc_tag))) { 1547 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1548 1549 goto fail; 1550 } 1551 if (!(txq->ift_sds.ifsd_flags = 1552 (uint8_t *) malloc(sizeof(uint8_t) * 1553 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1554 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1555 err = ENOMEM; 1556 goto fail; 1557 } 1558 if (!(txq->ift_sds.ifsd_m = 1559 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1560 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1561 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1562 err = ENOMEM; 1563 goto fail; 1564 } 1565 1566 /* Create the descriptor buffer dma maps */ 1567 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1568 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1569 return (0); 1570 1571 if (!(txq->ift_sds.ifsd_map = 1572 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1573 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1574 err = ENOMEM; 1575 goto fail; 1576 } 1577 1578 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1579 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1580 if (err != 0) { 1581 device_printf(dev, "Unable to create TX DMA map\n"); 1582 goto fail; 1583 } 1584 } 1585 #endif 1586 return (0); 1587 fail: 1588 /* We free all, it handles case where we are in the middle */ 1589 iflib_tx_structures_free(ctx); 1590 return (err); 1591 } 1592 1593 static void 1594 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1595 { 1596 bus_dmamap_t map; 1597 1598 map = NULL; 1599 if (txq->ift_sds.ifsd_map != NULL) 1600 map = txq->ift_sds.ifsd_map[i]; 1601 if (map != NULL) { 1602 bus_dmamap_unload(txq->ift_desc_tag, map); 1603 bus_dmamap_destroy(txq->ift_desc_tag, map); 1604 txq->ift_sds.ifsd_map[i] = NULL; 1605 } 1606 } 1607 1608 static void 1609 iflib_txq_destroy(iflib_txq_t txq) 1610 { 1611 if_ctx_t ctx = txq->ift_ctx; 1612 1613 for (int i = 0; i < txq->ift_size; i++) 1614 iflib_txsd_destroy(ctx, txq, i); 1615 if (txq->ift_sds.ifsd_map != NULL) { 1616 free(txq->ift_sds.ifsd_map, M_IFLIB); 1617 txq->ift_sds.ifsd_map = NULL; 1618 } 1619 if (txq->ift_sds.ifsd_m != NULL) { 1620 free(txq->ift_sds.ifsd_m, M_IFLIB); 1621 txq->ift_sds.ifsd_m = NULL; 1622 } 1623 if (txq->ift_sds.ifsd_flags != NULL) { 1624 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1625 txq->ift_sds.ifsd_flags = NULL; 1626 } 1627 if (txq->ift_desc_tag != NULL) { 1628 bus_dma_tag_destroy(txq->ift_desc_tag); 1629 txq->ift_desc_tag = NULL; 1630 } 1631 if (txq->ift_tso_desc_tag != NULL) { 1632 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1633 txq->ift_tso_desc_tag = NULL; 1634 } 1635 } 1636 1637 static void 1638 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1639 { 1640 struct mbuf **mp; 1641 1642 mp = &txq->ift_sds.ifsd_m[i]; 1643 if (*mp == NULL) 1644 return; 1645 1646 if (txq->ift_sds.ifsd_map != NULL) { 1647 bus_dmamap_sync(txq->ift_desc_tag, 1648 txq->ift_sds.ifsd_map[i], 1649 BUS_DMASYNC_POSTWRITE); 1650 bus_dmamap_unload(txq->ift_desc_tag, 1651 txq->ift_sds.ifsd_map[i]); 1652 } 1653 m_free(*mp); 1654 DBG_COUNTER_INC(tx_frees); 1655 *mp = NULL; 1656 } 1657 1658 static int 1659 iflib_txq_setup(iflib_txq_t txq) 1660 { 1661 if_ctx_t ctx = txq->ift_ctx; 1662 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1663 iflib_dma_info_t di; 1664 int i; 1665 1666 /* Set number of descriptors available */ 1667 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1668 /* XXX make configurable */ 1669 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1670 1671 /* Reset indices */ 1672 txq->ift_cidx_processed = 0; 1673 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1674 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1675 1676 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1677 bzero((void *)di->idi_vaddr, di->idi_size); 1678 1679 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1680 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1681 bus_dmamap_sync(di->idi_tag, di->idi_map, 1682 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1683 return (0); 1684 } 1685 1686 /********************************************************************* 1687 * 1688 * Allocate memory for rx_buffer structures. Since we use one 1689 * rx_buffer per received packet, the maximum number of rx_buffer's 1690 * that we'll need is equal to the number of receive descriptors 1691 * that we've allocated. 1692 * 1693 **********************************************************************/ 1694 static int 1695 iflib_rxsd_alloc(iflib_rxq_t rxq) 1696 { 1697 if_ctx_t ctx = rxq->ifr_ctx; 1698 if_shared_ctx_t sctx = ctx->ifc_sctx; 1699 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1700 device_t dev = ctx->ifc_dev; 1701 iflib_fl_t fl; 1702 int err; 1703 1704 MPASS(scctx->isc_nrxd[0] > 0); 1705 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1706 1707 fl = rxq->ifr_fl; 1708 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1709 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1710 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1711 1, 0, /* alignment, bounds */ 1712 BUS_SPACE_MAXADDR, /* lowaddr */ 1713 BUS_SPACE_MAXADDR, /* highaddr */ 1714 NULL, NULL, /* filter, filterarg */ 1715 sctx->isc_rx_maxsize, /* maxsize */ 1716 sctx->isc_rx_nsegments, /* nsegments */ 1717 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1718 0, /* flags */ 1719 NULL, /* lockfunc */ 1720 NULL, /* lockarg */ 1721 &fl->ifl_desc_tag); 1722 if (err) { 1723 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1724 __func__, err); 1725 goto fail; 1726 } 1727 if (!(fl->ifl_sds.ifsd_flags = 1728 (uint8_t *) malloc(sizeof(uint8_t) * 1729 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1730 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1731 err = ENOMEM; 1732 goto fail; 1733 } 1734 if (!(fl->ifl_sds.ifsd_m = 1735 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1736 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1737 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1738 err = ENOMEM; 1739 goto fail; 1740 } 1741 if (!(fl->ifl_sds.ifsd_cl = 1742 (caddr_t *) malloc(sizeof(caddr_t) * 1743 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1744 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1745 err = ENOMEM; 1746 goto fail; 1747 } 1748 1749 /* Create the descriptor buffer dma maps */ 1750 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1751 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1752 continue; 1753 1754 if (!(fl->ifl_sds.ifsd_map = 1755 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1756 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1757 err = ENOMEM; 1758 goto fail; 1759 } 1760 1761 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1762 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1763 if (err != 0) { 1764 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1765 goto fail; 1766 } 1767 } 1768 #endif 1769 } 1770 return (0); 1771 1772 fail: 1773 iflib_rx_structures_free(ctx); 1774 return (err); 1775 } 1776 1777 1778 /* 1779 * Internal service routines 1780 */ 1781 1782 struct rxq_refill_cb_arg { 1783 int error; 1784 bus_dma_segment_t seg; 1785 int nseg; 1786 }; 1787 1788 static void 1789 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1790 { 1791 struct rxq_refill_cb_arg *cb_arg = arg; 1792 1793 cb_arg->error = error; 1794 cb_arg->seg = segs[0]; 1795 cb_arg->nseg = nseg; 1796 } 1797 1798 1799 #ifdef ACPI_DMAR 1800 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1801 #else 1802 #define IS_DMAR(ctx) (0) 1803 #endif 1804 1805 /** 1806 * rxq_refill - refill an rxq free-buffer list 1807 * @ctx: the iflib context 1808 * @rxq: the free-list to refill 1809 * @n: the number of new buffers to allocate 1810 * 1811 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1812 * The caller must assure that @n does not exceed the queue's capacity. 1813 */ 1814 static void 1815 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1816 { 1817 struct mbuf *m; 1818 int idx, frag_idx = fl->ifl_fragidx; 1819 int pidx = fl->ifl_pidx; 1820 caddr_t cl, *sd_cl; 1821 struct mbuf **sd_m; 1822 uint8_t *sd_flags; 1823 struct if_rxd_update iru; 1824 bus_dmamap_t *sd_map; 1825 int n, i = 0; 1826 uint64_t bus_addr; 1827 int err; 1828 qidx_t credits; 1829 1830 sd_m = fl->ifl_sds.ifsd_m; 1831 sd_map = fl->ifl_sds.ifsd_map; 1832 sd_cl = fl->ifl_sds.ifsd_cl; 1833 sd_flags = fl->ifl_sds.ifsd_flags; 1834 idx = pidx; 1835 credits = fl->ifl_credits; 1836 1837 n = count; 1838 MPASS(n > 0); 1839 MPASS(credits + n <= fl->ifl_size); 1840 1841 if (pidx < fl->ifl_cidx) 1842 MPASS(pidx + n <= fl->ifl_cidx); 1843 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1844 MPASS(fl->ifl_gen == 0); 1845 if (pidx > fl->ifl_cidx) 1846 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1847 1848 DBG_COUNTER_INC(fl_refills); 1849 if (n > 8) 1850 DBG_COUNTER_INC(fl_refills_large); 1851 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1852 while (n--) { 1853 /* 1854 * We allocate an uninitialized mbuf + cluster, mbuf is 1855 * initialized after rx. 1856 * 1857 * If the cluster is still set then we know a minimum sized packet was received 1858 */ 1859 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1860 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1861 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1862 if ((cl = sd_cl[frag_idx]) == NULL) { 1863 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1864 break; 1865 #if MEMORY_LOGGING 1866 fl->ifl_cl_enqueued++; 1867 #endif 1868 } 1869 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1870 break; 1871 } 1872 #if MEMORY_LOGGING 1873 fl->ifl_m_enqueued++; 1874 #endif 1875 1876 DBG_COUNTER_INC(rx_allocs); 1877 #if defined(__i386__) || defined(__amd64__) 1878 if (!IS_DMAR(ctx)) { 1879 bus_addr = pmap_kextract((vm_offset_t)cl); 1880 } else 1881 #endif 1882 { 1883 struct rxq_refill_cb_arg cb_arg; 1884 iflib_rxq_t q; 1885 1886 cb_arg.error = 0; 1887 q = fl->ifl_rxq; 1888 MPASS(sd_map != NULL); 1889 MPASS(sd_map[frag_idx] != NULL); 1890 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1891 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1892 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1893 BUS_DMASYNC_PREREAD); 1894 1895 if (err != 0 || cb_arg.error) { 1896 /* 1897 * !zone_pack ? 1898 */ 1899 if (fl->ifl_zone == zone_pack) 1900 uma_zfree(fl->ifl_zone, cl); 1901 m_free(m); 1902 n = 0; 1903 goto done; 1904 } 1905 bus_addr = cb_arg.seg.ds_addr; 1906 } 1907 bit_set(fl->ifl_rx_bitmap, frag_idx); 1908 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1909 1910 MPASS(sd_m[frag_idx] == NULL); 1911 sd_cl[frag_idx] = cl; 1912 sd_m[frag_idx] = m; 1913 fl->ifl_rxd_idxs[i] = frag_idx; 1914 fl->ifl_bus_addrs[i] = bus_addr; 1915 fl->ifl_vm_addrs[i] = cl; 1916 credits++; 1917 i++; 1918 MPASS(credits <= fl->ifl_size); 1919 if (++idx == fl->ifl_size) { 1920 fl->ifl_gen = 1; 1921 idx = 0; 1922 } 1923 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1924 iru.iru_pidx = pidx; 1925 iru.iru_count = i; 1926 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1927 i = 0; 1928 pidx = idx; 1929 fl->ifl_pidx = idx; 1930 fl->ifl_credits = credits; 1931 } 1932 1933 } 1934 done: 1935 if (i) { 1936 iru.iru_pidx = pidx; 1937 iru.iru_count = i; 1938 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1939 fl->ifl_pidx = idx; 1940 fl->ifl_credits = credits; 1941 } 1942 DBG_COUNTER_INC(rxd_flush); 1943 if (fl->ifl_pidx == 0) 1944 pidx = fl->ifl_size - 1; 1945 else 1946 pidx = fl->ifl_pidx - 1; 1947 1948 if (sd_map) 1949 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1950 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1951 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1952 fl->ifl_fragidx = frag_idx; 1953 } 1954 1955 static __inline void 1956 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1957 { 1958 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1959 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1960 #ifdef INVARIANTS 1961 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1962 #endif 1963 1964 MPASS(fl->ifl_credits <= fl->ifl_size); 1965 MPASS(reclaimable == delta); 1966 1967 if (reclaimable > 0) 1968 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1969 } 1970 1971 static void 1972 iflib_fl_bufs_free(iflib_fl_t fl) 1973 { 1974 iflib_dma_info_t idi = fl->ifl_ifdi; 1975 uint32_t i; 1976 1977 for (i = 0; i < fl->ifl_size; i++) { 1978 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1979 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1980 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1981 1982 if (*sd_flags & RX_SW_DESC_INUSE) { 1983 if (fl->ifl_sds.ifsd_map != NULL) { 1984 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1985 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1986 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach) 1987 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1988 } 1989 if (*sd_m != NULL) { 1990 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 1991 uma_zfree(zone_mbuf, *sd_m); 1992 } 1993 if (*sd_cl != NULL) 1994 uma_zfree(fl->ifl_zone, *sd_cl); 1995 *sd_flags = 0; 1996 } else { 1997 MPASS(*sd_cl == NULL); 1998 MPASS(*sd_m == NULL); 1999 } 2000 #if MEMORY_LOGGING 2001 fl->ifl_m_dequeued++; 2002 fl->ifl_cl_dequeued++; 2003 #endif 2004 *sd_cl = NULL; 2005 *sd_m = NULL; 2006 } 2007 #ifdef INVARIANTS 2008 for (i = 0; i < fl->ifl_size; i++) { 2009 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2010 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2011 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2012 } 2013 #endif 2014 /* 2015 * Reset free list values 2016 */ 2017 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2018 bzero(idi->idi_vaddr, idi->idi_size); 2019 } 2020 2021 /********************************************************************* 2022 * 2023 * Initialize a receive ring and its buffers. 2024 * 2025 **********************************************************************/ 2026 static int 2027 iflib_fl_setup(iflib_fl_t fl) 2028 { 2029 iflib_rxq_t rxq = fl->ifl_rxq; 2030 if_ctx_t ctx = rxq->ifr_ctx; 2031 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2032 2033 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2034 /* 2035 ** Free current RX buffer structs and their mbufs 2036 */ 2037 iflib_fl_bufs_free(fl); 2038 /* Now replenish the mbufs */ 2039 MPASS(fl->ifl_credits == 0); 2040 /* 2041 * XXX don't set the max_frame_size to larger 2042 * than the hardware can handle 2043 */ 2044 if (sctx->isc_max_frame_size <= 2048) 2045 fl->ifl_buf_size = MCLBYTES; 2046 #ifndef CONTIGMALLOC_WORKS 2047 else 2048 fl->ifl_buf_size = MJUMPAGESIZE; 2049 #else 2050 else if (sctx->isc_max_frame_size <= 4096) 2051 fl->ifl_buf_size = MJUMPAGESIZE; 2052 else if (sctx->isc_max_frame_size <= 9216) 2053 fl->ifl_buf_size = MJUM9BYTES; 2054 else 2055 fl->ifl_buf_size = MJUM16BYTES; 2056 #endif 2057 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2058 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2059 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2060 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2061 2062 2063 /* avoid pre-allocating zillions of clusters to an idle card 2064 * potentially speeding up attach 2065 */ 2066 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2067 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2068 if (min(128, fl->ifl_size) != fl->ifl_credits) 2069 return (ENOBUFS); 2070 /* 2071 * handle failure 2072 */ 2073 MPASS(rxq != NULL); 2074 MPASS(fl->ifl_ifdi != NULL); 2075 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2076 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2077 return (0); 2078 } 2079 2080 /********************************************************************* 2081 * 2082 * Free receive ring data structures 2083 * 2084 **********************************************************************/ 2085 static void 2086 iflib_rx_sds_free(iflib_rxq_t rxq) 2087 { 2088 iflib_fl_t fl; 2089 int i; 2090 2091 if (rxq->ifr_fl != NULL) { 2092 for (i = 0; i < rxq->ifr_nfl; i++) { 2093 fl = &rxq->ifr_fl[i]; 2094 if (fl->ifl_desc_tag != NULL) { 2095 bus_dma_tag_destroy(fl->ifl_desc_tag); 2096 fl->ifl_desc_tag = NULL; 2097 } 2098 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2099 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2100 /* XXX destroy maps first */ 2101 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2102 fl->ifl_sds.ifsd_m = NULL; 2103 fl->ifl_sds.ifsd_cl = NULL; 2104 fl->ifl_sds.ifsd_map = NULL; 2105 } 2106 free(rxq->ifr_fl, M_IFLIB); 2107 rxq->ifr_fl = NULL; 2108 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2109 } 2110 } 2111 2112 /* 2113 * MI independent logic 2114 * 2115 */ 2116 static void 2117 iflib_timer(void *arg) 2118 { 2119 iflib_txq_t txq = arg; 2120 if_ctx_t ctx = txq->ift_ctx; 2121 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2122 2123 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2124 return; 2125 /* 2126 ** Check on the state of the TX queue(s), this 2127 ** can be done without the lock because its RO 2128 ** and the HUNG state will be static if set. 2129 */ 2130 IFDI_TIMER(ctx, txq->ift_id); 2131 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2132 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2133 (sctx->isc_pause_frames == 0))) 2134 goto hung; 2135 2136 if (ifmp_ring_is_stalled(txq->ift_br)) 2137 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2138 txq->ift_cleaned_prev = txq->ift_cleaned; 2139 /* handle any laggards */ 2140 if (txq->ift_db_pending) 2141 GROUPTASK_ENQUEUE(&txq->ift_task); 2142 2143 sctx->isc_pause_frames = 0; 2144 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2145 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2146 return; 2147 hung: 2148 CTX_LOCK(ctx); 2149 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2150 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2151 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2152 2153 IFDI_WATCHDOG_RESET(ctx); 2154 ctx->ifc_watchdog_events++; 2155 2156 ctx->ifc_flags |= IFC_DO_RESET; 2157 iflib_admin_intr_deferred(ctx); 2158 CTX_UNLOCK(ctx); 2159 } 2160 2161 static void 2162 iflib_init_locked(if_ctx_t ctx) 2163 { 2164 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2165 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2166 if_t ifp = ctx->ifc_ifp; 2167 iflib_fl_t fl; 2168 iflib_txq_t txq; 2169 iflib_rxq_t rxq; 2170 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2171 2172 2173 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2174 IFDI_INTR_DISABLE(ctx); 2175 2176 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2177 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2178 /* Set hardware offload abilities */ 2179 if_clearhwassist(ifp); 2180 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2181 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2182 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2183 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2184 if (if_getcapenable(ifp) & IFCAP_TSO4) 2185 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2186 if (if_getcapenable(ifp) & IFCAP_TSO6) 2187 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2188 2189 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2190 CALLOUT_LOCK(txq); 2191 callout_stop(&txq->ift_timer); 2192 CALLOUT_UNLOCK(txq); 2193 iflib_netmap_txq_init(ctx, txq); 2194 } 2195 #ifdef INVARIANTS 2196 i = if_getdrvflags(ifp); 2197 #endif 2198 IFDI_INIT(ctx); 2199 MPASS(if_getdrvflags(ifp) == i); 2200 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2201 /* XXX this should really be done on a per-queue basis */ 2202 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2203 MPASS(rxq->ifr_id == i); 2204 iflib_netmap_rxq_init(ctx, rxq); 2205 continue; 2206 } 2207 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2208 if (iflib_fl_setup(fl)) { 2209 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2210 goto done; 2211 } 2212 } 2213 } 2214 done: 2215 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2216 IFDI_INTR_ENABLE(ctx); 2217 txq = ctx->ifc_txqs; 2218 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2219 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2220 txq->ift_timer.c_cpu); 2221 } 2222 2223 static int 2224 iflib_media_change(if_t ifp) 2225 { 2226 if_ctx_t ctx = if_getsoftc(ifp); 2227 int err; 2228 2229 CTX_LOCK(ctx); 2230 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2231 iflib_init_locked(ctx); 2232 CTX_UNLOCK(ctx); 2233 return (err); 2234 } 2235 2236 static void 2237 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2238 { 2239 if_ctx_t ctx = if_getsoftc(ifp); 2240 2241 CTX_LOCK(ctx); 2242 IFDI_UPDATE_ADMIN_STATUS(ctx); 2243 IFDI_MEDIA_STATUS(ctx, ifmr); 2244 CTX_UNLOCK(ctx); 2245 } 2246 2247 static void 2248 iflib_stop(if_ctx_t ctx) 2249 { 2250 iflib_txq_t txq = ctx->ifc_txqs; 2251 iflib_rxq_t rxq = ctx->ifc_rxqs; 2252 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2253 iflib_dma_info_t di; 2254 iflib_fl_t fl; 2255 int i, j; 2256 2257 /* Tell the stack that the interface is no longer active */ 2258 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2259 2260 IFDI_INTR_DISABLE(ctx); 2261 DELAY(1000); 2262 IFDI_STOP(ctx); 2263 DELAY(1000); 2264 2265 iflib_debug_reset(); 2266 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2267 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2268 /* make sure all transmitters have completed before proceeding XXX */ 2269 2270 CALLOUT_LOCK(txq); 2271 callout_stop(&txq->ift_timer); 2272 CALLOUT_UNLOCK(txq); 2273 2274 /* clean any enqueued buffers */ 2275 iflib_ifmp_purge(txq); 2276 /* Free any existing tx buffers. */ 2277 for (j = 0; j < txq->ift_size; j++) { 2278 iflib_txsd_free(ctx, txq, j); 2279 } 2280 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2281 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2282 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2283 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2284 txq->ift_pullups = 0; 2285 ifmp_ring_reset_stats(txq->ift_br); 2286 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2287 bzero((void *)di->idi_vaddr, di->idi_size); 2288 } 2289 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2290 /* make sure all transmitters have completed before proceeding XXX */ 2291 2292 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) 2293 bzero((void *)di->idi_vaddr, di->idi_size); 2294 /* also resets the free lists pidx/cidx */ 2295 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2296 iflib_fl_bufs_free(fl); 2297 } 2298 } 2299 2300 static inline caddr_t 2301 calc_next_rxd(iflib_fl_t fl, int cidx) 2302 { 2303 qidx_t size; 2304 int nrxd; 2305 caddr_t start, end, cur, next; 2306 2307 nrxd = fl->ifl_size; 2308 size = fl->ifl_rxd_size; 2309 start = fl->ifl_ifdi->idi_vaddr; 2310 2311 if (__predict_false(size == 0)) 2312 return (start); 2313 cur = start + size*cidx; 2314 end = start + size*nrxd; 2315 next = CACHE_PTR_NEXT(cur); 2316 return (next < end ? next : start); 2317 } 2318 2319 static inline void 2320 prefetch_pkts(iflib_fl_t fl, int cidx) 2321 { 2322 int nextptr; 2323 int nrxd = fl->ifl_size; 2324 caddr_t next_rxd; 2325 2326 2327 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2328 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2329 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2330 next_rxd = calc_next_rxd(fl, cidx); 2331 prefetch(next_rxd); 2332 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2333 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2334 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2335 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2336 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2337 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2338 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2339 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2340 } 2341 2342 static void 2343 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2344 { 2345 int flid, cidx; 2346 bus_dmamap_t map; 2347 iflib_fl_t fl; 2348 iflib_dma_info_t di; 2349 int next; 2350 2351 map = NULL; 2352 flid = irf->irf_flid; 2353 cidx = irf->irf_idx; 2354 fl = &rxq->ifr_fl[flid]; 2355 sd->ifsd_fl = fl; 2356 sd->ifsd_cidx = cidx; 2357 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2358 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2359 fl->ifl_credits--; 2360 #if MEMORY_LOGGING 2361 fl->ifl_m_dequeued++; 2362 #endif 2363 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2364 prefetch_pkts(fl, cidx); 2365 if (fl->ifl_sds.ifsd_map != NULL) { 2366 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2367 prefetch(&fl->ifl_sds.ifsd_map[next]); 2368 map = fl->ifl_sds.ifsd_map[cidx]; 2369 di = fl->ifl_ifdi; 2370 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2371 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2372 bus_dmamap_sync(di->idi_tag, di->idi_map, 2373 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2374 2375 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2376 MPASS(fl->ifl_cidx == cidx); 2377 if (unload) 2378 bus_dmamap_unload(fl->ifl_desc_tag, map); 2379 } 2380 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2381 if (__predict_false(fl->ifl_cidx == 0)) 2382 fl->ifl_gen = 0; 2383 if (map != NULL) 2384 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2385 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2386 bit_clear(fl->ifl_rx_bitmap, cidx); 2387 } 2388 2389 static struct mbuf * 2390 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2391 { 2392 int i, padlen , flags; 2393 struct mbuf *m, *mh, *mt; 2394 caddr_t cl; 2395 2396 i = 0; 2397 mh = NULL; 2398 do { 2399 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2400 2401 MPASS(*sd->ifsd_cl != NULL); 2402 MPASS(*sd->ifsd_m != NULL); 2403 2404 /* Don't include zero-length frags */ 2405 if (ri->iri_frags[i].irf_len == 0) { 2406 /* XXX we can save the cluster here, but not the mbuf */ 2407 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2408 m_free(*sd->ifsd_m); 2409 *sd->ifsd_m = NULL; 2410 continue; 2411 } 2412 m = *sd->ifsd_m; 2413 *sd->ifsd_m = NULL; 2414 if (mh == NULL) { 2415 flags = M_PKTHDR|M_EXT; 2416 mh = mt = m; 2417 padlen = ri->iri_pad; 2418 } else { 2419 flags = M_EXT; 2420 mt->m_next = m; 2421 mt = m; 2422 /* assuming padding is only on the first fragment */ 2423 padlen = 0; 2424 } 2425 cl = *sd->ifsd_cl; 2426 *sd->ifsd_cl = NULL; 2427 2428 /* Can these two be made one ? */ 2429 m_init(m, M_NOWAIT, MT_DATA, flags); 2430 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2431 /* 2432 * These must follow m_init and m_cljset 2433 */ 2434 m->m_data += padlen; 2435 ri->iri_len -= padlen; 2436 m->m_len = ri->iri_frags[i].irf_len; 2437 } while (++i < ri->iri_nfrags); 2438 2439 return (mh); 2440 } 2441 2442 /* 2443 * Process one software descriptor 2444 */ 2445 static struct mbuf * 2446 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2447 { 2448 struct if_rxsd sd; 2449 struct mbuf *m; 2450 2451 /* should I merge this back in now that the two paths are basically duplicated? */ 2452 if (ri->iri_nfrags == 1 && 2453 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) { 2454 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2455 m = *sd.ifsd_m; 2456 *sd.ifsd_m = NULL; 2457 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2458 #ifndef __NO_STRICT_ALIGNMENT 2459 if (!IP_ALIGNED(m)) 2460 m->m_data += 2; 2461 #endif 2462 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2463 m->m_len = ri->iri_frags[0].irf_len; 2464 } else { 2465 m = assemble_segments(rxq, ri, &sd); 2466 } 2467 m->m_pkthdr.len = ri->iri_len; 2468 m->m_pkthdr.rcvif = ri->iri_ifp; 2469 m->m_flags |= ri->iri_flags; 2470 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2471 m->m_pkthdr.flowid = ri->iri_flowid; 2472 M_HASHTYPE_SET(m, ri->iri_rsstype); 2473 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2474 m->m_pkthdr.csum_data = ri->iri_csum_data; 2475 return (m); 2476 } 2477 2478 #if defined(INET6) || defined(INET) 2479 static void 2480 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2481 { 2482 CURVNET_SET(lc->ifp->if_vnet); 2483 #if defined(INET6) 2484 *v6 = VNET(ip6_forwarding); 2485 #endif 2486 #if defined(INET) 2487 *v4 = VNET(ipforwarding); 2488 #endif 2489 CURVNET_RESTORE(); 2490 } 2491 2492 /* 2493 * Returns true if it's possible this packet could be LROed. 2494 * if it returns false, it is guaranteed that tcp_lro_rx() 2495 * would not return zero. 2496 */ 2497 static bool 2498 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2499 { 2500 struct ether_header *eh; 2501 uint16_t eh_type; 2502 2503 eh = mtod(m, struct ether_header *); 2504 eh_type = ntohs(eh->ether_type); 2505 switch (eh_type) { 2506 #if defined(INET6) 2507 case ETHERTYPE_IPV6: 2508 return !v6_forwarding; 2509 #endif 2510 #if defined (INET) 2511 case ETHERTYPE_IP: 2512 return !v4_forwarding; 2513 #endif 2514 } 2515 2516 return false; 2517 } 2518 #else 2519 static void 2520 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2521 { 2522 } 2523 #endif 2524 2525 static bool 2526 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2527 { 2528 if_ctx_t ctx = rxq->ifr_ctx; 2529 if_shared_ctx_t sctx = ctx->ifc_sctx; 2530 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2531 int avail, i; 2532 qidx_t *cidxp; 2533 struct if_rxd_info ri; 2534 int err, budget_left, rx_bytes, rx_pkts; 2535 iflib_fl_t fl; 2536 struct ifnet *ifp; 2537 int lro_enabled; 2538 bool lro_possible = false; 2539 bool v4_forwarding, v6_forwarding; 2540 2541 /* 2542 * XXX early demux data packets so that if_input processing only handles 2543 * acks in interrupt context 2544 */ 2545 struct mbuf *m, *mh, *mt, *mf; 2546 2547 ifp = ctx->ifc_ifp; 2548 mh = mt = NULL; 2549 MPASS(budget > 0); 2550 rx_pkts = rx_bytes = 0; 2551 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2552 cidxp = &rxq->ifr_cq_cidx; 2553 else 2554 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2555 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2556 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2557 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2558 DBG_COUNTER_INC(rx_unavail); 2559 return (false); 2560 } 2561 2562 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2563 if (__predict_false(!CTX_ACTIVE(ctx))) { 2564 DBG_COUNTER_INC(rx_ctx_inactive); 2565 break; 2566 } 2567 /* 2568 * Reset client set fields to their default values 2569 */ 2570 rxd_info_zero(&ri); 2571 ri.iri_qsidx = rxq->ifr_id; 2572 ri.iri_cidx = *cidxp; 2573 ri.iri_ifp = ifp; 2574 ri.iri_frags = rxq->ifr_frags; 2575 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2576 2577 if (err) 2578 goto err; 2579 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2580 *cidxp = ri.iri_cidx; 2581 /* Update our consumer index */ 2582 /* XXX NB: shurd - check if this is still safe */ 2583 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2584 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2585 rxq->ifr_cq_gen = 0; 2586 } 2587 /* was this only a completion queue message? */ 2588 if (__predict_false(ri.iri_nfrags == 0)) 2589 continue; 2590 } 2591 MPASS(ri.iri_nfrags != 0); 2592 MPASS(ri.iri_len != 0); 2593 2594 /* will advance the cidx on the corresponding free lists */ 2595 m = iflib_rxd_pkt_get(rxq, &ri); 2596 if (avail == 0 && budget_left) 2597 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2598 2599 if (__predict_false(m == NULL)) { 2600 DBG_COUNTER_INC(rx_mbuf_null); 2601 continue; 2602 } 2603 /* imm_pkt: -- cxgb */ 2604 if (mh == NULL) 2605 mh = mt = m; 2606 else { 2607 mt->m_nextpkt = m; 2608 mt = m; 2609 } 2610 } 2611 /* make sure that we can refill faster than drain */ 2612 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2613 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2614 2615 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2616 if (lro_enabled) 2617 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2618 mt = mf = NULL; 2619 while (mh != NULL) { 2620 m = mh; 2621 mh = mh->m_nextpkt; 2622 m->m_nextpkt = NULL; 2623 #ifndef __NO_STRICT_ALIGNMENT 2624 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2625 continue; 2626 #endif 2627 rx_bytes += m->m_pkthdr.len; 2628 rx_pkts++; 2629 #if defined(INET6) || defined(INET) 2630 if (lro_enabled) { 2631 if (!lro_possible) { 2632 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2633 if (lro_possible && mf != NULL) { 2634 ifp->if_input(ifp, mf); 2635 DBG_COUNTER_INC(rx_if_input); 2636 mt = mf = NULL; 2637 } 2638 } 2639 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2640 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2641 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2642 continue; 2643 } 2644 } 2645 #endif 2646 if (lro_possible) { 2647 ifp->if_input(ifp, m); 2648 DBG_COUNTER_INC(rx_if_input); 2649 continue; 2650 } 2651 2652 if (mf == NULL) 2653 mf = m; 2654 if (mt != NULL) 2655 mt->m_nextpkt = m; 2656 mt = m; 2657 } 2658 if (mf != NULL) { 2659 ifp->if_input(ifp, mf); 2660 DBG_COUNTER_INC(rx_if_input); 2661 } 2662 2663 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2664 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2665 2666 /* 2667 * Flush any outstanding LRO work 2668 */ 2669 #if defined(INET6) || defined(INET) 2670 tcp_lro_flush_all(&rxq->ifr_lc); 2671 #endif 2672 if (avail) 2673 return true; 2674 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2675 err: 2676 CTX_LOCK(ctx); 2677 ctx->ifc_flags |= IFC_DO_RESET; 2678 iflib_admin_intr_deferred(ctx); 2679 CTX_UNLOCK(ctx); 2680 return (false); 2681 } 2682 2683 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2684 static inline qidx_t 2685 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2686 { 2687 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2688 qidx_t minthresh = txq->ift_size / 8; 2689 if (in_use > 4*minthresh) 2690 return (notify_count); 2691 if (in_use > 2*minthresh) 2692 return (notify_count >> 1); 2693 if (in_use > minthresh) 2694 return (notify_count >> 3); 2695 return (0); 2696 } 2697 2698 static inline qidx_t 2699 txq_max_rs_deferred(iflib_txq_t txq) 2700 { 2701 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2702 qidx_t minthresh = txq->ift_size / 8; 2703 if (txq->ift_in_use > 4*minthresh) 2704 return (notify_count); 2705 if (txq->ift_in_use > 2*minthresh) 2706 return (notify_count >> 1); 2707 if (txq->ift_in_use > minthresh) 2708 return (notify_count >> 2); 2709 return (2); 2710 } 2711 2712 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2713 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2714 2715 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2716 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2717 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2718 2719 /* forward compatibility for cxgb */ 2720 #define FIRST_QSET(ctx) 0 2721 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2722 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2723 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2724 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2725 2726 /* XXX we should be setting this to something other than zero */ 2727 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2728 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2729 2730 static inline bool 2731 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2732 { 2733 qidx_t dbval, max; 2734 bool rang; 2735 2736 rang = false; 2737 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2738 if (ring || txq->ift_db_pending >= max) { 2739 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2740 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2741 txq->ift_db_pending = txq->ift_npending = 0; 2742 rang = true; 2743 } 2744 return (rang); 2745 } 2746 2747 #ifdef PKT_DEBUG 2748 static void 2749 print_pkt(if_pkt_info_t pi) 2750 { 2751 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2752 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2753 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2754 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2755 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2756 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2757 } 2758 #endif 2759 2760 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2761 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2762 2763 static int 2764 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2765 { 2766 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2767 struct ether_vlan_header *eh; 2768 struct mbuf *m, *n; 2769 2770 n = m = *mp; 2771 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2772 M_WRITABLE(m) == 0) { 2773 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2774 return (ENOMEM); 2775 } else { 2776 m_freem(*mp); 2777 n = *mp = m; 2778 } 2779 } 2780 2781 /* 2782 * Determine where frame payload starts. 2783 * Jump over vlan headers if already present, 2784 * helpful for QinQ too. 2785 */ 2786 if (__predict_false(m->m_len < sizeof(*eh))) { 2787 txq->ift_pullups++; 2788 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2789 return (ENOMEM); 2790 } 2791 eh = mtod(m, struct ether_vlan_header *); 2792 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2793 pi->ipi_etype = ntohs(eh->evl_proto); 2794 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2795 } else { 2796 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2797 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2798 } 2799 2800 switch (pi->ipi_etype) { 2801 #ifdef INET 2802 case ETHERTYPE_IP: 2803 { 2804 struct ip *ip = NULL; 2805 struct tcphdr *th = NULL; 2806 int minthlen; 2807 2808 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2809 if (__predict_false(m->m_len < minthlen)) { 2810 /* 2811 * if this code bloat is causing too much of a hit 2812 * move it to a separate function and mark it noinline 2813 */ 2814 if (m->m_len == pi->ipi_ehdrlen) { 2815 n = m->m_next; 2816 MPASS(n); 2817 if (n->m_len >= sizeof(*ip)) { 2818 ip = (struct ip *)n->m_data; 2819 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2820 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2821 } else { 2822 txq->ift_pullups++; 2823 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2824 return (ENOMEM); 2825 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2826 } 2827 } else { 2828 txq->ift_pullups++; 2829 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2830 return (ENOMEM); 2831 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2832 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2833 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2834 } 2835 } else { 2836 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2837 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2838 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2839 } 2840 pi->ipi_ip_hlen = ip->ip_hl << 2; 2841 pi->ipi_ipproto = ip->ip_p; 2842 pi->ipi_flags |= IPI_TX_IPV4; 2843 2844 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2845 ip->ip_sum = 0; 2846 2847 if (IS_TSO4(pi)) { 2848 if (pi->ipi_ipproto == IPPROTO_TCP) { 2849 if (__predict_false(th == NULL)) { 2850 txq->ift_pullups++; 2851 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2852 return (ENOMEM); 2853 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2854 } 2855 pi->ipi_tcp_hflags = th->th_flags; 2856 pi->ipi_tcp_hlen = th->th_off << 2; 2857 pi->ipi_tcp_seq = th->th_seq; 2858 } 2859 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2860 return (ENXIO); 2861 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2862 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2863 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2864 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2865 ip->ip_sum = 0; 2866 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2867 } 2868 } 2869 break; 2870 } 2871 #endif 2872 #ifdef INET6 2873 case ETHERTYPE_IPV6: 2874 { 2875 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2876 struct tcphdr *th; 2877 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2878 2879 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2880 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2881 return (ENOMEM); 2882 } 2883 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2884 2885 /* XXX-BZ this will go badly in case of ext hdrs. */ 2886 pi->ipi_ipproto = ip6->ip6_nxt; 2887 pi->ipi_flags |= IPI_TX_IPV6; 2888 2889 if (IS_TSO6(pi)) { 2890 if (pi->ipi_ipproto == IPPROTO_TCP) { 2891 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2892 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2893 return (ENOMEM); 2894 } 2895 pi->ipi_tcp_hflags = th->th_flags; 2896 pi->ipi_tcp_hlen = th->th_off << 2; 2897 } 2898 2899 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2900 return (ENXIO); 2901 /* 2902 * The corresponding flag is set by the stack in the IPv4 2903 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2904 * So, set it here because the rest of the flow requires it. 2905 */ 2906 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2907 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2908 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2909 } 2910 break; 2911 } 2912 #endif 2913 default: 2914 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2915 pi->ipi_ip_hlen = 0; 2916 break; 2917 } 2918 *mp = m; 2919 2920 return (0); 2921 } 2922 2923 static __noinline struct mbuf * 2924 collapse_pkthdr(struct mbuf *m0) 2925 { 2926 struct mbuf *m, *m_next, *tmp; 2927 2928 m = m0; 2929 m_next = m->m_next; 2930 while (m_next != NULL && m_next->m_len == 0) { 2931 m = m_next; 2932 m->m_next = NULL; 2933 m_free(m); 2934 m_next = m_next->m_next; 2935 } 2936 m = m0; 2937 m->m_next = m_next; 2938 if ((m_next->m_flags & M_EXT) == 0) { 2939 m = m_defrag(m, M_NOWAIT); 2940 } else { 2941 tmp = m_next->m_next; 2942 memcpy(m_next, m, MPKTHSIZE); 2943 m = m_next; 2944 m->m_next = tmp; 2945 } 2946 return (m); 2947 } 2948 2949 /* 2950 * If dodgy hardware rejects the scatter gather chain we've handed it 2951 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2952 * m_defrag'd mbufs 2953 */ 2954 static __noinline struct mbuf * 2955 iflib_remove_mbuf(iflib_txq_t txq) 2956 { 2957 int ntxd, i, pidx; 2958 struct mbuf *m, *mh, **ifsd_m; 2959 2960 pidx = txq->ift_pidx; 2961 ifsd_m = txq->ift_sds.ifsd_m; 2962 ntxd = txq->ift_size; 2963 mh = m = ifsd_m[pidx]; 2964 ifsd_m[pidx] = NULL; 2965 #if MEMORY_LOGGING 2966 txq->ift_dequeued++; 2967 #endif 2968 i = 1; 2969 2970 while (m) { 2971 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2972 #if MEMORY_LOGGING 2973 txq->ift_dequeued++; 2974 #endif 2975 m = m->m_next; 2976 i++; 2977 } 2978 return (mh); 2979 } 2980 2981 static int 2982 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2983 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2984 int max_segs, int flags) 2985 { 2986 if_ctx_t ctx; 2987 if_shared_ctx_t sctx; 2988 if_softc_ctx_t scctx; 2989 int i, next, pidx, err, ntxd, count; 2990 struct mbuf *m, *tmp, **ifsd_m; 2991 2992 m = *m0; 2993 2994 /* 2995 * Please don't ever do this 2996 */ 2997 if (__predict_false(m->m_len == 0)) 2998 *m0 = m = collapse_pkthdr(m); 2999 3000 ctx = txq->ift_ctx; 3001 sctx = ctx->ifc_sctx; 3002 scctx = &ctx->ifc_softc_ctx; 3003 ifsd_m = txq->ift_sds.ifsd_m; 3004 ntxd = txq->ift_size; 3005 pidx = txq->ift_pidx; 3006 if (map != NULL) { 3007 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3008 3009 err = bus_dmamap_load_mbuf_sg(tag, map, 3010 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3011 if (err) 3012 return (err); 3013 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3014 count = 0; 3015 m = *m0; 3016 do { 3017 if (__predict_false(m->m_len <= 0)) { 3018 tmp = m; 3019 m = m->m_next; 3020 tmp->m_next = NULL; 3021 m_free(tmp); 3022 continue; 3023 } 3024 m = m->m_next; 3025 count++; 3026 } while (m != NULL); 3027 if (count > *nsegs) { 3028 ifsd_m[pidx] = *m0; 3029 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3030 return (0); 3031 } 3032 m = *m0; 3033 count = 0; 3034 do { 3035 next = (pidx + count) & (ntxd-1); 3036 MPASS(ifsd_m[next] == NULL); 3037 ifsd_m[next] = m; 3038 count++; 3039 tmp = m; 3040 m = m->m_next; 3041 } while (m != NULL); 3042 } else { 3043 int buflen, sgsize, maxsegsz, max_sgsize; 3044 vm_offset_t vaddr; 3045 vm_paddr_t curaddr; 3046 3047 count = i = 0; 3048 m = *m0; 3049 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3050 maxsegsz = scctx->isc_tx_tso_segsize_max; 3051 else 3052 maxsegsz = sctx->isc_tx_maxsegsize; 3053 3054 do { 3055 if (__predict_false(m->m_len <= 0)) { 3056 tmp = m; 3057 m = m->m_next; 3058 tmp->m_next = NULL; 3059 m_free(tmp); 3060 continue; 3061 } 3062 buflen = m->m_len; 3063 vaddr = (vm_offset_t)m->m_data; 3064 /* 3065 * see if we can't be smarter about physically 3066 * contiguous mappings 3067 */ 3068 next = (pidx + count) & (ntxd-1); 3069 MPASS(ifsd_m[next] == NULL); 3070 #if MEMORY_LOGGING 3071 txq->ift_enqueued++; 3072 #endif 3073 ifsd_m[next] = m; 3074 while (buflen > 0) { 3075 if (i >= max_segs) 3076 goto err; 3077 max_sgsize = MIN(buflen, maxsegsz); 3078 curaddr = pmap_kextract(vaddr); 3079 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3080 sgsize = MIN(sgsize, max_sgsize); 3081 segs[i].ds_addr = curaddr; 3082 segs[i].ds_len = sgsize; 3083 vaddr += sgsize; 3084 buflen -= sgsize; 3085 i++; 3086 } 3087 count++; 3088 tmp = m; 3089 m = m->m_next; 3090 } while (m != NULL); 3091 *nsegs = i; 3092 } 3093 return (0); 3094 err: 3095 *m0 = iflib_remove_mbuf(txq); 3096 return (EFBIG); 3097 } 3098 3099 static inline caddr_t 3100 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3101 { 3102 qidx_t size; 3103 int ntxd; 3104 caddr_t start, end, cur, next; 3105 3106 ntxd = txq->ift_size; 3107 size = txq->ift_txd_size[qid]; 3108 start = txq->ift_ifdi[qid].idi_vaddr; 3109 3110 if (__predict_false(size == 0)) 3111 return (start); 3112 cur = start + size*cidx; 3113 end = start + size*ntxd; 3114 next = CACHE_PTR_NEXT(cur); 3115 return (next < end ? next : start); 3116 } 3117 3118 /* 3119 * Pad an mbuf to ensure a minimum ethernet frame size. 3120 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3121 */ 3122 static __noinline int 3123 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3124 { 3125 /* 3126 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3127 * and ARP message is the smallest common payload I can think of 3128 */ 3129 static char pad[18]; /* just zeros */ 3130 int n; 3131 struct mbuf *new_head; 3132 3133 if (!M_WRITABLE(*m_head)) { 3134 new_head = m_dup(*m_head, M_NOWAIT); 3135 if (new_head == NULL) { 3136 m_freem(*m_head); 3137 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3138 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3139 return ENOMEM; 3140 } 3141 m_freem(*m_head); 3142 *m_head = new_head; 3143 } 3144 3145 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3146 n > 0; n -= sizeof(pad)) 3147 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3148 break; 3149 3150 if (n > 0) { 3151 m_freem(*m_head); 3152 device_printf(dev, "cannot pad short frame\n"); 3153 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3154 return (ENOBUFS); 3155 } 3156 3157 return 0; 3158 } 3159 3160 static int 3161 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3162 { 3163 if_ctx_t ctx; 3164 if_shared_ctx_t sctx; 3165 if_softc_ctx_t scctx; 3166 bus_dma_segment_t *segs; 3167 struct mbuf *m_head; 3168 void *next_txd; 3169 bus_dmamap_t map; 3170 struct if_pkt_info pi; 3171 int remap = 0; 3172 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3173 bus_dma_tag_t desc_tag; 3174 3175 segs = txq->ift_segs; 3176 ctx = txq->ift_ctx; 3177 sctx = ctx->ifc_sctx; 3178 scctx = &ctx->ifc_softc_ctx; 3179 segs = txq->ift_segs; 3180 ntxd = txq->ift_size; 3181 m_head = *m_headp; 3182 map = NULL; 3183 3184 /* 3185 * If we're doing TSO the next descriptor to clean may be quite far ahead 3186 */ 3187 cidx = txq->ift_cidx; 3188 pidx = txq->ift_pidx; 3189 if (ctx->ifc_flags & IFC_PREFETCH) { 3190 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3191 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3192 next_txd = calc_next_txd(txq, cidx, 0); 3193 prefetch(next_txd); 3194 } 3195 3196 /* prefetch the next cache line of mbuf pointers and flags */ 3197 prefetch(&txq->ift_sds.ifsd_m[next]); 3198 if (txq->ift_sds.ifsd_map != NULL) { 3199 prefetch(&txq->ift_sds.ifsd_map[next]); 3200 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3201 prefetch(&txq->ift_sds.ifsd_flags[next]); 3202 } 3203 } else if (txq->ift_sds.ifsd_map != NULL) 3204 map = txq->ift_sds.ifsd_map[pidx]; 3205 3206 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3207 desc_tag = txq->ift_tso_desc_tag; 3208 max_segs = scctx->isc_tx_tso_segments_max; 3209 } else { 3210 desc_tag = txq->ift_desc_tag; 3211 max_segs = scctx->isc_tx_nsegments; 3212 } 3213 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3214 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3215 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3216 if (err) 3217 return err; 3218 } 3219 m_head = *m_headp; 3220 3221 pkt_info_zero(&pi); 3222 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3223 pi.ipi_pidx = pidx; 3224 pi.ipi_qsidx = txq->ift_id; 3225 pi.ipi_len = m_head->m_pkthdr.len; 3226 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3227 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3228 3229 /* deliberate bitwise OR to make one condition */ 3230 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3231 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3232 return (err); 3233 m_head = *m_headp; 3234 } 3235 3236 retry: 3237 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3238 defrag: 3239 if (__predict_false(err)) { 3240 switch (err) { 3241 case EFBIG: 3242 /* try collapse once and defrag once */ 3243 if (remap == 0) 3244 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3245 if (remap == 1) 3246 m_head = m_defrag(*m_headp, M_NOWAIT); 3247 remap++; 3248 if (__predict_false(m_head == NULL)) 3249 goto defrag_failed; 3250 txq->ift_mbuf_defrag++; 3251 *m_headp = m_head; 3252 goto retry; 3253 break; 3254 case ENOMEM: 3255 txq->ift_no_tx_dma_setup++; 3256 break; 3257 default: 3258 txq->ift_no_tx_dma_setup++; 3259 m_freem(*m_headp); 3260 DBG_COUNTER_INC(tx_frees); 3261 *m_headp = NULL; 3262 break; 3263 } 3264 txq->ift_map_failed++; 3265 DBG_COUNTER_INC(encap_load_mbuf_fail); 3266 return (err); 3267 } 3268 3269 /* 3270 * XXX assumes a 1 to 1 relationship between segments and 3271 * descriptors - this does not hold true on all drivers, e.g. 3272 * cxgb 3273 */ 3274 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3275 txq->ift_no_desc_avail++; 3276 if (map != NULL) 3277 bus_dmamap_unload(desc_tag, map); 3278 DBG_COUNTER_INC(encap_txq_avail_fail); 3279 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3280 GROUPTASK_ENQUEUE(&txq->ift_task); 3281 return (ENOBUFS); 3282 } 3283 /* 3284 * On Intel cards we can greatly reduce the number of TX interrupts 3285 * we see by only setting report status on every Nth descriptor. 3286 * However, this also means that the driver will need to keep track 3287 * of the descriptors that RS was set on to check them for the DD bit. 3288 */ 3289 txq->ift_rs_pending += nsegs + 1; 3290 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3291 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3292 pi.ipi_flags |= IPI_TX_INTR; 3293 txq->ift_rs_pending = 0; 3294 } 3295 3296 pi.ipi_segs = segs; 3297 pi.ipi_nsegs = nsegs; 3298 3299 MPASS(pidx >= 0 && pidx < txq->ift_size); 3300 #ifdef PKT_DEBUG 3301 print_pkt(&pi); 3302 #endif 3303 if (map != NULL) 3304 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3305 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3306 if (map != NULL) 3307 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3308 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3309 DBG_COUNTER_INC(tx_encap); 3310 MPASS(pi.ipi_new_pidx < txq->ift_size); 3311 3312 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3313 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3314 ndesc += txq->ift_size; 3315 txq->ift_gen = 1; 3316 } 3317 /* 3318 * drivers can need as many as 3319 * two sentinels 3320 */ 3321 MPASS(ndesc <= pi.ipi_nsegs + 2); 3322 MPASS(pi.ipi_new_pidx != pidx); 3323 MPASS(ndesc > 0); 3324 txq->ift_in_use += ndesc; 3325 3326 /* 3327 * We update the last software descriptor again here because there may 3328 * be a sentinel and/or there may be more mbufs than segments 3329 */ 3330 txq->ift_pidx = pi.ipi_new_pidx; 3331 txq->ift_npending += pi.ipi_ndescs; 3332 } else if (__predict_false(err == EFBIG && remap < 2)) { 3333 *m_headp = m_head = iflib_remove_mbuf(txq); 3334 remap = 1; 3335 txq->ift_txd_encap_efbig++; 3336 goto defrag; 3337 } else 3338 DBG_COUNTER_INC(encap_txd_encap_fail); 3339 return (err); 3340 3341 defrag_failed: 3342 txq->ift_mbuf_defrag_failed++; 3343 txq->ift_map_failed++; 3344 m_freem(*m_headp); 3345 DBG_COUNTER_INC(tx_frees); 3346 *m_headp = NULL; 3347 return (ENOMEM); 3348 } 3349 3350 static void 3351 iflib_tx_desc_free(iflib_txq_t txq, int n) 3352 { 3353 int hasmap; 3354 uint32_t qsize, cidx, mask, gen; 3355 struct mbuf *m, **ifsd_m; 3356 uint8_t *ifsd_flags; 3357 bus_dmamap_t *ifsd_map; 3358 bool do_prefetch; 3359 3360 cidx = txq->ift_cidx; 3361 gen = txq->ift_gen; 3362 qsize = txq->ift_size; 3363 mask = qsize-1; 3364 hasmap = txq->ift_sds.ifsd_map != NULL; 3365 ifsd_flags = txq->ift_sds.ifsd_flags; 3366 ifsd_m = txq->ift_sds.ifsd_m; 3367 ifsd_map = txq->ift_sds.ifsd_map; 3368 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3369 3370 while (n--) { 3371 if (do_prefetch) { 3372 prefetch(ifsd_m[(cidx + 3) & mask]); 3373 prefetch(ifsd_m[(cidx + 4) & mask]); 3374 } 3375 if (ifsd_m[cidx] != NULL) { 3376 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3377 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3378 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3379 /* 3380 * does it matter if it's not the TSO tag? If so we'll 3381 * have to add the type to flags 3382 */ 3383 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3384 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3385 } 3386 if ((m = ifsd_m[cidx]) != NULL) { 3387 /* XXX we don't support any drivers that batch packets yet */ 3388 MPASS(m->m_nextpkt == NULL); 3389 /* if the number of clusters exceeds the number of segments 3390 * there won't be space on the ring to save a pointer to each 3391 * cluster so we simply free the list here 3392 */ 3393 if (m->m_flags & M_TOOBIG) { 3394 m_freem(m); 3395 } else { 3396 m_free(m); 3397 } 3398 ifsd_m[cidx] = NULL; 3399 #if MEMORY_LOGGING 3400 txq->ift_dequeued++; 3401 #endif 3402 DBG_COUNTER_INC(tx_frees); 3403 } 3404 } 3405 if (__predict_false(++cidx == qsize)) { 3406 cidx = 0; 3407 gen = 0; 3408 } 3409 } 3410 txq->ift_cidx = cidx; 3411 txq->ift_gen = gen; 3412 } 3413 3414 static __inline int 3415 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3416 { 3417 int reclaim; 3418 if_ctx_t ctx = txq->ift_ctx; 3419 3420 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3421 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3422 3423 /* 3424 * Need a rate-limiting check so that this isn't called every time 3425 */ 3426 iflib_tx_credits_update(ctx, txq); 3427 reclaim = DESC_RECLAIMABLE(txq); 3428 3429 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3430 #ifdef INVARIANTS 3431 if (iflib_verbose_debug) { 3432 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3433 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3434 reclaim, thresh); 3435 3436 } 3437 #endif 3438 return (0); 3439 } 3440 iflib_tx_desc_free(txq, reclaim); 3441 txq->ift_cleaned += reclaim; 3442 txq->ift_in_use -= reclaim; 3443 3444 return (reclaim); 3445 } 3446 3447 static struct mbuf ** 3448 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3449 { 3450 int next, size; 3451 struct mbuf **items; 3452 3453 size = r->size; 3454 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3455 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3456 3457 prefetch(items[(cidx + offset) & (size-1)]); 3458 if (remaining > 1) { 3459 prefetch2cachelines(&items[next]); 3460 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3461 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3462 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3463 } 3464 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3465 } 3466 3467 static void 3468 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3469 { 3470 3471 ifmp_ring_check_drainage(txq->ift_br, budget); 3472 } 3473 3474 static uint32_t 3475 iflib_txq_can_drain(struct ifmp_ring *r) 3476 { 3477 iflib_txq_t txq = r->cookie; 3478 if_ctx_t ctx = txq->ift_ctx; 3479 3480 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3481 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3482 } 3483 3484 static uint32_t 3485 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3486 { 3487 iflib_txq_t txq = r->cookie; 3488 if_ctx_t ctx = txq->ift_ctx; 3489 struct ifnet *ifp = ctx->ifc_ifp; 3490 struct mbuf **mp, *m; 3491 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3492 int reclaimed, err, in_use_prev, desc_used; 3493 bool do_prefetch, ring, rang; 3494 3495 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3496 !LINK_ACTIVE(ctx))) { 3497 DBG_COUNTER_INC(txq_drain_notready); 3498 return (0); 3499 } 3500 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3501 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3502 avail = IDXDIFF(pidx, cidx, r->size); 3503 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3504 DBG_COUNTER_INC(txq_drain_flushing); 3505 for (i = 0; i < avail; i++) { 3506 m_free(r->items[(cidx + i) & (r->size-1)]); 3507 r->items[(cidx + i) & (r->size-1)] = NULL; 3508 } 3509 return (avail); 3510 } 3511 3512 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3513 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3514 CALLOUT_LOCK(txq); 3515 callout_stop(&txq->ift_timer); 3516 CALLOUT_UNLOCK(txq); 3517 DBG_COUNTER_INC(txq_drain_oactive); 3518 return (0); 3519 } 3520 if (reclaimed) 3521 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3522 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3523 count = MIN(avail, TX_BATCH_SIZE); 3524 #ifdef INVARIANTS 3525 if (iflib_verbose_debug) 3526 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3527 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3528 #endif 3529 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3530 avail = TXQ_AVAIL(txq); 3531 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3532 int pidx_prev, rem = do_prefetch ? count - i : 0; 3533 3534 mp = _ring_peek_one(r, cidx, i, rem); 3535 MPASS(mp != NULL && *mp != NULL); 3536 if (__predict_false(*mp == (struct mbuf *)txq)) { 3537 consumed++; 3538 reclaimed++; 3539 continue; 3540 } 3541 in_use_prev = txq->ift_in_use; 3542 pidx_prev = txq->ift_pidx; 3543 err = iflib_encap(txq, mp); 3544 if (__predict_false(err)) { 3545 DBG_COUNTER_INC(txq_drain_encapfail); 3546 /* no room - bail out */ 3547 if (err == ENOBUFS) 3548 break; 3549 consumed++; 3550 DBG_COUNTER_INC(txq_drain_encapfail); 3551 /* we can't send this packet - skip it */ 3552 continue; 3553 } 3554 consumed++; 3555 pkt_sent++; 3556 m = *mp; 3557 DBG_COUNTER_INC(tx_sent); 3558 bytes_sent += m->m_pkthdr.len; 3559 mcast_sent += !!(m->m_flags & M_MCAST); 3560 avail = TXQ_AVAIL(txq); 3561 3562 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3563 desc_used += (txq->ift_in_use - in_use_prev); 3564 ETHER_BPF_MTAP(ifp, m); 3565 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3566 break; 3567 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3568 } 3569 3570 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3571 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3572 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3573 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3574 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3575 if (mcast_sent) 3576 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3577 #ifdef INVARIANTS 3578 if (iflib_verbose_debug) 3579 printf("consumed=%d\n", consumed); 3580 #endif 3581 return (consumed); 3582 } 3583 3584 static uint32_t 3585 iflib_txq_drain_always(struct ifmp_ring *r) 3586 { 3587 return (1); 3588 } 3589 3590 static uint32_t 3591 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3592 { 3593 int i, avail; 3594 struct mbuf **mp; 3595 iflib_txq_t txq; 3596 3597 txq = r->cookie; 3598 3599 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3600 CALLOUT_LOCK(txq); 3601 callout_stop(&txq->ift_timer); 3602 CALLOUT_UNLOCK(txq); 3603 3604 avail = IDXDIFF(pidx, cidx, r->size); 3605 for (i = 0; i < avail; i++) { 3606 mp = _ring_peek_one(r, cidx, i, avail - i); 3607 if (__predict_false(*mp == (struct mbuf *)txq)) 3608 continue; 3609 m_freem(*mp); 3610 } 3611 MPASS(ifmp_ring_is_stalled(r) == 0); 3612 return (avail); 3613 } 3614 3615 static void 3616 iflib_ifmp_purge(iflib_txq_t txq) 3617 { 3618 struct ifmp_ring *r; 3619 3620 r = txq->ift_br; 3621 r->drain = iflib_txq_drain_free; 3622 r->can_drain = iflib_txq_drain_always; 3623 3624 ifmp_ring_check_drainage(r, r->size); 3625 3626 r->drain = iflib_txq_drain; 3627 r->can_drain = iflib_txq_can_drain; 3628 } 3629 3630 static void 3631 _task_fn_tx(void *context) 3632 { 3633 iflib_txq_t txq = context; 3634 if_ctx_t ctx = txq->ift_ctx; 3635 struct ifnet *ifp = ctx->ifc_ifp; 3636 int rc; 3637 3638 #ifdef IFLIB_DIAGNOSTICS 3639 txq->ift_cpu_exec_count[curcpu]++; 3640 #endif 3641 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3642 return; 3643 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3644 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3645 netmap_tx_irq(ifp, txq->ift_id); 3646 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3647 return; 3648 } 3649 if (txq->ift_db_pending) 3650 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3651 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3652 if (ctx->ifc_flags & IFC_LEGACY) 3653 IFDI_INTR_ENABLE(ctx); 3654 else { 3655 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3656 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3657 } 3658 } 3659 3660 static void 3661 _task_fn_rx(void *context) 3662 { 3663 iflib_rxq_t rxq = context; 3664 if_ctx_t ctx = rxq->ifr_ctx; 3665 bool more; 3666 int rc; 3667 uint16_t budget; 3668 3669 #ifdef IFLIB_DIAGNOSTICS 3670 rxq->ifr_cpu_exec_count[curcpu]++; 3671 #endif 3672 DBG_COUNTER_INC(task_fn_rxs); 3673 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3674 return; 3675 more = true; 3676 #ifdef DEV_NETMAP 3677 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3678 u_int work = 0; 3679 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3680 more = false; 3681 } 3682 } 3683 #endif 3684 budget = ctx->ifc_sysctl_rx_budget; 3685 if (budget == 0) 3686 budget = 16; /* XXX */ 3687 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3688 if (ctx->ifc_flags & IFC_LEGACY) 3689 IFDI_INTR_ENABLE(ctx); 3690 else { 3691 DBG_COUNTER_INC(rx_intr_enables); 3692 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3693 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3694 } 3695 } 3696 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3697 return; 3698 if (more) 3699 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3700 } 3701 3702 static void 3703 _task_fn_admin(void *context) 3704 { 3705 if_ctx_t ctx = context; 3706 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3707 iflib_txq_t txq; 3708 int i; 3709 3710 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) { 3711 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3712 return; 3713 } 3714 } 3715 3716 CTX_LOCK(ctx); 3717 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3718 CALLOUT_LOCK(txq); 3719 callout_stop(&txq->ift_timer); 3720 CALLOUT_UNLOCK(txq); 3721 } 3722 IFDI_UPDATE_ADMIN_STATUS(ctx); 3723 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3724 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3725 IFDI_LINK_INTR_ENABLE(ctx); 3726 if (ctx->ifc_flags & IFC_DO_RESET) { 3727 ctx->ifc_flags &= ~IFC_DO_RESET; 3728 iflib_if_init_locked(ctx); 3729 } 3730 CTX_UNLOCK(ctx); 3731 3732 if (LINK_ACTIVE(ctx) == 0) 3733 return; 3734 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3735 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3736 } 3737 3738 3739 static void 3740 _task_fn_iov(void *context) 3741 { 3742 if_ctx_t ctx = context; 3743 3744 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3745 return; 3746 3747 CTX_LOCK(ctx); 3748 IFDI_VFLR_HANDLE(ctx); 3749 CTX_UNLOCK(ctx); 3750 } 3751 3752 static int 3753 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3754 { 3755 int err; 3756 if_int_delay_info_t info; 3757 if_ctx_t ctx; 3758 3759 info = (if_int_delay_info_t)arg1; 3760 ctx = info->iidi_ctx; 3761 info->iidi_req = req; 3762 info->iidi_oidp = oidp; 3763 CTX_LOCK(ctx); 3764 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3765 CTX_UNLOCK(ctx); 3766 return (err); 3767 } 3768 3769 /********************************************************************* 3770 * 3771 * IFNET FUNCTIONS 3772 * 3773 **********************************************************************/ 3774 3775 static void 3776 iflib_if_init_locked(if_ctx_t ctx) 3777 { 3778 iflib_stop(ctx); 3779 iflib_init_locked(ctx); 3780 } 3781 3782 3783 static void 3784 iflib_if_init(void *arg) 3785 { 3786 if_ctx_t ctx = arg; 3787 3788 CTX_LOCK(ctx); 3789 iflib_if_init_locked(ctx); 3790 CTX_UNLOCK(ctx); 3791 } 3792 3793 static int 3794 iflib_if_transmit(if_t ifp, struct mbuf *m) 3795 { 3796 if_ctx_t ctx = if_getsoftc(ifp); 3797 3798 iflib_txq_t txq; 3799 int err, qidx; 3800 3801 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3802 DBG_COUNTER_INC(tx_frees); 3803 m_freem(m); 3804 return (ENOBUFS); 3805 } 3806 3807 MPASS(m->m_nextpkt == NULL); 3808 qidx = 0; 3809 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3810 qidx = QIDX(ctx, m); 3811 /* 3812 * XXX calculate buf_ring based on flowid (divvy up bits?) 3813 */ 3814 txq = &ctx->ifc_txqs[qidx]; 3815 3816 #ifdef DRIVER_BACKPRESSURE 3817 if (txq->ift_closed) { 3818 while (m != NULL) { 3819 next = m->m_nextpkt; 3820 m->m_nextpkt = NULL; 3821 m_freem(m); 3822 m = next; 3823 } 3824 return (ENOBUFS); 3825 } 3826 #endif 3827 #ifdef notyet 3828 qidx = count = 0; 3829 mp = marr; 3830 next = m; 3831 do { 3832 count++; 3833 next = next->m_nextpkt; 3834 } while (next != NULL); 3835 3836 if (count > nitems(marr)) 3837 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3838 /* XXX check nextpkt */ 3839 m_freem(m); 3840 /* XXX simplify for now */ 3841 DBG_COUNTER_INC(tx_frees); 3842 return (ENOBUFS); 3843 } 3844 for (next = m, i = 0; next != NULL; i++) { 3845 mp[i] = next; 3846 next = next->m_nextpkt; 3847 mp[i]->m_nextpkt = NULL; 3848 } 3849 #endif 3850 DBG_COUNTER_INC(tx_seen); 3851 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3852 3853 GROUPTASK_ENQUEUE(&txq->ift_task); 3854 if (err) { 3855 /* support forthcoming later */ 3856 #ifdef DRIVER_BACKPRESSURE 3857 txq->ift_closed = TRUE; 3858 #endif 3859 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3860 m_freem(m); 3861 } 3862 3863 return (err); 3864 } 3865 3866 static void 3867 iflib_if_qflush(if_t ifp) 3868 { 3869 if_ctx_t ctx = if_getsoftc(ifp); 3870 iflib_txq_t txq = ctx->ifc_txqs; 3871 int i; 3872 3873 CTX_LOCK(ctx); 3874 ctx->ifc_flags |= IFC_QFLUSH; 3875 CTX_UNLOCK(ctx); 3876 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3877 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3878 iflib_txq_check_drain(txq, 0); 3879 CTX_LOCK(ctx); 3880 ctx->ifc_flags &= ~IFC_QFLUSH; 3881 CTX_UNLOCK(ctx); 3882 3883 if_qflush(ifp); 3884 } 3885 3886 3887 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3888 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3889 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3890 3891 static int 3892 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3893 { 3894 if_ctx_t ctx = if_getsoftc(ifp); 3895 struct ifreq *ifr = (struct ifreq *)data; 3896 #if defined(INET) || defined(INET6) 3897 struct ifaddr *ifa = (struct ifaddr *)data; 3898 #endif 3899 bool avoid_reset = FALSE; 3900 int err = 0, reinit = 0, bits; 3901 3902 switch (command) { 3903 case SIOCSIFADDR: 3904 #ifdef INET 3905 if (ifa->ifa_addr->sa_family == AF_INET) 3906 avoid_reset = TRUE; 3907 #endif 3908 #ifdef INET6 3909 if (ifa->ifa_addr->sa_family == AF_INET6) 3910 avoid_reset = TRUE; 3911 #endif 3912 /* 3913 ** Calling init results in link renegotiation, 3914 ** so we avoid doing it when possible. 3915 */ 3916 if (avoid_reset) { 3917 if_setflagbits(ifp, IFF_UP,0); 3918 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3919 reinit = 1; 3920 #ifdef INET 3921 if (!(if_getflags(ifp) & IFF_NOARP)) 3922 arp_ifinit(ifp, ifa); 3923 #endif 3924 } else 3925 err = ether_ioctl(ifp, command, data); 3926 break; 3927 case SIOCSIFMTU: 3928 CTX_LOCK(ctx); 3929 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3930 CTX_UNLOCK(ctx); 3931 break; 3932 } 3933 bits = if_getdrvflags(ifp); 3934 /* stop the driver and free any clusters before proceeding */ 3935 iflib_stop(ctx); 3936 3937 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3938 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3939 ctx->ifc_flags |= IFC_MULTISEG; 3940 else 3941 ctx->ifc_flags &= ~IFC_MULTISEG; 3942 err = if_setmtu(ifp, ifr->ifr_mtu); 3943 } 3944 iflib_init_locked(ctx); 3945 if_setdrvflags(ifp, bits); 3946 CTX_UNLOCK(ctx); 3947 break; 3948 case SIOCSIFFLAGS: 3949 CTX_LOCK(ctx); 3950 if (if_getflags(ifp) & IFF_UP) { 3951 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3952 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3953 (IFF_PROMISC | IFF_ALLMULTI)) { 3954 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3955 } 3956 } else 3957 reinit = 1; 3958 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3959 iflib_stop(ctx); 3960 } 3961 ctx->ifc_if_flags = if_getflags(ifp); 3962 CTX_UNLOCK(ctx); 3963 break; 3964 case SIOCADDMULTI: 3965 case SIOCDELMULTI: 3966 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3967 CTX_LOCK(ctx); 3968 IFDI_INTR_DISABLE(ctx); 3969 IFDI_MULTI_SET(ctx); 3970 IFDI_INTR_ENABLE(ctx); 3971 CTX_UNLOCK(ctx); 3972 } 3973 break; 3974 case SIOCSIFMEDIA: 3975 CTX_LOCK(ctx); 3976 IFDI_MEDIA_SET(ctx); 3977 CTX_UNLOCK(ctx); 3978 /* falls thru */ 3979 case SIOCGIFMEDIA: 3980 case SIOCGIFXMEDIA: 3981 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3982 break; 3983 case SIOCGI2C: 3984 { 3985 struct ifi2creq i2c; 3986 3987 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 3988 if (err != 0) 3989 break; 3990 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3991 err = EINVAL; 3992 break; 3993 } 3994 if (i2c.len > sizeof(i2c.data)) { 3995 err = EINVAL; 3996 break; 3997 } 3998 3999 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4000 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 4001 break; 4002 } 4003 case SIOCSIFCAP: 4004 { 4005 int mask, setmask; 4006 4007 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4008 setmask = 0; 4009 #ifdef TCP_OFFLOAD 4010 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4011 #endif 4012 setmask |= (mask & IFCAP_FLAGS); 4013 4014 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4015 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4016 if ((mask & IFCAP_WOL) && 4017 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4018 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4019 if_vlancap(ifp); 4020 /* 4021 * want to ensure that traffic has stopped before we change any of the flags 4022 */ 4023 if (setmask) { 4024 CTX_LOCK(ctx); 4025 bits = if_getdrvflags(ifp); 4026 if (bits & IFF_DRV_RUNNING) 4027 iflib_stop(ctx); 4028 if_togglecapenable(ifp, setmask); 4029 if (bits & IFF_DRV_RUNNING) 4030 iflib_init_locked(ctx); 4031 if_setdrvflags(ifp, bits); 4032 CTX_UNLOCK(ctx); 4033 } 4034 break; 4035 } 4036 case SIOCGPRIVATE_0: 4037 case SIOCSDRVSPEC: 4038 case SIOCGDRVSPEC: 4039 CTX_LOCK(ctx); 4040 err = IFDI_PRIV_IOCTL(ctx, command, data); 4041 CTX_UNLOCK(ctx); 4042 break; 4043 default: 4044 err = ether_ioctl(ifp, command, data); 4045 break; 4046 } 4047 if (reinit) 4048 iflib_if_init(ctx); 4049 return (err); 4050 } 4051 4052 static uint64_t 4053 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4054 { 4055 if_ctx_t ctx = if_getsoftc(ifp); 4056 4057 return (IFDI_GET_COUNTER(ctx, cnt)); 4058 } 4059 4060 /********************************************************************* 4061 * 4062 * OTHER FUNCTIONS EXPORTED TO THE STACK 4063 * 4064 **********************************************************************/ 4065 4066 static void 4067 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4068 { 4069 if_ctx_t ctx = if_getsoftc(ifp); 4070 4071 if ((void *)ctx != arg) 4072 return; 4073 4074 if ((vtag == 0) || (vtag > 4095)) 4075 return; 4076 4077 CTX_LOCK(ctx); 4078 IFDI_VLAN_REGISTER(ctx, vtag); 4079 /* Re-init to load the changes */ 4080 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4081 iflib_if_init_locked(ctx); 4082 CTX_UNLOCK(ctx); 4083 } 4084 4085 static void 4086 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4087 { 4088 if_ctx_t ctx = if_getsoftc(ifp); 4089 4090 if ((void *)ctx != arg) 4091 return; 4092 4093 if ((vtag == 0) || (vtag > 4095)) 4094 return; 4095 4096 CTX_LOCK(ctx); 4097 IFDI_VLAN_UNREGISTER(ctx, vtag); 4098 /* Re-init to load the changes */ 4099 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4100 iflib_if_init_locked(ctx); 4101 CTX_UNLOCK(ctx); 4102 } 4103 4104 static void 4105 iflib_led_func(void *arg, int onoff) 4106 { 4107 if_ctx_t ctx = arg; 4108 4109 CTX_LOCK(ctx); 4110 IFDI_LED_FUNC(ctx, onoff); 4111 CTX_UNLOCK(ctx); 4112 } 4113 4114 /********************************************************************* 4115 * 4116 * BUS FUNCTION DEFINITIONS 4117 * 4118 **********************************************************************/ 4119 4120 int 4121 iflib_device_probe(device_t dev) 4122 { 4123 pci_vendor_info_t *ent; 4124 4125 uint16_t pci_vendor_id, pci_device_id; 4126 uint16_t pci_subvendor_id, pci_subdevice_id; 4127 uint16_t pci_rev_id; 4128 if_shared_ctx_t sctx; 4129 4130 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4131 return (ENOTSUP); 4132 4133 pci_vendor_id = pci_get_vendor(dev); 4134 pci_device_id = pci_get_device(dev); 4135 pci_subvendor_id = pci_get_subvendor(dev); 4136 pci_subdevice_id = pci_get_subdevice(dev); 4137 pci_rev_id = pci_get_revid(dev); 4138 if (sctx->isc_parse_devinfo != NULL) 4139 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4140 4141 ent = sctx->isc_vendor_info; 4142 while (ent->pvi_vendor_id != 0) { 4143 if (pci_vendor_id != ent->pvi_vendor_id) { 4144 ent++; 4145 continue; 4146 } 4147 if ((pci_device_id == ent->pvi_device_id) && 4148 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4149 (ent->pvi_subvendor_id == 0)) && 4150 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4151 (ent->pvi_subdevice_id == 0)) && 4152 ((pci_rev_id == ent->pvi_rev_id) || 4153 (ent->pvi_rev_id == 0))) { 4154 4155 device_set_desc_copy(dev, ent->pvi_name); 4156 /* this needs to be changed to zero if the bus probing code 4157 * ever stops re-probing on best match because the sctx 4158 * may have its values over written by register calls 4159 * in subsequent probes 4160 */ 4161 return (BUS_PROBE_DEFAULT); 4162 } 4163 ent++; 4164 } 4165 return (ENXIO); 4166 } 4167 4168 int 4169 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4170 { 4171 int err, rid, msix, msix_bar; 4172 if_ctx_t ctx; 4173 if_t ifp; 4174 if_softc_ctx_t scctx; 4175 int i; 4176 uint16_t main_txq; 4177 uint16_t main_rxq; 4178 4179 4180 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4181 4182 if (sc == NULL) { 4183 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4184 device_set_softc(dev, ctx); 4185 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4186 } 4187 4188 ctx->ifc_sctx = sctx; 4189 ctx->ifc_dev = dev; 4190 ctx->ifc_softc = sc; 4191 4192 if ((err = iflib_register(ctx)) != 0) { 4193 device_printf(dev, "iflib_register failed %d\n", err); 4194 return (err); 4195 } 4196 iflib_add_device_sysctl_pre(ctx); 4197 4198 scctx = &ctx->ifc_softc_ctx; 4199 ifp = ctx->ifc_ifp; 4200 4201 /* 4202 * XXX sanity check that ntxd & nrxd are a power of 2 4203 */ 4204 if (ctx->ifc_sysctl_ntxqs != 0) 4205 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4206 if (ctx->ifc_sysctl_nrxqs != 0) 4207 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4208 4209 for (i = 0; i < sctx->isc_ntxqs; i++) { 4210 if (ctx->ifc_sysctl_ntxds[i] != 0) 4211 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4212 else 4213 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4214 } 4215 4216 for (i = 0; i < sctx->isc_nrxqs; i++) { 4217 if (ctx->ifc_sysctl_nrxds[i] != 0) 4218 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4219 else 4220 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4221 } 4222 4223 for (i = 0; i < sctx->isc_nrxqs; i++) { 4224 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4225 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4226 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4227 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4228 } 4229 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4230 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4231 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4232 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4233 } 4234 } 4235 4236 for (i = 0; i < sctx->isc_ntxqs; i++) { 4237 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4238 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4239 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4240 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4241 } 4242 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4243 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4244 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4245 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4246 } 4247 } 4248 4249 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4250 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4251 return (err); 4252 } 4253 _iflib_pre_assert(scctx); 4254 ctx->ifc_txrx = *scctx->isc_txrx; 4255 4256 #ifdef INVARIANTS 4257 MPASS(scctx->isc_capenable); 4258 if (scctx->isc_capenable & IFCAP_TXCSUM) 4259 MPASS(scctx->isc_tx_csum_flags); 4260 #endif 4261 4262 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4263 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4264 4265 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4266 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4267 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4268 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4269 4270 #ifdef ACPI_DMAR 4271 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4272 ctx->ifc_flags |= IFC_DMAR; 4273 #elif !(defined(__i386__) || defined(__amd64__)) 4274 /* set unconditionally for !x86 */ 4275 ctx->ifc_flags |= IFC_DMAR; 4276 #endif 4277 4278 msix_bar = scctx->isc_msix_bar; 4279 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4280 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4281 4282 /* XXX change for per-queue sizes */ 4283 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4284 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4285 for (i = 0; i < sctx->isc_nrxqs; i++) { 4286 if (!powerof2(scctx->isc_nrxd[i])) { 4287 /* round down instead? */ 4288 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4289 err = EINVAL; 4290 goto fail; 4291 } 4292 } 4293 for (i = 0; i < sctx->isc_ntxqs; i++) { 4294 if (!powerof2(scctx->isc_ntxd[i])) { 4295 device_printf(dev, 4296 "# tx descriptors must be a power of 2"); 4297 err = EINVAL; 4298 goto fail; 4299 } 4300 } 4301 4302 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4303 MAX_SINGLE_PACKET_FRACTION) 4304 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4305 MAX_SINGLE_PACKET_FRACTION); 4306 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4307 MAX_SINGLE_PACKET_FRACTION) 4308 scctx->isc_tx_tso_segments_max = max(1, 4309 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4310 4311 /* 4312 * Protect the stack against modern hardware 4313 */ 4314 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4315 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4316 4317 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4318 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4319 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4320 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4321 if (scctx->isc_rss_table_size == 0) 4322 scctx->isc_rss_table_size = 64; 4323 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4324 4325 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4326 /* XXX format name */ 4327 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4328 4329 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4330 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4331 device_printf(dev, "Unable to fetch CPU list\n"); 4332 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4333 } 4334 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4335 4336 /* 4337 ** Now setup MSI or MSI/X, should 4338 ** return us the number of supported 4339 ** vectors. (Will be 1 for MSI) 4340 */ 4341 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4342 msix = scctx->isc_vectors; 4343 } else if (scctx->isc_msix_bar != 0) 4344 /* 4345 * The simple fact that isc_msix_bar is not 0 does not mean we 4346 * we have a good value there that is known to work. 4347 */ 4348 msix = iflib_msix_init(ctx); 4349 else { 4350 scctx->isc_vectors = 1; 4351 scctx->isc_ntxqsets = 1; 4352 scctx->isc_nrxqsets = 1; 4353 scctx->isc_intr = IFLIB_INTR_LEGACY; 4354 msix = 0; 4355 } 4356 /* Get memory for the station queues */ 4357 if ((err = iflib_queues_alloc(ctx))) { 4358 device_printf(dev, "Unable to allocate queue memory\n"); 4359 goto fail; 4360 } 4361 4362 if ((err = iflib_qset_structures_setup(ctx))) { 4363 device_printf(dev, "qset structure setup failed %d\n", err); 4364 goto fail_queues; 4365 } 4366 4367 /* 4368 * Group taskqueues aren't properly set up until SMP is started, 4369 * so we disable interrupts until we can handle them post 4370 * SI_SUB_SMP. 4371 * 4372 * XXX: disabling interrupts doesn't actually work, at least for 4373 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4374 * we do null handling and depend on this not causing too large an 4375 * interrupt storm. 4376 */ 4377 IFDI_INTR_DISABLE(ctx); 4378 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4379 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4380 goto fail_intr_free; 4381 } 4382 if (msix <= 1) { 4383 rid = 0; 4384 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4385 MPASS(msix == 1); 4386 rid = 1; 4387 } 4388 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4389 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4390 goto fail_intr_free; 4391 } 4392 } 4393 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4394 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4395 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4396 goto fail_detach; 4397 } 4398 if ((err = iflib_netmap_attach(ctx))) { 4399 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4400 goto fail_detach; 4401 } 4402 *ctxp = ctx; 4403 4404 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4405 iflib_add_device_sysctl_post(ctx); 4406 ctx->ifc_flags |= IFC_INIT_DONE; 4407 return (0); 4408 fail_detach: 4409 ether_ifdetach(ctx->ifc_ifp); 4410 fail_intr_free: 4411 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4412 pci_release_msi(ctx->ifc_dev); 4413 fail_queues: 4414 /* XXX free queues */ 4415 fail: 4416 IFDI_DETACH(ctx); 4417 return (err); 4418 } 4419 4420 int 4421 iflib_device_attach(device_t dev) 4422 { 4423 if_ctx_t ctx; 4424 if_shared_ctx_t sctx; 4425 4426 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4427 return (ENOTSUP); 4428 4429 pci_enable_busmaster(dev); 4430 4431 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4432 } 4433 4434 int 4435 iflib_device_deregister(if_ctx_t ctx) 4436 { 4437 if_t ifp = ctx->ifc_ifp; 4438 iflib_txq_t txq; 4439 iflib_rxq_t rxq; 4440 device_t dev = ctx->ifc_dev; 4441 int i, j; 4442 struct taskqgroup *tqg; 4443 iflib_fl_t fl; 4444 4445 /* Make sure VLANS are not using driver */ 4446 if (if_vlantrunkinuse(ifp)) { 4447 device_printf(dev,"Vlan in use, detach first\n"); 4448 return (EBUSY); 4449 } 4450 4451 CTX_LOCK(ctx); 4452 ctx->ifc_in_detach = 1; 4453 iflib_stop(ctx); 4454 CTX_UNLOCK(ctx); 4455 4456 /* Unregister VLAN events */ 4457 if (ctx->ifc_vlan_attach_event != NULL) 4458 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4459 if (ctx->ifc_vlan_detach_event != NULL) 4460 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4461 4462 iflib_netmap_detach(ifp); 4463 ether_ifdetach(ifp); 4464 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4465 CTX_LOCK_DESTROY(ctx); 4466 if (ctx->ifc_led_dev != NULL) 4467 led_destroy(ctx->ifc_led_dev); 4468 /* XXX drain any dependent tasks */ 4469 tqg = qgroup_if_io_tqg; 4470 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4471 callout_drain(&txq->ift_timer); 4472 if (txq->ift_task.gt_uniq != NULL) 4473 taskqgroup_detach(tqg, &txq->ift_task); 4474 } 4475 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4476 if (rxq->ifr_task.gt_uniq != NULL) 4477 taskqgroup_detach(tqg, &rxq->ifr_task); 4478 4479 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4480 free(fl->ifl_rx_bitmap, M_IFLIB); 4481 4482 } 4483 tqg = qgroup_if_config_tqg; 4484 if (ctx->ifc_admin_task.gt_uniq != NULL) 4485 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4486 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4487 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4488 4489 IFDI_DETACH(ctx); 4490 device_set_softc(ctx->ifc_dev, NULL); 4491 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4492 pci_release_msi(dev); 4493 } 4494 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4495 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4496 } 4497 if (ctx->ifc_msix_mem != NULL) { 4498 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4499 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4500 ctx->ifc_msix_mem = NULL; 4501 } 4502 4503 bus_generic_detach(dev); 4504 if_free(ifp); 4505 4506 iflib_tx_structures_free(ctx); 4507 iflib_rx_structures_free(ctx); 4508 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4509 free(ctx->ifc_softc, M_IFLIB); 4510 free(ctx, M_IFLIB); 4511 return (0); 4512 } 4513 4514 4515 int 4516 iflib_device_detach(device_t dev) 4517 { 4518 if_ctx_t ctx = device_get_softc(dev); 4519 4520 return (iflib_device_deregister(ctx)); 4521 } 4522 4523 int 4524 iflib_device_suspend(device_t dev) 4525 { 4526 if_ctx_t ctx = device_get_softc(dev); 4527 4528 CTX_LOCK(ctx); 4529 IFDI_SUSPEND(ctx); 4530 CTX_UNLOCK(ctx); 4531 4532 return bus_generic_suspend(dev); 4533 } 4534 int 4535 iflib_device_shutdown(device_t dev) 4536 { 4537 if_ctx_t ctx = device_get_softc(dev); 4538 4539 CTX_LOCK(ctx); 4540 IFDI_SHUTDOWN(ctx); 4541 CTX_UNLOCK(ctx); 4542 4543 return bus_generic_suspend(dev); 4544 } 4545 4546 4547 int 4548 iflib_device_resume(device_t dev) 4549 { 4550 if_ctx_t ctx = device_get_softc(dev); 4551 iflib_txq_t txq = ctx->ifc_txqs; 4552 4553 CTX_LOCK(ctx); 4554 IFDI_RESUME(ctx); 4555 iflib_init_locked(ctx); 4556 CTX_UNLOCK(ctx); 4557 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4558 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4559 4560 return (bus_generic_resume(dev)); 4561 } 4562 4563 int 4564 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4565 { 4566 int error; 4567 if_ctx_t ctx = device_get_softc(dev); 4568 4569 CTX_LOCK(ctx); 4570 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4571 CTX_UNLOCK(ctx); 4572 4573 return (error); 4574 } 4575 4576 void 4577 iflib_device_iov_uninit(device_t dev) 4578 { 4579 if_ctx_t ctx = device_get_softc(dev); 4580 4581 CTX_LOCK(ctx); 4582 IFDI_IOV_UNINIT(ctx); 4583 CTX_UNLOCK(ctx); 4584 } 4585 4586 int 4587 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4588 { 4589 int error; 4590 if_ctx_t ctx = device_get_softc(dev); 4591 4592 CTX_LOCK(ctx); 4593 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4594 CTX_UNLOCK(ctx); 4595 4596 return (error); 4597 } 4598 4599 /********************************************************************* 4600 * 4601 * MODULE FUNCTION DEFINITIONS 4602 * 4603 **********************************************************************/ 4604 4605 /* 4606 * - Start a fast taskqueue thread for each core 4607 * - Start a taskqueue for control operations 4608 */ 4609 static int 4610 iflib_module_init(void) 4611 { 4612 return (0); 4613 } 4614 4615 static int 4616 iflib_module_event_handler(module_t mod, int what, void *arg) 4617 { 4618 int err; 4619 4620 switch (what) { 4621 case MOD_LOAD: 4622 if ((err = iflib_module_init()) != 0) 4623 return (err); 4624 break; 4625 case MOD_UNLOAD: 4626 return (EBUSY); 4627 default: 4628 return (EOPNOTSUPP); 4629 } 4630 4631 return (0); 4632 } 4633 4634 /********************************************************************* 4635 * 4636 * PUBLIC FUNCTION DEFINITIONS 4637 * ordered as in iflib.h 4638 * 4639 **********************************************************************/ 4640 4641 4642 static void 4643 _iflib_assert(if_shared_ctx_t sctx) 4644 { 4645 MPASS(sctx->isc_tx_maxsize); 4646 MPASS(sctx->isc_tx_maxsegsize); 4647 4648 MPASS(sctx->isc_rx_maxsize); 4649 MPASS(sctx->isc_rx_nsegments); 4650 MPASS(sctx->isc_rx_maxsegsize); 4651 4652 MPASS(sctx->isc_nrxd_min[0]); 4653 MPASS(sctx->isc_nrxd_max[0]); 4654 MPASS(sctx->isc_nrxd_default[0]); 4655 MPASS(sctx->isc_ntxd_min[0]); 4656 MPASS(sctx->isc_ntxd_max[0]); 4657 MPASS(sctx->isc_ntxd_default[0]); 4658 } 4659 4660 static void 4661 _iflib_pre_assert(if_softc_ctx_t scctx) 4662 { 4663 4664 MPASS(scctx->isc_txrx->ift_txd_encap); 4665 MPASS(scctx->isc_txrx->ift_txd_flush); 4666 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4667 MPASS(scctx->isc_txrx->ift_rxd_available); 4668 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4669 MPASS(scctx->isc_txrx->ift_rxd_refill); 4670 MPASS(scctx->isc_txrx->ift_rxd_flush); 4671 } 4672 4673 static int 4674 iflib_register(if_ctx_t ctx) 4675 { 4676 if_shared_ctx_t sctx = ctx->ifc_sctx; 4677 driver_t *driver = sctx->isc_driver; 4678 device_t dev = ctx->ifc_dev; 4679 if_t ifp; 4680 4681 _iflib_assert(sctx); 4682 4683 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4684 4685 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4686 if (ifp == NULL) { 4687 device_printf(dev, "can not allocate ifnet structure\n"); 4688 return (ENOMEM); 4689 } 4690 4691 /* 4692 * Initialize our context's device specific methods 4693 */ 4694 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4695 kobj_class_compile((kobj_class_t) driver); 4696 driver->refs++; 4697 4698 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4699 if_setsoftc(ifp, ctx); 4700 if_setdev(ifp, dev); 4701 if_setinitfn(ifp, iflib_if_init); 4702 if_setioctlfn(ifp, iflib_if_ioctl); 4703 if_settransmitfn(ifp, iflib_if_transmit); 4704 if_setqflushfn(ifp, iflib_if_qflush); 4705 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4706 4707 ctx->ifc_vlan_attach_event = 4708 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4709 EVENTHANDLER_PRI_FIRST); 4710 ctx->ifc_vlan_detach_event = 4711 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4712 EVENTHANDLER_PRI_FIRST); 4713 4714 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4715 iflib_media_change, iflib_media_status); 4716 4717 return (0); 4718 } 4719 4720 4721 static int 4722 iflib_queues_alloc(if_ctx_t ctx) 4723 { 4724 if_shared_ctx_t sctx = ctx->ifc_sctx; 4725 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4726 device_t dev = ctx->ifc_dev; 4727 int nrxqsets = scctx->isc_nrxqsets; 4728 int ntxqsets = scctx->isc_ntxqsets; 4729 iflib_txq_t txq; 4730 iflib_rxq_t rxq; 4731 iflib_fl_t fl = NULL; 4732 int i, j, cpu, err, txconf, rxconf; 4733 iflib_dma_info_t ifdip; 4734 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4735 uint32_t *txqsizes = scctx->isc_txqsizes; 4736 uint8_t nrxqs = sctx->isc_nrxqs; 4737 uint8_t ntxqs = sctx->isc_ntxqs; 4738 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4739 caddr_t *vaddrs; 4740 uint64_t *paddrs; 4741 struct ifmp_ring **brscp; 4742 4743 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4744 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4745 4746 brscp = NULL; 4747 txq = NULL; 4748 rxq = NULL; 4749 4750 /* Allocate the TX ring struct memory */ 4751 if (!(txq = 4752 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4753 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4754 device_printf(dev, "Unable to allocate TX ring memory\n"); 4755 err = ENOMEM; 4756 goto fail; 4757 } 4758 4759 /* Now allocate the RX */ 4760 if (!(rxq = 4761 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4762 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4763 device_printf(dev, "Unable to allocate RX ring memory\n"); 4764 err = ENOMEM; 4765 goto rx_fail; 4766 } 4767 4768 ctx->ifc_txqs = txq; 4769 ctx->ifc_rxqs = rxq; 4770 4771 /* 4772 * XXX handle allocation failure 4773 */ 4774 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4775 /* Set up some basics */ 4776 4777 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4778 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4779 err = ENOMEM; 4780 goto err_tx_desc; 4781 } 4782 txq->ift_ifdi = ifdip; 4783 for (j = 0; j < ntxqs; j++, ifdip++) { 4784 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4785 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4786 err = ENOMEM; 4787 goto err_tx_desc; 4788 } 4789 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4790 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4791 } 4792 txq->ift_ctx = ctx; 4793 txq->ift_id = i; 4794 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4795 txq->ift_br_offset = 1; 4796 } else { 4797 txq->ift_br_offset = 0; 4798 } 4799 /* XXX fix this */ 4800 txq->ift_timer.c_cpu = cpu; 4801 4802 if (iflib_txsd_alloc(txq)) { 4803 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4804 err = ENOMEM; 4805 goto err_tx_desc; 4806 } 4807 4808 /* Initialize the TX lock */ 4809 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4810 device_get_nameunit(dev), txq->ift_id); 4811 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4812 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4813 4814 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4815 device_get_nameunit(dev), txq->ift_id); 4816 4817 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4818 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4819 if (err) { 4820 /* XXX free any allocated rings */ 4821 device_printf(dev, "Unable to allocate buf_ring\n"); 4822 goto err_tx_desc; 4823 } 4824 } 4825 4826 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4827 /* Set up some basics */ 4828 4829 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4830 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4831 err = ENOMEM; 4832 goto err_tx_desc; 4833 } 4834 4835 rxq->ifr_ifdi = ifdip; 4836 /* XXX this needs to be changed if #rx queues != #tx queues */ 4837 rxq->ifr_ntxqirq = 1; 4838 rxq->ifr_txqid[0] = i; 4839 for (j = 0; j < nrxqs; j++, ifdip++) { 4840 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4841 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4842 err = ENOMEM; 4843 goto err_tx_desc; 4844 } 4845 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4846 } 4847 rxq->ifr_ctx = ctx; 4848 rxq->ifr_id = i; 4849 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4850 rxq->ifr_fl_offset = 1; 4851 } else { 4852 rxq->ifr_fl_offset = 0; 4853 } 4854 rxq->ifr_nfl = nfree_lists; 4855 if (!(fl = 4856 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4857 device_printf(dev, "Unable to allocate free list memory\n"); 4858 err = ENOMEM; 4859 goto err_tx_desc; 4860 } 4861 rxq->ifr_fl = fl; 4862 for (j = 0; j < nfree_lists; j++) { 4863 fl[j].ifl_rxq = rxq; 4864 fl[j].ifl_id = j; 4865 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4866 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4867 } 4868 /* Allocate receive buffers for the ring*/ 4869 if (iflib_rxsd_alloc(rxq)) { 4870 device_printf(dev, 4871 "Critical Failure setting up receive buffers\n"); 4872 err = ENOMEM; 4873 goto err_rx_desc; 4874 } 4875 4876 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4877 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 4878 } 4879 4880 /* TXQs */ 4881 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4882 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4883 for (i = 0; i < ntxqsets; i++) { 4884 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4885 4886 for (j = 0; j < ntxqs; j++, di++) { 4887 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4888 paddrs[i*ntxqs + j] = di->idi_paddr; 4889 } 4890 } 4891 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4892 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4893 iflib_tx_structures_free(ctx); 4894 free(vaddrs, M_IFLIB); 4895 free(paddrs, M_IFLIB); 4896 goto err_rx_desc; 4897 } 4898 free(vaddrs, M_IFLIB); 4899 free(paddrs, M_IFLIB); 4900 4901 /* RXQs */ 4902 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4903 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4904 for (i = 0; i < nrxqsets; i++) { 4905 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4906 4907 for (j = 0; j < nrxqs; j++, di++) { 4908 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4909 paddrs[i*nrxqs + j] = di->idi_paddr; 4910 } 4911 } 4912 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4913 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4914 iflib_tx_structures_free(ctx); 4915 free(vaddrs, M_IFLIB); 4916 free(paddrs, M_IFLIB); 4917 goto err_rx_desc; 4918 } 4919 free(vaddrs, M_IFLIB); 4920 free(paddrs, M_IFLIB); 4921 4922 return (0); 4923 4924 /* XXX handle allocation failure changes */ 4925 err_rx_desc: 4926 err_tx_desc: 4927 if (ctx->ifc_rxqs != NULL) 4928 free(ctx->ifc_rxqs, M_IFLIB); 4929 ctx->ifc_rxqs = NULL; 4930 if (ctx->ifc_txqs != NULL) 4931 free(ctx->ifc_txqs, M_IFLIB); 4932 ctx->ifc_txqs = NULL; 4933 rx_fail: 4934 if (brscp != NULL) 4935 free(brscp, M_IFLIB); 4936 if (rxq != NULL) 4937 free(rxq, M_IFLIB); 4938 if (txq != NULL) 4939 free(txq, M_IFLIB); 4940 fail: 4941 return (err); 4942 } 4943 4944 static int 4945 iflib_tx_structures_setup(if_ctx_t ctx) 4946 { 4947 iflib_txq_t txq = ctx->ifc_txqs; 4948 int i; 4949 4950 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4951 iflib_txq_setup(txq); 4952 4953 return (0); 4954 } 4955 4956 static void 4957 iflib_tx_structures_free(if_ctx_t ctx) 4958 { 4959 iflib_txq_t txq = ctx->ifc_txqs; 4960 int i, j; 4961 4962 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4963 iflib_txq_destroy(txq); 4964 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4965 iflib_dma_free(&txq->ift_ifdi[j]); 4966 } 4967 free(ctx->ifc_txqs, M_IFLIB); 4968 ctx->ifc_txqs = NULL; 4969 IFDI_QUEUES_FREE(ctx); 4970 } 4971 4972 /********************************************************************* 4973 * 4974 * Initialize all receive rings. 4975 * 4976 **********************************************************************/ 4977 static int 4978 iflib_rx_structures_setup(if_ctx_t ctx) 4979 { 4980 iflib_rxq_t rxq = ctx->ifc_rxqs; 4981 int q; 4982 #if defined(INET6) || defined(INET) 4983 int i, err; 4984 #endif 4985 4986 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 4987 #if defined(INET6) || defined(INET) 4988 tcp_lro_free(&rxq->ifr_lc); 4989 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 4990 TCP_LRO_ENTRIES, min(1024, 4991 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 4992 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 4993 goto fail; 4994 } 4995 rxq->ifr_lro_enabled = TRUE; 4996 #endif 4997 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 4998 } 4999 return (0); 5000 #if defined(INET6) || defined(INET) 5001 fail: 5002 /* 5003 * Free RX software descriptors allocated so far, we will only handle 5004 * the rings that completed, the failing case will have 5005 * cleaned up for itself. 'q' failed, so its the terminus. 5006 */ 5007 rxq = ctx->ifc_rxqs; 5008 for (i = 0; i < q; ++i, rxq++) { 5009 iflib_rx_sds_free(rxq); 5010 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5011 } 5012 return (err); 5013 #endif 5014 } 5015 5016 /********************************************************************* 5017 * 5018 * Free all receive rings. 5019 * 5020 **********************************************************************/ 5021 static void 5022 iflib_rx_structures_free(if_ctx_t ctx) 5023 { 5024 iflib_rxq_t rxq = ctx->ifc_rxqs; 5025 5026 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5027 iflib_rx_sds_free(rxq); 5028 } 5029 } 5030 5031 static int 5032 iflib_qset_structures_setup(if_ctx_t ctx) 5033 { 5034 int err; 5035 5036 if ((err = iflib_tx_structures_setup(ctx)) != 0) 5037 return (err); 5038 5039 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 5040 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5041 iflib_tx_structures_free(ctx); 5042 iflib_rx_structures_free(ctx); 5043 } 5044 return (err); 5045 } 5046 5047 int 5048 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5049 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 5050 { 5051 5052 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5053 } 5054 5055 #ifdef SMP 5056 static int 5057 find_nth(if_ctx_t ctx, int qid) 5058 { 5059 cpuset_t cpus; 5060 int i, cpuid, eqid, count; 5061 5062 CPU_COPY(&ctx->ifc_cpus, &cpus); 5063 count = CPU_COUNT(&cpus); 5064 eqid = qid % count; 5065 /* clear up to the qid'th bit */ 5066 for (i = 0; i < eqid; i++) { 5067 cpuid = CPU_FFS(&cpus); 5068 MPASS(cpuid != 0); 5069 CPU_CLR(cpuid-1, &cpus); 5070 } 5071 cpuid = CPU_FFS(&cpus); 5072 MPASS(cpuid != 0); 5073 return (cpuid-1); 5074 } 5075 5076 #ifdef SCHED_ULE 5077 extern struct cpu_group *cpu_top; /* CPU topology */ 5078 5079 static int 5080 find_child_with_core(int cpu, struct cpu_group *grp) 5081 { 5082 int i; 5083 5084 if (grp->cg_children == 0) 5085 return -1; 5086 5087 MPASS(grp->cg_child); 5088 for (i = 0; i < grp->cg_children; i++) { 5089 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5090 return i; 5091 } 5092 5093 return -1; 5094 } 5095 5096 /* 5097 * Find the nth thread on the specified core 5098 */ 5099 static int 5100 find_thread(int cpu, int thread_num) 5101 { 5102 struct cpu_group *grp; 5103 int i; 5104 cpuset_t cs; 5105 5106 grp = cpu_top; 5107 if (grp == NULL) 5108 return cpu; 5109 i = 0; 5110 while ((i = find_child_with_core(cpu, grp)) != -1) { 5111 /* If the child only has one cpu, don't descend */ 5112 if (grp->cg_child[i].cg_count <= 1) 5113 break; 5114 grp = &grp->cg_child[i]; 5115 } 5116 5117 /* If they don't share at least an L2 cache, use the same CPU */ 5118 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5119 return cpu; 5120 5121 /* Now pick one */ 5122 CPU_COPY(&grp->cg_mask, &cs); 5123 for (i = thread_num % grp->cg_count; i > 0; i--) { 5124 MPASS(CPU_FFS(&cs)); 5125 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5126 } 5127 MPASS(CPU_FFS(&cs)); 5128 return CPU_FFS(&cs) - 1; 5129 } 5130 #else 5131 static int 5132 find_thread(int cpu, int thread_num __unused) 5133 { 5134 return cpu; 5135 } 5136 #endif 5137 5138 static int 5139 get_thread_num(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5140 { 5141 switch (type) { 5142 case IFLIB_INTR_TX: 5143 /* TX queues get threads on the same core as the corresponding RX queue */ 5144 /* XXX handle multiple RX threads per core and more than two threads per core */ 5145 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5146 case IFLIB_INTR_RX: 5147 case IFLIB_INTR_RXTX: 5148 /* RX queues get the first thread on their core */ 5149 return qid / CPU_COUNT(&ctx->ifc_cpus); 5150 default: 5151 return -1; 5152 } 5153 } 5154 #else 5155 #define get_thread_num(ctx, type, qid) CPU_FIRST() 5156 #define find_thread(cpuid, tid) CPU_FIRST() 5157 #define find_nth(ctx, gid) CPU_FIRST() 5158 #endif 5159 5160 /* Just to avoid copy/paste */ 5161 static inline int 5162 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5163 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name) 5164 { 5165 int cpuid; 5166 int err, tid; 5167 5168 cpuid = find_nth(ctx, qid); 5169 tid = get_thread_num(ctx, type, qid); 5170 MPASS(tid >= 0); 5171 cpuid = find_thread(cpuid, tid); 5172 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5173 if (err) { 5174 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5175 return (err); 5176 } 5177 #ifdef notyet 5178 if (cpuid > ctx->ifc_cpuid_highest) 5179 ctx->ifc_cpuid_highest = cpuid; 5180 #endif 5181 return 0; 5182 } 5183 5184 int 5185 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5186 iflib_intr_type_t type, driver_filter_t *filter, 5187 void *filter_arg, int qid, char *name) 5188 { 5189 struct grouptask *gtask; 5190 struct taskqgroup *tqg; 5191 iflib_filter_info_t info; 5192 gtask_fn_t *fn; 5193 int tqrid, err; 5194 driver_filter_t *intr_fast; 5195 void *q; 5196 5197 info = &ctx->ifc_filter_info; 5198 tqrid = rid; 5199 5200 switch (type) { 5201 /* XXX merge tx/rx for netmap? */ 5202 case IFLIB_INTR_TX: 5203 q = &ctx->ifc_txqs[qid]; 5204 info = &ctx->ifc_txqs[qid].ift_filter_info; 5205 gtask = &ctx->ifc_txqs[qid].ift_task; 5206 tqg = qgroup_if_io_tqg; 5207 fn = _task_fn_tx; 5208 intr_fast = iflib_fast_intr; 5209 GROUPTASK_INIT(gtask, 0, fn, q); 5210 break; 5211 case IFLIB_INTR_RX: 5212 q = &ctx->ifc_rxqs[qid]; 5213 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5214 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5215 tqg = qgroup_if_io_tqg; 5216 fn = _task_fn_rx; 5217 intr_fast = iflib_fast_intr; 5218 GROUPTASK_INIT(gtask, 0, fn, q); 5219 break; 5220 case IFLIB_INTR_RXTX: 5221 q = &ctx->ifc_rxqs[qid]; 5222 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5223 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5224 tqg = qgroup_if_io_tqg; 5225 fn = _task_fn_rx; 5226 intr_fast = iflib_fast_intr_rxtx; 5227 GROUPTASK_INIT(gtask, 0, fn, q); 5228 break; 5229 case IFLIB_INTR_ADMIN: 5230 q = ctx; 5231 tqrid = -1; 5232 info = &ctx->ifc_filter_info; 5233 gtask = &ctx->ifc_admin_task; 5234 tqg = qgroup_if_config_tqg; 5235 fn = _task_fn_admin; 5236 intr_fast = iflib_fast_intr_ctx; 5237 break; 5238 default: 5239 panic("unknown net intr type"); 5240 } 5241 5242 info->ifi_filter = filter; 5243 info->ifi_filter_arg = filter_arg; 5244 info->ifi_task = gtask; 5245 info->ifi_ctx = q; 5246 5247 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5248 if (err != 0) { 5249 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5250 return (err); 5251 } 5252 if (type == IFLIB_INTR_ADMIN) 5253 return (0); 5254 5255 if (tqrid != -1) { 5256 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5257 if (err) 5258 return (err); 5259 } else { 5260 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5261 } 5262 5263 return (0); 5264 } 5265 5266 void 5267 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name) 5268 { 5269 struct grouptask *gtask; 5270 struct taskqgroup *tqg; 5271 gtask_fn_t *fn; 5272 void *q; 5273 int irq_num = -1; 5274 int err; 5275 5276 switch (type) { 5277 case IFLIB_INTR_TX: 5278 q = &ctx->ifc_txqs[qid]; 5279 gtask = &ctx->ifc_txqs[qid].ift_task; 5280 tqg = qgroup_if_io_tqg; 5281 fn = _task_fn_tx; 5282 if (irq != NULL) 5283 irq_num = rman_get_start(irq->ii_res); 5284 break; 5285 case IFLIB_INTR_RX: 5286 q = &ctx->ifc_rxqs[qid]; 5287 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5288 tqg = qgroup_if_io_tqg; 5289 fn = _task_fn_rx; 5290 if (irq != NULL) 5291 irq_num = rman_get_start(irq->ii_res); 5292 break; 5293 case IFLIB_INTR_IOV: 5294 q = ctx; 5295 gtask = &ctx->ifc_vflr_task; 5296 tqg = qgroup_if_config_tqg; 5297 fn = _task_fn_iov; 5298 break; 5299 default: 5300 panic("unknown net intr type"); 5301 } 5302 GROUPTASK_INIT(gtask, 0, fn, q); 5303 if (irq_num != -1) { 5304 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5305 if (err) 5306 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5307 } 5308 else { 5309 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5310 } 5311 } 5312 5313 void 5314 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5315 { 5316 if (irq->ii_tag) 5317 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5318 5319 if (irq->ii_res) 5320 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5321 } 5322 5323 static int 5324 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5325 { 5326 iflib_txq_t txq = ctx->ifc_txqs; 5327 iflib_rxq_t rxq = ctx->ifc_rxqs; 5328 if_irq_t irq = &ctx->ifc_legacy_irq; 5329 iflib_filter_info_t info; 5330 struct grouptask *gtask; 5331 struct taskqgroup *tqg; 5332 gtask_fn_t *fn; 5333 int tqrid; 5334 void *q; 5335 int err; 5336 5337 q = &ctx->ifc_rxqs[0]; 5338 info = &rxq[0].ifr_filter_info; 5339 gtask = &rxq[0].ifr_task; 5340 tqg = qgroup_if_io_tqg; 5341 tqrid = irq->ii_rid = *rid; 5342 fn = _task_fn_rx; 5343 5344 ctx->ifc_flags |= IFC_LEGACY; 5345 info->ifi_filter = filter; 5346 info->ifi_filter_arg = filter_arg; 5347 info->ifi_task = gtask; 5348 info->ifi_ctx = ctx; 5349 5350 /* We allocate a single interrupt resource */ 5351 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5352 return (err); 5353 GROUPTASK_INIT(gtask, 0, fn, q); 5354 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5355 5356 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5357 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5358 return (0); 5359 } 5360 5361 void 5362 iflib_led_create(if_ctx_t ctx) 5363 { 5364 5365 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5366 device_get_nameunit(ctx->ifc_dev)); 5367 } 5368 5369 void 5370 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5371 { 5372 5373 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5374 } 5375 5376 void 5377 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5378 { 5379 5380 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5381 } 5382 5383 void 5384 iflib_admin_intr_deferred(if_ctx_t ctx) 5385 { 5386 #ifdef INVARIANTS 5387 struct grouptask *gtask; 5388 5389 gtask = &ctx->ifc_admin_task; 5390 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5391 #endif 5392 5393 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5394 } 5395 5396 void 5397 iflib_iov_intr_deferred(if_ctx_t ctx) 5398 { 5399 5400 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5401 } 5402 5403 void 5404 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5405 { 5406 5407 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5408 } 5409 5410 void 5411 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5412 char *name) 5413 { 5414 5415 GROUPTASK_INIT(gtask, 0, fn, ctx); 5416 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5417 } 5418 5419 void 5420 iflib_config_gtask_deinit(struct grouptask *gtask) 5421 { 5422 5423 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5424 } 5425 5426 void 5427 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5428 { 5429 if_t ifp = ctx->ifc_ifp; 5430 iflib_txq_t txq = ctx->ifc_txqs; 5431 5432 if_setbaudrate(ifp, baudrate); 5433 if (baudrate >= IF_Gbps(10)) 5434 ctx->ifc_flags |= IFC_PREFETCH; 5435 5436 /* If link down, disable watchdog */ 5437 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5438 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5439 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5440 } 5441 ctx->ifc_link_state = link_state; 5442 if_link_state_change(ifp, link_state); 5443 } 5444 5445 static int 5446 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5447 { 5448 int credits; 5449 #ifdef INVARIANTS 5450 int credits_pre = txq->ift_cidx_processed; 5451 #endif 5452 5453 if (ctx->isc_txd_credits_update == NULL) 5454 return (0); 5455 5456 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5457 return (0); 5458 5459 txq->ift_processed += credits; 5460 txq->ift_cidx_processed += credits; 5461 5462 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5463 if (txq->ift_cidx_processed >= txq->ift_size) 5464 txq->ift_cidx_processed -= txq->ift_size; 5465 return (credits); 5466 } 5467 5468 static int 5469 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5470 { 5471 5472 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5473 budget)); 5474 } 5475 5476 void 5477 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5478 const char *description, if_int_delay_info_t info, 5479 int offset, int value) 5480 { 5481 info->iidi_ctx = ctx; 5482 info->iidi_offset = offset; 5483 info->iidi_value = value; 5484 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5485 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5486 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5487 info, 0, iflib_sysctl_int_delay, "I", description); 5488 } 5489 5490 struct mtx * 5491 iflib_ctx_lock_get(if_ctx_t ctx) 5492 { 5493 5494 return (&ctx->ifc_mtx); 5495 } 5496 5497 static int 5498 iflib_msix_init(if_ctx_t ctx) 5499 { 5500 device_t dev = ctx->ifc_dev; 5501 if_shared_ctx_t sctx = ctx->ifc_sctx; 5502 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5503 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5504 int iflib_num_tx_queues, iflib_num_rx_queues; 5505 int err, admincnt, bar; 5506 5507 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5508 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5509 5510 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5511 5512 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5513 admincnt = sctx->isc_admin_intrcnt; 5514 /* Override by global tuneable */ 5515 { 5516 int i; 5517 size_t len = sizeof(i); 5518 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0); 5519 if (err == 0) { 5520 if (i == 0) 5521 goto msi; 5522 } 5523 else { 5524 device_printf(dev, "unable to read hw.pci.enable_msix."); 5525 } 5526 } 5527 /* Override by tuneable */ 5528 if (scctx->isc_disable_msix) 5529 goto msi; 5530 5531 /* 5532 ** When used in a virtualized environment 5533 ** PCI BUSMASTER capability may not be set 5534 ** so explicity set it here and rewrite 5535 ** the ENABLE in the MSIX control register 5536 ** at this point to cause the host to 5537 ** successfully initialize us. 5538 */ 5539 { 5540 int msix_ctrl, rid; 5541 5542 pci_enable_busmaster(dev); 5543 rid = 0; 5544 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5545 rid += PCIR_MSIX_CTRL; 5546 msix_ctrl = pci_read_config(dev, rid, 2); 5547 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5548 pci_write_config(dev, rid, msix_ctrl, 2); 5549 } else { 5550 device_printf(dev, "PCIY_MSIX capability not found; " 5551 "or rid %d == 0.\n", rid); 5552 goto msi; 5553 } 5554 } 5555 5556 /* 5557 * bar == -1 => "trust me I know what I'm doing" 5558 * Some drivers are for hardware that is so shoddily 5559 * documented that no one knows which bars are which 5560 * so the developer has to map all bars. This hack 5561 * allows shoddy garbage to use msix in this framework. 5562 */ 5563 if (bar != -1) { 5564 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5565 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5566 if (ctx->ifc_msix_mem == NULL) { 5567 /* May not be enabled */ 5568 device_printf(dev, "Unable to map MSIX table \n"); 5569 goto msi; 5570 } 5571 } 5572 /* First try MSI/X */ 5573 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5574 device_printf(dev, "System has MSIX disabled \n"); 5575 bus_release_resource(dev, SYS_RES_MEMORY, 5576 bar, ctx->ifc_msix_mem); 5577 ctx->ifc_msix_mem = NULL; 5578 goto msi; 5579 } 5580 #if IFLIB_DEBUG 5581 /* use only 1 qset in debug mode */ 5582 queuemsgs = min(msgs - admincnt, 1); 5583 #else 5584 queuemsgs = msgs - admincnt; 5585 #endif 5586 #ifdef RSS 5587 queues = imin(queuemsgs, rss_getnumbuckets()); 5588 #else 5589 queues = queuemsgs; 5590 #endif 5591 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5592 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5593 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5594 #ifdef RSS 5595 /* If we're doing RSS, clamp at the number of RSS buckets */ 5596 if (queues > rss_getnumbuckets()) 5597 queues = rss_getnumbuckets(); 5598 #endif 5599 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5600 rx_queues = iflib_num_rx_queues; 5601 else 5602 rx_queues = queues; 5603 5604 if (rx_queues > scctx->isc_nrxqsets) 5605 rx_queues = scctx->isc_nrxqsets; 5606 5607 /* 5608 * We want this to be all logical CPUs by default 5609 */ 5610 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5611 tx_queues = iflib_num_tx_queues; 5612 else 5613 tx_queues = mp_ncpus; 5614 5615 if (tx_queues > scctx->isc_ntxqsets) 5616 tx_queues = scctx->isc_ntxqsets; 5617 5618 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5619 #ifdef INVARIANTS 5620 if (tx_queues != rx_queues) 5621 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5622 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5623 #endif 5624 tx_queues = min(rx_queues, tx_queues); 5625 rx_queues = min(rx_queues, tx_queues); 5626 } 5627 5628 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5629 5630 vectors = rx_queues + admincnt; 5631 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5632 device_printf(dev, 5633 "Using MSIX interrupts with %d vectors\n", vectors); 5634 scctx->isc_vectors = vectors; 5635 scctx->isc_nrxqsets = rx_queues; 5636 scctx->isc_ntxqsets = tx_queues; 5637 scctx->isc_intr = IFLIB_INTR_MSIX; 5638 5639 return (vectors); 5640 } else { 5641 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5642 } 5643 msi: 5644 vectors = pci_msi_count(dev); 5645 scctx->isc_nrxqsets = 1; 5646 scctx->isc_ntxqsets = 1; 5647 scctx->isc_vectors = vectors; 5648 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5649 device_printf(dev,"Using an MSI interrupt\n"); 5650 scctx->isc_intr = IFLIB_INTR_MSI; 5651 } else { 5652 device_printf(dev,"Using a Legacy interrupt\n"); 5653 scctx->isc_intr = IFLIB_INTR_LEGACY; 5654 } 5655 5656 return (vectors); 5657 } 5658 5659 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5660 5661 static int 5662 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5663 { 5664 int rc; 5665 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5666 struct sbuf *sb; 5667 char *ring_state = "UNKNOWN"; 5668 5669 /* XXX needed ? */ 5670 rc = sysctl_wire_old_buffer(req, 0); 5671 MPASS(rc == 0); 5672 if (rc != 0) 5673 return (rc); 5674 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5675 MPASS(sb != NULL); 5676 if (sb == NULL) 5677 return (ENOMEM); 5678 if (state[3] <= 3) 5679 ring_state = ring_states[state[3]]; 5680 5681 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5682 state[0], state[1], state[2], ring_state); 5683 rc = sbuf_finish(sb); 5684 sbuf_delete(sb); 5685 return(rc); 5686 } 5687 5688 enum iflib_ndesc_handler { 5689 IFLIB_NTXD_HANDLER, 5690 IFLIB_NRXD_HANDLER, 5691 }; 5692 5693 static int 5694 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5695 { 5696 if_ctx_t ctx = (void *)arg1; 5697 enum iflib_ndesc_handler type = arg2; 5698 char buf[256] = {0}; 5699 qidx_t *ndesc; 5700 char *p, *next; 5701 int nqs, rc, i; 5702 5703 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5704 5705 nqs = 8; 5706 switch(type) { 5707 case IFLIB_NTXD_HANDLER: 5708 ndesc = ctx->ifc_sysctl_ntxds; 5709 if (ctx->ifc_sctx) 5710 nqs = ctx->ifc_sctx->isc_ntxqs; 5711 break; 5712 case IFLIB_NRXD_HANDLER: 5713 ndesc = ctx->ifc_sysctl_nrxds; 5714 if (ctx->ifc_sctx) 5715 nqs = ctx->ifc_sctx->isc_nrxqs; 5716 break; 5717 } 5718 if (nqs == 0) 5719 nqs = 8; 5720 5721 for (i=0; i<8; i++) { 5722 if (i >= nqs) 5723 break; 5724 if (i) 5725 strcat(buf, ","); 5726 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5727 } 5728 5729 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5730 if (rc || req->newptr == NULL) 5731 return rc; 5732 5733 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5734 i++, p = strsep(&next, " ,")) { 5735 ndesc[i] = strtoul(p, NULL, 10); 5736 } 5737 5738 return(rc); 5739 } 5740 5741 #define NAME_BUFLEN 32 5742 static void 5743 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5744 { 5745 device_t dev = iflib_get_dev(ctx); 5746 struct sysctl_oid_list *child, *oid_list; 5747 struct sysctl_ctx_list *ctx_list; 5748 struct sysctl_oid *node; 5749 5750 ctx_list = device_get_sysctl_ctx(dev); 5751 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5752 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5753 CTLFLAG_RD, NULL, "IFLIB fields"); 5754 oid_list = SYSCTL_CHILDREN(node); 5755 5756 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5757 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5758 "driver version"); 5759 5760 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5761 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5762 "# of txqs to use, 0 => use default #"); 5763 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5764 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5765 "# of rxqs to use, 0 => use default #"); 5766 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5767 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5768 "permit #txq != #rxq"); 5769 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5770 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5771 "disable MSIX (default 0)"); 5772 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 5773 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 5774 "set the rx budget"); 5775 5776 /* XXX change for per-queue sizes */ 5777 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5778 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5779 mp_ndesc_handler, "A", 5780 "list of # of tx descriptors to use, 0 = use default #"); 5781 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5782 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5783 mp_ndesc_handler, "A", 5784 "list of # of rx descriptors to use, 0 = use default #"); 5785 } 5786 5787 static void 5788 iflib_add_device_sysctl_post(if_ctx_t ctx) 5789 { 5790 if_shared_ctx_t sctx = ctx->ifc_sctx; 5791 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5792 device_t dev = iflib_get_dev(ctx); 5793 struct sysctl_oid_list *child; 5794 struct sysctl_ctx_list *ctx_list; 5795 iflib_fl_t fl; 5796 iflib_txq_t txq; 5797 iflib_rxq_t rxq; 5798 int i, j; 5799 char namebuf[NAME_BUFLEN]; 5800 char *qfmt; 5801 struct sysctl_oid *queue_node, *fl_node, *node; 5802 struct sysctl_oid_list *queue_list, *fl_list; 5803 ctx_list = device_get_sysctl_ctx(dev); 5804 5805 node = ctx->ifc_sysctl_node; 5806 child = SYSCTL_CHILDREN(node); 5807 5808 if (scctx->isc_ntxqsets > 100) 5809 qfmt = "txq%03d"; 5810 else if (scctx->isc_ntxqsets > 10) 5811 qfmt = "txq%02d"; 5812 else 5813 qfmt = "txq%d"; 5814 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5815 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5816 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5817 CTLFLAG_RD, NULL, "Queue Name"); 5818 queue_list = SYSCTL_CHILDREN(queue_node); 5819 #if MEMORY_LOGGING 5820 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5821 CTLFLAG_RD, 5822 &txq->ift_dequeued, "total mbufs freed"); 5823 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5824 CTLFLAG_RD, 5825 &txq->ift_enqueued, "total mbufs enqueued"); 5826 #endif 5827 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5828 CTLFLAG_RD, 5829 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5830 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5831 CTLFLAG_RD, 5832 &txq->ift_pullups, "# of times m_pullup was called"); 5833 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5834 CTLFLAG_RD, 5835 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5836 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5837 CTLFLAG_RD, 5838 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5839 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5840 CTLFLAG_RD, 5841 &txq->ift_map_failed, "# of times dma map failed"); 5842 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5843 CTLFLAG_RD, 5844 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5845 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5846 CTLFLAG_RD, 5847 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5848 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5849 CTLFLAG_RD, 5850 &txq->ift_pidx, 1, "Producer Index"); 5851 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5852 CTLFLAG_RD, 5853 &txq->ift_cidx, 1, "Consumer Index"); 5854 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5855 CTLFLAG_RD, 5856 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5857 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5858 CTLFLAG_RD, 5859 &txq->ift_in_use, 1, "descriptors in use"); 5860 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5861 CTLFLAG_RD, 5862 &txq->ift_processed, "descriptors procesed for clean"); 5863 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5864 CTLFLAG_RD, 5865 &txq->ift_cleaned, "total cleaned"); 5866 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5867 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5868 0, mp_ring_state_handler, "A", "soft ring state"); 5869 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5870 CTLFLAG_RD, &txq->ift_br->enqueues, 5871 "# of enqueues to the mp_ring for this queue"); 5872 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5873 CTLFLAG_RD, &txq->ift_br->drops, 5874 "# of drops in the mp_ring for this queue"); 5875 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5876 CTLFLAG_RD, &txq->ift_br->starts, 5877 "# of normal consumer starts in the mp_ring for this queue"); 5878 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5879 CTLFLAG_RD, &txq->ift_br->stalls, 5880 "# of consumer stalls in the mp_ring for this queue"); 5881 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5882 CTLFLAG_RD, &txq->ift_br->restarts, 5883 "# of consumer restarts in the mp_ring for this queue"); 5884 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5885 CTLFLAG_RD, &txq->ift_br->abdications, 5886 "# of consumer abdications in the mp_ring for this queue"); 5887 } 5888 5889 if (scctx->isc_nrxqsets > 100) 5890 qfmt = "rxq%03d"; 5891 else if (scctx->isc_nrxqsets > 10) 5892 qfmt = "rxq%02d"; 5893 else 5894 qfmt = "rxq%d"; 5895 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5896 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5897 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5898 CTLFLAG_RD, NULL, "Queue Name"); 5899 queue_list = SYSCTL_CHILDREN(queue_node); 5900 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5901 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5902 CTLFLAG_RD, 5903 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5904 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5905 CTLFLAG_RD, 5906 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5907 } 5908 5909 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5910 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5911 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5912 CTLFLAG_RD, NULL, "freelist Name"); 5913 fl_list = SYSCTL_CHILDREN(fl_node); 5914 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5915 CTLFLAG_RD, 5916 &fl->ifl_pidx, 1, "Producer Index"); 5917 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5918 CTLFLAG_RD, 5919 &fl->ifl_cidx, 1, "Consumer Index"); 5920 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5921 CTLFLAG_RD, 5922 &fl->ifl_credits, 1, "credits available"); 5923 #if MEMORY_LOGGING 5924 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5925 CTLFLAG_RD, 5926 &fl->ifl_m_enqueued, "mbufs allocated"); 5927 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5928 CTLFLAG_RD, 5929 &fl->ifl_m_dequeued, "mbufs freed"); 5930 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5931 CTLFLAG_RD, 5932 &fl->ifl_cl_enqueued, "clusters allocated"); 5933 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5934 CTLFLAG_RD, 5935 &fl->ifl_cl_dequeued, "clusters freed"); 5936 #endif 5937 5938 } 5939 } 5940 5941 } 5942 5943 #ifndef __NO_STRICT_ALIGNMENT 5944 static struct mbuf * 5945 iflib_fixup_rx(struct mbuf *m) 5946 { 5947 struct mbuf *n; 5948 5949 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5950 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 5951 m->m_data += ETHER_HDR_LEN; 5952 n = m; 5953 } else { 5954 MGETHDR(n, M_NOWAIT, MT_DATA); 5955 if (n == NULL) { 5956 m_freem(m); 5957 return (NULL); 5958 } 5959 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 5960 m->m_data += ETHER_HDR_LEN; 5961 m->m_len -= ETHER_HDR_LEN; 5962 n->m_len = ETHER_HDR_LEN; 5963 M_MOVE_PKTHDR(n, m); 5964 n->m_next = m; 5965 } 5966 return (n); 5967 } 5968 #endif 5969