1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/sockio.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/module.h> 45 #include <sys/kobj.h> 46 #include <sys/rman.h> 47 #include <sys/sbuf.h> 48 #include <sys/smp.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 56 #include <net/if.h> 57 #include <net/if_var.h> 58 #include <net/if_types.h> 59 #include <net/if_media.h> 60 #include <net/bpf.h> 61 #include <net/ethernet.h> 62 #include <net/mp_ring.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/ip_var.h> 74 #include <netinet6/ip6_var.h> 75 76 #include <machine/bus.h> 77 #include <machine/in_cksum.h> 78 79 #include <vm/vm.h> 80 #include <vm/pmap.h> 81 82 #include <dev/led/led.h> 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pci_private.h> 86 87 #include <net/iflib.h> 88 89 #include "ifdi_if.h" 90 91 #if defined(__i386__) || defined(__amd64__) 92 #include <sys/memdesc.h> 93 #include <machine/bus.h> 94 #include <machine/md_var.h> 95 #include <machine/specialreg.h> 96 #include <x86/include/busdma_impl.h> 97 #include <x86/iommu/busdma_dmar.h> 98 #endif 99 100 #include <sys/bitstring.h> 101 /* 102 * enable accounting of every mbuf as it comes in to and goes out of 103 * iflib's software descriptor references 104 */ 105 #define MEMORY_LOGGING 0 106 /* 107 * Enable mbuf vectors for compressing long mbuf chains 108 */ 109 110 /* 111 * NB: 112 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 113 * we prefetch needs to be determined by the time spent in m_free vis a vis 114 * the cost of a prefetch. This will of course vary based on the workload: 115 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 116 * is quite expensive, thus suggesting very little prefetch. 117 * - small packet forwarding which is just returning a single mbuf to 118 * UMA will typically be very fast vis a vis the cost of a memory 119 * access. 120 */ 121 122 123 /* 124 * File organization: 125 * - private structures 126 * - iflib private utility functions 127 * - ifnet functions 128 * - vlan registry and other exported functions 129 * - iflib public core functions 130 * 131 * 132 */ 133 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct sx ifc_ctx_sx; 167 struct mtx ifc_state_mtx; 168 169 uint16_t ifc_nhwtxqs; 170 171 iflib_txq_t ifc_txqs; 172 iflib_rxq_t ifc_rxqs; 173 uint32_t ifc_if_flags; 174 uint32_t ifc_flags; 175 uint32_t ifc_max_fl_buf_size; 176 int ifc_in_detach; 177 178 int ifc_link_state; 179 int ifc_link_irq; 180 int ifc_watchdog_events; 181 struct cdev *ifc_led_dev; 182 struct resource *ifc_msix_mem; 183 184 struct if_irq ifc_legacy_irq; 185 struct grouptask ifc_admin_task; 186 struct grouptask ifc_vflr_task; 187 struct iflib_filter_info ifc_filter_info; 188 struct ifmedia ifc_media; 189 190 struct sysctl_oid *ifc_sysctl_node; 191 uint16_t ifc_sysctl_ntxqs; 192 uint16_t ifc_sysctl_nrxqs; 193 uint16_t ifc_sysctl_qs_eq_override; 194 uint16_t ifc_sysctl_rx_budget; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 uint8_t ifc_mac[ETHER_ADDR_LEN]; 212 char ifc_mtx_name[16]; 213 }; 214 215 216 void * 217 iflib_get_softc(if_ctx_t ctx) 218 { 219 220 return (ctx->ifc_softc); 221 } 222 223 device_t 224 iflib_get_dev(if_ctx_t ctx) 225 { 226 227 return (ctx->ifc_dev); 228 } 229 230 if_t 231 iflib_get_ifp(if_ctx_t ctx) 232 { 233 234 return (ctx->ifc_ifp); 235 } 236 237 struct ifmedia * 238 iflib_get_media(if_ctx_t ctx) 239 { 240 241 return (&ctx->ifc_media); 242 } 243 244 void 245 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 246 { 247 248 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 249 } 250 251 if_softc_ctx_t 252 iflib_get_softc_ctx(if_ctx_t ctx) 253 { 254 255 return (&ctx->ifc_softc_ctx); 256 } 257 258 if_shared_ctx_t 259 iflib_get_sctx(if_ctx_t ctx) 260 { 261 262 return (ctx->ifc_sctx); 263 } 264 265 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 266 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 267 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 268 269 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 270 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 271 272 #define RX_SW_DESC_MAP_CREATED (1 << 0) 273 #define TX_SW_DESC_MAP_CREATED (1 << 1) 274 #define RX_SW_DESC_INUSE (1 << 3) 275 #define TX_SW_DESC_MAPPED (1 << 4) 276 277 #define M_TOOBIG M_PROTO1 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 uint8_t *ifsd_flags; 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 struct mbuf **ifsd_m; /* pkthdr mbufs */ 289 uint8_t *ifsd_flags; 290 } if_txsd_vec_t; 291 292 293 /* magic number that should be high enough for any hardware */ 294 #define IFLIB_MAX_TX_SEGS 128 295 /* bnxt supports 64 with hardware LRO enabled */ 296 #define IFLIB_MAX_RX_SEGS 64 297 #define IFLIB_RX_COPY_THRESH 128 298 #define IFLIB_MAX_RX_REFRESH 32 299 /* The minimum descriptors per second before we start coalescing */ 300 #define IFLIB_MIN_DESC_SEC 16384 301 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 302 #define IFLIB_QUEUE_IDLE 0 303 #define IFLIB_QUEUE_HUNG 1 304 #define IFLIB_QUEUE_WORKING 2 305 /* maximum number of txqs that can share an rx interrupt */ 306 #define IFLIB_MAX_TX_SHARED_INTR 4 307 308 /* this should really scale with ring size - this is a fairly arbitrary value */ 309 #define TX_BATCH_SIZE 32 310 311 #define IFLIB_RESTART_BUDGET 8 312 313 #define IFC_LEGACY 0x001 314 #define IFC_QFLUSH 0x002 315 #define IFC_MULTISEG 0x004 316 #define IFC_DMAR 0x008 317 #define IFC_SC_ALLOCATED 0x010 318 #define IFC_INIT_DONE 0x020 319 #define IFC_PREFETCH 0x040 320 #define IFC_DO_RESET 0x080 321 #define IFC_DO_WATCHDOG 0x100 322 #define IFC_CHECK_HUNG 0x200 323 324 325 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 326 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 327 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 328 struct iflib_txq { 329 qidx_t ift_in_use; 330 qidx_t ift_cidx; 331 qidx_t ift_cidx_processed; 332 qidx_t ift_pidx; 333 uint8_t ift_gen; 334 uint8_t ift_br_offset; 335 uint16_t ift_npending; 336 uint16_t ift_db_pending; 337 uint16_t ift_rs_pending; 338 /* implicit pad */ 339 uint8_t ift_txd_size[8]; 340 uint64_t ift_processed; 341 uint64_t ift_cleaned; 342 uint64_t ift_cleaned_prev; 343 #if MEMORY_LOGGING 344 uint64_t ift_enqueued; 345 uint64_t ift_dequeued; 346 #endif 347 uint64_t ift_no_tx_dma_setup; 348 uint64_t ift_no_desc_avail; 349 uint64_t ift_mbuf_defrag_failed; 350 uint64_t ift_mbuf_defrag; 351 uint64_t ift_map_failed; 352 uint64_t ift_txd_encap_efbig; 353 uint64_t ift_pullups; 354 355 struct mtx ift_mtx; 356 struct mtx ift_db_mtx; 357 358 /* constant values */ 359 if_ctx_t ift_ctx; 360 struct ifmp_ring *ift_br; 361 struct grouptask ift_task; 362 qidx_t ift_size; 363 uint16_t ift_id; 364 struct callout ift_timer; 365 366 if_txsd_vec_t ift_sds; 367 uint8_t ift_qstatus; 368 uint8_t ift_closed; 369 uint8_t ift_update_freq; 370 struct iflib_filter_info ift_filter_info; 371 bus_dma_tag_t ift_desc_tag; 372 bus_dma_tag_t ift_tso_desc_tag; 373 iflib_dma_info_t ift_ifdi; 374 #define MTX_NAME_LEN 16 375 char ift_mtx_name[MTX_NAME_LEN]; 376 char ift_db_mtx_name[MTX_NAME_LEN]; 377 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 378 #ifdef IFLIB_DIAGNOSTICS 379 uint64_t ift_cpu_exec_count[256]; 380 #endif 381 } __aligned(CACHE_LINE_SIZE); 382 383 struct iflib_fl { 384 qidx_t ifl_cidx; 385 qidx_t ifl_pidx; 386 qidx_t ifl_credits; 387 uint8_t ifl_gen; 388 uint8_t ifl_rxd_size; 389 #if MEMORY_LOGGING 390 uint64_t ifl_m_enqueued; 391 uint64_t ifl_m_dequeued; 392 uint64_t ifl_cl_enqueued; 393 uint64_t ifl_cl_dequeued; 394 #endif 395 /* implicit pad */ 396 397 bitstr_t *ifl_rx_bitmap; 398 qidx_t ifl_fragidx; 399 /* constant */ 400 qidx_t ifl_size; 401 uint16_t ifl_buf_size; 402 uint16_t ifl_cltype; 403 uma_zone_t ifl_zone; 404 iflib_rxsd_array_t ifl_sds; 405 iflib_rxq_t ifl_rxq; 406 uint8_t ifl_id; 407 bus_dma_tag_t ifl_desc_tag; 408 iflib_dma_info_t ifl_ifdi; 409 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 410 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 411 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 412 } __aligned(CACHE_LINE_SIZE); 413 414 static inline qidx_t 415 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 416 { 417 qidx_t used; 418 419 if (pidx > cidx) 420 used = pidx - cidx; 421 else if (pidx < cidx) 422 used = size - cidx + pidx; 423 else if (gen == 0 && pidx == cidx) 424 used = 0; 425 else if (gen == 1 && pidx == cidx) 426 used = size; 427 else 428 panic("bad state"); 429 430 return (used); 431 } 432 433 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 434 435 #define IDXDIFF(head, tail, wrap) \ 436 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 437 438 struct iflib_rxq { 439 /* If there is a separate completion queue - 440 * these are the cq cidx and pidx. Otherwise 441 * these are unused. 442 */ 443 qidx_t ifr_size; 444 qidx_t ifr_cq_cidx; 445 qidx_t ifr_cq_pidx; 446 uint8_t ifr_cq_gen; 447 uint8_t ifr_fl_offset; 448 449 if_ctx_t ifr_ctx; 450 iflib_fl_t ifr_fl; 451 uint64_t ifr_rx_irq; 452 uint16_t ifr_id; 453 uint8_t ifr_lro_enabled; 454 uint8_t ifr_nfl; 455 uint8_t ifr_ntxqirq; 456 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 457 struct lro_ctrl ifr_lc; 458 struct grouptask ifr_task; 459 struct iflib_filter_info ifr_filter_info; 460 iflib_dma_info_t ifr_ifdi; 461 462 /* dynamically allocate if any drivers need a value substantially larger than this */ 463 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 464 #ifdef IFLIB_DIAGNOSTICS 465 uint64_t ifr_cpu_exec_count[256]; 466 #endif 467 } __aligned(CACHE_LINE_SIZE); 468 469 typedef struct if_rxsd { 470 caddr_t *ifsd_cl; 471 struct mbuf **ifsd_m; 472 iflib_fl_t ifsd_fl; 473 qidx_t ifsd_cidx; 474 } *if_rxsd_t; 475 476 /* multiple of word size */ 477 #ifdef __LP64__ 478 #define PKT_INFO_SIZE 6 479 #define RXD_INFO_SIZE 5 480 #define PKT_TYPE uint64_t 481 #else 482 #define PKT_INFO_SIZE 11 483 #define RXD_INFO_SIZE 8 484 #define PKT_TYPE uint32_t 485 #endif 486 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 487 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 488 489 typedef struct if_pkt_info_pad { 490 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 491 } *if_pkt_info_pad_t; 492 typedef struct if_rxd_info_pad { 493 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 494 } *if_rxd_info_pad_t; 495 496 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 497 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 498 499 500 static inline void 501 pkt_info_zero(if_pkt_info_t pi) 502 { 503 if_pkt_info_pad_t pi_pad; 504 505 pi_pad = (if_pkt_info_pad_t)pi; 506 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 507 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 508 #ifndef __LP64__ 509 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 510 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 511 #endif 512 } 513 514 static inline void 515 rxd_info_zero(if_rxd_info_t ri) 516 { 517 if_rxd_info_pad_t ri_pad; 518 int i; 519 520 ri_pad = (if_rxd_info_pad_t)ri; 521 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 522 ri_pad->rxd_val[i] = 0; 523 ri_pad->rxd_val[i+1] = 0; 524 ri_pad->rxd_val[i+2] = 0; 525 ri_pad->rxd_val[i+3] = 0; 526 } 527 #ifdef __LP64__ 528 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 529 #endif 530 } 531 532 /* 533 * Only allow a single packet to take up most 1/nth of the tx ring 534 */ 535 #define MAX_SINGLE_PACKET_FRACTION 12 536 #define IF_BAD_DMA (bus_addr_t)-1 537 538 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 539 540 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 541 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 542 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 543 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 544 545 546 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 547 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 548 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 549 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 550 551 552 553 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 554 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 555 556 557 /* Our boot-time initialization hook */ 558 static int iflib_module_event_handler(module_t, int, void *); 559 560 static moduledata_t iflib_moduledata = { 561 "iflib", 562 iflib_module_event_handler, 563 NULL 564 }; 565 566 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 567 MODULE_VERSION(iflib, 1); 568 569 MODULE_DEPEND(iflib, pci, 1, 1, 1); 570 MODULE_DEPEND(iflib, ether, 1, 1, 1); 571 572 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 573 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 574 575 #ifndef IFLIB_DEBUG_COUNTERS 576 #ifdef INVARIANTS 577 #define IFLIB_DEBUG_COUNTERS 1 578 #else 579 #define IFLIB_DEBUG_COUNTERS 0 580 #endif /* !INVARIANTS */ 581 #endif 582 583 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 584 "iflib driver parameters"); 585 586 /* 587 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 588 */ 589 static int iflib_min_tx_latency = 0; 590 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 591 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 592 static int iflib_no_tx_batch = 0; 593 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 594 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 595 596 597 #if IFLIB_DEBUG_COUNTERS 598 599 static int iflib_tx_seen; 600 static int iflib_tx_sent; 601 static int iflib_tx_encap; 602 static int iflib_rx_allocs; 603 static int iflib_fl_refills; 604 static int iflib_fl_refills_large; 605 static int iflib_tx_frees; 606 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 608 &iflib_tx_seen, 0, "# tx mbufs seen"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 610 &iflib_tx_sent, 0, "# tx mbufs sent"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 612 &iflib_tx_encap, 0, "# tx mbufs encapped"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 614 &iflib_tx_frees, 0, "# tx frees"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 616 &iflib_rx_allocs, 0, "# rx allocations"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 618 &iflib_fl_refills, 0, "# refills"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 620 &iflib_fl_refills_large, 0, "# large refills"); 621 622 623 static int iflib_txq_drain_flushing; 624 static int iflib_txq_drain_oactive; 625 static int iflib_txq_drain_notready; 626 static int iflib_txq_drain_encapfail; 627 628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 629 &iflib_txq_drain_flushing, 0, "# drain flushes"); 630 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 631 &iflib_txq_drain_oactive, 0, "# drain oactives"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 633 &iflib_txq_drain_notready, 0, "# drain notready"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 635 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 636 637 638 static int iflib_encap_load_mbuf_fail; 639 static int iflib_encap_pad_mbuf_fail; 640 static int iflib_encap_txq_avail_fail; 641 static int iflib_encap_txd_encap_fail; 642 643 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 644 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 645 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 646 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 648 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 650 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 651 652 static int iflib_task_fn_rxs; 653 static int iflib_rx_intr_enables; 654 static int iflib_fast_intrs; 655 static int iflib_intr_link; 656 static int iflib_intr_msix; 657 static int iflib_rx_unavail; 658 static int iflib_rx_ctx_inactive; 659 static int iflib_rx_zero_len; 660 static int iflib_rx_if_input; 661 static int iflib_rx_mbuf_null; 662 static int iflib_rxd_flush; 663 664 static int iflib_verbose_debug; 665 666 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 667 &iflib_intr_link, 0, "# intr link calls"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 669 &iflib_intr_msix, 0, "# intr msix calls"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 671 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 673 &iflib_rx_intr_enables, 0, "# rx intr enables"); 674 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 675 &iflib_fast_intrs, 0, "# fast_intr calls"); 676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 677 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 678 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 679 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 680 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 681 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 682 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 683 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 684 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 685 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 686 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 687 &iflib_rxd_flush, 0, "# times rxd_flush called"); 688 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 689 &iflib_verbose_debug, 0, "enable verbose debugging"); 690 691 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 692 static void 693 iflib_debug_reset(void) 694 { 695 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 696 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 697 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 698 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 699 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 700 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 701 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 702 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 703 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 704 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 705 } 706 707 #else 708 #define DBG_COUNTER_INC(name) 709 static void iflib_debug_reset(void) {} 710 #endif 711 712 713 714 #define IFLIB_DEBUG 0 715 716 static void iflib_tx_structures_free(if_ctx_t ctx); 717 static void iflib_rx_structures_free(if_ctx_t ctx); 718 static int iflib_queues_alloc(if_ctx_t ctx); 719 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 720 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 721 static int iflib_qset_structures_setup(if_ctx_t ctx); 722 static int iflib_msix_init(if_ctx_t ctx); 723 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 724 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 725 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 726 static int iflib_register(if_ctx_t); 727 static void iflib_init_locked(if_ctx_t ctx); 728 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 729 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 730 static void iflib_ifmp_purge(iflib_txq_t txq); 731 static void _iflib_pre_assert(if_softc_ctx_t scctx); 732 static void iflib_stop(if_ctx_t ctx); 733 static void iflib_if_init_locked(if_ctx_t ctx); 734 #ifndef __NO_STRICT_ALIGNMENT 735 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 736 #endif 737 738 #ifdef DEV_NETMAP 739 #include <sys/selinfo.h> 740 #include <net/netmap.h> 741 #include <dev/netmap/netmap_kern.h> 742 743 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 744 745 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 746 747 /* 748 * device-specific sysctl variables: 749 * 750 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 751 * During regular operations the CRC is stripped, but on some 752 * hardware reception of frames not multiple of 64 is slower, 753 * so using crcstrip=0 helps in benchmarks. 754 * 755 * iflib_rx_miss, iflib_rx_miss_bufs: 756 * count packets that might be missed due to lost interrupts. 757 */ 758 SYSCTL_DECL(_dev_netmap); 759 /* 760 * The xl driver by default strips CRCs and we do not override it. 761 */ 762 763 int iflib_crcstrip = 1; 764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 765 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 766 767 int iflib_rx_miss, iflib_rx_miss_bufs; 768 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 769 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 770 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 771 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 772 773 /* 774 * Register/unregister. We are already under netmap lock. 775 * Only called on the first register or the last unregister. 776 */ 777 static int 778 iflib_netmap_register(struct netmap_adapter *na, int onoff) 779 { 780 struct ifnet *ifp = na->ifp; 781 if_ctx_t ctx = ifp->if_softc; 782 int status; 783 784 CTX_LOCK(ctx); 785 IFDI_INTR_DISABLE(ctx); 786 787 /* Tell the stack that the interface is no longer active */ 788 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 789 790 if (!CTX_IS_VF(ctx)) 791 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 792 793 /* enable or disable flags and callbacks in na and ifp */ 794 if (onoff) { 795 nm_set_native_flags(na); 796 } else { 797 nm_clear_native_flags(na); 798 } 799 iflib_stop(ctx); 800 iflib_init_locked(ctx); 801 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 802 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 803 if (status) 804 nm_clear_native_flags(na); 805 CTX_UNLOCK(ctx); 806 return (status); 807 } 808 809 static int 810 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 811 { 812 struct netmap_adapter *na = kring->na; 813 u_int const lim = kring->nkr_num_slots - 1; 814 u_int head = kring->rhead; 815 struct netmap_ring *ring = kring->ring; 816 bus_dmamap_t *map; 817 struct if_rxd_update iru; 818 if_ctx_t ctx = rxq->ifr_ctx; 819 iflib_fl_t fl = &rxq->ifr_fl[0]; 820 uint32_t refill_pidx, nic_i; 821 822 if (nm_i == head && __predict_true(!init)) 823 return 0; 824 iru_init(&iru, rxq, 0 /* flid */); 825 map = fl->ifl_sds.ifsd_map; 826 refill_pidx = netmap_idx_k2n(kring, nm_i); 827 /* 828 * IMPORTANT: we must leave one free slot in the ring, 829 * so move head back by one unit 830 */ 831 head = nm_prev(head, lim); 832 nic_i = UINT_MAX; 833 while (nm_i != head) { 834 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 835 struct netmap_slot *slot = &ring->slot[nm_i]; 836 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 837 uint32_t nic_i_dma = refill_pidx; 838 nic_i = netmap_idx_k2n(kring, nm_i); 839 840 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 841 842 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 843 return netmap_ring_reinit(kring); 844 845 fl->ifl_vm_addrs[tmp_pidx] = addr; 846 if (__predict_false(init) && map) { 847 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 848 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 849 /* buffer has changed, reload map */ 850 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 851 } 852 slot->flags &= ~NS_BUF_CHANGED; 853 854 nm_i = nm_next(nm_i, lim); 855 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 856 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 857 continue; 858 859 iru.iru_pidx = refill_pidx; 860 iru.iru_count = tmp_pidx+1; 861 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 862 863 refill_pidx = nic_i; 864 if (map == NULL) 865 continue; 866 867 for (int n = 0; n < iru.iru_count; n++) { 868 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 869 BUS_DMASYNC_PREREAD); 870 /* XXX - change this to not use the netmap func*/ 871 nic_i_dma = nm_next(nic_i_dma, lim); 872 } 873 } 874 } 875 kring->nr_hwcur = head; 876 877 if (map) 878 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 879 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 880 if (__predict_true(nic_i != UINT_MAX)) 881 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 882 return (0); 883 } 884 885 /* 886 * Reconcile kernel and user view of the transmit ring. 887 * 888 * All information is in the kring. 889 * Userspace wants to send packets up to the one before kring->rhead, 890 * kernel knows kring->nr_hwcur is the first unsent packet. 891 * 892 * Here we push packets out (as many as possible), and possibly 893 * reclaim buffers from previously completed transmission. 894 * 895 * The caller (netmap) guarantees that there is only one instance 896 * running at any time. Any interference with other driver 897 * methods should be handled by the individual drivers. 898 */ 899 static int 900 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 901 { 902 struct netmap_adapter *na = kring->na; 903 struct ifnet *ifp = na->ifp; 904 struct netmap_ring *ring = kring->ring; 905 u_int nm_i; /* index into the netmap ring */ 906 u_int nic_i; /* index into the NIC ring */ 907 u_int n; 908 u_int const lim = kring->nkr_num_slots - 1; 909 u_int const head = kring->rhead; 910 struct if_pkt_info pi; 911 912 /* 913 * interrupts on every tx packet are expensive so request 914 * them every half ring, or where NS_REPORT is set 915 */ 916 u_int report_frequency = kring->nkr_num_slots >> 1; 917 /* device-specific */ 918 if_ctx_t ctx = ifp->if_softc; 919 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 920 921 if (txq->ift_sds.ifsd_map) 922 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 923 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 924 925 926 /* 927 * First part: process new packets to send. 928 * nm_i is the current index in the netmap ring, 929 * nic_i is the corresponding index in the NIC ring. 930 * 931 * If we have packets to send (nm_i != head) 932 * iterate over the netmap ring, fetch length and update 933 * the corresponding slot in the NIC ring. Some drivers also 934 * need to update the buffer's physical address in the NIC slot 935 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 936 * 937 * The netmap_reload_map() calls is especially expensive, 938 * even when (as in this case) the tag is 0, so do only 939 * when the buffer has actually changed. 940 * 941 * If possible do not set the report/intr bit on all slots, 942 * but only a few times per ring or when NS_REPORT is set. 943 * 944 * Finally, on 10G and faster drivers, it might be useful 945 * to prefetch the next slot and txr entry. 946 */ 947 948 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 949 pkt_info_zero(&pi); 950 pi.ipi_segs = txq->ift_segs; 951 pi.ipi_qsidx = kring->ring_id; 952 if (nm_i != head) { /* we have new packets to send */ 953 nic_i = netmap_idx_k2n(kring, nm_i); 954 955 __builtin_prefetch(&ring->slot[nm_i]); 956 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 957 if (txq->ift_sds.ifsd_map) 958 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 959 960 for (n = 0; nm_i != head; n++) { 961 struct netmap_slot *slot = &ring->slot[nm_i]; 962 u_int len = slot->len; 963 uint64_t paddr; 964 void *addr = PNMB(na, slot, &paddr); 965 int flags = (slot->flags & NS_REPORT || 966 nic_i == 0 || nic_i == report_frequency) ? 967 IPI_TX_INTR : 0; 968 969 /* device-specific */ 970 pi.ipi_len = len; 971 pi.ipi_segs[0].ds_addr = paddr; 972 pi.ipi_segs[0].ds_len = len; 973 pi.ipi_nsegs = 1; 974 pi.ipi_ndescs = 0; 975 pi.ipi_pidx = nic_i; 976 pi.ipi_flags = flags; 977 978 /* Fill the slot in the NIC ring. */ 979 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 980 981 /* prefetch for next round */ 982 __builtin_prefetch(&ring->slot[nm_i + 1]); 983 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 984 if (txq->ift_sds.ifsd_map) { 985 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 986 987 NM_CHECK_ADDR_LEN(na, addr, len); 988 989 if (slot->flags & NS_BUF_CHANGED) { 990 /* buffer has changed, reload map */ 991 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 992 } 993 /* make sure changes to the buffer are synced */ 994 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 995 BUS_DMASYNC_PREWRITE); 996 } 997 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 998 nm_i = nm_next(nm_i, lim); 999 nic_i = nm_next(nic_i, lim); 1000 } 1001 kring->nr_hwcur = head; 1002 1003 /* synchronize the NIC ring */ 1004 if (txq->ift_sds.ifsd_map) 1005 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1006 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1007 1008 /* (re)start the tx unit up to slot nic_i (excluded) */ 1009 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1010 } 1011 1012 /* 1013 * Second part: reclaim buffers for completed transmissions. 1014 */ 1015 if (iflib_tx_credits_update(ctx, txq)) { 1016 /* some tx completed, increment avail */ 1017 nic_i = txq->ift_cidx_processed; 1018 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1019 } 1020 return (0); 1021 } 1022 1023 /* 1024 * Reconcile kernel and user view of the receive ring. 1025 * Same as for the txsync, this routine must be efficient. 1026 * The caller guarantees a single invocations, but races against 1027 * the rest of the driver should be handled here. 1028 * 1029 * On call, kring->rhead is the first packet that userspace wants 1030 * to keep, and kring->rcur is the wakeup point. 1031 * The kernel has previously reported packets up to kring->rtail. 1032 * 1033 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1034 * of whether or not we received an interrupt. 1035 */ 1036 static int 1037 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1038 { 1039 struct netmap_adapter *na = kring->na; 1040 struct netmap_ring *ring = kring->ring; 1041 uint32_t nm_i; /* index into the netmap ring */ 1042 uint32_t nic_i; /* index into the NIC ring */ 1043 u_int i, n; 1044 u_int const lim = kring->nkr_num_slots - 1; 1045 u_int const head = netmap_idx_n2k(kring, kring->rhead); 1046 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1047 struct if_rxd_info ri; 1048 1049 struct ifnet *ifp = na->ifp; 1050 if_ctx_t ctx = ifp->if_softc; 1051 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1052 iflib_fl_t fl = rxq->ifr_fl; 1053 if (head > lim) 1054 return netmap_ring_reinit(kring); 1055 1056 /* XXX check sync modes */ 1057 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1058 if (fl->ifl_sds.ifsd_map == NULL) 1059 continue; 1060 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1061 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1062 } 1063 /* 1064 * First part: import newly received packets. 1065 * 1066 * nm_i is the index of the next free slot in the netmap ring, 1067 * nic_i is the index of the next received packet in the NIC ring, 1068 * and they may differ in case if_init() has been called while 1069 * in netmap mode. For the receive ring we have 1070 * 1071 * nic_i = rxr->next_check; 1072 * nm_i = kring->nr_hwtail (previous) 1073 * and 1074 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1075 * 1076 * rxr->next_check is set to 0 on a ring reinit 1077 */ 1078 if (netmap_no_pendintr || force_update) { 1079 int crclen = iflib_crcstrip ? 0 : 4; 1080 int error, avail; 1081 1082 for (i = 0; i < rxq->ifr_nfl; i++) { 1083 fl = &rxq->ifr_fl[i]; 1084 nic_i = fl->ifl_cidx; 1085 nm_i = netmap_idx_n2k(kring, nic_i); 1086 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1087 for (n = 0; avail > 0; n++, avail--) { 1088 rxd_info_zero(&ri); 1089 ri.iri_frags = rxq->ifr_frags; 1090 ri.iri_qsidx = kring->ring_id; 1091 ri.iri_ifp = ctx->ifc_ifp; 1092 ri.iri_cidx = nic_i; 1093 1094 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1095 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1096 ring->slot[nm_i].flags = 0; 1097 if (fl->ifl_sds.ifsd_map) 1098 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1099 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1100 nm_i = nm_next(nm_i, lim); 1101 nic_i = nm_next(nic_i, lim); 1102 } 1103 if (n) { /* update the state variables */ 1104 if (netmap_no_pendintr && !force_update) { 1105 /* diagnostics */ 1106 iflib_rx_miss ++; 1107 iflib_rx_miss_bufs += n; 1108 } 1109 fl->ifl_cidx = nic_i; 1110 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); 1111 } 1112 kring->nr_kflags &= ~NKR_PENDINTR; 1113 } 1114 } 1115 /* 1116 * Second part: skip past packets that userspace has released. 1117 * (kring->nr_hwcur to head excluded), 1118 * and make the buffers available for reception. 1119 * As usual nm_i is the index in the netmap ring, 1120 * nic_i is the index in the NIC ring, and 1121 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1122 */ 1123 /* XXX not sure how this will work with multiple free lists */ 1124 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 1125 1126 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1127 } 1128 1129 static void 1130 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1131 { 1132 struct ifnet *ifp = na->ifp; 1133 if_ctx_t ctx = ifp->if_softc; 1134 1135 CTX_LOCK(ctx); 1136 if (onoff) { 1137 IFDI_INTR_ENABLE(ctx); 1138 } else { 1139 IFDI_INTR_DISABLE(ctx); 1140 } 1141 CTX_UNLOCK(ctx); 1142 } 1143 1144 1145 static int 1146 iflib_netmap_attach(if_ctx_t ctx) 1147 { 1148 struct netmap_adapter na; 1149 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1150 1151 bzero(&na, sizeof(na)); 1152 1153 na.ifp = ctx->ifc_ifp; 1154 na.na_flags = NAF_BDG_MAYSLEEP; 1155 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1156 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1157 1158 na.num_tx_desc = scctx->isc_ntxd[0]; 1159 na.num_rx_desc = scctx->isc_nrxd[0]; 1160 na.nm_txsync = iflib_netmap_txsync; 1161 na.nm_rxsync = iflib_netmap_rxsync; 1162 na.nm_register = iflib_netmap_register; 1163 na.nm_intr = iflib_netmap_intr; 1164 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1165 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1166 return (netmap_attach(&na)); 1167 } 1168 1169 static void 1170 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1171 { 1172 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1173 struct netmap_slot *slot; 1174 1175 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1176 if (slot == NULL) 1177 return; 1178 if (txq->ift_sds.ifsd_map == NULL) 1179 return; 1180 1181 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1182 1183 /* 1184 * In netmap mode, set the map for the packet buffer. 1185 * NOTE: Some drivers (not this one) also need to set 1186 * the physical buffer address in the NIC ring. 1187 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1188 * netmap slot index, si 1189 */ 1190 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1191 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1192 } 1193 } 1194 1195 static void 1196 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1197 { 1198 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1199 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1200 struct netmap_slot *slot; 1201 uint32_t nm_i; 1202 1203 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1204 if (slot == NULL) 1205 return; 1206 nm_i = netmap_idx_n2k(kring, 0); 1207 netmap_fl_refill(rxq, kring, nm_i, true); 1208 } 1209 1210 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1211 1212 #else 1213 #define iflib_netmap_txq_init(ctx, txq) 1214 #define iflib_netmap_rxq_init(ctx, rxq) 1215 #define iflib_netmap_detach(ifp) 1216 1217 #define iflib_netmap_attach(ctx) (0) 1218 #define netmap_rx_irq(ifp, qid, budget) (0) 1219 #define netmap_tx_irq(ifp, qid) do {} while (0) 1220 1221 #endif 1222 1223 #if defined(__i386__) || defined(__amd64__) 1224 static __inline void 1225 prefetch(void *x) 1226 { 1227 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1228 } 1229 static __inline void 1230 prefetch2cachelines(void *x) 1231 { 1232 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1233 #if (CACHE_LINE_SIZE < 128) 1234 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1235 #endif 1236 } 1237 #else 1238 #define prefetch(x) 1239 #define prefetch2cachelines(x) 1240 #endif 1241 1242 static void 1243 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1244 { 1245 iflib_fl_t fl; 1246 1247 fl = &rxq->ifr_fl[flid]; 1248 iru->iru_paddrs = fl->ifl_bus_addrs; 1249 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1250 iru->iru_idxs = fl->ifl_rxd_idxs; 1251 iru->iru_qsidx = rxq->ifr_id; 1252 iru->iru_buf_size = fl->ifl_buf_size; 1253 iru->iru_flidx = fl->ifl_id; 1254 } 1255 1256 static void 1257 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1258 { 1259 if (err) 1260 return; 1261 *(bus_addr_t *) arg = segs[0].ds_addr; 1262 } 1263 1264 int 1265 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1266 { 1267 int err; 1268 if_shared_ctx_t sctx = ctx->ifc_sctx; 1269 device_t dev = ctx->ifc_dev; 1270 1271 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1272 1273 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1274 sctx->isc_q_align, 0, /* alignment, bounds */ 1275 BUS_SPACE_MAXADDR, /* lowaddr */ 1276 BUS_SPACE_MAXADDR, /* highaddr */ 1277 NULL, NULL, /* filter, filterarg */ 1278 size, /* maxsize */ 1279 1, /* nsegments */ 1280 size, /* maxsegsize */ 1281 BUS_DMA_ALLOCNOW, /* flags */ 1282 NULL, /* lockfunc */ 1283 NULL, /* lockarg */ 1284 &dma->idi_tag); 1285 if (err) { 1286 device_printf(dev, 1287 "%s: bus_dma_tag_create failed: %d\n", 1288 __func__, err); 1289 goto fail_0; 1290 } 1291 1292 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1293 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1294 if (err) { 1295 device_printf(dev, 1296 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1297 __func__, (uintmax_t)size, err); 1298 goto fail_1; 1299 } 1300 1301 dma->idi_paddr = IF_BAD_DMA; 1302 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1303 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1304 if (err || dma->idi_paddr == IF_BAD_DMA) { 1305 device_printf(dev, 1306 "%s: bus_dmamap_load failed: %d\n", 1307 __func__, err); 1308 goto fail_2; 1309 } 1310 1311 dma->idi_size = size; 1312 return (0); 1313 1314 fail_2: 1315 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1316 fail_1: 1317 bus_dma_tag_destroy(dma->idi_tag); 1318 fail_0: 1319 dma->idi_tag = NULL; 1320 1321 return (err); 1322 } 1323 1324 int 1325 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1326 { 1327 int i, err; 1328 iflib_dma_info_t *dmaiter; 1329 1330 dmaiter = dmalist; 1331 for (i = 0; i < count; i++, dmaiter++) { 1332 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1333 break; 1334 } 1335 if (err) 1336 iflib_dma_free_multi(dmalist, i); 1337 return (err); 1338 } 1339 1340 void 1341 iflib_dma_free(iflib_dma_info_t dma) 1342 { 1343 if (dma->idi_tag == NULL) 1344 return; 1345 if (dma->idi_paddr != IF_BAD_DMA) { 1346 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1347 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1348 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1349 dma->idi_paddr = IF_BAD_DMA; 1350 } 1351 if (dma->idi_vaddr != NULL) { 1352 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1353 dma->idi_vaddr = NULL; 1354 } 1355 bus_dma_tag_destroy(dma->idi_tag); 1356 dma->idi_tag = NULL; 1357 } 1358 1359 void 1360 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1361 { 1362 int i; 1363 iflib_dma_info_t *dmaiter = dmalist; 1364 1365 for (i = 0; i < count; i++, dmaiter++) 1366 iflib_dma_free(*dmaiter); 1367 } 1368 1369 #ifdef EARLY_AP_STARTUP 1370 static const int iflib_started = 1; 1371 #else 1372 /* 1373 * We used to abuse the smp_started flag to decide if the queues have been 1374 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1375 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1376 * is set. Run a SYSINIT() strictly after that to just set a usable 1377 * completion flag. 1378 */ 1379 1380 static int iflib_started; 1381 1382 static void 1383 iflib_record_started(void *arg) 1384 { 1385 iflib_started = 1; 1386 } 1387 1388 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1389 iflib_record_started, NULL); 1390 #endif 1391 1392 static int 1393 iflib_fast_intr(void *arg) 1394 { 1395 iflib_filter_info_t info = arg; 1396 struct grouptask *gtask = info->ifi_task; 1397 if (!iflib_started) 1398 return (FILTER_HANDLED); 1399 1400 DBG_COUNTER_INC(fast_intrs); 1401 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1402 return (FILTER_HANDLED); 1403 1404 GROUPTASK_ENQUEUE(gtask); 1405 return (FILTER_HANDLED); 1406 } 1407 1408 static int 1409 iflib_fast_intr_rxtx(void *arg) 1410 { 1411 iflib_filter_info_t info = arg; 1412 struct grouptask *gtask = info->ifi_task; 1413 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1414 if_ctx_t ctx = NULL;; 1415 int i, cidx; 1416 1417 if (!iflib_started) 1418 return (FILTER_HANDLED); 1419 1420 DBG_COUNTER_INC(fast_intrs); 1421 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1422 return (FILTER_HANDLED); 1423 1424 MPASS(rxq->ifr_ntxqirq); 1425 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1426 qidx_t txqid = rxq->ifr_txqid[i]; 1427 1428 ctx = rxq->ifr_ctx; 1429 1430 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1431 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1432 continue; 1433 } 1434 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1435 } 1436 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1437 cidx = rxq->ifr_cq_cidx; 1438 else 1439 cidx = rxq->ifr_fl[0].ifl_cidx; 1440 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1441 GROUPTASK_ENQUEUE(gtask); 1442 else 1443 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1444 return (FILTER_HANDLED); 1445 } 1446 1447 1448 static int 1449 iflib_fast_intr_ctx(void *arg) 1450 { 1451 iflib_filter_info_t info = arg; 1452 struct grouptask *gtask = info->ifi_task; 1453 1454 if (!iflib_started) 1455 return (FILTER_HANDLED); 1456 1457 DBG_COUNTER_INC(fast_intrs); 1458 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1459 return (FILTER_HANDLED); 1460 1461 GROUPTASK_ENQUEUE(gtask); 1462 return (FILTER_HANDLED); 1463 } 1464 1465 static int 1466 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1467 driver_filter_t filter, driver_intr_t handler, void *arg, 1468 char *name) 1469 { 1470 int rc, flags; 1471 struct resource *res; 1472 void *tag = NULL; 1473 device_t dev = ctx->ifc_dev; 1474 1475 flags = RF_ACTIVE; 1476 if (ctx->ifc_flags & IFC_LEGACY) 1477 flags |= RF_SHAREABLE; 1478 MPASS(rid < 512); 1479 irq->ii_rid = rid; 1480 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1481 if (res == NULL) { 1482 device_printf(dev, 1483 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1484 return (ENOMEM); 1485 } 1486 irq->ii_res = res; 1487 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1488 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1489 filter, handler, arg, &tag); 1490 if (rc != 0) { 1491 device_printf(dev, 1492 "failed to setup interrupt for rid %d, name %s: %d\n", 1493 rid, name ? name : "unknown", rc); 1494 return (rc); 1495 } else if (name) 1496 bus_describe_intr(dev, res, tag, "%s", name); 1497 1498 irq->ii_tag = tag; 1499 return (0); 1500 } 1501 1502 1503 /********************************************************************* 1504 * 1505 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1506 * the information needed to transmit a packet on the wire. This is 1507 * called only once at attach, setup is done every reset. 1508 * 1509 **********************************************************************/ 1510 1511 static int 1512 iflib_txsd_alloc(iflib_txq_t txq) 1513 { 1514 if_ctx_t ctx = txq->ift_ctx; 1515 if_shared_ctx_t sctx = ctx->ifc_sctx; 1516 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1517 device_t dev = ctx->ifc_dev; 1518 int err, nsegments, ntsosegments; 1519 1520 nsegments = scctx->isc_tx_nsegments; 1521 ntsosegments = scctx->isc_tx_tso_segments_max; 1522 MPASS(scctx->isc_ntxd[0] > 0); 1523 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1524 MPASS(nsegments > 0); 1525 MPASS(ntsosegments > 0); 1526 /* 1527 * Setup DMA descriptor areas. 1528 */ 1529 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1530 1, 0, /* alignment, bounds */ 1531 BUS_SPACE_MAXADDR, /* lowaddr */ 1532 BUS_SPACE_MAXADDR, /* highaddr */ 1533 NULL, NULL, /* filter, filterarg */ 1534 sctx->isc_tx_maxsize, /* maxsize */ 1535 nsegments, /* nsegments */ 1536 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1537 0, /* flags */ 1538 NULL, /* lockfunc */ 1539 NULL, /* lockfuncarg */ 1540 &txq->ift_desc_tag))) { 1541 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1542 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1543 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1544 goto fail; 1545 } 1546 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1547 1, 0, /* alignment, bounds */ 1548 BUS_SPACE_MAXADDR, /* lowaddr */ 1549 BUS_SPACE_MAXADDR, /* highaddr */ 1550 NULL, NULL, /* filter, filterarg */ 1551 scctx->isc_tx_tso_size_max, /* maxsize */ 1552 ntsosegments, /* nsegments */ 1553 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1554 0, /* flags */ 1555 NULL, /* lockfunc */ 1556 NULL, /* lockfuncarg */ 1557 &txq->ift_tso_desc_tag))) { 1558 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1559 1560 goto fail; 1561 } 1562 if (!(txq->ift_sds.ifsd_flags = 1563 (uint8_t *) malloc(sizeof(uint8_t) * 1564 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1565 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1566 err = ENOMEM; 1567 goto fail; 1568 } 1569 if (!(txq->ift_sds.ifsd_m = 1570 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1571 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1572 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1573 err = ENOMEM; 1574 goto fail; 1575 } 1576 1577 /* Create the descriptor buffer dma maps */ 1578 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1579 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1580 return (0); 1581 1582 if (!(txq->ift_sds.ifsd_map = 1583 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1584 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1585 err = ENOMEM; 1586 goto fail; 1587 } 1588 1589 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1590 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1591 if (err != 0) { 1592 device_printf(dev, "Unable to create TX DMA map\n"); 1593 goto fail; 1594 } 1595 } 1596 #endif 1597 return (0); 1598 fail: 1599 /* We free all, it handles case where we are in the middle */ 1600 iflib_tx_structures_free(ctx); 1601 return (err); 1602 } 1603 1604 static void 1605 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1606 { 1607 bus_dmamap_t map; 1608 1609 map = NULL; 1610 if (txq->ift_sds.ifsd_map != NULL) 1611 map = txq->ift_sds.ifsd_map[i]; 1612 if (map != NULL) { 1613 bus_dmamap_unload(txq->ift_desc_tag, map); 1614 bus_dmamap_destroy(txq->ift_desc_tag, map); 1615 txq->ift_sds.ifsd_map[i] = NULL; 1616 } 1617 } 1618 1619 static void 1620 iflib_txq_destroy(iflib_txq_t txq) 1621 { 1622 if_ctx_t ctx = txq->ift_ctx; 1623 1624 for (int i = 0; i < txq->ift_size; i++) 1625 iflib_txsd_destroy(ctx, txq, i); 1626 if (txq->ift_sds.ifsd_map != NULL) { 1627 free(txq->ift_sds.ifsd_map, M_IFLIB); 1628 txq->ift_sds.ifsd_map = NULL; 1629 } 1630 if (txq->ift_sds.ifsd_m != NULL) { 1631 free(txq->ift_sds.ifsd_m, M_IFLIB); 1632 txq->ift_sds.ifsd_m = NULL; 1633 } 1634 if (txq->ift_sds.ifsd_flags != NULL) { 1635 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1636 txq->ift_sds.ifsd_flags = NULL; 1637 } 1638 if (txq->ift_desc_tag != NULL) { 1639 bus_dma_tag_destroy(txq->ift_desc_tag); 1640 txq->ift_desc_tag = NULL; 1641 } 1642 if (txq->ift_tso_desc_tag != NULL) { 1643 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1644 txq->ift_tso_desc_tag = NULL; 1645 } 1646 } 1647 1648 static void 1649 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1650 { 1651 struct mbuf **mp; 1652 1653 mp = &txq->ift_sds.ifsd_m[i]; 1654 if (*mp == NULL) 1655 return; 1656 1657 if (txq->ift_sds.ifsd_map != NULL) { 1658 bus_dmamap_sync(txq->ift_desc_tag, 1659 txq->ift_sds.ifsd_map[i], 1660 BUS_DMASYNC_POSTWRITE); 1661 bus_dmamap_unload(txq->ift_desc_tag, 1662 txq->ift_sds.ifsd_map[i]); 1663 } 1664 m_free(*mp); 1665 DBG_COUNTER_INC(tx_frees); 1666 *mp = NULL; 1667 } 1668 1669 static int 1670 iflib_txq_setup(iflib_txq_t txq) 1671 { 1672 if_ctx_t ctx = txq->ift_ctx; 1673 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1674 iflib_dma_info_t di; 1675 int i; 1676 1677 /* Set number of descriptors available */ 1678 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1679 /* XXX make configurable */ 1680 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1681 1682 /* Reset indices */ 1683 txq->ift_cidx_processed = 0; 1684 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1685 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1686 1687 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1688 bzero((void *)di->idi_vaddr, di->idi_size); 1689 1690 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1691 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1692 bus_dmamap_sync(di->idi_tag, di->idi_map, 1693 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1694 return (0); 1695 } 1696 1697 /********************************************************************* 1698 * 1699 * Allocate memory for rx_buffer structures. Since we use one 1700 * rx_buffer per received packet, the maximum number of rx_buffer's 1701 * that we'll need is equal to the number of receive descriptors 1702 * that we've allocated. 1703 * 1704 **********************************************************************/ 1705 static int 1706 iflib_rxsd_alloc(iflib_rxq_t rxq) 1707 { 1708 if_ctx_t ctx = rxq->ifr_ctx; 1709 if_shared_ctx_t sctx = ctx->ifc_sctx; 1710 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1711 device_t dev = ctx->ifc_dev; 1712 iflib_fl_t fl; 1713 int err; 1714 1715 MPASS(scctx->isc_nrxd[0] > 0); 1716 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1717 1718 fl = rxq->ifr_fl; 1719 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1720 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1721 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1722 1, 0, /* alignment, bounds */ 1723 BUS_SPACE_MAXADDR, /* lowaddr */ 1724 BUS_SPACE_MAXADDR, /* highaddr */ 1725 NULL, NULL, /* filter, filterarg */ 1726 sctx->isc_rx_maxsize, /* maxsize */ 1727 sctx->isc_rx_nsegments, /* nsegments */ 1728 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1729 0, /* flags */ 1730 NULL, /* lockfunc */ 1731 NULL, /* lockarg */ 1732 &fl->ifl_desc_tag); 1733 if (err) { 1734 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1735 __func__, err); 1736 goto fail; 1737 } 1738 if (!(fl->ifl_sds.ifsd_flags = 1739 (uint8_t *) malloc(sizeof(uint8_t) * 1740 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1741 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1742 err = ENOMEM; 1743 goto fail; 1744 } 1745 if (!(fl->ifl_sds.ifsd_m = 1746 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1747 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1748 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1749 err = ENOMEM; 1750 goto fail; 1751 } 1752 if (!(fl->ifl_sds.ifsd_cl = 1753 (caddr_t *) malloc(sizeof(caddr_t) * 1754 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1755 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1756 err = ENOMEM; 1757 goto fail; 1758 } 1759 1760 /* Create the descriptor buffer dma maps */ 1761 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1762 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1763 continue; 1764 1765 if (!(fl->ifl_sds.ifsd_map = 1766 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1767 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1768 err = ENOMEM; 1769 goto fail; 1770 } 1771 1772 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1773 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1774 if (err != 0) { 1775 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1776 goto fail; 1777 } 1778 } 1779 #endif 1780 } 1781 return (0); 1782 1783 fail: 1784 iflib_rx_structures_free(ctx); 1785 return (err); 1786 } 1787 1788 1789 /* 1790 * Internal service routines 1791 */ 1792 1793 struct rxq_refill_cb_arg { 1794 int error; 1795 bus_dma_segment_t seg; 1796 int nseg; 1797 }; 1798 1799 static void 1800 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1801 { 1802 struct rxq_refill_cb_arg *cb_arg = arg; 1803 1804 cb_arg->error = error; 1805 cb_arg->seg = segs[0]; 1806 cb_arg->nseg = nseg; 1807 } 1808 1809 1810 #ifdef ACPI_DMAR 1811 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1812 #else 1813 #define IS_DMAR(ctx) (0) 1814 #endif 1815 1816 /** 1817 * rxq_refill - refill an rxq free-buffer list 1818 * @ctx: the iflib context 1819 * @rxq: the free-list to refill 1820 * @n: the number of new buffers to allocate 1821 * 1822 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1823 * The caller must assure that @n does not exceed the queue's capacity. 1824 */ 1825 static void 1826 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1827 { 1828 struct mbuf *m; 1829 int idx, frag_idx = fl->ifl_fragidx; 1830 int pidx = fl->ifl_pidx; 1831 caddr_t cl, *sd_cl; 1832 struct mbuf **sd_m; 1833 uint8_t *sd_flags; 1834 struct if_rxd_update iru; 1835 bus_dmamap_t *sd_map; 1836 int n, i = 0; 1837 uint64_t bus_addr; 1838 int err; 1839 qidx_t credits; 1840 1841 sd_m = fl->ifl_sds.ifsd_m; 1842 sd_map = fl->ifl_sds.ifsd_map; 1843 sd_cl = fl->ifl_sds.ifsd_cl; 1844 sd_flags = fl->ifl_sds.ifsd_flags; 1845 idx = pidx; 1846 credits = fl->ifl_credits; 1847 1848 n = count; 1849 MPASS(n > 0); 1850 MPASS(credits + n <= fl->ifl_size); 1851 1852 if (pidx < fl->ifl_cidx) 1853 MPASS(pidx + n <= fl->ifl_cidx); 1854 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1855 MPASS(fl->ifl_gen == 0); 1856 if (pidx > fl->ifl_cidx) 1857 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1858 1859 DBG_COUNTER_INC(fl_refills); 1860 if (n > 8) 1861 DBG_COUNTER_INC(fl_refills_large); 1862 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1863 while (n--) { 1864 /* 1865 * We allocate an uninitialized mbuf + cluster, mbuf is 1866 * initialized after rx. 1867 * 1868 * If the cluster is still set then we know a minimum sized packet was received 1869 */ 1870 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1871 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1872 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1873 if ((cl = sd_cl[frag_idx]) == NULL) { 1874 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1875 break; 1876 #if MEMORY_LOGGING 1877 fl->ifl_cl_enqueued++; 1878 #endif 1879 } 1880 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1881 break; 1882 } 1883 #if MEMORY_LOGGING 1884 fl->ifl_m_enqueued++; 1885 #endif 1886 1887 DBG_COUNTER_INC(rx_allocs); 1888 #if defined(__i386__) || defined(__amd64__) 1889 if (!IS_DMAR(ctx)) { 1890 bus_addr = pmap_kextract((vm_offset_t)cl); 1891 } else 1892 #endif 1893 { 1894 struct rxq_refill_cb_arg cb_arg; 1895 1896 cb_arg.error = 0; 1897 MPASS(sd_map != NULL); 1898 MPASS(sd_map[frag_idx] != NULL); 1899 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1900 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1901 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1902 BUS_DMASYNC_PREREAD); 1903 1904 if (err != 0 || cb_arg.error) { 1905 /* 1906 * !zone_pack ? 1907 */ 1908 if (fl->ifl_zone == zone_pack) 1909 uma_zfree(fl->ifl_zone, cl); 1910 m_free(m); 1911 n = 0; 1912 goto done; 1913 } 1914 bus_addr = cb_arg.seg.ds_addr; 1915 } 1916 bit_set(fl->ifl_rx_bitmap, frag_idx); 1917 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1918 1919 MPASS(sd_m[frag_idx] == NULL); 1920 sd_cl[frag_idx] = cl; 1921 sd_m[frag_idx] = m; 1922 fl->ifl_rxd_idxs[i] = frag_idx; 1923 fl->ifl_bus_addrs[i] = bus_addr; 1924 fl->ifl_vm_addrs[i] = cl; 1925 credits++; 1926 i++; 1927 MPASS(credits <= fl->ifl_size); 1928 if (++idx == fl->ifl_size) { 1929 fl->ifl_gen = 1; 1930 idx = 0; 1931 } 1932 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1933 iru.iru_pidx = pidx; 1934 iru.iru_count = i; 1935 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1936 i = 0; 1937 pidx = idx; 1938 fl->ifl_pidx = idx; 1939 fl->ifl_credits = credits; 1940 } 1941 1942 } 1943 done: 1944 if (i) { 1945 iru.iru_pidx = pidx; 1946 iru.iru_count = i; 1947 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1948 fl->ifl_pidx = idx; 1949 fl->ifl_credits = credits; 1950 } 1951 DBG_COUNTER_INC(rxd_flush); 1952 if (fl->ifl_pidx == 0) 1953 pidx = fl->ifl_size - 1; 1954 else 1955 pidx = fl->ifl_pidx - 1; 1956 1957 if (sd_map) 1958 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1959 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1960 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1961 fl->ifl_fragidx = frag_idx; 1962 } 1963 1964 static __inline void 1965 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1966 { 1967 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1968 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1969 #ifdef INVARIANTS 1970 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1971 #endif 1972 1973 MPASS(fl->ifl_credits <= fl->ifl_size); 1974 MPASS(reclaimable == delta); 1975 1976 if (reclaimable > 0) 1977 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1978 } 1979 1980 static void 1981 iflib_fl_bufs_free(iflib_fl_t fl) 1982 { 1983 iflib_dma_info_t idi = fl->ifl_ifdi; 1984 uint32_t i; 1985 1986 for (i = 0; i < fl->ifl_size; i++) { 1987 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1988 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1989 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1990 1991 if (*sd_flags & RX_SW_DESC_INUSE) { 1992 if (fl->ifl_sds.ifsd_map != NULL) { 1993 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1994 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1995 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach) 1996 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1997 } 1998 if (*sd_m != NULL) { 1999 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2000 uma_zfree(zone_mbuf, *sd_m); 2001 } 2002 if (*sd_cl != NULL) 2003 uma_zfree(fl->ifl_zone, *sd_cl); 2004 *sd_flags = 0; 2005 } else { 2006 MPASS(*sd_cl == NULL); 2007 MPASS(*sd_m == NULL); 2008 } 2009 #if MEMORY_LOGGING 2010 fl->ifl_m_dequeued++; 2011 fl->ifl_cl_dequeued++; 2012 #endif 2013 *sd_cl = NULL; 2014 *sd_m = NULL; 2015 } 2016 #ifdef INVARIANTS 2017 for (i = 0; i < fl->ifl_size; i++) { 2018 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2019 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2020 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2021 } 2022 #endif 2023 /* 2024 * Reset free list values 2025 */ 2026 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2027 bzero(idi->idi_vaddr, idi->idi_size); 2028 } 2029 2030 /********************************************************************* 2031 * 2032 * Initialize a receive ring and its buffers. 2033 * 2034 **********************************************************************/ 2035 static int 2036 iflib_fl_setup(iflib_fl_t fl) 2037 { 2038 iflib_rxq_t rxq = fl->ifl_rxq; 2039 if_ctx_t ctx = rxq->ifr_ctx; 2040 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2041 2042 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2043 /* 2044 ** Free current RX buffer structs and their mbufs 2045 */ 2046 iflib_fl_bufs_free(fl); 2047 /* Now replenish the mbufs */ 2048 MPASS(fl->ifl_credits == 0); 2049 /* 2050 * XXX don't set the max_frame_size to larger 2051 * than the hardware can handle 2052 */ 2053 if (sctx->isc_max_frame_size <= 2048) 2054 fl->ifl_buf_size = MCLBYTES; 2055 #ifndef CONTIGMALLOC_WORKS 2056 else 2057 fl->ifl_buf_size = MJUMPAGESIZE; 2058 #else 2059 else if (sctx->isc_max_frame_size <= 4096) 2060 fl->ifl_buf_size = MJUMPAGESIZE; 2061 else if (sctx->isc_max_frame_size <= 9216) 2062 fl->ifl_buf_size = MJUM9BYTES; 2063 else 2064 fl->ifl_buf_size = MJUM16BYTES; 2065 #endif 2066 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2067 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2068 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2069 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2070 2071 2072 /* avoid pre-allocating zillions of clusters to an idle card 2073 * potentially speeding up attach 2074 */ 2075 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2076 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2077 if (min(128, fl->ifl_size) != fl->ifl_credits) 2078 return (ENOBUFS); 2079 /* 2080 * handle failure 2081 */ 2082 MPASS(rxq != NULL); 2083 MPASS(fl->ifl_ifdi != NULL); 2084 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2085 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2086 return (0); 2087 } 2088 2089 /********************************************************************* 2090 * 2091 * Free receive ring data structures 2092 * 2093 **********************************************************************/ 2094 static void 2095 iflib_rx_sds_free(iflib_rxq_t rxq) 2096 { 2097 iflib_fl_t fl; 2098 int i; 2099 2100 if (rxq->ifr_fl != NULL) { 2101 for (i = 0; i < rxq->ifr_nfl; i++) { 2102 fl = &rxq->ifr_fl[i]; 2103 if (fl->ifl_desc_tag != NULL) { 2104 bus_dma_tag_destroy(fl->ifl_desc_tag); 2105 fl->ifl_desc_tag = NULL; 2106 } 2107 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2108 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2109 /* XXX destroy maps first */ 2110 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2111 fl->ifl_sds.ifsd_m = NULL; 2112 fl->ifl_sds.ifsd_cl = NULL; 2113 fl->ifl_sds.ifsd_map = NULL; 2114 } 2115 free(rxq->ifr_fl, M_IFLIB); 2116 rxq->ifr_fl = NULL; 2117 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2118 } 2119 } 2120 2121 /* 2122 * MI independent logic 2123 * 2124 */ 2125 static void 2126 iflib_timer(void *arg) 2127 { 2128 iflib_txq_t txq = arg; 2129 if_ctx_t ctx = txq->ift_ctx; 2130 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2131 2132 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2133 return; 2134 /* 2135 ** Check on the state of the TX queue(s), this 2136 ** can be done without the lock because its RO 2137 ** and the HUNG state will be static if set. 2138 */ 2139 IFDI_TIMER(ctx, txq->ift_id); 2140 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2141 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2142 (sctx->isc_pause_frames == 0))) 2143 goto hung; 2144 2145 if (ifmp_ring_is_stalled(txq->ift_br)) 2146 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2147 txq->ift_cleaned_prev = txq->ift_cleaned; 2148 /* handle any laggards */ 2149 if (txq->ift_db_pending) 2150 GROUPTASK_ENQUEUE(&txq->ift_task); 2151 2152 sctx->isc_pause_frames = 0; 2153 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2154 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2155 return; 2156 hung: 2157 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2158 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2159 STATE_LOCK(ctx); 2160 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2161 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2162 iflib_admin_intr_deferred(ctx); 2163 STATE_UNLOCK(ctx); 2164 } 2165 2166 static void 2167 iflib_init_locked(if_ctx_t ctx) 2168 { 2169 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2170 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2171 if_t ifp = ctx->ifc_ifp; 2172 iflib_fl_t fl; 2173 iflib_txq_t txq; 2174 iflib_rxq_t rxq; 2175 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2176 2177 2178 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2179 IFDI_INTR_DISABLE(ctx); 2180 2181 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2182 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2183 /* Set hardware offload abilities */ 2184 if_clearhwassist(ifp); 2185 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2186 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2187 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2188 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2189 if (if_getcapenable(ifp) & IFCAP_TSO4) 2190 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2191 if (if_getcapenable(ifp) & IFCAP_TSO6) 2192 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2193 2194 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2195 CALLOUT_LOCK(txq); 2196 callout_stop(&txq->ift_timer); 2197 CALLOUT_UNLOCK(txq); 2198 iflib_netmap_txq_init(ctx, txq); 2199 } 2200 #ifdef INVARIANTS 2201 i = if_getdrvflags(ifp); 2202 #endif 2203 IFDI_INIT(ctx); 2204 MPASS(if_getdrvflags(ifp) == i); 2205 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2206 /* XXX this should really be done on a per-queue basis */ 2207 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2208 MPASS(rxq->ifr_id == i); 2209 iflib_netmap_rxq_init(ctx, rxq); 2210 continue; 2211 } 2212 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2213 if (iflib_fl_setup(fl)) { 2214 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2215 goto done; 2216 } 2217 } 2218 } 2219 done: 2220 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2221 IFDI_INTR_ENABLE(ctx); 2222 txq = ctx->ifc_txqs; 2223 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2224 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2225 txq->ift_timer.c_cpu); 2226 } 2227 2228 static int 2229 iflib_media_change(if_t ifp) 2230 { 2231 if_ctx_t ctx = if_getsoftc(ifp); 2232 int err; 2233 2234 CTX_LOCK(ctx); 2235 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2236 iflib_init_locked(ctx); 2237 CTX_UNLOCK(ctx); 2238 return (err); 2239 } 2240 2241 static void 2242 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2243 { 2244 if_ctx_t ctx = if_getsoftc(ifp); 2245 2246 CTX_LOCK(ctx); 2247 IFDI_UPDATE_ADMIN_STATUS(ctx); 2248 IFDI_MEDIA_STATUS(ctx, ifmr); 2249 CTX_UNLOCK(ctx); 2250 } 2251 2252 static void 2253 iflib_stop(if_ctx_t ctx) 2254 { 2255 iflib_txq_t txq = ctx->ifc_txqs; 2256 iflib_rxq_t rxq = ctx->ifc_rxqs; 2257 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2258 iflib_dma_info_t di; 2259 iflib_fl_t fl; 2260 int i, j; 2261 2262 /* Tell the stack that the interface is no longer active */ 2263 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2264 2265 IFDI_INTR_DISABLE(ctx); 2266 DELAY(1000); 2267 IFDI_STOP(ctx); 2268 DELAY(1000); 2269 2270 iflib_debug_reset(); 2271 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2272 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2273 /* make sure all transmitters have completed before proceeding XXX */ 2274 2275 CALLOUT_LOCK(txq); 2276 callout_stop(&txq->ift_timer); 2277 CALLOUT_UNLOCK(txq); 2278 2279 /* clean any enqueued buffers */ 2280 iflib_ifmp_purge(txq); 2281 /* Free any existing tx buffers. */ 2282 for (j = 0; j < txq->ift_size; j++) { 2283 iflib_txsd_free(ctx, txq, j); 2284 } 2285 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2286 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2287 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2288 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2289 txq->ift_pullups = 0; 2290 ifmp_ring_reset_stats(txq->ift_br); 2291 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2292 bzero((void *)di->idi_vaddr, di->idi_size); 2293 } 2294 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2295 /* make sure all transmitters have completed before proceeding XXX */ 2296 2297 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++) 2298 bzero((void *)di->idi_vaddr, di->idi_size); 2299 /* also resets the free lists pidx/cidx */ 2300 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2301 iflib_fl_bufs_free(fl); 2302 } 2303 } 2304 2305 static inline caddr_t 2306 calc_next_rxd(iflib_fl_t fl, int cidx) 2307 { 2308 qidx_t size; 2309 int nrxd; 2310 caddr_t start, end, cur, next; 2311 2312 nrxd = fl->ifl_size; 2313 size = fl->ifl_rxd_size; 2314 start = fl->ifl_ifdi->idi_vaddr; 2315 2316 if (__predict_false(size == 0)) 2317 return (start); 2318 cur = start + size*cidx; 2319 end = start + size*nrxd; 2320 next = CACHE_PTR_NEXT(cur); 2321 return (next < end ? next : start); 2322 } 2323 2324 static inline void 2325 prefetch_pkts(iflib_fl_t fl, int cidx) 2326 { 2327 int nextptr; 2328 int nrxd = fl->ifl_size; 2329 caddr_t next_rxd; 2330 2331 2332 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2333 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2334 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2335 next_rxd = calc_next_rxd(fl, cidx); 2336 prefetch(next_rxd); 2337 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2338 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2339 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2340 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2341 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2342 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2343 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2344 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2345 } 2346 2347 static void 2348 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2349 { 2350 int flid, cidx; 2351 bus_dmamap_t map; 2352 iflib_fl_t fl; 2353 iflib_dma_info_t di; 2354 int next; 2355 2356 map = NULL; 2357 flid = irf->irf_flid; 2358 cidx = irf->irf_idx; 2359 fl = &rxq->ifr_fl[flid]; 2360 sd->ifsd_fl = fl; 2361 sd->ifsd_cidx = cidx; 2362 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2363 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2364 fl->ifl_credits--; 2365 #if MEMORY_LOGGING 2366 fl->ifl_m_dequeued++; 2367 #endif 2368 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2369 prefetch_pkts(fl, cidx); 2370 if (fl->ifl_sds.ifsd_map != NULL) { 2371 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2372 prefetch(&fl->ifl_sds.ifsd_map[next]); 2373 map = fl->ifl_sds.ifsd_map[cidx]; 2374 di = fl->ifl_ifdi; 2375 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2376 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2377 bus_dmamap_sync(di->idi_tag, di->idi_map, 2378 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2379 2380 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2381 MPASS(fl->ifl_cidx == cidx); 2382 if (unload) 2383 bus_dmamap_unload(fl->ifl_desc_tag, map); 2384 } 2385 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2386 if (__predict_false(fl->ifl_cidx == 0)) 2387 fl->ifl_gen = 0; 2388 if (map != NULL) 2389 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2390 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2391 bit_clear(fl->ifl_rx_bitmap, cidx); 2392 } 2393 2394 static struct mbuf * 2395 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2396 { 2397 int i, padlen , flags; 2398 struct mbuf *m, *mh, *mt; 2399 caddr_t cl; 2400 2401 i = 0; 2402 mh = NULL; 2403 do { 2404 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2405 2406 MPASS(*sd->ifsd_cl != NULL); 2407 MPASS(*sd->ifsd_m != NULL); 2408 2409 /* Don't include zero-length frags */ 2410 if (ri->iri_frags[i].irf_len == 0) { 2411 /* XXX we can save the cluster here, but not the mbuf */ 2412 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2413 m_free(*sd->ifsd_m); 2414 *sd->ifsd_m = NULL; 2415 continue; 2416 } 2417 m = *sd->ifsd_m; 2418 *sd->ifsd_m = NULL; 2419 if (mh == NULL) { 2420 flags = M_PKTHDR|M_EXT; 2421 mh = mt = m; 2422 padlen = ri->iri_pad; 2423 } else { 2424 flags = M_EXT; 2425 mt->m_next = m; 2426 mt = m; 2427 /* assuming padding is only on the first fragment */ 2428 padlen = 0; 2429 } 2430 cl = *sd->ifsd_cl; 2431 *sd->ifsd_cl = NULL; 2432 2433 /* Can these two be made one ? */ 2434 m_init(m, M_NOWAIT, MT_DATA, flags); 2435 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2436 /* 2437 * These must follow m_init and m_cljset 2438 */ 2439 m->m_data += padlen; 2440 ri->iri_len -= padlen; 2441 m->m_len = ri->iri_frags[i].irf_len; 2442 } while (++i < ri->iri_nfrags); 2443 2444 return (mh); 2445 } 2446 2447 /* 2448 * Process one software descriptor 2449 */ 2450 static struct mbuf * 2451 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2452 { 2453 struct if_rxsd sd; 2454 struct mbuf *m; 2455 2456 /* should I merge this back in now that the two paths are basically duplicated? */ 2457 if (ri->iri_nfrags == 1 && 2458 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2459 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2460 m = *sd.ifsd_m; 2461 *sd.ifsd_m = NULL; 2462 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2463 #ifndef __NO_STRICT_ALIGNMENT 2464 if (!IP_ALIGNED(m)) 2465 m->m_data += 2; 2466 #endif 2467 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2468 m->m_len = ri->iri_frags[0].irf_len; 2469 } else { 2470 m = assemble_segments(rxq, ri, &sd); 2471 } 2472 m->m_pkthdr.len = ri->iri_len; 2473 m->m_pkthdr.rcvif = ri->iri_ifp; 2474 m->m_flags |= ri->iri_flags; 2475 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2476 m->m_pkthdr.flowid = ri->iri_flowid; 2477 M_HASHTYPE_SET(m, ri->iri_rsstype); 2478 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2479 m->m_pkthdr.csum_data = ri->iri_csum_data; 2480 return (m); 2481 } 2482 2483 #if defined(INET6) || defined(INET) 2484 static void 2485 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2486 { 2487 CURVNET_SET(lc->ifp->if_vnet); 2488 #if defined(INET6) 2489 *v6 = VNET(ip6_forwarding); 2490 #endif 2491 #if defined(INET) 2492 *v4 = VNET(ipforwarding); 2493 #endif 2494 CURVNET_RESTORE(); 2495 } 2496 2497 /* 2498 * Returns true if it's possible this packet could be LROed. 2499 * if it returns false, it is guaranteed that tcp_lro_rx() 2500 * would not return zero. 2501 */ 2502 static bool 2503 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2504 { 2505 struct ether_header *eh; 2506 uint16_t eh_type; 2507 2508 eh = mtod(m, struct ether_header *); 2509 eh_type = ntohs(eh->ether_type); 2510 switch (eh_type) { 2511 #if defined(INET6) 2512 case ETHERTYPE_IPV6: 2513 return !v6_forwarding; 2514 #endif 2515 #if defined (INET) 2516 case ETHERTYPE_IP: 2517 return !v4_forwarding; 2518 #endif 2519 } 2520 2521 return false; 2522 } 2523 #else 2524 static void 2525 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2526 { 2527 } 2528 #endif 2529 2530 static bool 2531 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2532 { 2533 if_ctx_t ctx = rxq->ifr_ctx; 2534 if_shared_ctx_t sctx = ctx->ifc_sctx; 2535 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2536 int avail, i; 2537 qidx_t *cidxp; 2538 struct if_rxd_info ri; 2539 int err, budget_left, rx_bytes, rx_pkts; 2540 iflib_fl_t fl; 2541 struct ifnet *ifp; 2542 int lro_enabled; 2543 bool lro_possible = false; 2544 bool v4_forwarding, v6_forwarding; 2545 2546 /* 2547 * XXX early demux data packets so that if_input processing only handles 2548 * acks in interrupt context 2549 */ 2550 struct mbuf *m, *mh, *mt, *mf; 2551 2552 ifp = ctx->ifc_ifp; 2553 mh = mt = NULL; 2554 MPASS(budget > 0); 2555 rx_pkts = rx_bytes = 0; 2556 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2557 cidxp = &rxq->ifr_cq_cidx; 2558 else 2559 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2560 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2561 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2562 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2563 DBG_COUNTER_INC(rx_unavail); 2564 return (false); 2565 } 2566 2567 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2568 if (__predict_false(!CTX_ACTIVE(ctx))) { 2569 DBG_COUNTER_INC(rx_ctx_inactive); 2570 break; 2571 } 2572 /* 2573 * Reset client set fields to their default values 2574 */ 2575 rxd_info_zero(&ri); 2576 ri.iri_qsidx = rxq->ifr_id; 2577 ri.iri_cidx = *cidxp; 2578 ri.iri_ifp = ifp; 2579 ri.iri_frags = rxq->ifr_frags; 2580 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2581 2582 if (err) 2583 goto err; 2584 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2585 *cidxp = ri.iri_cidx; 2586 /* Update our consumer index */ 2587 /* XXX NB: shurd - check if this is still safe */ 2588 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2589 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2590 rxq->ifr_cq_gen = 0; 2591 } 2592 /* was this only a completion queue message? */ 2593 if (__predict_false(ri.iri_nfrags == 0)) 2594 continue; 2595 } 2596 MPASS(ri.iri_nfrags != 0); 2597 MPASS(ri.iri_len != 0); 2598 2599 /* will advance the cidx on the corresponding free lists */ 2600 m = iflib_rxd_pkt_get(rxq, &ri); 2601 if (avail == 0 && budget_left) 2602 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2603 2604 if (__predict_false(m == NULL)) { 2605 DBG_COUNTER_INC(rx_mbuf_null); 2606 continue; 2607 } 2608 /* imm_pkt: -- cxgb */ 2609 if (mh == NULL) 2610 mh = mt = m; 2611 else { 2612 mt->m_nextpkt = m; 2613 mt = m; 2614 } 2615 } 2616 /* make sure that we can refill faster than drain */ 2617 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2618 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2619 2620 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2621 if (lro_enabled) 2622 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2623 mt = mf = NULL; 2624 while (mh != NULL) { 2625 m = mh; 2626 mh = mh->m_nextpkt; 2627 m->m_nextpkt = NULL; 2628 #ifndef __NO_STRICT_ALIGNMENT 2629 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2630 continue; 2631 #endif 2632 rx_bytes += m->m_pkthdr.len; 2633 rx_pkts++; 2634 #if defined(INET6) || defined(INET) 2635 if (lro_enabled) { 2636 if (!lro_possible) { 2637 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2638 if (lro_possible && mf != NULL) { 2639 ifp->if_input(ifp, mf); 2640 DBG_COUNTER_INC(rx_if_input); 2641 mt = mf = NULL; 2642 } 2643 } 2644 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2645 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2646 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2647 continue; 2648 } 2649 } 2650 #endif 2651 if (lro_possible) { 2652 ifp->if_input(ifp, m); 2653 DBG_COUNTER_INC(rx_if_input); 2654 continue; 2655 } 2656 2657 if (mf == NULL) 2658 mf = m; 2659 if (mt != NULL) 2660 mt->m_nextpkt = m; 2661 mt = m; 2662 } 2663 if (mf != NULL) { 2664 ifp->if_input(ifp, mf); 2665 DBG_COUNTER_INC(rx_if_input); 2666 } 2667 2668 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2669 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2670 2671 /* 2672 * Flush any outstanding LRO work 2673 */ 2674 #if defined(INET6) || defined(INET) 2675 tcp_lro_flush_all(&rxq->ifr_lc); 2676 #endif 2677 if (avail) 2678 return true; 2679 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2680 err: 2681 STATE_LOCK(ctx); 2682 ctx->ifc_flags |= IFC_DO_RESET; 2683 iflib_admin_intr_deferred(ctx); 2684 STATE_UNLOCK(ctx); 2685 return (false); 2686 } 2687 2688 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2689 static inline qidx_t 2690 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2691 { 2692 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2693 qidx_t minthresh = txq->ift_size / 8; 2694 if (in_use > 4*minthresh) 2695 return (notify_count); 2696 if (in_use > 2*minthresh) 2697 return (notify_count >> 1); 2698 if (in_use > minthresh) 2699 return (notify_count >> 3); 2700 return (0); 2701 } 2702 2703 static inline qidx_t 2704 txq_max_rs_deferred(iflib_txq_t txq) 2705 { 2706 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2707 qidx_t minthresh = txq->ift_size / 8; 2708 if (txq->ift_in_use > 4*minthresh) 2709 return (notify_count); 2710 if (txq->ift_in_use > 2*minthresh) 2711 return (notify_count >> 1); 2712 if (txq->ift_in_use > minthresh) 2713 return (notify_count >> 2); 2714 return (2); 2715 } 2716 2717 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2718 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2719 2720 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2721 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2722 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2723 2724 /* forward compatibility for cxgb */ 2725 #define FIRST_QSET(ctx) 0 2726 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2727 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2728 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2729 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2730 2731 /* XXX we should be setting this to something other than zero */ 2732 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2733 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2734 2735 static inline bool 2736 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2737 { 2738 qidx_t dbval, max; 2739 bool rang; 2740 2741 rang = false; 2742 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2743 if (ring || txq->ift_db_pending >= max) { 2744 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2745 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2746 txq->ift_db_pending = txq->ift_npending = 0; 2747 rang = true; 2748 } 2749 return (rang); 2750 } 2751 2752 #ifdef PKT_DEBUG 2753 static void 2754 print_pkt(if_pkt_info_t pi) 2755 { 2756 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2757 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2758 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2759 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2760 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2761 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2762 } 2763 #endif 2764 2765 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2766 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2767 2768 static int 2769 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2770 { 2771 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2772 struct ether_vlan_header *eh; 2773 struct mbuf *m, *n; 2774 2775 n = m = *mp; 2776 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2777 M_WRITABLE(m) == 0) { 2778 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2779 return (ENOMEM); 2780 } else { 2781 m_freem(*mp); 2782 n = *mp = m; 2783 } 2784 } 2785 2786 /* 2787 * Determine where frame payload starts. 2788 * Jump over vlan headers if already present, 2789 * helpful for QinQ too. 2790 */ 2791 if (__predict_false(m->m_len < sizeof(*eh))) { 2792 txq->ift_pullups++; 2793 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2794 return (ENOMEM); 2795 } 2796 eh = mtod(m, struct ether_vlan_header *); 2797 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2798 pi->ipi_etype = ntohs(eh->evl_proto); 2799 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2800 } else { 2801 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2802 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2803 } 2804 2805 switch (pi->ipi_etype) { 2806 #ifdef INET 2807 case ETHERTYPE_IP: 2808 { 2809 struct ip *ip = NULL; 2810 struct tcphdr *th = NULL; 2811 int minthlen; 2812 2813 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2814 if (__predict_false(m->m_len < minthlen)) { 2815 /* 2816 * if this code bloat is causing too much of a hit 2817 * move it to a separate function and mark it noinline 2818 */ 2819 if (m->m_len == pi->ipi_ehdrlen) { 2820 n = m->m_next; 2821 MPASS(n); 2822 if (n->m_len >= sizeof(*ip)) { 2823 ip = (struct ip *)n->m_data; 2824 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2825 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2826 } else { 2827 txq->ift_pullups++; 2828 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2829 return (ENOMEM); 2830 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2831 } 2832 } else { 2833 txq->ift_pullups++; 2834 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2835 return (ENOMEM); 2836 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2837 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2838 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2839 } 2840 } else { 2841 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2842 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2843 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2844 } 2845 pi->ipi_ip_hlen = ip->ip_hl << 2; 2846 pi->ipi_ipproto = ip->ip_p; 2847 pi->ipi_flags |= IPI_TX_IPV4; 2848 2849 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2850 ip->ip_sum = 0; 2851 2852 if (IS_TSO4(pi)) { 2853 if (pi->ipi_ipproto == IPPROTO_TCP) { 2854 if (__predict_false(th == NULL)) { 2855 txq->ift_pullups++; 2856 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2857 return (ENOMEM); 2858 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2859 } 2860 pi->ipi_tcp_hflags = th->th_flags; 2861 pi->ipi_tcp_hlen = th->th_off << 2; 2862 pi->ipi_tcp_seq = th->th_seq; 2863 } 2864 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2865 return (ENXIO); 2866 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2867 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2868 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2869 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2870 ip->ip_sum = 0; 2871 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2872 } 2873 } 2874 break; 2875 } 2876 #endif 2877 #ifdef INET6 2878 case ETHERTYPE_IPV6: 2879 { 2880 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2881 struct tcphdr *th; 2882 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2883 2884 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2885 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2886 return (ENOMEM); 2887 } 2888 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2889 2890 /* XXX-BZ this will go badly in case of ext hdrs. */ 2891 pi->ipi_ipproto = ip6->ip6_nxt; 2892 pi->ipi_flags |= IPI_TX_IPV6; 2893 2894 if (IS_TSO6(pi)) { 2895 if (pi->ipi_ipproto == IPPROTO_TCP) { 2896 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2897 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2898 return (ENOMEM); 2899 } 2900 pi->ipi_tcp_hflags = th->th_flags; 2901 pi->ipi_tcp_hlen = th->th_off << 2; 2902 } 2903 2904 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2905 return (ENXIO); 2906 /* 2907 * The corresponding flag is set by the stack in the IPv4 2908 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2909 * So, set it here because the rest of the flow requires it. 2910 */ 2911 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2912 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2913 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2914 } 2915 break; 2916 } 2917 #endif 2918 default: 2919 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2920 pi->ipi_ip_hlen = 0; 2921 break; 2922 } 2923 *mp = m; 2924 2925 return (0); 2926 } 2927 2928 static __noinline struct mbuf * 2929 collapse_pkthdr(struct mbuf *m0) 2930 { 2931 struct mbuf *m, *m_next, *tmp; 2932 2933 m = m0; 2934 m_next = m->m_next; 2935 while (m_next != NULL && m_next->m_len == 0) { 2936 m = m_next; 2937 m->m_next = NULL; 2938 m_free(m); 2939 m_next = m_next->m_next; 2940 } 2941 m = m0; 2942 m->m_next = m_next; 2943 if ((m_next->m_flags & M_EXT) == 0) { 2944 m = m_defrag(m, M_NOWAIT); 2945 } else { 2946 tmp = m_next->m_next; 2947 memcpy(m_next, m, MPKTHSIZE); 2948 m = m_next; 2949 m->m_next = tmp; 2950 } 2951 return (m); 2952 } 2953 2954 /* 2955 * If dodgy hardware rejects the scatter gather chain we've handed it 2956 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2957 * m_defrag'd mbufs 2958 */ 2959 static __noinline struct mbuf * 2960 iflib_remove_mbuf(iflib_txq_t txq) 2961 { 2962 int ntxd, i, pidx; 2963 struct mbuf *m, *mh, **ifsd_m; 2964 2965 pidx = txq->ift_pidx; 2966 ifsd_m = txq->ift_sds.ifsd_m; 2967 ntxd = txq->ift_size; 2968 mh = m = ifsd_m[pidx]; 2969 ifsd_m[pidx] = NULL; 2970 #if MEMORY_LOGGING 2971 txq->ift_dequeued++; 2972 #endif 2973 i = 1; 2974 2975 while (m) { 2976 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2977 #if MEMORY_LOGGING 2978 txq->ift_dequeued++; 2979 #endif 2980 m = m->m_next; 2981 i++; 2982 } 2983 return (mh); 2984 } 2985 2986 static int 2987 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2988 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2989 int max_segs, int flags) 2990 { 2991 if_ctx_t ctx; 2992 if_shared_ctx_t sctx; 2993 if_softc_ctx_t scctx; 2994 int i, next, pidx, err, ntxd, count; 2995 struct mbuf *m, *tmp, **ifsd_m; 2996 2997 m = *m0; 2998 2999 /* 3000 * Please don't ever do this 3001 */ 3002 if (__predict_false(m->m_len == 0)) 3003 *m0 = m = collapse_pkthdr(m); 3004 3005 ctx = txq->ift_ctx; 3006 sctx = ctx->ifc_sctx; 3007 scctx = &ctx->ifc_softc_ctx; 3008 ifsd_m = txq->ift_sds.ifsd_m; 3009 ntxd = txq->ift_size; 3010 pidx = txq->ift_pidx; 3011 if (map != NULL) { 3012 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3013 3014 err = bus_dmamap_load_mbuf_sg(tag, map, 3015 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3016 if (err) 3017 return (err); 3018 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3019 count = 0; 3020 m = *m0; 3021 do { 3022 if (__predict_false(m->m_len <= 0)) { 3023 tmp = m; 3024 m = m->m_next; 3025 tmp->m_next = NULL; 3026 m_free(tmp); 3027 continue; 3028 } 3029 m = m->m_next; 3030 count++; 3031 } while (m != NULL); 3032 if (count > *nsegs) { 3033 ifsd_m[pidx] = *m0; 3034 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3035 return (0); 3036 } 3037 m = *m0; 3038 count = 0; 3039 do { 3040 next = (pidx + count) & (ntxd-1); 3041 MPASS(ifsd_m[next] == NULL); 3042 ifsd_m[next] = m; 3043 count++; 3044 tmp = m; 3045 m = m->m_next; 3046 } while (m != NULL); 3047 } else { 3048 int buflen, sgsize, maxsegsz, max_sgsize; 3049 vm_offset_t vaddr; 3050 vm_paddr_t curaddr; 3051 3052 count = i = 0; 3053 m = *m0; 3054 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3055 maxsegsz = scctx->isc_tx_tso_segsize_max; 3056 else 3057 maxsegsz = sctx->isc_tx_maxsegsize; 3058 3059 do { 3060 if (__predict_false(m->m_len <= 0)) { 3061 tmp = m; 3062 m = m->m_next; 3063 tmp->m_next = NULL; 3064 m_free(tmp); 3065 continue; 3066 } 3067 buflen = m->m_len; 3068 vaddr = (vm_offset_t)m->m_data; 3069 /* 3070 * see if we can't be smarter about physically 3071 * contiguous mappings 3072 */ 3073 next = (pidx + count) & (ntxd-1); 3074 MPASS(ifsd_m[next] == NULL); 3075 #if MEMORY_LOGGING 3076 txq->ift_enqueued++; 3077 #endif 3078 ifsd_m[next] = m; 3079 while (buflen > 0) { 3080 if (i >= max_segs) 3081 goto err; 3082 max_sgsize = MIN(buflen, maxsegsz); 3083 curaddr = pmap_kextract(vaddr); 3084 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3085 sgsize = MIN(sgsize, max_sgsize); 3086 segs[i].ds_addr = curaddr; 3087 segs[i].ds_len = sgsize; 3088 vaddr += sgsize; 3089 buflen -= sgsize; 3090 i++; 3091 } 3092 count++; 3093 tmp = m; 3094 m = m->m_next; 3095 } while (m != NULL); 3096 *nsegs = i; 3097 } 3098 return (0); 3099 err: 3100 *m0 = iflib_remove_mbuf(txq); 3101 return (EFBIG); 3102 } 3103 3104 static inline caddr_t 3105 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3106 { 3107 qidx_t size; 3108 int ntxd; 3109 caddr_t start, end, cur, next; 3110 3111 ntxd = txq->ift_size; 3112 size = txq->ift_txd_size[qid]; 3113 start = txq->ift_ifdi[qid].idi_vaddr; 3114 3115 if (__predict_false(size == 0)) 3116 return (start); 3117 cur = start + size*cidx; 3118 end = start + size*ntxd; 3119 next = CACHE_PTR_NEXT(cur); 3120 return (next < end ? next : start); 3121 } 3122 3123 /* 3124 * Pad an mbuf to ensure a minimum ethernet frame size. 3125 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3126 */ 3127 static __noinline int 3128 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3129 { 3130 /* 3131 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3132 * and ARP message is the smallest common payload I can think of 3133 */ 3134 static char pad[18]; /* just zeros */ 3135 int n; 3136 struct mbuf *new_head; 3137 3138 if (!M_WRITABLE(*m_head)) { 3139 new_head = m_dup(*m_head, M_NOWAIT); 3140 if (new_head == NULL) { 3141 m_freem(*m_head); 3142 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3143 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3144 return ENOMEM; 3145 } 3146 m_freem(*m_head); 3147 *m_head = new_head; 3148 } 3149 3150 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3151 n > 0; n -= sizeof(pad)) 3152 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3153 break; 3154 3155 if (n > 0) { 3156 m_freem(*m_head); 3157 device_printf(dev, "cannot pad short frame\n"); 3158 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3159 return (ENOBUFS); 3160 } 3161 3162 return 0; 3163 } 3164 3165 static int 3166 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3167 { 3168 if_ctx_t ctx; 3169 if_shared_ctx_t sctx; 3170 if_softc_ctx_t scctx; 3171 bus_dma_segment_t *segs; 3172 struct mbuf *m_head; 3173 void *next_txd; 3174 bus_dmamap_t map; 3175 struct if_pkt_info pi; 3176 int remap = 0; 3177 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3178 bus_dma_tag_t desc_tag; 3179 3180 segs = txq->ift_segs; 3181 ctx = txq->ift_ctx; 3182 sctx = ctx->ifc_sctx; 3183 scctx = &ctx->ifc_softc_ctx; 3184 segs = txq->ift_segs; 3185 ntxd = txq->ift_size; 3186 m_head = *m_headp; 3187 map = NULL; 3188 3189 /* 3190 * If we're doing TSO the next descriptor to clean may be quite far ahead 3191 */ 3192 cidx = txq->ift_cidx; 3193 pidx = txq->ift_pidx; 3194 if (ctx->ifc_flags & IFC_PREFETCH) { 3195 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3196 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3197 next_txd = calc_next_txd(txq, cidx, 0); 3198 prefetch(next_txd); 3199 } 3200 3201 /* prefetch the next cache line of mbuf pointers and flags */ 3202 prefetch(&txq->ift_sds.ifsd_m[next]); 3203 if (txq->ift_sds.ifsd_map != NULL) { 3204 prefetch(&txq->ift_sds.ifsd_map[next]); 3205 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3206 prefetch(&txq->ift_sds.ifsd_flags[next]); 3207 } 3208 } else if (txq->ift_sds.ifsd_map != NULL) 3209 map = txq->ift_sds.ifsd_map[pidx]; 3210 3211 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3212 desc_tag = txq->ift_tso_desc_tag; 3213 max_segs = scctx->isc_tx_tso_segments_max; 3214 } else { 3215 desc_tag = txq->ift_desc_tag; 3216 max_segs = scctx->isc_tx_nsegments; 3217 } 3218 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3219 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3220 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3221 if (err) 3222 return err; 3223 } 3224 m_head = *m_headp; 3225 3226 pkt_info_zero(&pi); 3227 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3228 pi.ipi_pidx = pidx; 3229 pi.ipi_qsidx = txq->ift_id; 3230 pi.ipi_len = m_head->m_pkthdr.len; 3231 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3232 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3233 3234 /* deliberate bitwise OR to make one condition */ 3235 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3236 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3237 return (err); 3238 m_head = *m_headp; 3239 } 3240 3241 retry: 3242 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3243 defrag: 3244 if (__predict_false(err)) { 3245 switch (err) { 3246 case EFBIG: 3247 /* try collapse once and defrag once */ 3248 if (remap == 0) { 3249 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3250 /* try defrag if collapsing fails */ 3251 if (m_head == NULL) 3252 remap++; 3253 } 3254 if (remap == 1) 3255 m_head = m_defrag(*m_headp, M_NOWAIT); 3256 remap++; 3257 if (__predict_false(m_head == NULL)) 3258 goto defrag_failed; 3259 txq->ift_mbuf_defrag++; 3260 *m_headp = m_head; 3261 goto retry; 3262 break; 3263 case ENOMEM: 3264 txq->ift_no_tx_dma_setup++; 3265 break; 3266 default: 3267 txq->ift_no_tx_dma_setup++; 3268 m_freem(*m_headp); 3269 DBG_COUNTER_INC(tx_frees); 3270 *m_headp = NULL; 3271 break; 3272 } 3273 txq->ift_map_failed++; 3274 DBG_COUNTER_INC(encap_load_mbuf_fail); 3275 return (err); 3276 } 3277 3278 /* 3279 * XXX assumes a 1 to 1 relationship between segments and 3280 * descriptors - this does not hold true on all drivers, e.g. 3281 * cxgb 3282 */ 3283 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3284 txq->ift_no_desc_avail++; 3285 if (map != NULL) 3286 bus_dmamap_unload(desc_tag, map); 3287 DBG_COUNTER_INC(encap_txq_avail_fail); 3288 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3289 GROUPTASK_ENQUEUE(&txq->ift_task); 3290 return (ENOBUFS); 3291 } 3292 /* 3293 * On Intel cards we can greatly reduce the number of TX interrupts 3294 * we see by only setting report status on every Nth descriptor. 3295 * However, this also means that the driver will need to keep track 3296 * of the descriptors that RS was set on to check them for the DD bit. 3297 */ 3298 txq->ift_rs_pending += nsegs + 1; 3299 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3300 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3301 pi.ipi_flags |= IPI_TX_INTR; 3302 txq->ift_rs_pending = 0; 3303 } 3304 3305 pi.ipi_segs = segs; 3306 pi.ipi_nsegs = nsegs; 3307 3308 MPASS(pidx >= 0 && pidx < txq->ift_size); 3309 #ifdef PKT_DEBUG 3310 print_pkt(&pi); 3311 #endif 3312 if (map != NULL) 3313 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3314 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3315 if (map != NULL) 3316 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3317 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3318 DBG_COUNTER_INC(tx_encap); 3319 MPASS(pi.ipi_new_pidx < txq->ift_size); 3320 3321 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3322 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3323 ndesc += txq->ift_size; 3324 txq->ift_gen = 1; 3325 } 3326 /* 3327 * drivers can need as many as 3328 * two sentinels 3329 */ 3330 MPASS(ndesc <= pi.ipi_nsegs + 2); 3331 MPASS(pi.ipi_new_pidx != pidx); 3332 MPASS(ndesc > 0); 3333 txq->ift_in_use += ndesc; 3334 3335 /* 3336 * We update the last software descriptor again here because there may 3337 * be a sentinel and/or there may be more mbufs than segments 3338 */ 3339 txq->ift_pidx = pi.ipi_new_pidx; 3340 txq->ift_npending += pi.ipi_ndescs; 3341 } else { 3342 *m_headp = m_head = iflib_remove_mbuf(txq); 3343 if (err == EFBIG) { 3344 txq->ift_txd_encap_efbig++; 3345 if (remap < 2) { 3346 remap = 1; 3347 goto defrag; 3348 } 3349 } 3350 DBG_COUNTER_INC(encap_txd_encap_fail); 3351 goto defrag_failed; 3352 } 3353 return (err); 3354 3355 defrag_failed: 3356 txq->ift_mbuf_defrag_failed++; 3357 txq->ift_map_failed++; 3358 m_freem(*m_headp); 3359 DBG_COUNTER_INC(tx_frees); 3360 *m_headp = NULL; 3361 return (ENOMEM); 3362 } 3363 3364 static void 3365 iflib_tx_desc_free(iflib_txq_t txq, int n) 3366 { 3367 int hasmap; 3368 uint32_t qsize, cidx, mask, gen; 3369 struct mbuf *m, **ifsd_m; 3370 uint8_t *ifsd_flags; 3371 bus_dmamap_t *ifsd_map; 3372 bool do_prefetch; 3373 3374 cidx = txq->ift_cidx; 3375 gen = txq->ift_gen; 3376 qsize = txq->ift_size; 3377 mask = qsize-1; 3378 hasmap = txq->ift_sds.ifsd_map != NULL; 3379 ifsd_flags = txq->ift_sds.ifsd_flags; 3380 ifsd_m = txq->ift_sds.ifsd_m; 3381 ifsd_map = txq->ift_sds.ifsd_map; 3382 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3383 3384 while (n--) { 3385 if (do_prefetch) { 3386 prefetch(ifsd_m[(cidx + 3) & mask]); 3387 prefetch(ifsd_m[(cidx + 4) & mask]); 3388 } 3389 if (ifsd_m[cidx] != NULL) { 3390 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3391 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3392 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3393 /* 3394 * does it matter if it's not the TSO tag? If so we'll 3395 * have to add the type to flags 3396 */ 3397 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3398 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3399 } 3400 if ((m = ifsd_m[cidx]) != NULL) { 3401 /* XXX we don't support any drivers that batch packets yet */ 3402 MPASS(m->m_nextpkt == NULL); 3403 /* if the number of clusters exceeds the number of segments 3404 * there won't be space on the ring to save a pointer to each 3405 * cluster so we simply free the list here 3406 */ 3407 if (m->m_flags & M_TOOBIG) { 3408 m_freem(m); 3409 } else { 3410 m_free(m); 3411 } 3412 ifsd_m[cidx] = NULL; 3413 #if MEMORY_LOGGING 3414 txq->ift_dequeued++; 3415 #endif 3416 DBG_COUNTER_INC(tx_frees); 3417 } 3418 } 3419 if (__predict_false(++cidx == qsize)) { 3420 cidx = 0; 3421 gen = 0; 3422 } 3423 } 3424 txq->ift_cidx = cidx; 3425 txq->ift_gen = gen; 3426 } 3427 3428 static __inline int 3429 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3430 { 3431 int reclaim; 3432 if_ctx_t ctx = txq->ift_ctx; 3433 3434 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3435 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3436 3437 /* 3438 * Need a rate-limiting check so that this isn't called every time 3439 */ 3440 iflib_tx_credits_update(ctx, txq); 3441 reclaim = DESC_RECLAIMABLE(txq); 3442 3443 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3444 #ifdef INVARIANTS 3445 if (iflib_verbose_debug) { 3446 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3447 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3448 reclaim, thresh); 3449 3450 } 3451 #endif 3452 return (0); 3453 } 3454 iflib_tx_desc_free(txq, reclaim); 3455 txq->ift_cleaned += reclaim; 3456 txq->ift_in_use -= reclaim; 3457 3458 return (reclaim); 3459 } 3460 3461 static struct mbuf ** 3462 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3463 { 3464 int next, size; 3465 struct mbuf **items; 3466 3467 size = r->size; 3468 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3469 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3470 3471 prefetch(items[(cidx + offset) & (size-1)]); 3472 if (remaining > 1) { 3473 prefetch2cachelines(&items[next]); 3474 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3475 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3476 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3477 } 3478 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3479 } 3480 3481 static void 3482 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3483 { 3484 3485 ifmp_ring_check_drainage(txq->ift_br, budget); 3486 } 3487 3488 static uint32_t 3489 iflib_txq_can_drain(struct ifmp_ring *r) 3490 { 3491 iflib_txq_t txq = r->cookie; 3492 if_ctx_t ctx = txq->ift_ctx; 3493 3494 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3495 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3496 } 3497 3498 static uint32_t 3499 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3500 { 3501 iflib_txq_t txq = r->cookie; 3502 if_ctx_t ctx = txq->ift_ctx; 3503 struct ifnet *ifp = ctx->ifc_ifp; 3504 struct mbuf **mp, *m; 3505 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3506 int reclaimed, err, in_use_prev, desc_used; 3507 bool do_prefetch, ring, rang; 3508 3509 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3510 !LINK_ACTIVE(ctx))) { 3511 DBG_COUNTER_INC(txq_drain_notready); 3512 return (0); 3513 } 3514 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3515 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3516 avail = IDXDIFF(pidx, cidx, r->size); 3517 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3518 DBG_COUNTER_INC(txq_drain_flushing); 3519 for (i = 0; i < avail; i++) { 3520 m_free(r->items[(cidx + i) & (r->size-1)]); 3521 r->items[(cidx + i) & (r->size-1)] = NULL; 3522 } 3523 return (avail); 3524 } 3525 3526 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3527 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3528 CALLOUT_LOCK(txq); 3529 callout_stop(&txq->ift_timer); 3530 CALLOUT_UNLOCK(txq); 3531 DBG_COUNTER_INC(txq_drain_oactive); 3532 return (0); 3533 } 3534 if (reclaimed) 3535 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3536 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3537 count = MIN(avail, TX_BATCH_SIZE); 3538 #ifdef INVARIANTS 3539 if (iflib_verbose_debug) 3540 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3541 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3542 #endif 3543 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3544 avail = TXQ_AVAIL(txq); 3545 err = 0; 3546 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3547 int rem = do_prefetch ? count - i : 0; 3548 3549 mp = _ring_peek_one(r, cidx, i, rem); 3550 MPASS(mp != NULL && *mp != NULL); 3551 if (__predict_false(*mp == (struct mbuf *)txq)) { 3552 consumed++; 3553 reclaimed++; 3554 continue; 3555 } 3556 in_use_prev = txq->ift_in_use; 3557 err = iflib_encap(txq, mp); 3558 if (__predict_false(err)) { 3559 DBG_COUNTER_INC(txq_drain_encapfail); 3560 /* no room - bail out */ 3561 if (err == ENOBUFS) 3562 break; 3563 consumed++; 3564 DBG_COUNTER_INC(txq_drain_encapfail); 3565 /* we can't send this packet - skip it */ 3566 continue; 3567 } 3568 consumed++; 3569 pkt_sent++; 3570 m = *mp; 3571 DBG_COUNTER_INC(tx_sent); 3572 bytes_sent += m->m_pkthdr.len; 3573 mcast_sent += !!(m->m_flags & M_MCAST); 3574 avail = TXQ_AVAIL(txq); 3575 3576 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3577 desc_used += (txq->ift_in_use - in_use_prev); 3578 ETHER_BPF_MTAP(ifp, m); 3579 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3580 break; 3581 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3582 } 3583 3584 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3585 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3586 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3587 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3588 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3589 if (mcast_sent) 3590 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3591 #ifdef INVARIANTS 3592 if (iflib_verbose_debug) 3593 printf("consumed=%d\n", consumed); 3594 #endif 3595 return (consumed); 3596 } 3597 3598 static uint32_t 3599 iflib_txq_drain_always(struct ifmp_ring *r) 3600 { 3601 return (1); 3602 } 3603 3604 static uint32_t 3605 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3606 { 3607 int i, avail; 3608 struct mbuf **mp; 3609 iflib_txq_t txq; 3610 3611 txq = r->cookie; 3612 3613 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3614 CALLOUT_LOCK(txq); 3615 callout_stop(&txq->ift_timer); 3616 CALLOUT_UNLOCK(txq); 3617 3618 avail = IDXDIFF(pidx, cidx, r->size); 3619 for (i = 0; i < avail; i++) { 3620 mp = _ring_peek_one(r, cidx, i, avail - i); 3621 if (__predict_false(*mp == (struct mbuf *)txq)) 3622 continue; 3623 m_freem(*mp); 3624 } 3625 MPASS(ifmp_ring_is_stalled(r) == 0); 3626 return (avail); 3627 } 3628 3629 static void 3630 iflib_ifmp_purge(iflib_txq_t txq) 3631 { 3632 struct ifmp_ring *r; 3633 3634 r = txq->ift_br; 3635 r->drain = iflib_txq_drain_free; 3636 r->can_drain = iflib_txq_drain_always; 3637 3638 ifmp_ring_check_drainage(r, r->size); 3639 3640 r->drain = iflib_txq_drain; 3641 r->can_drain = iflib_txq_can_drain; 3642 } 3643 3644 static void 3645 _task_fn_tx(void *context) 3646 { 3647 iflib_txq_t txq = context; 3648 if_ctx_t ctx = txq->ift_ctx; 3649 struct ifnet *ifp = ctx->ifc_ifp; 3650 3651 #ifdef IFLIB_DIAGNOSTICS 3652 txq->ift_cpu_exec_count[curcpu]++; 3653 #endif 3654 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3655 return; 3656 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3657 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3658 netmap_tx_irq(ifp, txq->ift_id); 3659 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3660 return; 3661 } 3662 if (txq->ift_db_pending) 3663 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3664 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3665 if (ctx->ifc_flags & IFC_LEGACY) 3666 IFDI_INTR_ENABLE(ctx); 3667 else { 3668 #ifdef INVARIANTS 3669 int rc = 3670 #endif 3671 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3672 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3673 } 3674 } 3675 3676 static void 3677 _task_fn_rx(void *context) 3678 { 3679 iflib_rxq_t rxq = context; 3680 if_ctx_t ctx = rxq->ifr_ctx; 3681 bool more; 3682 uint16_t budget; 3683 3684 #ifdef IFLIB_DIAGNOSTICS 3685 rxq->ifr_cpu_exec_count[curcpu]++; 3686 #endif 3687 DBG_COUNTER_INC(task_fn_rxs); 3688 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3689 return; 3690 more = true; 3691 #ifdef DEV_NETMAP 3692 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3693 u_int work = 0; 3694 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3695 more = false; 3696 } 3697 } 3698 #endif 3699 budget = ctx->ifc_sysctl_rx_budget; 3700 if (budget == 0) 3701 budget = 16; /* XXX */ 3702 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3703 if (ctx->ifc_flags & IFC_LEGACY) 3704 IFDI_INTR_ENABLE(ctx); 3705 else { 3706 #ifdef INVARIANTS 3707 int rc = 3708 #endif 3709 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3710 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3711 DBG_COUNTER_INC(rx_intr_enables); 3712 } 3713 } 3714 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3715 return; 3716 if (more) 3717 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3718 } 3719 3720 static void 3721 _task_fn_admin(void *context) 3722 { 3723 if_ctx_t ctx = context; 3724 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3725 iflib_txq_t txq; 3726 int i; 3727 bool oactive, running, do_reset, do_watchdog; 3728 3729 STATE_LOCK(ctx); 3730 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3731 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3732 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3733 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3734 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3735 STATE_UNLOCK(ctx); 3736 3737 if (!running & !oactive) 3738 return; 3739 3740 CTX_LOCK(ctx); 3741 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3742 CALLOUT_LOCK(txq); 3743 callout_stop(&txq->ift_timer); 3744 CALLOUT_UNLOCK(txq); 3745 } 3746 if (do_watchdog) { 3747 ctx->ifc_watchdog_events++; 3748 IFDI_WATCHDOG_RESET(ctx); 3749 } 3750 IFDI_UPDATE_ADMIN_STATUS(ctx); 3751 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3752 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3753 IFDI_LINK_INTR_ENABLE(ctx); 3754 if (do_reset) 3755 iflib_if_init_locked(ctx); 3756 CTX_UNLOCK(ctx); 3757 3758 if (LINK_ACTIVE(ctx) == 0) 3759 return; 3760 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3761 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3762 } 3763 3764 3765 static void 3766 _task_fn_iov(void *context) 3767 { 3768 if_ctx_t ctx = context; 3769 3770 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3771 return; 3772 3773 CTX_LOCK(ctx); 3774 IFDI_VFLR_HANDLE(ctx); 3775 CTX_UNLOCK(ctx); 3776 } 3777 3778 static int 3779 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3780 { 3781 int err; 3782 if_int_delay_info_t info; 3783 if_ctx_t ctx; 3784 3785 info = (if_int_delay_info_t)arg1; 3786 ctx = info->iidi_ctx; 3787 info->iidi_req = req; 3788 info->iidi_oidp = oidp; 3789 CTX_LOCK(ctx); 3790 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3791 CTX_UNLOCK(ctx); 3792 return (err); 3793 } 3794 3795 /********************************************************************* 3796 * 3797 * IFNET FUNCTIONS 3798 * 3799 **********************************************************************/ 3800 3801 static void 3802 iflib_if_init_locked(if_ctx_t ctx) 3803 { 3804 iflib_stop(ctx); 3805 iflib_init_locked(ctx); 3806 } 3807 3808 3809 static void 3810 iflib_if_init(void *arg) 3811 { 3812 if_ctx_t ctx = arg; 3813 3814 CTX_LOCK(ctx); 3815 iflib_if_init_locked(ctx); 3816 CTX_UNLOCK(ctx); 3817 } 3818 3819 static int 3820 iflib_if_transmit(if_t ifp, struct mbuf *m) 3821 { 3822 if_ctx_t ctx = if_getsoftc(ifp); 3823 3824 iflib_txq_t txq; 3825 int err, qidx; 3826 3827 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3828 DBG_COUNTER_INC(tx_frees); 3829 m_freem(m); 3830 return (ENOBUFS); 3831 } 3832 3833 MPASS(m->m_nextpkt == NULL); 3834 qidx = 0; 3835 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3836 qidx = QIDX(ctx, m); 3837 /* 3838 * XXX calculate buf_ring based on flowid (divvy up bits?) 3839 */ 3840 txq = &ctx->ifc_txqs[qidx]; 3841 3842 #ifdef DRIVER_BACKPRESSURE 3843 if (txq->ift_closed) { 3844 while (m != NULL) { 3845 next = m->m_nextpkt; 3846 m->m_nextpkt = NULL; 3847 m_freem(m); 3848 m = next; 3849 } 3850 return (ENOBUFS); 3851 } 3852 #endif 3853 #ifdef notyet 3854 qidx = count = 0; 3855 mp = marr; 3856 next = m; 3857 do { 3858 count++; 3859 next = next->m_nextpkt; 3860 } while (next != NULL); 3861 3862 if (count > nitems(marr)) 3863 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3864 /* XXX check nextpkt */ 3865 m_freem(m); 3866 /* XXX simplify for now */ 3867 DBG_COUNTER_INC(tx_frees); 3868 return (ENOBUFS); 3869 } 3870 for (next = m, i = 0; next != NULL; i++) { 3871 mp[i] = next; 3872 next = next->m_nextpkt; 3873 mp[i]->m_nextpkt = NULL; 3874 } 3875 #endif 3876 DBG_COUNTER_INC(tx_seen); 3877 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3878 3879 GROUPTASK_ENQUEUE(&txq->ift_task); 3880 if (err) { 3881 /* support forthcoming later */ 3882 #ifdef DRIVER_BACKPRESSURE 3883 txq->ift_closed = TRUE; 3884 #endif 3885 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3886 m_freem(m); 3887 } 3888 3889 return (err); 3890 } 3891 3892 static void 3893 iflib_if_qflush(if_t ifp) 3894 { 3895 if_ctx_t ctx = if_getsoftc(ifp); 3896 iflib_txq_t txq = ctx->ifc_txqs; 3897 int i; 3898 3899 STATE_LOCK(ctx); 3900 ctx->ifc_flags |= IFC_QFLUSH; 3901 STATE_UNLOCK(ctx); 3902 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3903 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3904 iflib_txq_check_drain(txq, 0); 3905 STATE_LOCK(ctx); 3906 ctx->ifc_flags &= ~IFC_QFLUSH; 3907 STATE_UNLOCK(ctx); 3908 3909 if_qflush(ifp); 3910 } 3911 3912 3913 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3914 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3915 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3916 3917 static int 3918 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3919 { 3920 if_ctx_t ctx = if_getsoftc(ifp); 3921 struct ifreq *ifr = (struct ifreq *)data; 3922 #if defined(INET) || defined(INET6) 3923 struct ifaddr *ifa = (struct ifaddr *)data; 3924 #endif 3925 bool avoid_reset = FALSE; 3926 int err = 0, reinit = 0, bits; 3927 3928 switch (command) { 3929 case SIOCSIFADDR: 3930 #ifdef INET 3931 if (ifa->ifa_addr->sa_family == AF_INET) 3932 avoid_reset = TRUE; 3933 #endif 3934 #ifdef INET6 3935 if (ifa->ifa_addr->sa_family == AF_INET6) 3936 avoid_reset = TRUE; 3937 #endif 3938 /* 3939 ** Calling init results in link renegotiation, 3940 ** so we avoid doing it when possible. 3941 */ 3942 if (avoid_reset) { 3943 if_setflagbits(ifp, IFF_UP,0); 3944 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3945 reinit = 1; 3946 #ifdef INET 3947 if (!(if_getflags(ifp) & IFF_NOARP)) 3948 arp_ifinit(ifp, ifa); 3949 #endif 3950 } else 3951 err = ether_ioctl(ifp, command, data); 3952 break; 3953 case SIOCSIFMTU: 3954 CTX_LOCK(ctx); 3955 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3956 CTX_UNLOCK(ctx); 3957 break; 3958 } 3959 bits = if_getdrvflags(ifp); 3960 /* stop the driver and free any clusters before proceeding */ 3961 iflib_stop(ctx); 3962 3963 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3964 STATE_LOCK(ctx); 3965 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3966 ctx->ifc_flags |= IFC_MULTISEG; 3967 else 3968 ctx->ifc_flags &= ~IFC_MULTISEG; 3969 STATE_UNLOCK(ctx); 3970 err = if_setmtu(ifp, ifr->ifr_mtu); 3971 } 3972 iflib_init_locked(ctx); 3973 STATE_LOCK(ctx); 3974 if_setdrvflags(ifp, bits); 3975 STATE_UNLOCK(ctx); 3976 CTX_UNLOCK(ctx); 3977 break; 3978 case SIOCSIFFLAGS: 3979 CTX_LOCK(ctx); 3980 if (if_getflags(ifp) & IFF_UP) { 3981 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3982 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3983 (IFF_PROMISC | IFF_ALLMULTI)) { 3984 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3985 } 3986 } else 3987 reinit = 1; 3988 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3989 iflib_stop(ctx); 3990 } 3991 ctx->ifc_if_flags = if_getflags(ifp); 3992 CTX_UNLOCK(ctx); 3993 break; 3994 case SIOCADDMULTI: 3995 case SIOCDELMULTI: 3996 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3997 CTX_LOCK(ctx); 3998 IFDI_INTR_DISABLE(ctx); 3999 IFDI_MULTI_SET(ctx); 4000 IFDI_INTR_ENABLE(ctx); 4001 CTX_UNLOCK(ctx); 4002 } 4003 break; 4004 case SIOCSIFMEDIA: 4005 CTX_LOCK(ctx); 4006 IFDI_MEDIA_SET(ctx); 4007 CTX_UNLOCK(ctx); 4008 /* falls thru */ 4009 case SIOCGIFMEDIA: 4010 case SIOCGIFXMEDIA: 4011 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4012 break; 4013 case SIOCGI2C: 4014 { 4015 struct ifi2creq i2c; 4016 4017 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4018 if (err != 0) 4019 break; 4020 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4021 err = EINVAL; 4022 break; 4023 } 4024 if (i2c.len > sizeof(i2c.data)) { 4025 err = EINVAL; 4026 break; 4027 } 4028 4029 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4030 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4031 sizeof(i2c)); 4032 break; 4033 } 4034 case SIOCSIFCAP: 4035 { 4036 int mask, setmask; 4037 4038 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4039 setmask = 0; 4040 #ifdef TCP_OFFLOAD 4041 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4042 #endif 4043 setmask |= (mask & IFCAP_FLAGS); 4044 4045 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4046 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4047 if ((mask & IFCAP_WOL) && 4048 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4049 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4050 if_vlancap(ifp); 4051 /* 4052 * want to ensure that traffic has stopped before we change any of the flags 4053 */ 4054 if (setmask) { 4055 CTX_LOCK(ctx); 4056 bits = if_getdrvflags(ifp); 4057 if (bits & IFF_DRV_RUNNING) 4058 iflib_stop(ctx); 4059 STATE_LOCK(ctx); 4060 if_togglecapenable(ifp, setmask); 4061 STATE_UNLOCK(ctx); 4062 if (bits & IFF_DRV_RUNNING) 4063 iflib_init_locked(ctx); 4064 STATE_LOCK(ctx); 4065 if_setdrvflags(ifp, bits); 4066 STATE_UNLOCK(ctx); 4067 CTX_UNLOCK(ctx); 4068 } 4069 break; 4070 } 4071 case SIOCGPRIVATE_0: 4072 case SIOCSDRVSPEC: 4073 case SIOCGDRVSPEC: 4074 CTX_LOCK(ctx); 4075 err = IFDI_PRIV_IOCTL(ctx, command, data); 4076 CTX_UNLOCK(ctx); 4077 break; 4078 default: 4079 err = ether_ioctl(ifp, command, data); 4080 break; 4081 } 4082 if (reinit) 4083 iflib_if_init(ctx); 4084 return (err); 4085 } 4086 4087 static uint64_t 4088 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4089 { 4090 if_ctx_t ctx = if_getsoftc(ifp); 4091 4092 return (IFDI_GET_COUNTER(ctx, cnt)); 4093 } 4094 4095 /********************************************************************* 4096 * 4097 * OTHER FUNCTIONS EXPORTED TO THE STACK 4098 * 4099 **********************************************************************/ 4100 4101 static void 4102 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4103 { 4104 if_ctx_t ctx = if_getsoftc(ifp); 4105 4106 if ((void *)ctx != arg) 4107 return; 4108 4109 if ((vtag == 0) || (vtag > 4095)) 4110 return; 4111 4112 CTX_LOCK(ctx); 4113 IFDI_VLAN_REGISTER(ctx, vtag); 4114 /* Re-init to load the changes */ 4115 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4116 iflib_if_init_locked(ctx); 4117 CTX_UNLOCK(ctx); 4118 } 4119 4120 static void 4121 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4122 { 4123 if_ctx_t ctx = if_getsoftc(ifp); 4124 4125 if ((void *)ctx != arg) 4126 return; 4127 4128 if ((vtag == 0) || (vtag > 4095)) 4129 return; 4130 4131 CTX_LOCK(ctx); 4132 IFDI_VLAN_UNREGISTER(ctx, vtag); 4133 /* Re-init to load the changes */ 4134 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4135 iflib_if_init_locked(ctx); 4136 CTX_UNLOCK(ctx); 4137 } 4138 4139 static void 4140 iflib_led_func(void *arg, int onoff) 4141 { 4142 if_ctx_t ctx = arg; 4143 4144 CTX_LOCK(ctx); 4145 IFDI_LED_FUNC(ctx, onoff); 4146 CTX_UNLOCK(ctx); 4147 } 4148 4149 /********************************************************************* 4150 * 4151 * BUS FUNCTION DEFINITIONS 4152 * 4153 **********************************************************************/ 4154 4155 int 4156 iflib_device_probe(device_t dev) 4157 { 4158 pci_vendor_info_t *ent; 4159 4160 uint16_t pci_vendor_id, pci_device_id; 4161 uint16_t pci_subvendor_id, pci_subdevice_id; 4162 uint16_t pci_rev_id; 4163 if_shared_ctx_t sctx; 4164 4165 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4166 return (ENOTSUP); 4167 4168 pci_vendor_id = pci_get_vendor(dev); 4169 pci_device_id = pci_get_device(dev); 4170 pci_subvendor_id = pci_get_subvendor(dev); 4171 pci_subdevice_id = pci_get_subdevice(dev); 4172 pci_rev_id = pci_get_revid(dev); 4173 if (sctx->isc_parse_devinfo != NULL) 4174 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4175 4176 ent = sctx->isc_vendor_info; 4177 while (ent->pvi_vendor_id != 0) { 4178 if (pci_vendor_id != ent->pvi_vendor_id) { 4179 ent++; 4180 continue; 4181 } 4182 if ((pci_device_id == ent->pvi_device_id) && 4183 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4184 (ent->pvi_subvendor_id == 0)) && 4185 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4186 (ent->pvi_subdevice_id == 0)) && 4187 ((pci_rev_id == ent->pvi_rev_id) || 4188 (ent->pvi_rev_id == 0))) { 4189 4190 device_set_desc_copy(dev, ent->pvi_name); 4191 /* this needs to be changed to zero if the bus probing code 4192 * ever stops re-probing on best match because the sctx 4193 * may have its values over written by register calls 4194 * in subsequent probes 4195 */ 4196 return (BUS_PROBE_DEFAULT); 4197 } 4198 ent++; 4199 } 4200 return (ENXIO); 4201 } 4202 4203 int 4204 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4205 { 4206 int err, rid, msix; 4207 if_ctx_t ctx; 4208 if_t ifp; 4209 if_softc_ctx_t scctx; 4210 int i; 4211 uint16_t main_txq; 4212 uint16_t main_rxq; 4213 4214 4215 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4216 4217 if (sc == NULL) { 4218 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4219 device_set_softc(dev, ctx); 4220 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4221 } 4222 4223 ctx->ifc_sctx = sctx; 4224 ctx->ifc_dev = dev; 4225 ctx->ifc_softc = sc; 4226 4227 if ((err = iflib_register(ctx)) != 0) { 4228 device_printf(dev, "iflib_register failed %d\n", err); 4229 return (err); 4230 } 4231 iflib_add_device_sysctl_pre(ctx); 4232 4233 scctx = &ctx->ifc_softc_ctx; 4234 ifp = ctx->ifc_ifp; 4235 ctx->ifc_nhwtxqs = sctx->isc_ntxqs; 4236 4237 /* 4238 * XXX sanity check that ntxd & nrxd are a power of 2 4239 */ 4240 if (ctx->ifc_sysctl_ntxqs != 0) 4241 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4242 if (ctx->ifc_sysctl_nrxqs != 0) 4243 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4244 4245 for (i = 0; i < sctx->isc_ntxqs; i++) { 4246 if (ctx->ifc_sysctl_ntxds[i] != 0) 4247 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4248 else 4249 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4250 } 4251 4252 for (i = 0; i < sctx->isc_nrxqs; i++) { 4253 if (ctx->ifc_sysctl_nrxds[i] != 0) 4254 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4255 else 4256 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4257 } 4258 4259 for (i = 0; i < sctx->isc_nrxqs; i++) { 4260 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4261 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4262 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4263 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4264 } 4265 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4266 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4267 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4268 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4269 } 4270 } 4271 4272 for (i = 0; i < sctx->isc_ntxqs; i++) { 4273 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4274 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4275 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4276 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4277 } 4278 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4279 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4280 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4281 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4282 } 4283 } 4284 4285 CTX_LOCK(ctx); 4286 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4287 CTX_UNLOCK(ctx); 4288 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4289 return (err); 4290 } 4291 _iflib_pre_assert(scctx); 4292 ctx->ifc_txrx = *scctx->isc_txrx; 4293 4294 #ifdef INVARIANTS 4295 MPASS(scctx->isc_capenable); 4296 if (scctx->isc_capenable & IFCAP_TXCSUM) 4297 MPASS(scctx->isc_tx_csum_flags); 4298 #endif 4299 4300 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4301 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4302 4303 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4304 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4305 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4306 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4307 4308 #ifdef ACPI_DMAR 4309 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4310 ctx->ifc_flags |= IFC_DMAR; 4311 #elif !(defined(__i386__) || defined(__amd64__)) 4312 /* set unconditionally for !x86 */ 4313 ctx->ifc_flags |= IFC_DMAR; 4314 #endif 4315 4316 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4317 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4318 4319 /* XXX change for per-queue sizes */ 4320 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4321 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4322 for (i = 0; i < sctx->isc_nrxqs; i++) { 4323 if (!powerof2(scctx->isc_nrxd[i])) { 4324 /* round down instead? */ 4325 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4326 err = EINVAL; 4327 goto fail; 4328 } 4329 } 4330 for (i = 0; i < sctx->isc_ntxqs; i++) { 4331 if (!powerof2(scctx->isc_ntxd[i])) { 4332 device_printf(dev, 4333 "# tx descriptors must be a power of 2"); 4334 err = EINVAL; 4335 goto fail; 4336 } 4337 } 4338 4339 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4340 MAX_SINGLE_PACKET_FRACTION) 4341 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4342 MAX_SINGLE_PACKET_FRACTION); 4343 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4344 MAX_SINGLE_PACKET_FRACTION) 4345 scctx->isc_tx_tso_segments_max = max(1, 4346 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4347 4348 /* 4349 * Protect the stack against modern hardware 4350 */ 4351 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4352 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4353 4354 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4355 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4356 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4357 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4358 if (scctx->isc_rss_table_size == 0) 4359 scctx->isc_rss_table_size = 64; 4360 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4361 4362 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4363 /* XXX format name */ 4364 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4365 4366 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4367 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4368 device_printf(dev, "Unable to fetch CPU list\n"); 4369 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4370 } 4371 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4372 4373 /* 4374 ** Now setup MSI or MSI/X, should 4375 ** return us the number of supported 4376 ** vectors. (Will be 1 for MSI) 4377 */ 4378 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4379 msix = scctx->isc_vectors; 4380 } else if (scctx->isc_msix_bar != 0) 4381 /* 4382 * The simple fact that isc_msix_bar is not 0 does not mean we 4383 * we have a good value there that is known to work. 4384 */ 4385 msix = iflib_msix_init(ctx); 4386 else { 4387 scctx->isc_vectors = 1; 4388 scctx->isc_ntxqsets = 1; 4389 scctx->isc_nrxqsets = 1; 4390 scctx->isc_intr = IFLIB_INTR_LEGACY; 4391 msix = 0; 4392 } 4393 /* Get memory for the station queues */ 4394 if ((err = iflib_queues_alloc(ctx))) { 4395 device_printf(dev, "Unable to allocate queue memory\n"); 4396 goto fail; 4397 } 4398 4399 if ((err = iflib_qset_structures_setup(ctx))) { 4400 device_printf(dev, "qset structure setup failed %d\n", err); 4401 goto fail_queues; 4402 } 4403 4404 /* 4405 * Group taskqueues aren't properly set up until SMP is started, 4406 * so we disable interrupts until we can handle them post 4407 * SI_SUB_SMP. 4408 * 4409 * XXX: disabling interrupts doesn't actually work, at least for 4410 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4411 * we do null handling and depend on this not causing too large an 4412 * interrupt storm. 4413 */ 4414 IFDI_INTR_DISABLE(ctx); 4415 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4416 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4417 goto fail_intr_free; 4418 } 4419 if (msix <= 1) { 4420 rid = 0; 4421 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4422 MPASS(msix == 1); 4423 rid = 1; 4424 } 4425 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4426 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4427 goto fail_intr_free; 4428 } 4429 } 4430 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4431 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4432 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4433 goto fail_detach; 4434 } 4435 if ((err = iflib_netmap_attach(ctx))) { 4436 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4437 goto fail_detach; 4438 } 4439 *ctxp = ctx; 4440 4441 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4442 iflib_add_device_sysctl_post(ctx); 4443 ctx->ifc_flags |= IFC_INIT_DONE; 4444 CTX_UNLOCK(ctx); 4445 return (0); 4446 fail_detach: 4447 ether_ifdetach(ctx->ifc_ifp); 4448 fail_intr_free: 4449 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4450 pci_release_msi(ctx->ifc_dev); 4451 fail_queues: 4452 /* XXX free queues */ 4453 fail: 4454 IFDI_DETACH(ctx); 4455 CTX_UNLOCK(ctx); 4456 return (err); 4457 } 4458 4459 int 4460 iflib_device_attach(device_t dev) 4461 { 4462 if_ctx_t ctx; 4463 if_shared_ctx_t sctx; 4464 4465 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4466 return (ENOTSUP); 4467 4468 pci_enable_busmaster(dev); 4469 4470 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4471 } 4472 4473 int 4474 iflib_device_deregister(if_ctx_t ctx) 4475 { 4476 if_t ifp = ctx->ifc_ifp; 4477 iflib_txq_t txq; 4478 iflib_rxq_t rxq; 4479 device_t dev = ctx->ifc_dev; 4480 int i, j; 4481 struct taskqgroup *tqg; 4482 iflib_fl_t fl; 4483 4484 /* Make sure VLANS are not using driver */ 4485 if (if_vlantrunkinuse(ifp)) { 4486 device_printf(dev,"Vlan in use, detach first\n"); 4487 return (EBUSY); 4488 } 4489 4490 CTX_LOCK(ctx); 4491 ctx->ifc_in_detach = 1; 4492 iflib_stop(ctx); 4493 CTX_UNLOCK(ctx); 4494 4495 /* Unregister VLAN events */ 4496 if (ctx->ifc_vlan_attach_event != NULL) 4497 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4498 if (ctx->ifc_vlan_detach_event != NULL) 4499 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4500 4501 iflib_netmap_detach(ifp); 4502 ether_ifdetach(ifp); 4503 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4504 CTX_LOCK_DESTROY(ctx); 4505 if (ctx->ifc_led_dev != NULL) 4506 led_destroy(ctx->ifc_led_dev); 4507 /* XXX drain any dependent tasks */ 4508 tqg = qgroup_if_io_tqg; 4509 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4510 callout_drain(&txq->ift_timer); 4511 if (txq->ift_task.gt_uniq != NULL) 4512 taskqgroup_detach(tqg, &txq->ift_task); 4513 } 4514 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4515 if (rxq->ifr_task.gt_uniq != NULL) 4516 taskqgroup_detach(tqg, &rxq->ifr_task); 4517 4518 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4519 free(fl->ifl_rx_bitmap, M_IFLIB); 4520 4521 } 4522 tqg = qgroup_if_config_tqg; 4523 if (ctx->ifc_admin_task.gt_uniq != NULL) 4524 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4525 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4526 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4527 4528 IFDI_DETACH(ctx); 4529 device_set_softc(ctx->ifc_dev, NULL); 4530 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4531 pci_release_msi(dev); 4532 } 4533 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4534 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4535 } 4536 if (ctx->ifc_msix_mem != NULL) { 4537 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4538 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4539 ctx->ifc_msix_mem = NULL; 4540 } 4541 4542 bus_generic_detach(dev); 4543 if_free(ifp); 4544 4545 iflib_tx_structures_free(ctx); 4546 iflib_rx_structures_free(ctx); 4547 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4548 free(ctx->ifc_softc, M_IFLIB); 4549 free(ctx, M_IFLIB); 4550 return (0); 4551 } 4552 4553 4554 int 4555 iflib_device_detach(device_t dev) 4556 { 4557 if_ctx_t ctx = device_get_softc(dev); 4558 4559 return (iflib_device_deregister(ctx)); 4560 } 4561 4562 int 4563 iflib_device_suspend(device_t dev) 4564 { 4565 if_ctx_t ctx = device_get_softc(dev); 4566 4567 CTX_LOCK(ctx); 4568 IFDI_SUSPEND(ctx); 4569 CTX_UNLOCK(ctx); 4570 4571 return bus_generic_suspend(dev); 4572 } 4573 int 4574 iflib_device_shutdown(device_t dev) 4575 { 4576 if_ctx_t ctx = device_get_softc(dev); 4577 4578 CTX_LOCK(ctx); 4579 IFDI_SHUTDOWN(ctx); 4580 CTX_UNLOCK(ctx); 4581 4582 return bus_generic_suspend(dev); 4583 } 4584 4585 4586 int 4587 iflib_device_resume(device_t dev) 4588 { 4589 if_ctx_t ctx = device_get_softc(dev); 4590 iflib_txq_t txq = ctx->ifc_txqs; 4591 4592 CTX_LOCK(ctx); 4593 IFDI_RESUME(ctx); 4594 iflib_init_locked(ctx); 4595 CTX_UNLOCK(ctx); 4596 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4597 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4598 4599 return (bus_generic_resume(dev)); 4600 } 4601 4602 int 4603 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4604 { 4605 int error; 4606 if_ctx_t ctx = device_get_softc(dev); 4607 4608 CTX_LOCK(ctx); 4609 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4610 CTX_UNLOCK(ctx); 4611 4612 return (error); 4613 } 4614 4615 void 4616 iflib_device_iov_uninit(device_t dev) 4617 { 4618 if_ctx_t ctx = device_get_softc(dev); 4619 4620 CTX_LOCK(ctx); 4621 IFDI_IOV_UNINIT(ctx); 4622 CTX_UNLOCK(ctx); 4623 } 4624 4625 int 4626 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4627 { 4628 int error; 4629 if_ctx_t ctx = device_get_softc(dev); 4630 4631 CTX_LOCK(ctx); 4632 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4633 CTX_UNLOCK(ctx); 4634 4635 return (error); 4636 } 4637 4638 /********************************************************************* 4639 * 4640 * MODULE FUNCTION DEFINITIONS 4641 * 4642 **********************************************************************/ 4643 4644 /* 4645 * - Start a fast taskqueue thread for each core 4646 * - Start a taskqueue for control operations 4647 */ 4648 static int 4649 iflib_module_init(void) 4650 { 4651 return (0); 4652 } 4653 4654 static int 4655 iflib_module_event_handler(module_t mod, int what, void *arg) 4656 { 4657 int err; 4658 4659 switch (what) { 4660 case MOD_LOAD: 4661 if ((err = iflib_module_init()) != 0) 4662 return (err); 4663 break; 4664 case MOD_UNLOAD: 4665 return (EBUSY); 4666 default: 4667 return (EOPNOTSUPP); 4668 } 4669 4670 return (0); 4671 } 4672 4673 /********************************************************************* 4674 * 4675 * PUBLIC FUNCTION DEFINITIONS 4676 * ordered as in iflib.h 4677 * 4678 **********************************************************************/ 4679 4680 4681 static void 4682 _iflib_assert(if_shared_ctx_t sctx) 4683 { 4684 MPASS(sctx->isc_tx_maxsize); 4685 MPASS(sctx->isc_tx_maxsegsize); 4686 4687 MPASS(sctx->isc_rx_maxsize); 4688 MPASS(sctx->isc_rx_nsegments); 4689 MPASS(sctx->isc_rx_maxsegsize); 4690 4691 MPASS(sctx->isc_nrxd_min[0]); 4692 MPASS(sctx->isc_nrxd_max[0]); 4693 MPASS(sctx->isc_nrxd_default[0]); 4694 MPASS(sctx->isc_ntxd_min[0]); 4695 MPASS(sctx->isc_ntxd_max[0]); 4696 MPASS(sctx->isc_ntxd_default[0]); 4697 } 4698 4699 static void 4700 _iflib_pre_assert(if_softc_ctx_t scctx) 4701 { 4702 4703 MPASS(scctx->isc_txrx->ift_txd_encap); 4704 MPASS(scctx->isc_txrx->ift_txd_flush); 4705 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4706 MPASS(scctx->isc_txrx->ift_rxd_available); 4707 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4708 MPASS(scctx->isc_txrx->ift_rxd_refill); 4709 MPASS(scctx->isc_txrx->ift_rxd_flush); 4710 } 4711 4712 static int 4713 iflib_register(if_ctx_t ctx) 4714 { 4715 if_shared_ctx_t sctx = ctx->ifc_sctx; 4716 driver_t *driver = sctx->isc_driver; 4717 device_t dev = ctx->ifc_dev; 4718 if_t ifp; 4719 4720 _iflib_assert(sctx); 4721 4722 CTX_LOCK_INIT(ctx); 4723 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4724 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4725 if (ifp == NULL) { 4726 device_printf(dev, "can not allocate ifnet structure\n"); 4727 return (ENOMEM); 4728 } 4729 4730 /* 4731 * Initialize our context's device specific methods 4732 */ 4733 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4734 kobj_class_compile((kobj_class_t) driver); 4735 driver->refs++; 4736 4737 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4738 if_setsoftc(ifp, ctx); 4739 if_setdev(ifp, dev); 4740 if_setinitfn(ifp, iflib_if_init); 4741 if_setioctlfn(ifp, iflib_if_ioctl); 4742 if_settransmitfn(ifp, iflib_if_transmit); 4743 if_setqflushfn(ifp, iflib_if_qflush); 4744 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4745 4746 ctx->ifc_vlan_attach_event = 4747 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4748 EVENTHANDLER_PRI_FIRST); 4749 ctx->ifc_vlan_detach_event = 4750 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4751 EVENTHANDLER_PRI_FIRST); 4752 4753 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4754 iflib_media_change, iflib_media_status); 4755 4756 return (0); 4757 } 4758 4759 4760 static int 4761 iflib_queues_alloc(if_ctx_t ctx) 4762 { 4763 if_shared_ctx_t sctx = ctx->ifc_sctx; 4764 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4765 device_t dev = ctx->ifc_dev; 4766 int nrxqsets = scctx->isc_nrxqsets; 4767 int ntxqsets = scctx->isc_ntxqsets; 4768 iflib_txq_t txq; 4769 iflib_rxq_t rxq; 4770 iflib_fl_t fl = NULL; 4771 int i, j, cpu, err, txconf, rxconf; 4772 iflib_dma_info_t ifdip; 4773 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4774 uint32_t *txqsizes = scctx->isc_txqsizes; 4775 uint8_t nrxqs = sctx->isc_nrxqs; 4776 uint8_t ntxqs = sctx->isc_ntxqs; 4777 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4778 caddr_t *vaddrs; 4779 uint64_t *paddrs; 4780 4781 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4782 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4783 4784 /* Allocate the TX ring struct memory */ 4785 if (!(ctx->ifc_txqs = 4786 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4787 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4788 device_printf(dev, "Unable to allocate TX ring memory\n"); 4789 err = ENOMEM; 4790 goto fail; 4791 } 4792 4793 /* Now allocate the RX */ 4794 if (!(ctx->ifc_rxqs = 4795 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4796 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4797 device_printf(dev, "Unable to allocate RX ring memory\n"); 4798 err = ENOMEM; 4799 goto rx_fail; 4800 } 4801 4802 txq = ctx->ifc_txqs; 4803 rxq = ctx->ifc_rxqs; 4804 4805 /* 4806 * XXX handle allocation failure 4807 */ 4808 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4809 /* Set up some basics */ 4810 4811 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4812 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4813 err = ENOMEM; 4814 goto err_tx_desc; 4815 } 4816 txq->ift_ifdi = ifdip; 4817 for (j = 0; j < ntxqs; j++, ifdip++) { 4818 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4819 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4820 err = ENOMEM; 4821 goto err_tx_desc; 4822 } 4823 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4824 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4825 } 4826 txq->ift_ctx = ctx; 4827 txq->ift_id = i; 4828 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4829 txq->ift_br_offset = 1; 4830 } else { 4831 txq->ift_br_offset = 0; 4832 } 4833 /* XXX fix this */ 4834 txq->ift_timer.c_cpu = cpu; 4835 4836 if (iflib_txsd_alloc(txq)) { 4837 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4838 err = ENOMEM; 4839 goto err_tx_desc; 4840 } 4841 4842 /* Initialize the TX lock */ 4843 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4844 device_get_nameunit(dev), txq->ift_id); 4845 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4846 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4847 4848 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4849 device_get_nameunit(dev), txq->ift_id); 4850 4851 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4852 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4853 if (err) { 4854 /* XXX free any allocated rings */ 4855 device_printf(dev, "Unable to allocate buf_ring\n"); 4856 goto err_tx_desc; 4857 } 4858 } 4859 4860 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4861 /* Set up some basics */ 4862 4863 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4864 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4865 err = ENOMEM; 4866 goto err_tx_desc; 4867 } 4868 4869 rxq->ifr_ifdi = ifdip; 4870 /* XXX this needs to be changed if #rx queues != #tx queues */ 4871 rxq->ifr_ntxqirq = 1; 4872 rxq->ifr_txqid[0] = i; 4873 for (j = 0; j < nrxqs; j++, ifdip++) { 4874 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4875 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4876 err = ENOMEM; 4877 goto err_tx_desc; 4878 } 4879 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4880 } 4881 rxq->ifr_ctx = ctx; 4882 rxq->ifr_id = i; 4883 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4884 rxq->ifr_fl_offset = 1; 4885 } else { 4886 rxq->ifr_fl_offset = 0; 4887 } 4888 rxq->ifr_nfl = nfree_lists; 4889 if (!(fl = 4890 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4891 device_printf(dev, "Unable to allocate free list memory\n"); 4892 err = ENOMEM; 4893 goto err_tx_desc; 4894 } 4895 rxq->ifr_fl = fl; 4896 for (j = 0; j < nfree_lists; j++) { 4897 fl[j].ifl_rxq = rxq; 4898 fl[j].ifl_id = j; 4899 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4900 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4901 } 4902 /* Allocate receive buffers for the ring*/ 4903 if (iflib_rxsd_alloc(rxq)) { 4904 device_printf(dev, 4905 "Critical Failure setting up receive buffers\n"); 4906 err = ENOMEM; 4907 goto err_rx_desc; 4908 } 4909 4910 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4911 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 4912 } 4913 4914 /* TXQs */ 4915 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4916 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4917 for (i = 0; i < ntxqsets; i++) { 4918 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4919 4920 for (j = 0; j < ntxqs; j++, di++) { 4921 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4922 paddrs[i*ntxqs + j] = di->idi_paddr; 4923 } 4924 } 4925 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4926 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4927 iflib_tx_structures_free(ctx); 4928 free(vaddrs, M_IFLIB); 4929 free(paddrs, M_IFLIB); 4930 goto err_rx_desc; 4931 } 4932 free(vaddrs, M_IFLIB); 4933 free(paddrs, M_IFLIB); 4934 4935 /* RXQs */ 4936 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4937 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4938 for (i = 0; i < nrxqsets; i++) { 4939 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4940 4941 for (j = 0; j < nrxqs; j++, di++) { 4942 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4943 paddrs[i*nrxqs + j] = di->idi_paddr; 4944 } 4945 } 4946 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4947 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4948 iflib_tx_structures_free(ctx); 4949 free(vaddrs, M_IFLIB); 4950 free(paddrs, M_IFLIB); 4951 goto err_rx_desc; 4952 } 4953 free(vaddrs, M_IFLIB); 4954 free(paddrs, M_IFLIB); 4955 4956 return (0); 4957 4958 /* XXX handle allocation failure changes */ 4959 err_rx_desc: 4960 err_tx_desc: 4961 rx_fail: 4962 if (ctx->ifc_rxqs != NULL) 4963 free(ctx->ifc_rxqs, M_IFLIB); 4964 ctx->ifc_rxqs = NULL; 4965 if (ctx->ifc_txqs != NULL) 4966 free(ctx->ifc_txqs, M_IFLIB); 4967 ctx->ifc_txqs = NULL; 4968 fail: 4969 return (err); 4970 } 4971 4972 static int 4973 iflib_tx_structures_setup(if_ctx_t ctx) 4974 { 4975 iflib_txq_t txq = ctx->ifc_txqs; 4976 int i; 4977 4978 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4979 iflib_txq_setup(txq); 4980 4981 return (0); 4982 } 4983 4984 static void 4985 iflib_tx_structures_free(if_ctx_t ctx) 4986 { 4987 iflib_txq_t txq = ctx->ifc_txqs; 4988 int i, j; 4989 4990 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4991 iflib_txq_destroy(txq); 4992 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4993 iflib_dma_free(&txq->ift_ifdi[j]); 4994 } 4995 free(ctx->ifc_txqs, M_IFLIB); 4996 ctx->ifc_txqs = NULL; 4997 IFDI_QUEUES_FREE(ctx); 4998 } 4999 5000 /********************************************************************* 5001 * 5002 * Initialize all receive rings. 5003 * 5004 **********************************************************************/ 5005 static int 5006 iflib_rx_structures_setup(if_ctx_t ctx) 5007 { 5008 iflib_rxq_t rxq = ctx->ifc_rxqs; 5009 int q; 5010 #if defined(INET6) || defined(INET) 5011 int i, err; 5012 #endif 5013 5014 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5015 #if defined(INET6) || defined(INET) 5016 tcp_lro_free(&rxq->ifr_lc); 5017 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5018 TCP_LRO_ENTRIES, min(1024, 5019 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5020 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5021 goto fail; 5022 } 5023 rxq->ifr_lro_enabled = TRUE; 5024 #endif 5025 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5026 } 5027 return (0); 5028 #if defined(INET6) || defined(INET) 5029 fail: 5030 /* 5031 * Free RX software descriptors allocated so far, we will only handle 5032 * the rings that completed, the failing case will have 5033 * cleaned up for itself. 'q' failed, so its the terminus. 5034 */ 5035 rxq = ctx->ifc_rxqs; 5036 for (i = 0; i < q; ++i, rxq++) { 5037 iflib_rx_sds_free(rxq); 5038 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5039 } 5040 return (err); 5041 #endif 5042 } 5043 5044 /********************************************************************* 5045 * 5046 * Free all receive rings. 5047 * 5048 **********************************************************************/ 5049 static void 5050 iflib_rx_structures_free(if_ctx_t ctx) 5051 { 5052 iflib_rxq_t rxq = ctx->ifc_rxqs; 5053 5054 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5055 iflib_rx_sds_free(rxq); 5056 } 5057 } 5058 5059 static int 5060 iflib_qset_structures_setup(if_ctx_t ctx) 5061 { 5062 int err; 5063 5064 if ((err = iflib_tx_structures_setup(ctx)) != 0) 5065 return (err); 5066 5067 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 5068 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5069 iflib_tx_structures_free(ctx); 5070 iflib_rx_structures_free(ctx); 5071 } 5072 return (err); 5073 } 5074 5075 int 5076 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5077 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 5078 { 5079 5080 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5081 } 5082 5083 #ifdef SMP 5084 static int 5085 find_nth(if_ctx_t ctx, int qid) 5086 { 5087 cpuset_t cpus; 5088 int i, cpuid, eqid, count; 5089 5090 CPU_COPY(&ctx->ifc_cpus, &cpus); 5091 count = CPU_COUNT(&cpus); 5092 eqid = qid % count; 5093 /* clear up to the qid'th bit */ 5094 for (i = 0; i < eqid; i++) { 5095 cpuid = CPU_FFS(&cpus); 5096 MPASS(cpuid != 0); 5097 CPU_CLR(cpuid-1, &cpus); 5098 } 5099 cpuid = CPU_FFS(&cpus); 5100 MPASS(cpuid != 0); 5101 return (cpuid-1); 5102 } 5103 5104 #ifdef SCHED_ULE 5105 extern struct cpu_group *cpu_top; /* CPU topology */ 5106 5107 static int 5108 find_child_with_core(int cpu, struct cpu_group *grp) 5109 { 5110 int i; 5111 5112 if (grp->cg_children == 0) 5113 return -1; 5114 5115 MPASS(grp->cg_child); 5116 for (i = 0; i < grp->cg_children; i++) { 5117 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5118 return i; 5119 } 5120 5121 return -1; 5122 } 5123 5124 /* 5125 * Find the nth "close" core to the specified core 5126 * "close" is defined as the deepest level that shares 5127 * at least an L2 cache. With threads, this will be 5128 * threads on the same core. If the sahred cache is L3 5129 * or higher, simply returns the same core. 5130 */ 5131 static int 5132 find_close_core(int cpu, int core_offset) 5133 { 5134 struct cpu_group *grp; 5135 int i; 5136 int fcpu; 5137 cpuset_t cs; 5138 5139 grp = cpu_top; 5140 if (grp == NULL) 5141 return cpu; 5142 i = 0; 5143 while ((i = find_child_with_core(cpu, grp)) != -1) { 5144 /* If the child only has one cpu, don't descend */ 5145 if (grp->cg_child[i].cg_count <= 1) 5146 break; 5147 grp = &grp->cg_child[i]; 5148 } 5149 5150 /* If they don't share at least an L2 cache, use the same CPU */ 5151 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5152 return cpu; 5153 5154 /* Now pick one */ 5155 CPU_COPY(&grp->cg_mask, &cs); 5156 5157 /* Add the selected CPU offset to core offset. */ 5158 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5159 if (fcpu - 1 == cpu) 5160 break; 5161 CPU_CLR(fcpu - 1, &cs); 5162 } 5163 MPASS(fcpu); 5164 5165 core_offset += i; 5166 5167 CPU_COPY(&grp->cg_mask, &cs); 5168 for (i = core_offset % grp->cg_count; i > 0; i--) { 5169 MPASS(CPU_FFS(&cs)); 5170 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5171 } 5172 MPASS(CPU_FFS(&cs)); 5173 return CPU_FFS(&cs) - 1; 5174 } 5175 #else 5176 static int 5177 find_close_core(int cpu, int core_offset __unused) 5178 { 5179 return cpu; 5180 } 5181 #endif 5182 5183 static int 5184 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5185 { 5186 switch (type) { 5187 case IFLIB_INTR_TX: 5188 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5189 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5190 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5191 case IFLIB_INTR_RX: 5192 case IFLIB_INTR_RXTX: 5193 /* RX queues get the specified core */ 5194 return qid / CPU_COUNT(&ctx->ifc_cpus); 5195 default: 5196 return -1; 5197 } 5198 } 5199 #else 5200 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5201 #define find_close_core(cpuid, tid) CPU_FIRST() 5202 #define find_nth(ctx, gid) CPU_FIRST() 5203 #endif 5204 5205 /* Just to avoid copy/paste */ 5206 static inline int 5207 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5208 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name) 5209 { 5210 int cpuid; 5211 int err, tid; 5212 5213 cpuid = find_nth(ctx, qid); 5214 tid = get_core_offset(ctx, type, qid); 5215 MPASS(tid >= 0); 5216 cpuid = find_close_core(cpuid, tid); 5217 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5218 if (err) { 5219 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5220 return (err); 5221 } 5222 #ifdef notyet 5223 if (cpuid > ctx->ifc_cpuid_highest) 5224 ctx->ifc_cpuid_highest = cpuid; 5225 #endif 5226 return 0; 5227 } 5228 5229 int 5230 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5231 iflib_intr_type_t type, driver_filter_t *filter, 5232 void *filter_arg, int qid, char *name) 5233 { 5234 struct grouptask *gtask; 5235 struct taskqgroup *tqg; 5236 iflib_filter_info_t info; 5237 gtask_fn_t *fn; 5238 int tqrid, err; 5239 driver_filter_t *intr_fast; 5240 void *q; 5241 5242 info = &ctx->ifc_filter_info; 5243 tqrid = rid; 5244 5245 switch (type) { 5246 /* XXX merge tx/rx for netmap? */ 5247 case IFLIB_INTR_TX: 5248 q = &ctx->ifc_txqs[qid]; 5249 info = &ctx->ifc_txqs[qid].ift_filter_info; 5250 gtask = &ctx->ifc_txqs[qid].ift_task; 5251 tqg = qgroup_if_io_tqg; 5252 fn = _task_fn_tx; 5253 intr_fast = iflib_fast_intr; 5254 GROUPTASK_INIT(gtask, 0, fn, q); 5255 break; 5256 case IFLIB_INTR_RX: 5257 q = &ctx->ifc_rxqs[qid]; 5258 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5259 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5260 tqg = qgroup_if_io_tqg; 5261 fn = _task_fn_rx; 5262 intr_fast = iflib_fast_intr; 5263 GROUPTASK_INIT(gtask, 0, fn, q); 5264 break; 5265 case IFLIB_INTR_RXTX: 5266 q = &ctx->ifc_rxqs[qid]; 5267 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5268 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5269 tqg = qgroup_if_io_tqg; 5270 fn = _task_fn_rx; 5271 intr_fast = iflib_fast_intr_rxtx; 5272 GROUPTASK_INIT(gtask, 0, fn, q); 5273 break; 5274 case IFLIB_INTR_ADMIN: 5275 q = ctx; 5276 tqrid = -1; 5277 info = &ctx->ifc_filter_info; 5278 gtask = &ctx->ifc_admin_task; 5279 tqg = qgroup_if_config_tqg; 5280 fn = _task_fn_admin; 5281 intr_fast = iflib_fast_intr_ctx; 5282 break; 5283 default: 5284 panic("unknown net intr type"); 5285 } 5286 5287 info->ifi_filter = filter; 5288 info->ifi_filter_arg = filter_arg; 5289 info->ifi_task = gtask; 5290 info->ifi_ctx = q; 5291 5292 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5293 if (err != 0) { 5294 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5295 return (err); 5296 } 5297 if (type == IFLIB_INTR_ADMIN) 5298 return (0); 5299 5300 if (tqrid != -1) { 5301 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5302 if (err) 5303 return (err); 5304 } else { 5305 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5306 } 5307 5308 return (0); 5309 } 5310 5311 void 5312 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name) 5313 { 5314 struct grouptask *gtask; 5315 struct taskqgroup *tqg; 5316 gtask_fn_t *fn; 5317 void *q; 5318 int irq_num = -1; 5319 int err; 5320 5321 switch (type) { 5322 case IFLIB_INTR_TX: 5323 q = &ctx->ifc_txqs[qid]; 5324 gtask = &ctx->ifc_txqs[qid].ift_task; 5325 tqg = qgroup_if_io_tqg; 5326 fn = _task_fn_tx; 5327 if (irq != NULL) 5328 irq_num = rman_get_start(irq->ii_res); 5329 break; 5330 case IFLIB_INTR_RX: 5331 q = &ctx->ifc_rxqs[qid]; 5332 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5333 tqg = qgroup_if_io_tqg; 5334 fn = _task_fn_rx; 5335 if (irq != NULL) 5336 irq_num = rman_get_start(irq->ii_res); 5337 break; 5338 case IFLIB_INTR_IOV: 5339 q = ctx; 5340 gtask = &ctx->ifc_vflr_task; 5341 tqg = qgroup_if_config_tqg; 5342 fn = _task_fn_iov; 5343 break; 5344 default: 5345 panic("unknown net intr type"); 5346 } 5347 GROUPTASK_INIT(gtask, 0, fn, q); 5348 if (irq_num != -1) { 5349 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5350 if (err) 5351 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5352 } 5353 else { 5354 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5355 } 5356 } 5357 5358 void 5359 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5360 { 5361 if (irq->ii_tag) 5362 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5363 5364 if (irq->ii_res) 5365 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5366 } 5367 5368 static int 5369 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5370 { 5371 iflib_txq_t txq = ctx->ifc_txqs; 5372 iflib_rxq_t rxq = ctx->ifc_rxqs; 5373 if_irq_t irq = &ctx->ifc_legacy_irq; 5374 iflib_filter_info_t info; 5375 struct grouptask *gtask; 5376 struct taskqgroup *tqg; 5377 gtask_fn_t *fn; 5378 int tqrid; 5379 void *q; 5380 int err; 5381 5382 q = &ctx->ifc_rxqs[0]; 5383 info = &rxq[0].ifr_filter_info; 5384 gtask = &rxq[0].ifr_task; 5385 tqg = qgroup_if_io_tqg; 5386 tqrid = irq->ii_rid = *rid; 5387 fn = _task_fn_rx; 5388 5389 ctx->ifc_flags |= IFC_LEGACY; 5390 info->ifi_filter = filter; 5391 info->ifi_filter_arg = filter_arg; 5392 info->ifi_task = gtask; 5393 info->ifi_ctx = ctx; 5394 5395 /* We allocate a single interrupt resource */ 5396 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5397 return (err); 5398 GROUPTASK_INIT(gtask, 0, fn, q); 5399 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5400 5401 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5402 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5403 return (0); 5404 } 5405 5406 void 5407 iflib_led_create(if_ctx_t ctx) 5408 { 5409 5410 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5411 device_get_nameunit(ctx->ifc_dev)); 5412 } 5413 5414 void 5415 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5416 { 5417 5418 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5419 } 5420 5421 void 5422 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5423 { 5424 5425 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5426 } 5427 5428 void 5429 iflib_admin_intr_deferred(if_ctx_t ctx) 5430 { 5431 #ifdef INVARIANTS 5432 struct grouptask *gtask; 5433 5434 gtask = &ctx->ifc_admin_task; 5435 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5436 #endif 5437 5438 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5439 } 5440 5441 void 5442 iflib_iov_intr_deferred(if_ctx_t ctx) 5443 { 5444 5445 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5446 } 5447 5448 void 5449 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5450 { 5451 5452 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5453 } 5454 5455 void 5456 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5457 const char *name) 5458 { 5459 5460 GROUPTASK_INIT(gtask, 0, fn, ctx); 5461 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5462 } 5463 5464 void 5465 iflib_config_gtask_deinit(struct grouptask *gtask) 5466 { 5467 5468 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5469 } 5470 5471 void 5472 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5473 { 5474 if_t ifp = ctx->ifc_ifp; 5475 iflib_txq_t txq = ctx->ifc_txqs; 5476 5477 if_setbaudrate(ifp, baudrate); 5478 if (baudrate >= IF_Gbps(10)) { 5479 STATE_LOCK(ctx); 5480 ctx->ifc_flags |= IFC_PREFETCH; 5481 STATE_UNLOCK(ctx); 5482 } 5483 /* If link down, disable watchdog */ 5484 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5485 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5486 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5487 } 5488 ctx->ifc_link_state = link_state; 5489 if_link_state_change(ifp, link_state); 5490 } 5491 5492 static int 5493 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5494 { 5495 int credits; 5496 #ifdef INVARIANTS 5497 int credits_pre = txq->ift_cidx_processed; 5498 #endif 5499 5500 if (ctx->isc_txd_credits_update == NULL) 5501 return (0); 5502 5503 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5504 return (0); 5505 5506 txq->ift_processed += credits; 5507 txq->ift_cidx_processed += credits; 5508 5509 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5510 if (txq->ift_cidx_processed >= txq->ift_size) 5511 txq->ift_cidx_processed -= txq->ift_size; 5512 return (credits); 5513 } 5514 5515 static int 5516 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5517 { 5518 5519 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5520 budget)); 5521 } 5522 5523 void 5524 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5525 const char *description, if_int_delay_info_t info, 5526 int offset, int value) 5527 { 5528 info->iidi_ctx = ctx; 5529 info->iidi_offset = offset; 5530 info->iidi_value = value; 5531 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5532 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5533 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5534 info, 0, iflib_sysctl_int_delay, "I", description); 5535 } 5536 5537 struct sx * 5538 iflib_ctx_lock_get(if_ctx_t ctx) 5539 { 5540 5541 return (&ctx->ifc_ctx_sx); 5542 } 5543 5544 static int 5545 iflib_msix_init(if_ctx_t ctx) 5546 { 5547 device_t dev = ctx->ifc_dev; 5548 if_shared_ctx_t sctx = ctx->ifc_sctx; 5549 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5550 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5551 int iflib_num_tx_queues, iflib_num_rx_queues; 5552 int err, admincnt, bar; 5553 5554 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5555 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5556 5557 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5558 5559 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5560 admincnt = sctx->isc_admin_intrcnt; 5561 /* Override by global tuneable */ 5562 { 5563 int i; 5564 size_t len = sizeof(i); 5565 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0); 5566 if (err == 0) { 5567 if (i == 0) 5568 goto msi; 5569 } 5570 else { 5571 device_printf(dev, "unable to read hw.pci.enable_msix."); 5572 } 5573 } 5574 /* Override by tuneable */ 5575 if (scctx->isc_disable_msix) 5576 goto msi; 5577 5578 /* 5579 ** When used in a virtualized environment 5580 ** PCI BUSMASTER capability may not be set 5581 ** so explicity set it here and rewrite 5582 ** the ENABLE in the MSIX control register 5583 ** at this point to cause the host to 5584 ** successfully initialize us. 5585 */ 5586 { 5587 int msix_ctrl, rid; 5588 5589 pci_enable_busmaster(dev); 5590 rid = 0; 5591 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5592 rid += PCIR_MSIX_CTRL; 5593 msix_ctrl = pci_read_config(dev, rid, 2); 5594 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5595 pci_write_config(dev, rid, msix_ctrl, 2); 5596 } else { 5597 device_printf(dev, "PCIY_MSIX capability not found; " 5598 "or rid %d == 0.\n", rid); 5599 goto msi; 5600 } 5601 } 5602 5603 /* 5604 * bar == -1 => "trust me I know what I'm doing" 5605 * Some drivers are for hardware that is so shoddily 5606 * documented that no one knows which bars are which 5607 * so the developer has to map all bars. This hack 5608 * allows shoddy garbage to use msix in this framework. 5609 */ 5610 if (bar != -1) { 5611 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5612 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5613 if (ctx->ifc_msix_mem == NULL) { 5614 /* May not be enabled */ 5615 device_printf(dev, "Unable to map MSIX table \n"); 5616 goto msi; 5617 } 5618 } 5619 /* First try MSI/X */ 5620 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5621 device_printf(dev, "System has MSIX disabled \n"); 5622 bus_release_resource(dev, SYS_RES_MEMORY, 5623 bar, ctx->ifc_msix_mem); 5624 ctx->ifc_msix_mem = NULL; 5625 goto msi; 5626 } 5627 #if IFLIB_DEBUG 5628 /* use only 1 qset in debug mode */ 5629 queuemsgs = min(msgs - admincnt, 1); 5630 #else 5631 queuemsgs = msgs - admincnt; 5632 #endif 5633 #ifdef RSS 5634 queues = imin(queuemsgs, rss_getnumbuckets()); 5635 #else 5636 queues = queuemsgs; 5637 #endif 5638 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5639 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5640 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5641 #ifdef RSS 5642 /* If we're doing RSS, clamp at the number of RSS buckets */ 5643 if (queues > rss_getnumbuckets()) 5644 queues = rss_getnumbuckets(); 5645 #endif 5646 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5647 rx_queues = iflib_num_rx_queues; 5648 else 5649 rx_queues = queues; 5650 5651 if (rx_queues > scctx->isc_nrxqsets) 5652 rx_queues = scctx->isc_nrxqsets; 5653 5654 /* 5655 * We want this to be all logical CPUs by default 5656 */ 5657 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5658 tx_queues = iflib_num_tx_queues; 5659 else 5660 tx_queues = mp_ncpus; 5661 5662 if (tx_queues > scctx->isc_ntxqsets) 5663 tx_queues = scctx->isc_ntxqsets; 5664 5665 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5666 #ifdef INVARIANTS 5667 if (tx_queues != rx_queues) 5668 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5669 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5670 #endif 5671 tx_queues = min(rx_queues, tx_queues); 5672 rx_queues = min(rx_queues, tx_queues); 5673 } 5674 5675 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5676 5677 vectors = rx_queues + admincnt; 5678 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5679 device_printf(dev, 5680 "Using MSIX interrupts with %d vectors\n", vectors); 5681 scctx->isc_vectors = vectors; 5682 scctx->isc_nrxqsets = rx_queues; 5683 scctx->isc_ntxqsets = tx_queues; 5684 scctx->isc_intr = IFLIB_INTR_MSIX; 5685 5686 return (vectors); 5687 } else { 5688 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5689 } 5690 msi: 5691 vectors = pci_msi_count(dev); 5692 scctx->isc_nrxqsets = 1; 5693 scctx->isc_ntxqsets = 1; 5694 scctx->isc_vectors = vectors; 5695 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5696 device_printf(dev,"Using an MSI interrupt\n"); 5697 scctx->isc_intr = IFLIB_INTR_MSI; 5698 } else { 5699 device_printf(dev,"Using a Legacy interrupt\n"); 5700 scctx->isc_intr = IFLIB_INTR_LEGACY; 5701 } 5702 5703 return (vectors); 5704 } 5705 5706 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5707 5708 static int 5709 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5710 { 5711 int rc; 5712 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5713 struct sbuf *sb; 5714 char *ring_state = "UNKNOWN"; 5715 5716 /* XXX needed ? */ 5717 rc = sysctl_wire_old_buffer(req, 0); 5718 MPASS(rc == 0); 5719 if (rc != 0) 5720 return (rc); 5721 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5722 MPASS(sb != NULL); 5723 if (sb == NULL) 5724 return (ENOMEM); 5725 if (state[3] <= 3) 5726 ring_state = ring_states[state[3]]; 5727 5728 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5729 state[0], state[1], state[2], ring_state); 5730 rc = sbuf_finish(sb); 5731 sbuf_delete(sb); 5732 return(rc); 5733 } 5734 5735 enum iflib_ndesc_handler { 5736 IFLIB_NTXD_HANDLER, 5737 IFLIB_NRXD_HANDLER, 5738 }; 5739 5740 static int 5741 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5742 { 5743 if_ctx_t ctx = (void *)arg1; 5744 enum iflib_ndesc_handler type = arg2; 5745 char buf[256] = {0}; 5746 qidx_t *ndesc; 5747 char *p, *next; 5748 int nqs, rc, i; 5749 5750 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5751 5752 nqs = 8; 5753 switch(type) { 5754 case IFLIB_NTXD_HANDLER: 5755 ndesc = ctx->ifc_sysctl_ntxds; 5756 if (ctx->ifc_sctx) 5757 nqs = ctx->ifc_sctx->isc_ntxqs; 5758 break; 5759 case IFLIB_NRXD_HANDLER: 5760 ndesc = ctx->ifc_sysctl_nrxds; 5761 if (ctx->ifc_sctx) 5762 nqs = ctx->ifc_sctx->isc_nrxqs; 5763 break; 5764 default: 5765 panic("unhandled type"); 5766 } 5767 if (nqs == 0) 5768 nqs = 8; 5769 5770 for (i=0; i<8; i++) { 5771 if (i >= nqs) 5772 break; 5773 if (i) 5774 strcat(buf, ","); 5775 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5776 } 5777 5778 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5779 if (rc || req->newptr == NULL) 5780 return rc; 5781 5782 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5783 i++, p = strsep(&next, " ,")) { 5784 ndesc[i] = strtoul(p, NULL, 10); 5785 } 5786 5787 return(rc); 5788 } 5789 5790 #define NAME_BUFLEN 32 5791 static void 5792 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5793 { 5794 device_t dev = iflib_get_dev(ctx); 5795 struct sysctl_oid_list *child, *oid_list; 5796 struct sysctl_ctx_list *ctx_list; 5797 struct sysctl_oid *node; 5798 5799 ctx_list = device_get_sysctl_ctx(dev); 5800 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5801 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5802 CTLFLAG_RD, NULL, "IFLIB fields"); 5803 oid_list = SYSCTL_CHILDREN(node); 5804 5805 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5806 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5807 "driver version"); 5808 5809 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5810 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5811 "# of txqs to use, 0 => use default #"); 5812 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5813 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5814 "# of rxqs to use, 0 => use default #"); 5815 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5816 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5817 "permit #txq != #rxq"); 5818 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5819 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5820 "disable MSIX (default 0)"); 5821 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 5822 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 5823 "set the rx budget"); 5824 5825 /* XXX change for per-queue sizes */ 5826 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5827 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5828 mp_ndesc_handler, "A", 5829 "list of # of tx descriptors to use, 0 = use default #"); 5830 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5831 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5832 mp_ndesc_handler, "A", 5833 "list of # of rx descriptors to use, 0 = use default #"); 5834 } 5835 5836 static void 5837 iflib_add_device_sysctl_post(if_ctx_t ctx) 5838 { 5839 if_shared_ctx_t sctx = ctx->ifc_sctx; 5840 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5841 device_t dev = iflib_get_dev(ctx); 5842 struct sysctl_oid_list *child; 5843 struct sysctl_ctx_list *ctx_list; 5844 iflib_fl_t fl; 5845 iflib_txq_t txq; 5846 iflib_rxq_t rxq; 5847 int i, j; 5848 char namebuf[NAME_BUFLEN]; 5849 char *qfmt; 5850 struct sysctl_oid *queue_node, *fl_node, *node; 5851 struct sysctl_oid_list *queue_list, *fl_list; 5852 ctx_list = device_get_sysctl_ctx(dev); 5853 5854 node = ctx->ifc_sysctl_node; 5855 child = SYSCTL_CHILDREN(node); 5856 5857 if (scctx->isc_ntxqsets > 100) 5858 qfmt = "txq%03d"; 5859 else if (scctx->isc_ntxqsets > 10) 5860 qfmt = "txq%02d"; 5861 else 5862 qfmt = "txq%d"; 5863 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5864 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5865 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5866 CTLFLAG_RD, NULL, "Queue Name"); 5867 queue_list = SYSCTL_CHILDREN(queue_node); 5868 #if MEMORY_LOGGING 5869 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5870 CTLFLAG_RD, 5871 &txq->ift_dequeued, "total mbufs freed"); 5872 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5873 CTLFLAG_RD, 5874 &txq->ift_enqueued, "total mbufs enqueued"); 5875 #endif 5876 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5877 CTLFLAG_RD, 5878 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5879 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5880 CTLFLAG_RD, 5881 &txq->ift_pullups, "# of times m_pullup was called"); 5882 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5883 CTLFLAG_RD, 5884 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5885 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5886 CTLFLAG_RD, 5887 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5888 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5889 CTLFLAG_RD, 5890 &txq->ift_map_failed, "# of times dma map failed"); 5891 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5892 CTLFLAG_RD, 5893 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5894 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5895 CTLFLAG_RD, 5896 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5897 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5898 CTLFLAG_RD, 5899 &txq->ift_pidx, 1, "Producer Index"); 5900 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5901 CTLFLAG_RD, 5902 &txq->ift_cidx, 1, "Consumer Index"); 5903 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5904 CTLFLAG_RD, 5905 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5906 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5907 CTLFLAG_RD, 5908 &txq->ift_in_use, 1, "descriptors in use"); 5909 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5910 CTLFLAG_RD, 5911 &txq->ift_processed, "descriptors procesed for clean"); 5912 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5913 CTLFLAG_RD, 5914 &txq->ift_cleaned, "total cleaned"); 5915 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5916 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5917 0, mp_ring_state_handler, "A", "soft ring state"); 5918 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5919 CTLFLAG_RD, &txq->ift_br->enqueues, 5920 "# of enqueues to the mp_ring for this queue"); 5921 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5922 CTLFLAG_RD, &txq->ift_br->drops, 5923 "# of drops in the mp_ring for this queue"); 5924 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5925 CTLFLAG_RD, &txq->ift_br->starts, 5926 "# of normal consumer starts in the mp_ring for this queue"); 5927 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5928 CTLFLAG_RD, &txq->ift_br->stalls, 5929 "# of consumer stalls in the mp_ring for this queue"); 5930 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5931 CTLFLAG_RD, &txq->ift_br->restarts, 5932 "# of consumer restarts in the mp_ring for this queue"); 5933 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5934 CTLFLAG_RD, &txq->ift_br->abdications, 5935 "# of consumer abdications in the mp_ring for this queue"); 5936 } 5937 5938 if (scctx->isc_nrxqsets > 100) 5939 qfmt = "rxq%03d"; 5940 else if (scctx->isc_nrxqsets > 10) 5941 qfmt = "rxq%02d"; 5942 else 5943 qfmt = "rxq%d"; 5944 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5945 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5946 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5947 CTLFLAG_RD, NULL, "Queue Name"); 5948 queue_list = SYSCTL_CHILDREN(queue_node); 5949 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5950 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5951 CTLFLAG_RD, 5952 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5953 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5954 CTLFLAG_RD, 5955 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5956 } 5957 5958 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5959 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5960 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5961 CTLFLAG_RD, NULL, "freelist Name"); 5962 fl_list = SYSCTL_CHILDREN(fl_node); 5963 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5964 CTLFLAG_RD, 5965 &fl->ifl_pidx, 1, "Producer Index"); 5966 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5967 CTLFLAG_RD, 5968 &fl->ifl_cidx, 1, "Consumer Index"); 5969 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5970 CTLFLAG_RD, 5971 &fl->ifl_credits, 1, "credits available"); 5972 #if MEMORY_LOGGING 5973 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5974 CTLFLAG_RD, 5975 &fl->ifl_m_enqueued, "mbufs allocated"); 5976 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5977 CTLFLAG_RD, 5978 &fl->ifl_m_dequeued, "mbufs freed"); 5979 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5980 CTLFLAG_RD, 5981 &fl->ifl_cl_enqueued, "clusters allocated"); 5982 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5983 CTLFLAG_RD, 5984 &fl->ifl_cl_dequeued, "clusters freed"); 5985 #endif 5986 5987 } 5988 } 5989 5990 } 5991 5992 #ifndef __NO_STRICT_ALIGNMENT 5993 static struct mbuf * 5994 iflib_fixup_rx(struct mbuf *m) 5995 { 5996 struct mbuf *n; 5997 5998 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5999 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6000 m->m_data += ETHER_HDR_LEN; 6001 n = m; 6002 } else { 6003 MGETHDR(n, M_NOWAIT, MT_DATA); 6004 if (n == NULL) { 6005 m_freem(m); 6006 return (NULL); 6007 } 6008 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6009 m->m_data += ETHER_HDR_LEN; 6010 m->m_len -= ETHER_HDR_LEN; 6011 n->m_len = ETHER_HDR_LEN; 6012 M_MOVE_PKTHDR(n, m); 6013 n->m_next = m; 6014 } 6015 return (n); 6016 } 6017 #endif 6018