1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 static void iflib_tqg_detach(if_ctx_t ctx); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 uint8_t ifc_sysctl_use_logical_cores; 199 bool ifc_cpus_are_physical_cores; 200 201 qidx_t ifc_sysctl_ntxds[8]; 202 qidx_t ifc_sysctl_nrxds[8]; 203 struct if_txrx ifc_txrx; 204 #define isc_txd_encap ifc_txrx.ift_txd_encap 205 #define isc_txd_flush ifc_txrx.ift_txd_flush 206 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 207 #define isc_rxd_available ifc_txrx.ift_rxd_available 208 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 210 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 212 eventhandler_tag ifc_vlan_attach_event; 213 eventhandler_tag ifc_vlan_detach_event; 214 struct ether_addr ifc_mac; 215 }; 216 217 void * 218 iflib_get_softc(if_ctx_t ctx) 219 { 220 221 return (ctx->ifc_softc); 222 } 223 224 device_t 225 iflib_get_dev(if_ctx_t ctx) 226 { 227 228 return (ctx->ifc_dev); 229 } 230 231 if_t 232 iflib_get_ifp(if_ctx_t ctx) 233 { 234 235 return (ctx->ifc_ifp); 236 } 237 238 struct ifmedia * 239 iflib_get_media(if_ctx_t ctx) 240 { 241 242 return (ctx->ifc_mediap); 243 } 244 245 uint32_t 246 iflib_get_flags(if_ctx_t ctx) 247 { 248 return (ctx->ifc_flags); 249 } 250 251 void 252 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 253 { 254 255 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 256 } 257 258 if_softc_ctx_t 259 iflib_get_softc_ctx(if_ctx_t ctx) 260 { 261 262 return (&ctx->ifc_softc_ctx); 263 } 264 265 if_shared_ctx_t 266 iflib_get_sctx(if_ctx_t ctx) 267 { 268 269 return (ctx->ifc_sctx); 270 } 271 272 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 273 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 274 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 275 276 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 277 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 289 struct mbuf **ifsd_m; /* pkthdr mbufs */ 290 } if_txsd_vec_t; 291 292 /* magic number that should be high enough for any hardware */ 293 #define IFLIB_MAX_TX_SEGS 128 294 #define IFLIB_RX_COPY_THRESH 128 295 #define IFLIB_MAX_RX_REFRESH 32 296 /* The minimum descriptors per second before we start coalescing */ 297 #define IFLIB_MIN_DESC_SEC 16384 298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 299 #define IFLIB_QUEUE_IDLE 0 300 #define IFLIB_QUEUE_HUNG 1 301 #define IFLIB_QUEUE_WORKING 2 302 /* maximum number of txqs that can share an rx interrupt */ 303 #define IFLIB_MAX_TX_SHARED_INTR 4 304 305 /* this should really scale with ring size - this is a fairly arbitrary value */ 306 #define TX_BATCH_SIZE 32 307 308 #define IFLIB_RESTART_BUDGET 8 309 310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 313 314 struct iflib_txq { 315 qidx_t ift_in_use; 316 qidx_t ift_cidx; 317 qidx_t ift_cidx_processed; 318 qidx_t ift_pidx; 319 uint8_t ift_gen; 320 uint8_t ift_br_offset; 321 uint16_t ift_npending; 322 uint16_t ift_db_pending; 323 uint16_t ift_rs_pending; 324 /* implicit pad */ 325 uint8_t ift_txd_size[8]; 326 uint64_t ift_processed; 327 uint64_t ift_cleaned; 328 uint64_t ift_cleaned_prev; 329 #if MEMORY_LOGGING 330 uint64_t ift_enqueued; 331 uint64_t ift_dequeued; 332 #endif 333 uint64_t ift_no_tx_dma_setup; 334 uint64_t ift_no_desc_avail; 335 uint64_t ift_mbuf_defrag_failed; 336 uint64_t ift_mbuf_defrag; 337 uint64_t ift_map_failed; 338 uint64_t ift_txd_encap_efbig; 339 uint64_t ift_pullups; 340 uint64_t ift_last_timer_tick; 341 342 struct mtx ift_mtx; 343 struct mtx ift_db_mtx; 344 345 /* constant values */ 346 if_ctx_t ift_ctx; 347 struct ifmp_ring *ift_br; 348 struct grouptask ift_task; 349 qidx_t ift_size; 350 uint16_t ift_id; 351 struct callout ift_timer; 352 #ifdef DEV_NETMAP 353 struct callout ift_netmap_timer; 354 #endif /* DEV_NETMAP */ 355 356 if_txsd_vec_t ift_sds; 357 uint8_t ift_qstatus; 358 uint8_t ift_closed; 359 uint8_t ift_update_freq; 360 struct iflib_filter_info ift_filter_info; 361 bus_dma_tag_t ift_buf_tag; 362 bus_dma_tag_t ift_tso_buf_tag; 363 iflib_dma_info_t ift_ifdi; 364 #define MTX_NAME_LEN 32 365 char ift_mtx_name[MTX_NAME_LEN]; 366 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 367 #ifdef IFLIB_DIAGNOSTICS 368 uint64_t ift_cpu_exec_count[256]; 369 #endif 370 } __aligned(CACHE_LINE_SIZE); 371 372 struct iflib_fl { 373 qidx_t ifl_cidx; 374 qidx_t ifl_pidx; 375 qidx_t ifl_credits; 376 uint8_t ifl_gen; 377 uint8_t ifl_rxd_size; 378 #if MEMORY_LOGGING 379 uint64_t ifl_m_enqueued; 380 uint64_t ifl_m_dequeued; 381 uint64_t ifl_cl_enqueued; 382 uint64_t ifl_cl_dequeued; 383 #endif 384 /* implicit pad */ 385 bitstr_t *ifl_rx_bitmap; 386 qidx_t ifl_fragidx; 387 /* constant */ 388 qidx_t ifl_size; 389 uint16_t ifl_buf_size; 390 uint16_t ifl_cltype; 391 uma_zone_t ifl_zone; 392 iflib_rxsd_array_t ifl_sds; 393 iflib_rxq_t ifl_rxq; 394 uint8_t ifl_id; 395 bus_dma_tag_t ifl_buf_tag; 396 iflib_dma_info_t ifl_ifdi; 397 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 398 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 399 } __aligned(CACHE_LINE_SIZE); 400 401 static inline qidx_t 402 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 403 { 404 qidx_t used; 405 406 if (pidx > cidx) 407 used = pidx - cidx; 408 else if (pidx < cidx) 409 used = size - cidx + pidx; 410 else if (gen == 0 && pidx == cidx) 411 used = 0; 412 else if (gen == 1 && pidx == cidx) 413 used = size; 414 else 415 panic("bad state"); 416 417 return (used); 418 } 419 420 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 421 422 #define IDXDIFF(head, tail, wrap) \ 423 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 424 425 struct iflib_rxq { 426 if_ctx_t ifr_ctx; 427 iflib_fl_t ifr_fl; 428 uint64_t ifr_rx_irq; 429 struct pfil_head *pfil; 430 /* 431 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 432 * the completion queue consumer index. Otherwise it's unused. 433 */ 434 qidx_t ifr_cq_cidx; 435 uint16_t ifr_id; 436 uint8_t ifr_nfl; 437 uint8_t ifr_ntxqirq; 438 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 439 uint8_t ifr_fl_offset; 440 struct lro_ctrl ifr_lc; 441 struct grouptask ifr_task; 442 struct callout ifr_watchdog; 443 struct iflib_filter_info ifr_filter_info; 444 iflib_dma_info_t ifr_ifdi; 445 446 /* dynamically allocate if any drivers need a value substantially larger than this */ 447 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 448 #ifdef IFLIB_DIAGNOSTICS 449 uint64_t ifr_cpu_exec_count[256]; 450 #endif 451 } __aligned(CACHE_LINE_SIZE); 452 453 typedef struct if_rxsd { 454 caddr_t *ifsd_cl; 455 iflib_fl_t ifsd_fl; 456 } *if_rxsd_t; 457 458 /* multiple of word size */ 459 #ifdef __LP64__ 460 #define PKT_INFO_SIZE 6 461 #define RXD_INFO_SIZE 5 462 #define PKT_TYPE uint64_t 463 #else 464 #define PKT_INFO_SIZE 11 465 #define RXD_INFO_SIZE 8 466 #define PKT_TYPE uint32_t 467 #endif 468 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 469 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 470 471 typedef struct if_pkt_info_pad { 472 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 473 } *if_pkt_info_pad_t; 474 typedef struct if_rxd_info_pad { 475 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 476 } *if_rxd_info_pad_t; 477 478 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 479 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 480 481 static inline void 482 pkt_info_zero(if_pkt_info_t pi) 483 { 484 if_pkt_info_pad_t pi_pad; 485 486 pi_pad = (if_pkt_info_pad_t)pi; 487 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 488 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 489 #ifndef __LP64__ 490 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 491 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 492 #endif 493 } 494 495 static device_method_t iflib_pseudo_methods[] = { 496 DEVMETHOD(device_attach, noop_attach), 497 DEVMETHOD(device_detach, iflib_pseudo_detach), 498 DEVMETHOD_END 499 }; 500 501 driver_t iflib_pseudodriver = { 502 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 503 }; 504 505 static inline void 506 rxd_info_zero(if_rxd_info_t ri) 507 { 508 if_rxd_info_pad_t ri_pad; 509 int i; 510 511 ri_pad = (if_rxd_info_pad_t)ri; 512 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 513 ri_pad->rxd_val[i] = 0; 514 ri_pad->rxd_val[i+1] = 0; 515 ri_pad->rxd_val[i+2] = 0; 516 ri_pad->rxd_val[i+3] = 0; 517 } 518 #ifdef __LP64__ 519 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 520 #endif 521 } 522 523 /* 524 * Only allow a single packet to take up most 1/nth of the tx ring 525 */ 526 #define MAX_SINGLE_PACKET_FRACTION 12 527 #define IF_BAD_DMA (bus_addr_t)-1 528 529 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 530 531 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 532 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 533 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 534 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 535 536 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 537 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 538 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 539 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 540 541 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 542 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 543 544 void 545 iflib_set_detach(if_ctx_t ctx) 546 { 547 STATE_LOCK(ctx); 548 ctx->ifc_flags |= IFC_IN_DETACH; 549 STATE_UNLOCK(ctx); 550 } 551 552 /* Our boot-time initialization hook */ 553 static int iflib_module_event_handler(module_t, int, void *); 554 555 static moduledata_t iflib_moduledata = { 556 "iflib", 557 iflib_module_event_handler, 558 NULL 559 }; 560 561 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 562 MODULE_VERSION(iflib, 1); 563 564 MODULE_DEPEND(iflib, pci, 1, 1, 1); 565 MODULE_DEPEND(iflib, ether, 1, 1, 1); 566 567 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 568 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 569 570 #ifndef IFLIB_DEBUG_COUNTERS 571 #ifdef INVARIANTS 572 #define IFLIB_DEBUG_COUNTERS 1 573 #else 574 #define IFLIB_DEBUG_COUNTERS 0 575 #endif /* !INVARIANTS */ 576 #endif 577 578 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 579 "iflib driver parameters"); 580 581 /* 582 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 583 */ 584 static int iflib_min_tx_latency = 0; 585 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 586 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 587 static int iflib_no_tx_batch = 0; 588 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 589 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 590 static int iflib_timer_default = 1000; 591 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 592 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 593 594 595 #if IFLIB_DEBUG_COUNTERS 596 597 static int iflib_tx_seen; 598 static int iflib_tx_sent; 599 static int iflib_tx_encap; 600 static int iflib_rx_allocs; 601 static int iflib_fl_refills; 602 static int iflib_fl_refills_large; 603 static int iflib_tx_frees; 604 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 606 &iflib_tx_seen, 0, "# TX mbufs seen"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 608 &iflib_tx_sent, 0, "# TX mbufs sent"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 610 &iflib_tx_encap, 0, "# TX mbufs encapped"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 612 &iflib_tx_frees, 0, "# TX frees"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 614 &iflib_rx_allocs, 0, "# RX allocations"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 616 &iflib_fl_refills, 0, "# refills"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 618 &iflib_fl_refills_large, 0, "# large refills"); 619 620 static int iflib_txq_drain_flushing; 621 static int iflib_txq_drain_oactive; 622 static int iflib_txq_drain_notready; 623 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 625 &iflib_txq_drain_flushing, 0, "# drain flushes"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 627 &iflib_txq_drain_oactive, 0, "# drain oactives"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 629 &iflib_txq_drain_notready, 0, "# drain notready"); 630 631 static int iflib_encap_load_mbuf_fail; 632 static int iflib_encap_pad_mbuf_fail; 633 static int iflib_encap_txq_avail_fail; 634 static int iflib_encap_txd_encap_fail; 635 636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 637 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 639 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 641 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 643 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 644 645 static int iflib_task_fn_rxs; 646 static int iflib_rx_intr_enables; 647 static int iflib_fast_intrs; 648 static int iflib_rx_unavail; 649 static int iflib_rx_ctx_inactive; 650 static int iflib_rx_if_input; 651 static int iflib_rxd_flush; 652 653 static int iflib_verbose_debug; 654 655 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 656 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 658 &iflib_rx_intr_enables, 0, "# RX intr enables"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 660 &iflib_fast_intrs, 0, "# fast_intr calls"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 662 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 664 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 666 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 668 &iflib_rxd_flush, 0, "# times rxd_flush called"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 670 &iflib_verbose_debug, 0, "enable verbose debugging"); 671 672 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 673 static void 674 iflib_debug_reset(void) 675 { 676 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 677 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 678 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 679 iflib_txq_drain_notready = 680 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 681 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 682 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 683 iflib_rx_unavail = 684 iflib_rx_ctx_inactive = iflib_rx_if_input = 685 iflib_rxd_flush = 0; 686 } 687 688 #else 689 #define DBG_COUNTER_INC(name) 690 static void iflib_debug_reset(void) {} 691 #endif 692 693 #define IFLIB_DEBUG 0 694 695 static void iflib_tx_structures_free(if_ctx_t ctx); 696 static void iflib_rx_structures_free(if_ctx_t ctx); 697 static int iflib_queues_alloc(if_ctx_t ctx); 698 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 699 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 700 static int iflib_qset_structures_setup(if_ctx_t ctx); 701 static int iflib_msix_init(if_ctx_t ctx); 702 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 703 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 704 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 705 #ifdef ALTQ 706 static void iflib_altq_if_start(if_t ifp); 707 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 708 #endif 709 static int iflib_register(if_ctx_t); 710 static void iflib_deregister(if_ctx_t); 711 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 712 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 713 static void iflib_init_locked(if_ctx_t ctx); 714 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 715 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 716 static void iflib_ifmp_purge(iflib_txq_t txq); 717 static void _iflib_pre_assert(if_softc_ctx_t scctx); 718 static void iflib_if_init_locked(if_ctx_t ctx); 719 static void iflib_free_intr_mem(if_ctx_t ctx); 720 #ifndef __NO_STRICT_ALIGNMENT 721 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 722 #endif 723 724 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 725 SLIST_HEAD_INITIALIZER(cpu_offsets); 726 struct cpu_offset { 727 SLIST_ENTRY(cpu_offset) entries; 728 cpuset_t set; 729 unsigned int refcount; 730 uint16_t next_cpuid; 731 }; 732 static struct mtx cpu_offset_mtx; 733 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 734 MTX_DEF); 735 736 DEBUGNET_DEFINE(iflib); 737 738 static int 739 iflib_num_rx_descs(if_ctx_t ctx) 740 { 741 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 742 if_shared_ctx_t sctx = ctx->ifc_sctx; 743 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 744 745 return scctx->isc_nrxd[first_rxq]; 746 } 747 748 static int 749 iflib_num_tx_descs(if_ctx_t ctx) 750 { 751 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 752 if_shared_ctx_t sctx = ctx->ifc_sctx; 753 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 754 755 return scctx->isc_ntxd[first_txq]; 756 } 757 758 #ifdef DEV_NETMAP 759 #include <sys/selinfo.h> 760 #include <net/netmap.h> 761 #include <dev/netmap/netmap_kern.h> 762 763 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 764 765 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 766 static void iflib_netmap_timer(void *arg); 767 768 /* 769 * device-specific sysctl variables: 770 * 771 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 772 * During regular operations the CRC is stripped, but on some 773 * hardware reception of frames not multiple of 64 is slower, 774 * so using crcstrip=0 helps in benchmarks. 775 * 776 * iflib_rx_miss, iflib_rx_miss_bufs: 777 * count packets that might be missed due to lost interrupts. 778 */ 779 SYSCTL_DECL(_dev_netmap); 780 /* 781 * The xl driver by default strips CRCs and we do not override it. 782 */ 783 784 int iflib_crcstrip = 1; 785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 786 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 787 788 int iflib_rx_miss, iflib_rx_miss_bufs; 789 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 790 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 791 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 792 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 793 794 /* 795 * Register/unregister. We are already under netmap lock. 796 * Only called on the first register or the last unregister. 797 */ 798 static int 799 iflib_netmap_register(struct netmap_adapter *na, int onoff) 800 { 801 if_t ifp = na->ifp; 802 if_ctx_t ctx = ifp->if_softc; 803 int status; 804 805 CTX_LOCK(ctx); 806 if (!CTX_IS_VF(ctx)) 807 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 808 809 iflib_stop(ctx); 810 811 /* 812 * Enable (or disable) netmap flags, and intercept (or restore) 813 * ifp->if_transmit. This is done once the device has been stopped 814 * to prevent race conditions. Also, this must be done after 815 * calling netmap_disable_all_rings() and before calling 816 * netmap_enable_all_rings(), so that these two functions see the 817 * updated state of the NAF_NETMAP_ON bit. 818 */ 819 if (onoff) { 820 nm_set_native_flags(na); 821 } else { 822 nm_clear_native_flags(na); 823 } 824 825 iflib_init_locked(ctx); 826 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 827 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 828 if (status) 829 nm_clear_native_flags(na); 830 CTX_UNLOCK(ctx); 831 return (status); 832 } 833 834 static int 835 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 836 { 837 if_t ifp = na->ifp; 838 if_ctx_t ctx = ifp->if_softc; 839 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 840 iflib_fl_t fl = &rxq->ifr_fl[0]; 841 842 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 843 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 844 info->num_tx_descs = iflib_num_tx_descs(ctx); 845 info->num_rx_descs = iflib_num_rx_descs(ctx); 846 info->rx_buf_maxsize = fl->ifl_buf_size; 847 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 848 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 849 info->num_rx_descs, info->rx_buf_maxsize); 850 851 return 0; 852 } 853 854 static int 855 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 856 { 857 struct netmap_adapter *na = kring->na; 858 u_int const lim = kring->nkr_num_slots - 1; 859 struct netmap_ring *ring = kring->ring; 860 bus_dmamap_t *map; 861 struct if_rxd_update iru; 862 if_ctx_t ctx = rxq->ifr_ctx; 863 iflib_fl_t fl = &rxq->ifr_fl[0]; 864 u_int nic_i_first, nic_i; 865 u_int nm_i; 866 int i, n; 867 #if IFLIB_DEBUG_COUNTERS 868 int rf_count = 0; 869 #endif 870 871 /* 872 * This function is used both at initialization and in rxsync. 873 * At initialization we need to prepare (with isc_rxd_refill()) 874 * all the netmap buffers currently owned by the kernel, in 875 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 876 * (except for kring->nkr_hwofs). These may be less than 877 * kring->nkr_num_slots if netmap_reset() was called while 878 * an application using the kring that still owned some 879 * buffers. 880 * At rxsync time, both indexes point to the next buffer to be 881 * refilled. 882 * In any case we publish (with isc_rxd_flush()) up to 883 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 884 * pointer to overrun the head/cons pointer, although this is 885 * not necessary for some NICs (e.g. vmx). 886 */ 887 if (__predict_false(init)) { 888 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 889 } else { 890 n = kring->rhead - kring->nr_hwcur; 891 if (n == 0) 892 return (0); /* Nothing to do. */ 893 if (n < 0) 894 n += kring->nkr_num_slots; 895 } 896 897 iru_init(&iru, rxq, 0 /* flid */); 898 map = fl->ifl_sds.ifsd_map; 899 nic_i = fl->ifl_pidx; 900 nm_i = netmap_idx_n2k(kring, nic_i); 901 if (__predict_false(init)) { 902 /* 903 * On init/reset, nic_i must be 0, and we must 904 * start to refill from hwtail (see netmap_reset()). 905 */ 906 MPASS(nic_i == 0); 907 MPASS(nm_i == kring->nr_hwtail); 908 } else 909 MPASS(nm_i == kring->nr_hwcur); 910 DBG_COUNTER_INC(fl_refills); 911 while (n > 0) { 912 #if IFLIB_DEBUG_COUNTERS 913 if (++rf_count == 9) 914 DBG_COUNTER_INC(fl_refills_large); 915 #endif 916 nic_i_first = nic_i; 917 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 918 struct netmap_slot *slot = &ring->slot[nm_i]; 919 uint64_t paddr; 920 void *addr = PNMB(na, slot, &paddr); 921 922 MPASS(i < IFLIB_MAX_RX_REFRESH); 923 924 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 925 return netmap_ring_reinit(kring); 926 927 fl->ifl_bus_addrs[i] = paddr + 928 nm_get_offset(kring, slot); 929 fl->ifl_rxd_idxs[i] = nic_i; 930 931 if (__predict_false(init)) { 932 netmap_load_map(na, fl->ifl_buf_tag, 933 map[nic_i], addr); 934 } else if (slot->flags & NS_BUF_CHANGED) { 935 /* buffer has changed, reload map */ 936 netmap_reload_map(na, fl->ifl_buf_tag, 937 map[nic_i], addr); 938 } 939 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 940 BUS_DMASYNC_PREREAD); 941 slot->flags &= ~NS_BUF_CHANGED; 942 943 nm_i = nm_next(nm_i, lim); 944 nic_i = nm_next(nic_i, lim); 945 } 946 947 iru.iru_pidx = nic_i_first; 948 iru.iru_count = i; 949 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 950 } 951 fl->ifl_pidx = nic_i; 952 /* 953 * At the end of the loop we must have refilled everything 954 * we could possibly refill. 955 */ 956 MPASS(nm_i == kring->rhead); 957 kring->nr_hwcur = nm_i; 958 959 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 960 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 961 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 962 nm_prev(nic_i, lim)); 963 DBG_COUNTER_INC(rxd_flush); 964 965 return (0); 966 } 967 968 #define NETMAP_TX_TIMER_US 90 969 970 /* 971 * Reconcile kernel and user view of the transmit ring. 972 * 973 * All information is in the kring. 974 * Userspace wants to send packets up to the one before kring->rhead, 975 * kernel knows kring->nr_hwcur is the first unsent packet. 976 * 977 * Here we push packets out (as many as possible), and possibly 978 * reclaim buffers from previously completed transmission. 979 * 980 * The caller (netmap) guarantees that there is only one instance 981 * running at any time. Any interference with other driver 982 * methods should be handled by the individual drivers. 983 */ 984 static int 985 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 986 { 987 struct netmap_adapter *na = kring->na; 988 if_t ifp = na->ifp; 989 struct netmap_ring *ring = kring->ring; 990 u_int nm_i; /* index into the netmap kring */ 991 u_int nic_i; /* index into the NIC ring */ 992 u_int n; 993 u_int const lim = kring->nkr_num_slots - 1; 994 u_int const head = kring->rhead; 995 struct if_pkt_info pi; 996 997 /* 998 * interrupts on every tx packet are expensive so request 999 * them every half ring, or where NS_REPORT is set 1000 */ 1001 u_int report_frequency = kring->nkr_num_slots >> 1; 1002 /* device-specific */ 1003 if_ctx_t ctx = ifp->if_softc; 1004 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1005 1006 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1007 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1008 1009 /* 1010 * First part: process new packets to send. 1011 * nm_i is the current index in the netmap kring, 1012 * nic_i is the corresponding index in the NIC ring. 1013 * 1014 * If we have packets to send (nm_i != head) 1015 * iterate over the netmap ring, fetch length and update 1016 * the corresponding slot in the NIC ring. Some drivers also 1017 * need to update the buffer's physical address in the NIC slot 1018 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1019 * 1020 * The netmap_reload_map() calls is especially expensive, 1021 * even when (as in this case) the tag is 0, so do only 1022 * when the buffer has actually changed. 1023 * 1024 * If possible do not set the report/intr bit on all slots, 1025 * but only a few times per ring or when NS_REPORT is set. 1026 * 1027 * Finally, on 10G and faster drivers, it might be useful 1028 * to prefetch the next slot and txr entry. 1029 */ 1030 1031 nm_i = kring->nr_hwcur; 1032 if (nm_i != head) { /* we have new packets to send */ 1033 uint32_t pkt_len = 0, seg_idx = 0; 1034 int nic_i_start = -1, flags = 0; 1035 pkt_info_zero(&pi); 1036 pi.ipi_segs = txq->ift_segs; 1037 pi.ipi_qsidx = kring->ring_id; 1038 nic_i = netmap_idx_k2n(kring, nm_i); 1039 1040 __builtin_prefetch(&ring->slot[nm_i]); 1041 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1042 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1043 1044 for (n = 0; nm_i != head; n++) { 1045 struct netmap_slot *slot = &ring->slot[nm_i]; 1046 uint64_t offset = nm_get_offset(kring, slot); 1047 u_int len = slot->len; 1048 uint64_t paddr; 1049 void *addr = PNMB(na, slot, &paddr); 1050 1051 flags |= (slot->flags & NS_REPORT || 1052 nic_i == 0 || nic_i == report_frequency) ? 1053 IPI_TX_INTR : 0; 1054 1055 /* 1056 * If this is the first packet fragment, save the 1057 * index of the first NIC slot for later. 1058 */ 1059 if (nic_i_start < 0) 1060 nic_i_start = nic_i; 1061 1062 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1063 pi.ipi_segs[seg_idx].ds_len = len; 1064 if (len) { 1065 pkt_len += len; 1066 seg_idx++; 1067 } 1068 1069 if (!(slot->flags & NS_MOREFRAG)) { 1070 pi.ipi_len = pkt_len; 1071 pi.ipi_nsegs = seg_idx; 1072 pi.ipi_pidx = nic_i_start; 1073 pi.ipi_ndescs = 0; 1074 pi.ipi_flags = flags; 1075 1076 /* Prepare the NIC TX ring. */ 1077 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1078 DBG_COUNTER_INC(tx_encap); 1079 1080 /* Reinit per-packet info for the next one. */ 1081 flags = seg_idx = pkt_len = 0; 1082 nic_i_start = -1; 1083 } 1084 1085 /* prefetch for next round */ 1086 __builtin_prefetch(&ring->slot[nm_i + 1]); 1087 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1088 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1089 1090 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1091 1092 if (slot->flags & NS_BUF_CHANGED) { 1093 /* buffer has changed, reload map */ 1094 netmap_reload_map(na, txq->ift_buf_tag, 1095 txq->ift_sds.ifsd_map[nic_i], addr); 1096 } 1097 /* make sure changes to the buffer are synced */ 1098 bus_dmamap_sync(txq->ift_buf_tag, 1099 txq->ift_sds.ifsd_map[nic_i], 1100 BUS_DMASYNC_PREWRITE); 1101 1102 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1103 nm_i = nm_next(nm_i, lim); 1104 nic_i = nm_next(nic_i, lim); 1105 } 1106 kring->nr_hwcur = nm_i; 1107 1108 /* synchronize the NIC ring */ 1109 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1110 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1111 1112 /* (re)start the tx unit up to slot nic_i (excluded) */ 1113 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1114 } 1115 1116 /* 1117 * Second part: reclaim buffers for completed transmissions. 1118 * 1119 * If there are unclaimed buffers, attempt to reclaim them. 1120 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1121 * trigger a per-tx-queue timer to try again later. 1122 */ 1123 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1124 if (iflib_tx_credits_update(ctx, txq)) { 1125 /* some tx completed, increment avail */ 1126 nic_i = txq->ift_cidx_processed; 1127 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1128 } 1129 } 1130 1131 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1132 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1133 callout_reset_sbt_on(&txq->ift_netmap_timer, 1134 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1135 iflib_netmap_timer, txq, 1136 txq->ift_netmap_timer.c_cpu, 0); 1137 } 1138 return (0); 1139 } 1140 1141 /* 1142 * Reconcile kernel and user view of the receive ring. 1143 * Same as for the txsync, this routine must be efficient. 1144 * The caller guarantees a single invocations, but races against 1145 * the rest of the driver should be handled here. 1146 * 1147 * On call, kring->rhead is the first packet that userspace wants 1148 * to keep, and kring->rcur is the wakeup point. 1149 * The kernel has previously reported packets up to kring->rtail. 1150 * 1151 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1152 * of whether or not we received an interrupt. 1153 */ 1154 static int 1155 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1156 { 1157 struct netmap_adapter *na = kring->na; 1158 struct netmap_ring *ring = kring->ring; 1159 if_t ifp = na->ifp; 1160 uint32_t nm_i; /* index into the netmap ring */ 1161 uint32_t nic_i; /* index into the NIC ring */ 1162 u_int n; 1163 u_int const lim = kring->nkr_num_slots - 1; 1164 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1165 int i = 0; 1166 1167 if_ctx_t ctx = ifp->if_softc; 1168 if_shared_ctx_t sctx = ctx->ifc_sctx; 1169 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1170 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1171 iflib_fl_t fl = &rxq->ifr_fl[0]; 1172 struct if_rxd_info ri; 1173 qidx_t *cidxp; 1174 1175 /* 1176 * netmap only uses free list 0, to avoid out of order consumption 1177 * of receive buffers 1178 */ 1179 1180 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1181 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1182 1183 /* 1184 * First part: import newly received packets. 1185 * 1186 * nm_i is the index of the next free slot in the netmap ring, 1187 * nic_i is the index of the next received packet in the NIC ring 1188 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1189 * differ in case if_init() has been called while 1190 * in netmap mode. For the receive ring we have 1191 * 1192 * nic_i = fl->ifl_cidx; 1193 * nm_i = kring->nr_hwtail (previous) 1194 * and 1195 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1196 * 1197 * fl->ifl_cidx is set to 0 on a ring reinit 1198 */ 1199 if (netmap_no_pendintr || force_update) { 1200 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1201 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1202 int crclen = iflib_crcstrip ? 0 : 4; 1203 int error, avail; 1204 1205 /* 1206 * For the free list consumer index, we use the same 1207 * logic as in iflib_rxeof(). 1208 */ 1209 if (have_rxcq) 1210 cidxp = &rxq->ifr_cq_cidx; 1211 else 1212 cidxp = &fl->ifl_cidx; 1213 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1214 rxq->ifr_id, *cidxp, USHRT_MAX); 1215 1216 nic_i = fl->ifl_cidx; 1217 nm_i = netmap_idx_n2k(kring, nic_i); 1218 MPASS(nm_i == kring->nr_hwtail); 1219 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1220 rxd_info_zero(&ri); 1221 ri.iri_frags = rxq->ifr_frags; 1222 ri.iri_qsidx = kring->ring_id; 1223 ri.iri_ifp = ctx->ifc_ifp; 1224 ri.iri_cidx = *cidxp; 1225 1226 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1227 for (i = 0; i < ri.iri_nfrags; i++) { 1228 if (error) { 1229 ring->slot[nm_i].len = 0; 1230 ring->slot[nm_i].flags = 0; 1231 } else { 1232 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1233 if (i == (ri.iri_nfrags - 1)) { 1234 ring->slot[nm_i].len -= crclen; 1235 ring->slot[nm_i].flags = 0; 1236 } else 1237 ring->slot[nm_i].flags = NS_MOREFRAG; 1238 } 1239 1240 bus_dmamap_sync(fl->ifl_buf_tag, 1241 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1242 nm_i = nm_next(nm_i, lim); 1243 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1244 } 1245 1246 if (have_rxcq) { 1247 *cidxp = ri.iri_cidx; 1248 while (*cidxp >= scctx->isc_nrxd[0]) 1249 *cidxp -= scctx->isc_nrxd[0]; 1250 } 1251 1252 } 1253 if (n) { /* update the state variables */ 1254 if (netmap_no_pendintr && !force_update) { 1255 /* diagnostics */ 1256 iflib_rx_miss ++; 1257 iflib_rx_miss_bufs += n; 1258 } 1259 kring->nr_hwtail = nm_i; 1260 } 1261 kring->nr_kflags &= ~NKR_PENDINTR; 1262 } 1263 /* 1264 * Second part: skip past packets that userspace has released. 1265 * (kring->nr_hwcur to head excluded), 1266 * and make the buffers available for reception. 1267 * As usual nm_i is the index in the netmap ring, 1268 * nic_i is the index in the NIC ring, and 1269 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1270 */ 1271 netmap_fl_refill(rxq, kring, false); 1272 1273 return (0); 1274 } 1275 1276 static void 1277 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1278 { 1279 if_ctx_t ctx = na->ifp->if_softc; 1280 1281 CTX_LOCK(ctx); 1282 if (onoff) { 1283 IFDI_INTR_ENABLE(ctx); 1284 } else { 1285 IFDI_INTR_DISABLE(ctx); 1286 } 1287 CTX_UNLOCK(ctx); 1288 } 1289 1290 static int 1291 iflib_netmap_attach(if_ctx_t ctx) 1292 { 1293 struct netmap_adapter na; 1294 1295 bzero(&na, sizeof(na)); 1296 1297 na.ifp = ctx->ifc_ifp; 1298 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1299 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1300 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1301 1302 na.num_tx_desc = iflib_num_tx_descs(ctx); 1303 na.num_rx_desc = iflib_num_rx_descs(ctx); 1304 na.nm_txsync = iflib_netmap_txsync; 1305 na.nm_rxsync = iflib_netmap_rxsync; 1306 na.nm_register = iflib_netmap_register; 1307 na.nm_intr = iflib_netmap_intr; 1308 na.nm_config = iflib_netmap_config; 1309 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1310 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1311 return (netmap_attach(&na)); 1312 } 1313 1314 static int 1315 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1316 { 1317 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1318 struct netmap_slot *slot; 1319 1320 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1321 if (slot == NULL) 1322 return (0); 1323 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1324 /* 1325 * In netmap mode, set the map for the packet buffer. 1326 * NOTE: Some drivers (not this one) also need to set 1327 * the physical buffer address in the NIC ring. 1328 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1329 * netmap slot index, si 1330 */ 1331 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1332 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1333 NMB(na, slot + si)); 1334 } 1335 return (1); 1336 } 1337 1338 static int 1339 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1340 { 1341 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1342 struct netmap_kring *kring; 1343 struct netmap_slot *slot; 1344 1345 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1346 if (slot == NULL) 1347 return (0); 1348 kring = na->rx_rings[rxq->ifr_id]; 1349 netmap_fl_refill(rxq, kring, true); 1350 return (1); 1351 } 1352 1353 static void 1354 iflib_netmap_timer(void *arg) 1355 { 1356 iflib_txq_t txq = arg; 1357 if_ctx_t ctx = txq->ift_ctx; 1358 1359 /* 1360 * Wake up the netmap application, to give it a chance to 1361 * call txsync and reclaim more completed TX buffers. 1362 */ 1363 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1364 } 1365 1366 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1367 1368 #else 1369 #define iflib_netmap_txq_init(ctx, txq) (0) 1370 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1371 #define iflib_netmap_detach(ifp) 1372 #define netmap_enable_all_rings(ifp) 1373 #define netmap_disable_all_rings(ifp) 1374 1375 #define iflib_netmap_attach(ctx) (0) 1376 #define netmap_rx_irq(ifp, qid, budget) (0) 1377 #endif 1378 1379 #if defined(__i386__) || defined(__amd64__) 1380 static __inline void 1381 prefetch(void *x) 1382 { 1383 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1384 } 1385 static __inline void 1386 prefetch2cachelines(void *x) 1387 { 1388 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1389 #if (CACHE_LINE_SIZE < 128) 1390 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1391 #endif 1392 } 1393 #else 1394 #define prefetch(x) 1395 #define prefetch2cachelines(x) 1396 #endif 1397 1398 static void 1399 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1400 { 1401 iflib_fl_t fl; 1402 1403 fl = &rxq->ifr_fl[flid]; 1404 iru->iru_paddrs = fl->ifl_bus_addrs; 1405 iru->iru_idxs = fl->ifl_rxd_idxs; 1406 iru->iru_qsidx = rxq->ifr_id; 1407 iru->iru_buf_size = fl->ifl_buf_size; 1408 iru->iru_flidx = fl->ifl_id; 1409 } 1410 1411 static void 1412 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1413 { 1414 if (err) 1415 return; 1416 *(bus_addr_t *) arg = segs[0].ds_addr; 1417 } 1418 1419 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1420 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1421 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1422 1423 int 1424 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1425 { 1426 int err; 1427 device_t dev = ctx->ifc_dev; 1428 bus_addr_t lowaddr; 1429 1430 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1431 1432 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1433 align, 0, /* alignment, bounds */ 1434 lowaddr, /* lowaddr */ 1435 BUS_SPACE_MAXADDR, /* highaddr */ 1436 NULL, NULL, /* filter, filterarg */ 1437 size, /* maxsize */ 1438 1, /* nsegments */ 1439 size, /* maxsegsize */ 1440 BUS_DMA_ALLOCNOW, /* flags */ 1441 NULL, /* lockfunc */ 1442 NULL, /* lockarg */ 1443 &dma->idi_tag); 1444 if (err) { 1445 device_printf(dev, 1446 "%s: bus_dma_tag_create failed: %d\n", 1447 __func__, err); 1448 goto fail_0; 1449 } 1450 1451 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1452 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1453 if (err) { 1454 device_printf(dev, 1455 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1456 __func__, (uintmax_t)size, err); 1457 goto fail_1; 1458 } 1459 1460 dma->idi_paddr = IF_BAD_DMA; 1461 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1462 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1463 if (err || dma->idi_paddr == IF_BAD_DMA) { 1464 device_printf(dev, 1465 "%s: bus_dmamap_load failed: %d\n", 1466 __func__, err); 1467 goto fail_2; 1468 } 1469 1470 dma->idi_size = size; 1471 return (0); 1472 1473 fail_2: 1474 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1475 fail_1: 1476 bus_dma_tag_destroy(dma->idi_tag); 1477 fail_0: 1478 dma->idi_tag = NULL; 1479 1480 return (err); 1481 } 1482 1483 int 1484 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1485 { 1486 if_shared_ctx_t sctx = ctx->ifc_sctx; 1487 1488 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1489 1490 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1491 } 1492 1493 int 1494 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1495 { 1496 int i, err; 1497 iflib_dma_info_t *dmaiter; 1498 1499 dmaiter = dmalist; 1500 for (i = 0; i < count; i++, dmaiter++) { 1501 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1502 break; 1503 } 1504 if (err) 1505 iflib_dma_free_multi(dmalist, i); 1506 return (err); 1507 } 1508 1509 void 1510 iflib_dma_free(iflib_dma_info_t dma) 1511 { 1512 if (dma->idi_tag == NULL) 1513 return; 1514 if (dma->idi_paddr != IF_BAD_DMA) { 1515 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1516 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1517 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1518 dma->idi_paddr = IF_BAD_DMA; 1519 } 1520 if (dma->idi_vaddr != NULL) { 1521 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1522 dma->idi_vaddr = NULL; 1523 } 1524 bus_dma_tag_destroy(dma->idi_tag); 1525 dma->idi_tag = NULL; 1526 } 1527 1528 void 1529 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1530 { 1531 int i; 1532 iflib_dma_info_t *dmaiter = dmalist; 1533 1534 for (i = 0; i < count; i++, dmaiter++) 1535 iflib_dma_free(*dmaiter); 1536 } 1537 1538 static int 1539 iflib_fast_intr(void *arg) 1540 { 1541 iflib_filter_info_t info = arg; 1542 struct grouptask *gtask = info->ifi_task; 1543 int result; 1544 1545 DBG_COUNTER_INC(fast_intrs); 1546 if (info->ifi_filter != NULL) { 1547 result = info->ifi_filter(info->ifi_filter_arg); 1548 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1549 return (result); 1550 } 1551 1552 GROUPTASK_ENQUEUE(gtask); 1553 return (FILTER_HANDLED); 1554 } 1555 1556 static int 1557 iflib_fast_intr_rxtx(void *arg) 1558 { 1559 iflib_filter_info_t info = arg; 1560 struct grouptask *gtask = info->ifi_task; 1561 if_ctx_t ctx; 1562 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1563 iflib_txq_t txq; 1564 void *sc; 1565 int i, cidx, result; 1566 qidx_t txqid; 1567 bool intr_enable, intr_legacy; 1568 1569 DBG_COUNTER_INC(fast_intrs); 1570 if (info->ifi_filter != NULL) { 1571 result = info->ifi_filter(info->ifi_filter_arg); 1572 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1573 return (result); 1574 } 1575 1576 ctx = rxq->ifr_ctx; 1577 sc = ctx->ifc_softc; 1578 intr_enable = false; 1579 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1580 MPASS(rxq->ifr_ntxqirq); 1581 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1582 txqid = rxq->ifr_txqid[i]; 1583 txq = &ctx->ifc_txqs[txqid]; 1584 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1585 BUS_DMASYNC_POSTREAD); 1586 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1587 if (intr_legacy) 1588 intr_enable = true; 1589 else 1590 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1591 continue; 1592 } 1593 GROUPTASK_ENQUEUE(&txq->ift_task); 1594 } 1595 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1596 cidx = rxq->ifr_cq_cidx; 1597 else 1598 cidx = rxq->ifr_fl[0].ifl_cidx; 1599 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1600 GROUPTASK_ENQUEUE(gtask); 1601 else { 1602 if (intr_legacy) 1603 intr_enable = true; 1604 else 1605 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1606 DBG_COUNTER_INC(rx_intr_enables); 1607 } 1608 if (intr_enable) 1609 IFDI_INTR_ENABLE(ctx); 1610 return (FILTER_HANDLED); 1611 } 1612 1613 static int 1614 iflib_fast_intr_ctx(void *arg) 1615 { 1616 iflib_filter_info_t info = arg; 1617 struct grouptask *gtask = info->ifi_task; 1618 int result; 1619 1620 DBG_COUNTER_INC(fast_intrs); 1621 if (info->ifi_filter != NULL) { 1622 result = info->ifi_filter(info->ifi_filter_arg); 1623 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1624 return (result); 1625 } 1626 1627 GROUPTASK_ENQUEUE(gtask); 1628 return (FILTER_HANDLED); 1629 } 1630 1631 static int 1632 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1633 driver_filter_t filter, driver_intr_t handler, void *arg, 1634 const char *name) 1635 { 1636 struct resource *res; 1637 void *tag = NULL; 1638 device_t dev = ctx->ifc_dev; 1639 int flags, i, rc; 1640 1641 flags = RF_ACTIVE; 1642 if (ctx->ifc_flags & IFC_LEGACY) 1643 flags |= RF_SHAREABLE; 1644 MPASS(rid < 512); 1645 i = rid; 1646 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1647 if (res == NULL) { 1648 device_printf(dev, 1649 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1650 return (ENOMEM); 1651 } 1652 irq->ii_res = res; 1653 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1654 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1655 filter, handler, arg, &tag); 1656 if (rc != 0) { 1657 device_printf(dev, 1658 "failed to setup interrupt for rid %d, name %s: %d\n", 1659 rid, name ? name : "unknown", rc); 1660 return (rc); 1661 } else if (name) 1662 bus_describe_intr(dev, res, tag, "%s", name); 1663 1664 irq->ii_tag = tag; 1665 return (0); 1666 } 1667 1668 /********************************************************************* 1669 * 1670 * Allocate DMA resources for TX buffers as well as memory for the TX 1671 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1672 * iflib_sw_tx_desc_array structure, storing all the information that 1673 * is needed to transmit a packet on the wire. This is called only 1674 * once at attach, setup is done every reset. 1675 * 1676 **********************************************************************/ 1677 static int 1678 iflib_txsd_alloc(iflib_txq_t txq) 1679 { 1680 if_ctx_t ctx = txq->ift_ctx; 1681 if_shared_ctx_t sctx = ctx->ifc_sctx; 1682 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1683 device_t dev = ctx->ifc_dev; 1684 bus_size_t tsomaxsize; 1685 bus_addr_t lowaddr; 1686 int err, nsegments, ntsosegments; 1687 bool tso; 1688 1689 nsegments = scctx->isc_tx_nsegments; 1690 ntsosegments = scctx->isc_tx_tso_segments_max; 1691 tsomaxsize = scctx->isc_tx_tso_size_max; 1692 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1693 tsomaxsize += sizeof(struct ether_vlan_header); 1694 MPASS(scctx->isc_ntxd[0] > 0); 1695 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1696 MPASS(nsegments > 0); 1697 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1698 MPASS(ntsosegments > 0); 1699 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1700 } 1701 1702 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1703 1704 /* 1705 * Set up DMA tags for TX buffers. 1706 */ 1707 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1708 1, 0, /* alignment, bounds */ 1709 lowaddr, /* lowaddr */ 1710 BUS_SPACE_MAXADDR, /* highaddr */ 1711 NULL, NULL, /* filter, filterarg */ 1712 sctx->isc_tx_maxsize, /* maxsize */ 1713 nsegments, /* nsegments */ 1714 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1715 0, /* flags */ 1716 NULL, /* lockfunc */ 1717 NULL, /* lockfuncarg */ 1718 &txq->ift_buf_tag))) { 1719 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1720 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1721 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1722 goto fail; 1723 } 1724 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1725 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1726 1, 0, /* alignment, bounds */ 1727 lowaddr, /* lowaddr */ 1728 BUS_SPACE_MAXADDR, /* highaddr */ 1729 NULL, NULL, /* filter, filterarg */ 1730 tsomaxsize, /* maxsize */ 1731 ntsosegments, /* nsegments */ 1732 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1733 0, /* flags */ 1734 NULL, /* lockfunc */ 1735 NULL, /* lockfuncarg */ 1736 &txq->ift_tso_buf_tag))) { 1737 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1738 err); 1739 goto fail; 1740 } 1741 1742 /* Allocate memory for the TX mbuf map. */ 1743 if (!(txq->ift_sds.ifsd_m = 1744 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1745 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1746 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1747 err = ENOMEM; 1748 goto fail; 1749 } 1750 1751 /* 1752 * Create the DMA maps for TX buffers. 1753 */ 1754 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1755 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1756 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1757 device_printf(dev, 1758 "Unable to allocate TX buffer DMA map memory\n"); 1759 err = ENOMEM; 1760 goto fail; 1761 } 1762 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1763 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1764 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1765 device_printf(dev, 1766 "Unable to allocate TSO TX buffer map memory\n"); 1767 err = ENOMEM; 1768 goto fail; 1769 } 1770 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1771 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1772 &txq->ift_sds.ifsd_map[i]); 1773 if (err != 0) { 1774 device_printf(dev, "Unable to create TX DMA map\n"); 1775 goto fail; 1776 } 1777 if (!tso) 1778 continue; 1779 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1780 &txq->ift_sds.ifsd_tso_map[i]); 1781 if (err != 0) { 1782 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1783 goto fail; 1784 } 1785 } 1786 return (0); 1787 fail: 1788 /* We free all, it handles case where we are in the middle */ 1789 iflib_tx_structures_free(ctx); 1790 return (err); 1791 } 1792 1793 static void 1794 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1795 { 1796 bus_dmamap_t map; 1797 1798 if (txq->ift_sds.ifsd_map != NULL) { 1799 map = txq->ift_sds.ifsd_map[i]; 1800 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1801 bus_dmamap_unload(txq->ift_buf_tag, map); 1802 bus_dmamap_destroy(txq->ift_buf_tag, map); 1803 txq->ift_sds.ifsd_map[i] = NULL; 1804 } 1805 1806 if (txq->ift_sds.ifsd_tso_map != NULL) { 1807 map = txq->ift_sds.ifsd_tso_map[i]; 1808 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1809 BUS_DMASYNC_POSTWRITE); 1810 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1811 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1812 txq->ift_sds.ifsd_tso_map[i] = NULL; 1813 } 1814 } 1815 1816 static void 1817 iflib_txq_destroy(iflib_txq_t txq) 1818 { 1819 if_ctx_t ctx = txq->ift_ctx; 1820 1821 for (int i = 0; i < txq->ift_size; i++) 1822 iflib_txsd_destroy(ctx, txq, i); 1823 1824 if (txq->ift_br != NULL) { 1825 ifmp_ring_free(txq->ift_br); 1826 txq->ift_br = NULL; 1827 } 1828 1829 mtx_destroy(&txq->ift_mtx); 1830 1831 if (txq->ift_sds.ifsd_map != NULL) { 1832 free(txq->ift_sds.ifsd_map, M_IFLIB); 1833 txq->ift_sds.ifsd_map = NULL; 1834 } 1835 if (txq->ift_sds.ifsd_tso_map != NULL) { 1836 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1837 txq->ift_sds.ifsd_tso_map = NULL; 1838 } 1839 if (txq->ift_sds.ifsd_m != NULL) { 1840 free(txq->ift_sds.ifsd_m, M_IFLIB); 1841 txq->ift_sds.ifsd_m = NULL; 1842 } 1843 if (txq->ift_buf_tag != NULL) { 1844 bus_dma_tag_destroy(txq->ift_buf_tag); 1845 txq->ift_buf_tag = NULL; 1846 } 1847 if (txq->ift_tso_buf_tag != NULL) { 1848 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1849 txq->ift_tso_buf_tag = NULL; 1850 } 1851 if (txq->ift_ifdi != NULL) { 1852 free(txq->ift_ifdi, M_IFLIB); 1853 } 1854 } 1855 1856 static void 1857 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1858 { 1859 struct mbuf **mp; 1860 1861 mp = &txq->ift_sds.ifsd_m[i]; 1862 if (*mp == NULL) 1863 return; 1864 1865 if (txq->ift_sds.ifsd_map != NULL) { 1866 bus_dmamap_sync(txq->ift_buf_tag, 1867 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1868 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1869 } 1870 if (txq->ift_sds.ifsd_tso_map != NULL) { 1871 bus_dmamap_sync(txq->ift_tso_buf_tag, 1872 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1873 bus_dmamap_unload(txq->ift_tso_buf_tag, 1874 txq->ift_sds.ifsd_tso_map[i]); 1875 } 1876 m_freem(*mp); 1877 DBG_COUNTER_INC(tx_frees); 1878 *mp = NULL; 1879 } 1880 1881 static int 1882 iflib_txq_setup(iflib_txq_t txq) 1883 { 1884 if_ctx_t ctx = txq->ift_ctx; 1885 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1886 if_shared_ctx_t sctx = ctx->ifc_sctx; 1887 iflib_dma_info_t di; 1888 int i; 1889 1890 /* Set number of descriptors available */ 1891 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1892 /* XXX make configurable */ 1893 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1894 1895 /* Reset indices */ 1896 txq->ift_cidx_processed = 0; 1897 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1898 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1899 1900 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1901 bzero((void *)di->idi_vaddr, di->idi_size); 1902 1903 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1904 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1905 bus_dmamap_sync(di->idi_tag, di->idi_map, 1906 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1907 return (0); 1908 } 1909 1910 /********************************************************************* 1911 * 1912 * Allocate DMA resources for RX buffers as well as memory for the RX 1913 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1914 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1915 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1916 * Since we use use one entry in iflib_sw_rx_desc_array per received 1917 * packet, the maximum number of entries we'll need is equal to the 1918 * number of hardware receive descriptors that we've allocated. 1919 * 1920 **********************************************************************/ 1921 static int 1922 iflib_rxsd_alloc(iflib_rxq_t rxq) 1923 { 1924 if_ctx_t ctx = rxq->ifr_ctx; 1925 if_shared_ctx_t sctx = ctx->ifc_sctx; 1926 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1927 device_t dev = ctx->ifc_dev; 1928 iflib_fl_t fl; 1929 bus_addr_t lowaddr; 1930 int err; 1931 1932 MPASS(scctx->isc_nrxd[0] > 0); 1933 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1934 1935 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1936 1937 fl = rxq->ifr_fl; 1938 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1939 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1940 /* Set up DMA tag for RX buffers. */ 1941 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1942 1, 0, /* alignment, bounds */ 1943 lowaddr, /* lowaddr */ 1944 BUS_SPACE_MAXADDR, /* highaddr */ 1945 NULL, NULL, /* filter, filterarg */ 1946 sctx->isc_rx_maxsize, /* maxsize */ 1947 sctx->isc_rx_nsegments, /* nsegments */ 1948 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1949 0, /* flags */ 1950 NULL, /* lockfunc */ 1951 NULL, /* lockarg */ 1952 &fl->ifl_buf_tag); 1953 if (err) { 1954 device_printf(dev, 1955 "Unable to allocate RX DMA tag: %d\n", err); 1956 goto fail; 1957 } 1958 1959 /* Allocate memory for the RX mbuf map. */ 1960 if (!(fl->ifl_sds.ifsd_m = 1961 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1962 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1963 device_printf(dev, 1964 "Unable to allocate RX mbuf map memory\n"); 1965 err = ENOMEM; 1966 goto fail; 1967 } 1968 1969 /* Allocate memory for the direct RX cluster pointer map. */ 1970 if (!(fl->ifl_sds.ifsd_cl = 1971 (caddr_t *) malloc(sizeof(caddr_t) * 1972 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1973 device_printf(dev, 1974 "Unable to allocate RX cluster map memory\n"); 1975 err = ENOMEM; 1976 goto fail; 1977 } 1978 1979 /* Allocate memory for the RX cluster bus address map. */ 1980 if (!(fl->ifl_sds.ifsd_ba = 1981 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1982 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1983 device_printf(dev, 1984 "Unable to allocate RX bus address map memory\n"); 1985 err = ENOMEM; 1986 goto fail; 1987 } 1988 1989 /* 1990 * Create the DMA maps for RX buffers. 1991 */ 1992 if (!(fl->ifl_sds.ifsd_map = 1993 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1994 device_printf(dev, 1995 "Unable to allocate RX buffer DMA map memory\n"); 1996 err = ENOMEM; 1997 goto fail; 1998 } 1999 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2000 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2001 &fl->ifl_sds.ifsd_map[i]); 2002 if (err != 0) { 2003 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2004 goto fail; 2005 } 2006 } 2007 } 2008 return (0); 2009 2010 fail: 2011 iflib_rx_structures_free(ctx); 2012 return (err); 2013 } 2014 2015 /* 2016 * Internal service routines 2017 */ 2018 2019 struct rxq_refill_cb_arg { 2020 int error; 2021 bus_dma_segment_t seg; 2022 int nseg; 2023 }; 2024 2025 static void 2026 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2027 { 2028 struct rxq_refill_cb_arg *cb_arg = arg; 2029 2030 cb_arg->error = error; 2031 cb_arg->seg = segs[0]; 2032 cb_arg->nseg = nseg; 2033 } 2034 2035 /** 2036 * iflib_fl_refill - refill an rxq free-buffer list 2037 * @ctx: the iflib context 2038 * @fl: the free list to refill 2039 * @count: the number of new buffers to allocate 2040 * 2041 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2042 * The caller must assure that @count does not exceed the queue's capacity 2043 * minus one (since we always leave a descriptor unavailable). 2044 */ 2045 static uint8_t 2046 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2047 { 2048 struct if_rxd_update iru; 2049 struct rxq_refill_cb_arg cb_arg; 2050 struct mbuf *m; 2051 caddr_t cl, *sd_cl; 2052 struct mbuf **sd_m; 2053 bus_dmamap_t *sd_map; 2054 bus_addr_t bus_addr, *sd_ba; 2055 int err, frag_idx, i, idx, n, pidx; 2056 qidx_t credits; 2057 2058 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2059 2060 sd_m = fl->ifl_sds.ifsd_m; 2061 sd_map = fl->ifl_sds.ifsd_map; 2062 sd_cl = fl->ifl_sds.ifsd_cl; 2063 sd_ba = fl->ifl_sds.ifsd_ba; 2064 pidx = fl->ifl_pidx; 2065 idx = pidx; 2066 frag_idx = fl->ifl_fragidx; 2067 credits = fl->ifl_credits; 2068 2069 i = 0; 2070 n = count; 2071 MPASS(n > 0); 2072 MPASS(credits + n <= fl->ifl_size); 2073 2074 if (pidx < fl->ifl_cidx) 2075 MPASS(pidx + n <= fl->ifl_cidx); 2076 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2077 MPASS(fl->ifl_gen == 0); 2078 if (pidx > fl->ifl_cidx) 2079 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2080 2081 DBG_COUNTER_INC(fl_refills); 2082 if (n > 8) 2083 DBG_COUNTER_INC(fl_refills_large); 2084 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2085 while (n-- > 0) { 2086 /* 2087 * We allocate an uninitialized mbuf + cluster, mbuf is 2088 * initialized after rx. 2089 * 2090 * If the cluster is still set then we know a minimum sized 2091 * packet was received 2092 */ 2093 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2094 &frag_idx); 2095 if (frag_idx < 0) 2096 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2097 MPASS(frag_idx >= 0); 2098 if ((cl = sd_cl[frag_idx]) == NULL) { 2099 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2100 if (__predict_false(cl == NULL)) 2101 break; 2102 2103 cb_arg.error = 0; 2104 MPASS(sd_map != NULL); 2105 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2106 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2107 BUS_DMA_NOWAIT); 2108 if (__predict_false(err != 0 || cb_arg.error)) { 2109 uma_zfree(fl->ifl_zone, cl); 2110 break; 2111 } 2112 2113 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2114 sd_cl[frag_idx] = cl; 2115 #if MEMORY_LOGGING 2116 fl->ifl_cl_enqueued++; 2117 #endif 2118 } else { 2119 bus_addr = sd_ba[frag_idx]; 2120 } 2121 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2122 BUS_DMASYNC_PREREAD); 2123 2124 if (sd_m[frag_idx] == NULL) { 2125 m = m_gethdr(M_NOWAIT, MT_NOINIT); 2126 if (__predict_false(m == NULL)) 2127 break; 2128 sd_m[frag_idx] = m; 2129 } 2130 bit_set(fl->ifl_rx_bitmap, frag_idx); 2131 #if MEMORY_LOGGING 2132 fl->ifl_m_enqueued++; 2133 #endif 2134 2135 DBG_COUNTER_INC(rx_allocs); 2136 fl->ifl_rxd_idxs[i] = frag_idx; 2137 fl->ifl_bus_addrs[i] = bus_addr; 2138 credits++; 2139 i++; 2140 MPASS(credits <= fl->ifl_size); 2141 if (++idx == fl->ifl_size) { 2142 #ifdef INVARIANTS 2143 fl->ifl_gen = 1; 2144 #endif 2145 idx = 0; 2146 } 2147 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2148 iru.iru_pidx = pidx; 2149 iru.iru_count = i; 2150 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2151 fl->ifl_pidx = idx; 2152 fl->ifl_credits = credits; 2153 pidx = idx; 2154 i = 0; 2155 } 2156 } 2157 2158 if (n < count - 1) { 2159 if (i != 0) { 2160 iru.iru_pidx = pidx; 2161 iru.iru_count = i; 2162 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2163 fl->ifl_pidx = idx; 2164 fl->ifl_credits = credits; 2165 } 2166 DBG_COUNTER_INC(rxd_flush); 2167 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2168 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2169 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2170 fl->ifl_id, fl->ifl_pidx); 2171 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2172 fl->ifl_fragidx = frag_idx + 1; 2173 if (fl->ifl_fragidx == fl->ifl_size) 2174 fl->ifl_fragidx = 0; 2175 } else { 2176 fl->ifl_fragidx = frag_idx; 2177 } 2178 } 2179 2180 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2181 } 2182 2183 static inline uint8_t 2184 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2185 { 2186 /* 2187 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2188 * This is important as it confuses most NICs. For instance, 2189 * Intel NICs have (per receive ring) RDH and RDT registers, where 2190 * RDH points to the next receive descriptor to be used by the NIC, 2191 * and RDT for the next receive descriptor to be published by the 2192 * driver to the NIC (RDT - 1 is thus the last valid one). 2193 * The condition RDH == RDT means no descriptors are available to 2194 * the NIC, and thus it would be ambiguous if it also meant that 2195 * all the descriptors are available to the NIC. 2196 */ 2197 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2198 #ifdef INVARIANTS 2199 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2200 #endif 2201 2202 MPASS(fl->ifl_credits <= fl->ifl_size); 2203 MPASS(reclaimable == delta); 2204 2205 if (reclaimable > 0) 2206 return (iflib_fl_refill(ctx, fl, reclaimable)); 2207 return (0); 2208 } 2209 2210 uint8_t 2211 iflib_in_detach(if_ctx_t ctx) 2212 { 2213 bool in_detach; 2214 2215 STATE_LOCK(ctx); 2216 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2217 STATE_UNLOCK(ctx); 2218 return (in_detach); 2219 } 2220 2221 static void 2222 iflib_fl_bufs_free(iflib_fl_t fl) 2223 { 2224 iflib_dma_info_t idi = fl->ifl_ifdi; 2225 bus_dmamap_t sd_map; 2226 uint32_t i; 2227 2228 for (i = 0; i < fl->ifl_size; i++) { 2229 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2230 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2231 2232 if (*sd_cl != NULL) { 2233 sd_map = fl->ifl_sds.ifsd_map[i]; 2234 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2235 BUS_DMASYNC_POSTREAD); 2236 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2237 uma_zfree(fl->ifl_zone, *sd_cl); 2238 *sd_cl = NULL; 2239 if (*sd_m != NULL) { 2240 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2241 uma_zfree(zone_mbuf, *sd_m); 2242 *sd_m = NULL; 2243 } 2244 } else { 2245 MPASS(*sd_m == NULL); 2246 } 2247 #if MEMORY_LOGGING 2248 fl->ifl_m_dequeued++; 2249 fl->ifl_cl_dequeued++; 2250 #endif 2251 } 2252 #ifdef INVARIANTS 2253 for (i = 0; i < fl->ifl_size; i++) { 2254 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2255 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2256 } 2257 #endif 2258 /* 2259 * Reset free list values 2260 */ 2261 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2262 bzero(idi->idi_vaddr, idi->idi_size); 2263 } 2264 2265 /********************************************************************* 2266 * 2267 * Initialize a free list and its buffers. 2268 * 2269 **********************************************************************/ 2270 static int 2271 iflib_fl_setup(iflib_fl_t fl) 2272 { 2273 iflib_rxq_t rxq = fl->ifl_rxq; 2274 if_ctx_t ctx = rxq->ifr_ctx; 2275 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2276 int qidx; 2277 2278 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2279 /* 2280 ** Free current RX buffer structs and their mbufs 2281 */ 2282 iflib_fl_bufs_free(fl); 2283 /* Now replenish the mbufs */ 2284 MPASS(fl->ifl_credits == 0); 2285 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2286 if (scctx->isc_rxd_buf_size[qidx] != 0) 2287 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2288 else 2289 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2290 /* 2291 * ifl_buf_size may be a driver-supplied value, so pull it up 2292 * to the selected mbuf size. 2293 */ 2294 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2295 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2296 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2297 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2298 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2299 2300 /* 2301 * Avoid pre-allocating zillions of clusters to an idle card 2302 * potentially speeding up attach. In any case make sure 2303 * to leave a descriptor unavailable. See the comment in 2304 * iflib_fl_refill_all(). 2305 */ 2306 MPASS(fl->ifl_size > 0); 2307 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2308 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2309 return (ENOBUFS); 2310 /* 2311 * handle failure 2312 */ 2313 MPASS(rxq != NULL); 2314 MPASS(fl->ifl_ifdi != NULL); 2315 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2316 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2317 return (0); 2318 } 2319 2320 /********************************************************************* 2321 * 2322 * Free receive ring data structures 2323 * 2324 **********************************************************************/ 2325 static void 2326 iflib_rx_sds_free(iflib_rxq_t rxq) 2327 { 2328 iflib_fl_t fl; 2329 int i, j; 2330 2331 if (rxq->ifr_fl != NULL) { 2332 for (i = 0; i < rxq->ifr_nfl; i++) { 2333 fl = &rxq->ifr_fl[i]; 2334 if (fl->ifl_buf_tag != NULL) { 2335 if (fl->ifl_sds.ifsd_map != NULL) { 2336 for (j = 0; j < fl->ifl_size; j++) { 2337 bus_dmamap_sync( 2338 fl->ifl_buf_tag, 2339 fl->ifl_sds.ifsd_map[j], 2340 BUS_DMASYNC_POSTREAD); 2341 bus_dmamap_unload( 2342 fl->ifl_buf_tag, 2343 fl->ifl_sds.ifsd_map[j]); 2344 bus_dmamap_destroy( 2345 fl->ifl_buf_tag, 2346 fl->ifl_sds.ifsd_map[j]); 2347 } 2348 } 2349 bus_dma_tag_destroy(fl->ifl_buf_tag); 2350 fl->ifl_buf_tag = NULL; 2351 } 2352 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2353 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2354 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2355 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2356 free(fl->ifl_rx_bitmap, M_IFLIB); 2357 fl->ifl_sds.ifsd_m = NULL; 2358 fl->ifl_sds.ifsd_cl = NULL; 2359 fl->ifl_sds.ifsd_ba = NULL; 2360 fl->ifl_sds.ifsd_map = NULL; 2361 fl->ifl_rx_bitmap = NULL; 2362 } 2363 free(rxq->ifr_fl, M_IFLIB); 2364 rxq->ifr_fl = NULL; 2365 free(rxq->ifr_ifdi, M_IFLIB); 2366 rxq->ifr_ifdi = NULL; 2367 rxq->ifr_cq_cidx = 0; 2368 } 2369 } 2370 2371 /* 2372 * Timer routine 2373 */ 2374 static void 2375 iflib_timer(void *arg) 2376 { 2377 iflib_txq_t txq = arg; 2378 if_ctx_t ctx = txq->ift_ctx; 2379 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2380 uint64_t this_tick = ticks; 2381 2382 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2383 return; 2384 2385 /* 2386 ** Check on the state of the TX queue(s), this 2387 ** can be done without the lock because its RO 2388 ** and the HUNG state will be static if set. 2389 */ 2390 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2391 txq->ift_last_timer_tick = this_tick; 2392 IFDI_TIMER(ctx, txq->ift_id); 2393 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2394 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2395 (sctx->isc_pause_frames == 0))) 2396 goto hung; 2397 2398 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2399 ifmp_ring_is_stalled(txq->ift_br)) { 2400 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2401 ("queue can't be marked as hung if interface is down")); 2402 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2403 } 2404 txq->ift_cleaned_prev = txq->ift_cleaned; 2405 } 2406 /* handle any laggards */ 2407 if (txq->ift_db_pending) 2408 GROUPTASK_ENQUEUE(&txq->ift_task); 2409 2410 sctx->isc_pause_frames = 0; 2411 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2412 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2413 txq, txq->ift_timer.c_cpu); 2414 return; 2415 2416 hung: 2417 device_printf(ctx->ifc_dev, 2418 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2419 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2420 STATE_LOCK(ctx); 2421 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2422 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2423 iflib_admin_intr_deferred(ctx); 2424 STATE_UNLOCK(ctx); 2425 } 2426 2427 static uint16_t 2428 iflib_get_mbuf_size_for(unsigned int size) 2429 { 2430 2431 if (size <= MCLBYTES) 2432 return (MCLBYTES); 2433 else 2434 return (MJUMPAGESIZE); 2435 } 2436 2437 static void 2438 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2439 { 2440 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2441 2442 /* 2443 * XXX don't set the max_frame_size to larger 2444 * than the hardware can handle 2445 */ 2446 ctx->ifc_rx_mbuf_sz = 2447 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2448 } 2449 2450 uint32_t 2451 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2452 { 2453 2454 return (ctx->ifc_rx_mbuf_sz); 2455 } 2456 2457 static void 2458 iflib_init_locked(if_ctx_t ctx) 2459 { 2460 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2461 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2462 if_t ifp = ctx->ifc_ifp; 2463 iflib_fl_t fl; 2464 iflib_txq_t txq; 2465 iflib_rxq_t rxq; 2466 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2467 2468 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2469 IFDI_INTR_DISABLE(ctx); 2470 2471 /* 2472 * See iflib_stop(). Useful in case iflib_init_locked() is 2473 * called without first calling iflib_stop(). 2474 */ 2475 netmap_disable_all_rings(ifp); 2476 2477 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2478 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2479 /* Set hardware offload abilities */ 2480 if_clearhwassist(ifp); 2481 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2482 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2483 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2484 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2485 if (if_getcapenable(ifp) & IFCAP_TSO4) 2486 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2487 if (if_getcapenable(ifp) & IFCAP_TSO6) 2488 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2489 2490 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2491 CALLOUT_LOCK(txq); 2492 callout_stop(&txq->ift_timer); 2493 #ifdef DEV_NETMAP 2494 callout_stop(&txq->ift_netmap_timer); 2495 #endif /* DEV_NETMAP */ 2496 CALLOUT_UNLOCK(txq); 2497 (void)iflib_netmap_txq_init(ctx, txq); 2498 } 2499 2500 /* 2501 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2502 * that drivers can use the value when setting up the hardware receive 2503 * buffers. 2504 */ 2505 iflib_calc_rx_mbuf_sz(ctx); 2506 2507 #ifdef INVARIANTS 2508 i = if_getdrvflags(ifp); 2509 #endif 2510 IFDI_INIT(ctx); 2511 MPASS(if_getdrvflags(ifp) == i); 2512 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2513 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2514 /* This rxq is in netmap mode. Skip normal init. */ 2515 continue; 2516 } 2517 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2518 if (iflib_fl_setup(fl)) { 2519 device_printf(ctx->ifc_dev, 2520 "setting up free list %d failed - " 2521 "check cluster settings\n", j); 2522 goto done; 2523 } 2524 } 2525 } 2526 done: 2527 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2528 IFDI_INTR_ENABLE(ctx); 2529 txq = ctx->ifc_txqs; 2530 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2531 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2532 txq->ift_timer.c_cpu); 2533 2534 /* Re-enable txsync/rxsync. */ 2535 netmap_enable_all_rings(ifp); 2536 } 2537 2538 static int 2539 iflib_media_change(if_t ifp) 2540 { 2541 if_ctx_t ctx = if_getsoftc(ifp); 2542 int err; 2543 2544 CTX_LOCK(ctx); 2545 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2546 iflib_if_init_locked(ctx); 2547 CTX_UNLOCK(ctx); 2548 return (err); 2549 } 2550 2551 static void 2552 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2553 { 2554 if_ctx_t ctx = if_getsoftc(ifp); 2555 2556 CTX_LOCK(ctx); 2557 IFDI_UPDATE_ADMIN_STATUS(ctx); 2558 IFDI_MEDIA_STATUS(ctx, ifmr); 2559 CTX_UNLOCK(ctx); 2560 } 2561 2562 void 2563 iflib_stop(if_ctx_t ctx) 2564 { 2565 iflib_txq_t txq = ctx->ifc_txqs; 2566 iflib_rxq_t rxq = ctx->ifc_rxqs; 2567 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2568 if_shared_ctx_t sctx = ctx->ifc_sctx; 2569 iflib_dma_info_t di; 2570 iflib_fl_t fl; 2571 int i, j; 2572 2573 /* Tell the stack that the interface is no longer active */ 2574 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2575 2576 IFDI_INTR_DISABLE(ctx); 2577 DELAY(1000); 2578 IFDI_STOP(ctx); 2579 DELAY(1000); 2580 2581 /* 2582 * Stop any pending txsync/rxsync and prevent new ones 2583 * form starting. Processes blocked in poll() will get 2584 * POLLERR. 2585 */ 2586 netmap_disable_all_rings(ctx->ifc_ifp); 2587 2588 iflib_debug_reset(); 2589 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2590 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2591 /* make sure all transmitters have completed before proceeding XXX */ 2592 2593 CALLOUT_LOCK(txq); 2594 callout_stop(&txq->ift_timer); 2595 #ifdef DEV_NETMAP 2596 callout_stop(&txq->ift_netmap_timer); 2597 #endif /* DEV_NETMAP */ 2598 CALLOUT_UNLOCK(txq); 2599 2600 /* clean any enqueued buffers */ 2601 iflib_ifmp_purge(txq); 2602 /* Free any existing tx buffers. */ 2603 for (j = 0; j < txq->ift_size; j++) { 2604 iflib_txsd_free(ctx, txq, j); 2605 } 2606 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2607 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2608 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2609 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2610 txq->ift_pullups = 0; 2611 ifmp_ring_reset_stats(txq->ift_br); 2612 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2613 bzero((void *)di->idi_vaddr, di->idi_size); 2614 } 2615 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2616 /* make sure all transmitters have completed before proceeding XXX */ 2617 2618 rxq->ifr_cq_cidx = 0; 2619 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2620 bzero((void *)di->idi_vaddr, di->idi_size); 2621 /* also resets the free lists pidx/cidx */ 2622 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2623 iflib_fl_bufs_free(fl); 2624 } 2625 } 2626 2627 static inline caddr_t 2628 calc_next_rxd(iflib_fl_t fl, int cidx) 2629 { 2630 qidx_t size; 2631 int nrxd; 2632 caddr_t start, end, cur, next; 2633 2634 nrxd = fl->ifl_size; 2635 size = fl->ifl_rxd_size; 2636 start = fl->ifl_ifdi->idi_vaddr; 2637 2638 if (__predict_false(size == 0)) 2639 return (start); 2640 cur = start + size*cidx; 2641 end = start + size*nrxd; 2642 next = CACHE_PTR_NEXT(cur); 2643 return (next < end ? next : start); 2644 } 2645 2646 static inline void 2647 prefetch_pkts(iflib_fl_t fl, int cidx) 2648 { 2649 int nextptr; 2650 int nrxd = fl->ifl_size; 2651 caddr_t next_rxd; 2652 2653 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2654 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2655 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2656 next_rxd = calc_next_rxd(fl, cidx); 2657 prefetch(next_rxd); 2658 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2659 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2660 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2661 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2662 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2663 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2664 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2665 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2666 } 2667 2668 static struct mbuf * 2669 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2670 int *pf_rv, if_rxd_info_t ri) 2671 { 2672 bus_dmamap_t map; 2673 iflib_fl_t fl; 2674 caddr_t payload; 2675 struct mbuf *m; 2676 int flid, cidx, len, next; 2677 2678 map = NULL; 2679 flid = irf->irf_flid; 2680 cidx = irf->irf_idx; 2681 fl = &rxq->ifr_fl[flid]; 2682 sd->ifsd_fl = fl; 2683 m = fl->ifl_sds.ifsd_m[cidx]; 2684 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2685 fl->ifl_credits--; 2686 #if MEMORY_LOGGING 2687 fl->ifl_m_dequeued++; 2688 #endif 2689 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2690 prefetch_pkts(fl, cidx); 2691 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2692 prefetch(&fl->ifl_sds.ifsd_map[next]); 2693 map = fl->ifl_sds.ifsd_map[cidx]; 2694 2695 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2696 2697 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2698 irf->irf_len != 0) { 2699 payload = *sd->ifsd_cl; 2700 payload += ri->iri_pad; 2701 len = ri->iri_len - ri->iri_pad; 2702 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2703 len | PFIL_MEMPTR | PFIL_IN, NULL); 2704 switch (*pf_rv) { 2705 case PFIL_DROPPED: 2706 case PFIL_CONSUMED: 2707 /* 2708 * The filter ate it. Everything is recycled. 2709 */ 2710 m = NULL; 2711 unload = 0; 2712 break; 2713 case PFIL_REALLOCED: 2714 /* 2715 * The filter copied it. Everything is recycled. 2716 */ 2717 m = pfil_mem2mbuf(payload); 2718 unload = 0; 2719 break; 2720 case PFIL_PASS: 2721 /* 2722 * Filter said it was OK, so receive like 2723 * normal 2724 */ 2725 fl->ifl_sds.ifsd_m[cidx] = NULL; 2726 break; 2727 default: 2728 MPASS(0); 2729 } 2730 } else { 2731 fl->ifl_sds.ifsd_m[cidx] = NULL; 2732 if (pf_rv != NULL) 2733 *pf_rv = PFIL_PASS; 2734 } 2735 2736 if (unload && irf->irf_len != 0) 2737 bus_dmamap_unload(fl->ifl_buf_tag, map); 2738 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2739 if (__predict_false(fl->ifl_cidx == 0)) 2740 fl->ifl_gen = 0; 2741 bit_clear(fl->ifl_rx_bitmap, cidx); 2742 return (m); 2743 } 2744 2745 static struct mbuf * 2746 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2747 { 2748 struct mbuf *m, *mh, *mt; 2749 caddr_t cl; 2750 int *pf_rv_ptr, flags, i, padlen; 2751 bool consumed; 2752 2753 i = 0; 2754 mh = NULL; 2755 consumed = false; 2756 *pf_rv = PFIL_PASS; 2757 pf_rv_ptr = pf_rv; 2758 do { 2759 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2760 pf_rv_ptr, ri); 2761 2762 MPASS(*sd->ifsd_cl != NULL); 2763 2764 /* 2765 * Exclude zero-length frags & frags from 2766 * packets the filter has consumed or dropped 2767 */ 2768 if (ri->iri_frags[i].irf_len == 0 || consumed || 2769 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2770 if (mh == NULL) { 2771 /* everything saved here */ 2772 consumed = true; 2773 pf_rv_ptr = NULL; 2774 continue; 2775 } 2776 /* XXX we can save the cluster here, but not the mbuf */ 2777 m_init(m, M_NOWAIT, MT_DATA, 0); 2778 m_free(m); 2779 continue; 2780 } 2781 if (mh == NULL) { 2782 flags = M_PKTHDR|M_EXT; 2783 mh = mt = m; 2784 padlen = ri->iri_pad; 2785 } else { 2786 flags = M_EXT; 2787 mt->m_next = m; 2788 mt = m; 2789 /* assuming padding is only on the first fragment */ 2790 padlen = 0; 2791 } 2792 cl = *sd->ifsd_cl; 2793 *sd->ifsd_cl = NULL; 2794 2795 /* Can these two be made one ? */ 2796 m_init(m, M_NOWAIT, MT_DATA, flags); 2797 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2798 /* 2799 * These must follow m_init and m_cljset 2800 */ 2801 m->m_data += padlen; 2802 ri->iri_len -= padlen; 2803 m->m_len = ri->iri_frags[i].irf_len; 2804 } while (++i < ri->iri_nfrags); 2805 2806 return (mh); 2807 } 2808 2809 /* 2810 * Process one software descriptor 2811 */ 2812 static struct mbuf * 2813 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2814 { 2815 struct if_rxsd sd; 2816 struct mbuf *m; 2817 int pf_rv; 2818 2819 /* should I merge this back in now that the two paths are basically duplicated? */ 2820 if (ri->iri_nfrags == 1 && 2821 ri->iri_frags[0].irf_len != 0 && 2822 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2823 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2824 &pf_rv, ri); 2825 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2826 return (m); 2827 if (pf_rv == PFIL_PASS) { 2828 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2829 #ifndef __NO_STRICT_ALIGNMENT 2830 if (!IP_ALIGNED(m)) 2831 m->m_data += 2; 2832 #endif 2833 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2834 m->m_len = ri->iri_frags[0].irf_len; 2835 } 2836 } else { 2837 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2838 if (m == NULL) 2839 return (NULL); 2840 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2841 return (m); 2842 } 2843 m->m_pkthdr.len = ri->iri_len; 2844 m->m_pkthdr.rcvif = ri->iri_ifp; 2845 m->m_flags |= ri->iri_flags; 2846 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2847 m->m_pkthdr.flowid = ri->iri_flowid; 2848 M_HASHTYPE_SET(m, ri->iri_rsstype); 2849 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2850 m->m_pkthdr.csum_data = ri->iri_csum_data; 2851 return (m); 2852 } 2853 2854 #if defined(INET6) || defined(INET) 2855 static void 2856 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2857 { 2858 CURVNET_SET(lc->ifp->if_vnet); 2859 #if defined(INET6) 2860 *v6 = V_ip6_forwarding; 2861 #endif 2862 #if defined(INET) 2863 *v4 = V_ipforwarding; 2864 #endif 2865 CURVNET_RESTORE(); 2866 } 2867 2868 /* 2869 * Returns true if it's possible this packet could be LROed. 2870 * if it returns false, it is guaranteed that tcp_lro_rx() 2871 * would not return zero. 2872 */ 2873 static bool 2874 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2875 { 2876 struct ether_header *eh; 2877 2878 eh = mtod(m, struct ether_header *); 2879 switch (eh->ether_type) { 2880 #if defined(INET6) 2881 case htons(ETHERTYPE_IPV6): 2882 return (!v6_forwarding); 2883 #endif 2884 #if defined (INET) 2885 case htons(ETHERTYPE_IP): 2886 return (!v4_forwarding); 2887 #endif 2888 } 2889 2890 return false; 2891 } 2892 #else 2893 static void 2894 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2895 { 2896 } 2897 #endif 2898 2899 static void 2900 _task_fn_rx_watchdog(void *context) 2901 { 2902 iflib_rxq_t rxq = context; 2903 2904 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2905 } 2906 2907 static uint8_t 2908 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2909 { 2910 if_t ifp; 2911 if_ctx_t ctx = rxq->ifr_ctx; 2912 if_shared_ctx_t sctx = ctx->ifc_sctx; 2913 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2914 int avail, i; 2915 qidx_t *cidxp; 2916 struct if_rxd_info ri; 2917 int err, budget_left, rx_bytes, rx_pkts; 2918 iflib_fl_t fl; 2919 int lro_enabled; 2920 bool v4_forwarding, v6_forwarding, lro_possible; 2921 uint8_t retval = 0; 2922 2923 /* 2924 * XXX early demux data packets so that if_input processing only handles 2925 * acks in interrupt context 2926 */ 2927 struct mbuf *m, *mh, *mt, *mf; 2928 2929 NET_EPOCH_ASSERT(); 2930 2931 lro_possible = v4_forwarding = v6_forwarding = false; 2932 ifp = ctx->ifc_ifp; 2933 mh = mt = NULL; 2934 MPASS(budget > 0); 2935 rx_pkts = rx_bytes = 0; 2936 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2937 cidxp = &rxq->ifr_cq_cidx; 2938 else 2939 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2940 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2941 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2942 retval |= iflib_fl_refill_all(ctx, fl); 2943 DBG_COUNTER_INC(rx_unavail); 2944 return (retval); 2945 } 2946 2947 /* pfil needs the vnet to be set */ 2948 CURVNET_SET_QUIET(ifp->if_vnet); 2949 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2950 if (__predict_false(!CTX_ACTIVE(ctx))) { 2951 DBG_COUNTER_INC(rx_ctx_inactive); 2952 break; 2953 } 2954 /* 2955 * Reset client set fields to their default values 2956 */ 2957 rxd_info_zero(&ri); 2958 ri.iri_qsidx = rxq->ifr_id; 2959 ri.iri_cidx = *cidxp; 2960 ri.iri_ifp = ifp; 2961 ri.iri_frags = rxq->ifr_frags; 2962 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2963 2964 if (err) 2965 goto err; 2966 rx_pkts += 1; 2967 rx_bytes += ri.iri_len; 2968 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2969 *cidxp = ri.iri_cidx; 2970 /* Update our consumer index */ 2971 /* XXX NB: shurd - check if this is still safe */ 2972 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2973 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2974 /* was this only a completion queue message? */ 2975 if (__predict_false(ri.iri_nfrags == 0)) 2976 continue; 2977 } 2978 MPASS(ri.iri_nfrags != 0); 2979 MPASS(ri.iri_len != 0); 2980 2981 /* will advance the cidx on the corresponding free lists */ 2982 m = iflib_rxd_pkt_get(rxq, &ri); 2983 avail--; 2984 budget_left--; 2985 if (avail == 0 && budget_left) 2986 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2987 2988 if (__predict_false(m == NULL)) 2989 continue; 2990 2991 /* imm_pkt: -- cxgb */ 2992 if (mh == NULL) 2993 mh = mt = m; 2994 else { 2995 mt->m_nextpkt = m; 2996 mt = m; 2997 } 2998 } 2999 CURVNET_RESTORE(); 3000 /* make sure that we can refill faster than drain */ 3001 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3002 retval |= iflib_fl_refill_all(ctx, fl); 3003 3004 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3005 if (lro_enabled) 3006 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 3007 mt = mf = NULL; 3008 while (mh != NULL) { 3009 m = mh; 3010 mh = mh->m_nextpkt; 3011 m->m_nextpkt = NULL; 3012 #ifndef __NO_STRICT_ALIGNMENT 3013 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3014 continue; 3015 #endif 3016 #if defined(INET6) || defined(INET) 3017 if (lro_enabled) { 3018 if (!lro_possible) { 3019 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 3020 if (lro_possible && mf != NULL) { 3021 ifp->if_input(ifp, mf); 3022 DBG_COUNTER_INC(rx_if_input); 3023 mt = mf = NULL; 3024 } 3025 } 3026 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 3027 (CSUM_L4_CALC|CSUM_L4_VALID)) { 3028 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 3029 continue; 3030 } 3031 } 3032 #endif 3033 if (lro_possible) { 3034 ifp->if_input(ifp, m); 3035 DBG_COUNTER_INC(rx_if_input); 3036 continue; 3037 } 3038 3039 if (mf == NULL) 3040 mf = m; 3041 if (mt != NULL) 3042 mt->m_nextpkt = m; 3043 mt = m; 3044 } 3045 if (mf != NULL) { 3046 ifp->if_input(ifp, mf); 3047 DBG_COUNTER_INC(rx_if_input); 3048 } 3049 3050 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3051 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3052 3053 /* 3054 * Flush any outstanding LRO work 3055 */ 3056 #if defined(INET6) || defined(INET) 3057 tcp_lro_flush_all(&rxq->ifr_lc); 3058 #endif 3059 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3060 retval |= IFLIB_RXEOF_MORE; 3061 return (retval); 3062 err: 3063 STATE_LOCK(ctx); 3064 ctx->ifc_flags |= IFC_DO_RESET; 3065 iflib_admin_intr_deferred(ctx); 3066 STATE_UNLOCK(ctx); 3067 return (0); 3068 } 3069 3070 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 3071 static inline qidx_t 3072 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3073 { 3074 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3075 qidx_t minthresh = txq->ift_size / 8; 3076 if (in_use > 4*minthresh) 3077 return (notify_count); 3078 if (in_use > 2*minthresh) 3079 return (notify_count >> 1); 3080 if (in_use > minthresh) 3081 return (notify_count >> 3); 3082 return (0); 3083 } 3084 3085 static inline qidx_t 3086 txq_max_rs_deferred(iflib_txq_t txq) 3087 { 3088 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3089 qidx_t minthresh = txq->ift_size / 8; 3090 if (txq->ift_in_use > 4*minthresh) 3091 return (notify_count); 3092 if (txq->ift_in_use > 2*minthresh) 3093 return (notify_count >> 1); 3094 if (txq->ift_in_use > minthresh) 3095 return (notify_count >> 2); 3096 return (2); 3097 } 3098 3099 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3100 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3101 3102 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3103 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3104 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3105 3106 /* forward compatibility for cxgb */ 3107 #define FIRST_QSET(ctx) 0 3108 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3109 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3110 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3111 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3112 3113 /* XXX we should be setting this to something other than zero */ 3114 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3115 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3116 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3117 3118 static inline bool 3119 iflib_txd_db_check(iflib_txq_t txq, int ring) 3120 { 3121 if_ctx_t ctx = txq->ift_ctx; 3122 qidx_t dbval, max; 3123 3124 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3125 3126 /* force || threshold exceeded || at the edge of the ring */ 3127 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3128 3129 /* 3130 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3131 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3132 * producer index explicitly (INTC). 3133 */ 3134 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3135 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3136 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3137 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3138 3139 /* 3140 * Absent bugs there are zero packets pending so reset pending counts to zero. 3141 */ 3142 txq->ift_db_pending = txq->ift_npending = 0; 3143 return (true); 3144 } 3145 return (false); 3146 } 3147 3148 #ifdef PKT_DEBUG 3149 static void 3150 print_pkt(if_pkt_info_t pi) 3151 { 3152 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3153 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3154 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3155 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3156 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3157 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3158 } 3159 #endif 3160 3161 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3162 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3163 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3164 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3165 3166 static int 3167 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3168 { 3169 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3170 struct ether_vlan_header *eh; 3171 struct mbuf *m; 3172 3173 m = *mp; 3174 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3175 M_WRITABLE(m) == 0) { 3176 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3177 return (ENOMEM); 3178 } else { 3179 m_freem(*mp); 3180 DBG_COUNTER_INC(tx_frees); 3181 *mp = m; 3182 } 3183 } 3184 3185 /* 3186 * Determine where frame payload starts. 3187 * Jump over vlan headers if already present, 3188 * helpful for QinQ too. 3189 */ 3190 if (__predict_false(m->m_len < sizeof(*eh))) { 3191 txq->ift_pullups++; 3192 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3193 return (ENOMEM); 3194 } 3195 eh = mtod(m, struct ether_vlan_header *); 3196 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3197 pi->ipi_etype = ntohs(eh->evl_proto); 3198 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3199 } else { 3200 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3201 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3202 } 3203 3204 switch (pi->ipi_etype) { 3205 #ifdef INET 3206 case ETHERTYPE_IP: 3207 { 3208 struct mbuf *n; 3209 struct ip *ip = NULL; 3210 struct tcphdr *th = NULL; 3211 int minthlen; 3212 3213 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3214 if (__predict_false(m->m_len < minthlen)) { 3215 /* 3216 * if this code bloat is causing too much of a hit 3217 * move it to a separate function and mark it noinline 3218 */ 3219 if (m->m_len == pi->ipi_ehdrlen) { 3220 n = m->m_next; 3221 MPASS(n); 3222 if (n->m_len >= sizeof(*ip)) { 3223 ip = (struct ip *)n->m_data; 3224 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3225 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3226 } else { 3227 txq->ift_pullups++; 3228 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3229 return (ENOMEM); 3230 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3231 } 3232 } else { 3233 txq->ift_pullups++; 3234 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3235 return (ENOMEM); 3236 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3237 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3238 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3239 } 3240 } else { 3241 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3242 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3243 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3244 } 3245 pi->ipi_ip_hlen = ip->ip_hl << 2; 3246 pi->ipi_ipproto = ip->ip_p; 3247 pi->ipi_flags |= IPI_TX_IPV4; 3248 3249 /* TCP checksum offload may require TCP header length */ 3250 if (IS_TX_OFFLOAD4(pi)) { 3251 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3252 if (__predict_false(th == NULL)) { 3253 txq->ift_pullups++; 3254 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3255 return (ENOMEM); 3256 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3257 } 3258 pi->ipi_tcp_hflags = th->th_flags; 3259 pi->ipi_tcp_hlen = th->th_off << 2; 3260 pi->ipi_tcp_seq = th->th_seq; 3261 } 3262 if (IS_TSO4(pi)) { 3263 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3264 return (ENXIO); 3265 /* 3266 * TSO always requires hardware checksum offload. 3267 */ 3268 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3269 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3270 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3271 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3272 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3273 ip->ip_sum = 0; 3274 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3275 } 3276 } 3277 } 3278 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3279 ip->ip_sum = 0; 3280 3281 break; 3282 } 3283 #endif 3284 #ifdef INET6 3285 case ETHERTYPE_IPV6: 3286 { 3287 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3288 struct tcphdr *th; 3289 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3290 3291 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3292 txq->ift_pullups++; 3293 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3294 return (ENOMEM); 3295 } 3296 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3297 3298 /* XXX-BZ this will go badly in case of ext hdrs. */ 3299 pi->ipi_ipproto = ip6->ip6_nxt; 3300 pi->ipi_flags |= IPI_TX_IPV6; 3301 3302 /* TCP checksum offload may require TCP header length */ 3303 if (IS_TX_OFFLOAD6(pi)) { 3304 if (pi->ipi_ipproto == IPPROTO_TCP) { 3305 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3306 txq->ift_pullups++; 3307 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3308 return (ENOMEM); 3309 } 3310 pi->ipi_tcp_hflags = th->th_flags; 3311 pi->ipi_tcp_hlen = th->th_off << 2; 3312 pi->ipi_tcp_seq = th->th_seq; 3313 } 3314 if (IS_TSO6(pi)) { 3315 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3316 return (ENXIO); 3317 /* 3318 * TSO always requires hardware checksum offload. 3319 */ 3320 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3321 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3322 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3323 } 3324 } 3325 break; 3326 } 3327 #endif 3328 default: 3329 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3330 pi->ipi_ip_hlen = 0; 3331 break; 3332 } 3333 *mp = m; 3334 3335 return (0); 3336 } 3337 3338 /* 3339 * If dodgy hardware rejects the scatter gather chain we've handed it 3340 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3341 * m_defrag'd mbufs 3342 */ 3343 static __noinline struct mbuf * 3344 iflib_remove_mbuf(iflib_txq_t txq) 3345 { 3346 int ntxd, pidx; 3347 struct mbuf *m, **ifsd_m; 3348 3349 ifsd_m = txq->ift_sds.ifsd_m; 3350 ntxd = txq->ift_size; 3351 pidx = txq->ift_pidx & (ntxd - 1); 3352 ifsd_m = txq->ift_sds.ifsd_m; 3353 m = ifsd_m[pidx]; 3354 ifsd_m[pidx] = NULL; 3355 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3356 if (txq->ift_sds.ifsd_tso_map != NULL) 3357 bus_dmamap_unload(txq->ift_tso_buf_tag, 3358 txq->ift_sds.ifsd_tso_map[pidx]); 3359 #if MEMORY_LOGGING 3360 txq->ift_dequeued++; 3361 #endif 3362 return (m); 3363 } 3364 3365 static inline caddr_t 3366 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3367 { 3368 qidx_t size; 3369 int ntxd; 3370 caddr_t start, end, cur, next; 3371 3372 ntxd = txq->ift_size; 3373 size = txq->ift_txd_size[qid]; 3374 start = txq->ift_ifdi[qid].idi_vaddr; 3375 3376 if (__predict_false(size == 0)) 3377 return (start); 3378 cur = start + size*cidx; 3379 end = start + size*ntxd; 3380 next = CACHE_PTR_NEXT(cur); 3381 return (next < end ? next : start); 3382 } 3383 3384 /* 3385 * Pad an mbuf to ensure a minimum ethernet frame size. 3386 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3387 */ 3388 static __noinline int 3389 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3390 { 3391 /* 3392 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3393 * and ARP message is the smallest common payload I can think of 3394 */ 3395 static char pad[18]; /* just zeros */ 3396 int n; 3397 struct mbuf *new_head; 3398 3399 if (!M_WRITABLE(*m_head)) { 3400 new_head = m_dup(*m_head, M_NOWAIT); 3401 if (new_head == NULL) { 3402 m_freem(*m_head); 3403 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3404 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3405 DBG_COUNTER_INC(tx_frees); 3406 return ENOMEM; 3407 } 3408 m_freem(*m_head); 3409 *m_head = new_head; 3410 } 3411 3412 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3413 n > 0; n -= sizeof(pad)) 3414 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3415 break; 3416 3417 if (n > 0) { 3418 m_freem(*m_head); 3419 device_printf(dev, "cannot pad short frame\n"); 3420 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3421 DBG_COUNTER_INC(tx_frees); 3422 return (ENOBUFS); 3423 } 3424 3425 return 0; 3426 } 3427 3428 static int 3429 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3430 { 3431 if_ctx_t ctx; 3432 if_shared_ctx_t sctx; 3433 if_softc_ctx_t scctx; 3434 bus_dma_tag_t buf_tag; 3435 bus_dma_segment_t *segs; 3436 struct mbuf *m_head, **ifsd_m; 3437 void *next_txd; 3438 bus_dmamap_t map; 3439 struct if_pkt_info pi; 3440 int remap = 0; 3441 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3442 3443 ctx = txq->ift_ctx; 3444 sctx = ctx->ifc_sctx; 3445 scctx = &ctx->ifc_softc_ctx; 3446 segs = txq->ift_segs; 3447 ntxd = txq->ift_size; 3448 m_head = *m_headp; 3449 map = NULL; 3450 3451 /* 3452 * If we're doing TSO the next descriptor to clean may be quite far ahead 3453 */ 3454 cidx = txq->ift_cidx; 3455 pidx = txq->ift_pidx; 3456 if (ctx->ifc_flags & IFC_PREFETCH) { 3457 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3458 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3459 next_txd = calc_next_txd(txq, cidx, 0); 3460 prefetch(next_txd); 3461 } 3462 3463 /* prefetch the next cache line of mbuf pointers and flags */ 3464 prefetch(&txq->ift_sds.ifsd_m[next]); 3465 prefetch(&txq->ift_sds.ifsd_map[next]); 3466 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3467 } 3468 map = txq->ift_sds.ifsd_map[pidx]; 3469 ifsd_m = txq->ift_sds.ifsd_m; 3470 3471 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3472 buf_tag = txq->ift_tso_buf_tag; 3473 max_segs = scctx->isc_tx_tso_segments_max; 3474 map = txq->ift_sds.ifsd_tso_map[pidx]; 3475 MPASS(buf_tag != NULL); 3476 MPASS(max_segs > 0); 3477 } else { 3478 buf_tag = txq->ift_buf_tag; 3479 max_segs = scctx->isc_tx_nsegments; 3480 map = txq->ift_sds.ifsd_map[pidx]; 3481 } 3482 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3483 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3484 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3485 if (err) { 3486 DBG_COUNTER_INC(encap_txd_encap_fail); 3487 return err; 3488 } 3489 } 3490 m_head = *m_headp; 3491 3492 pkt_info_zero(&pi); 3493 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3494 pi.ipi_pidx = pidx; 3495 pi.ipi_qsidx = txq->ift_id; 3496 pi.ipi_len = m_head->m_pkthdr.len; 3497 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3498 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3499 3500 /* deliberate bitwise OR to make one condition */ 3501 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3502 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3503 DBG_COUNTER_INC(encap_txd_encap_fail); 3504 return (err); 3505 } 3506 m_head = *m_headp; 3507 } 3508 3509 retry: 3510 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3511 BUS_DMA_NOWAIT); 3512 defrag: 3513 if (__predict_false(err)) { 3514 switch (err) { 3515 case EFBIG: 3516 /* try collapse once and defrag once */ 3517 if (remap == 0) { 3518 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3519 /* try defrag if collapsing fails */ 3520 if (m_head == NULL) 3521 remap++; 3522 } 3523 if (remap == 1) { 3524 txq->ift_mbuf_defrag++; 3525 m_head = m_defrag(*m_headp, M_NOWAIT); 3526 } 3527 /* 3528 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3529 * failed to map an mbuf that was run through m_defrag 3530 */ 3531 MPASS(remap <= 1); 3532 if (__predict_false(m_head == NULL || remap > 1)) 3533 goto defrag_failed; 3534 remap++; 3535 *m_headp = m_head; 3536 goto retry; 3537 break; 3538 case ENOMEM: 3539 txq->ift_no_tx_dma_setup++; 3540 break; 3541 default: 3542 txq->ift_no_tx_dma_setup++; 3543 m_freem(*m_headp); 3544 DBG_COUNTER_INC(tx_frees); 3545 *m_headp = NULL; 3546 break; 3547 } 3548 txq->ift_map_failed++; 3549 DBG_COUNTER_INC(encap_load_mbuf_fail); 3550 DBG_COUNTER_INC(encap_txd_encap_fail); 3551 return (err); 3552 } 3553 ifsd_m[pidx] = m_head; 3554 /* 3555 * XXX assumes a 1 to 1 relationship between segments and 3556 * descriptors - this does not hold true on all drivers, e.g. 3557 * cxgb 3558 */ 3559 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3560 txq->ift_no_desc_avail++; 3561 bus_dmamap_unload(buf_tag, map); 3562 DBG_COUNTER_INC(encap_txq_avail_fail); 3563 DBG_COUNTER_INC(encap_txd_encap_fail); 3564 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3565 GROUPTASK_ENQUEUE(&txq->ift_task); 3566 return (ENOBUFS); 3567 } 3568 /* 3569 * On Intel cards we can greatly reduce the number of TX interrupts 3570 * we see by only setting report status on every Nth descriptor. 3571 * However, this also means that the driver will need to keep track 3572 * of the descriptors that RS was set on to check them for the DD bit. 3573 */ 3574 txq->ift_rs_pending += nsegs + 1; 3575 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3576 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3577 pi.ipi_flags |= IPI_TX_INTR; 3578 txq->ift_rs_pending = 0; 3579 } 3580 3581 pi.ipi_segs = segs; 3582 pi.ipi_nsegs = nsegs; 3583 3584 MPASS(pidx >= 0 && pidx < txq->ift_size); 3585 #ifdef PKT_DEBUG 3586 print_pkt(&pi); 3587 #endif 3588 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3589 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3590 DBG_COUNTER_INC(tx_encap); 3591 MPASS(pi.ipi_new_pidx < txq->ift_size); 3592 3593 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3594 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3595 ndesc += txq->ift_size; 3596 txq->ift_gen = 1; 3597 } 3598 /* 3599 * drivers can need as many as 3600 * two sentinels 3601 */ 3602 MPASS(ndesc <= pi.ipi_nsegs + 2); 3603 MPASS(pi.ipi_new_pidx != pidx); 3604 MPASS(ndesc > 0); 3605 txq->ift_in_use += ndesc; 3606 txq->ift_db_pending += ndesc; 3607 3608 /* 3609 * We update the last software descriptor again here because there may 3610 * be a sentinel and/or there may be more mbufs than segments 3611 */ 3612 txq->ift_pidx = pi.ipi_new_pidx; 3613 txq->ift_npending += pi.ipi_ndescs; 3614 } else { 3615 *m_headp = m_head = iflib_remove_mbuf(txq); 3616 if (err == EFBIG) { 3617 txq->ift_txd_encap_efbig++; 3618 if (remap < 2) { 3619 remap = 1; 3620 goto defrag; 3621 } 3622 } 3623 goto defrag_failed; 3624 } 3625 /* 3626 * err can't possibly be non-zero here, so we don't neet to test it 3627 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3628 */ 3629 return (err); 3630 3631 defrag_failed: 3632 txq->ift_mbuf_defrag_failed++; 3633 txq->ift_map_failed++; 3634 m_freem(*m_headp); 3635 DBG_COUNTER_INC(tx_frees); 3636 *m_headp = NULL; 3637 DBG_COUNTER_INC(encap_txd_encap_fail); 3638 return (ENOMEM); 3639 } 3640 3641 static void 3642 iflib_tx_desc_free(iflib_txq_t txq, int n) 3643 { 3644 uint32_t qsize, cidx, mask, gen; 3645 struct mbuf *m, **ifsd_m; 3646 bool do_prefetch; 3647 3648 cidx = txq->ift_cidx; 3649 gen = txq->ift_gen; 3650 qsize = txq->ift_size; 3651 mask = qsize-1; 3652 ifsd_m = txq->ift_sds.ifsd_m; 3653 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3654 3655 while (n-- > 0) { 3656 if (do_prefetch) { 3657 prefetch(ifsd_m[(cidx + 3) & mask]); 3658 prefetch(ifsd_m[(cidx + 4) & mask]); 3659 } 3660 if ((m = ifsd_m[cidx]) != NULL) { 3661 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3662 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3663 bus_dmamap_sync(txq->ift_tso_buf_tag, 3664 txq->ift_sds.ifsd_tso_map[cidx], 3665 BUS_DMASYNC_POSTWRITE); 3666 bus_dmamap_unload(txq->ift_tso_buf_tag, 3667 txq->ift_sds.ifsd_tso_map[cidx]); 3668 } else { 3669 bus_dmamap_sync(txq->ift_buf_tag, 3670 txq->ift_sds.ifsd_map[cidx], 3671 BUS_DMASYNC_POSTWRITE); 3672 bus_dmamap_unload(txq->ift_buf_tag, 3673 txq->ift_sds.ifsd_map[cidx]); 3674 } 3675 /* XXX we don't support any drivers that batch packets yet */ 3676 MPASS(m->m_nextpkt == NULL); 3677 m_freem(m); 3678 ifsd_m[cidx] = NULL; 3679 #if MEMORY_LOGGING 3680 txq->ift_dequeued++; 3681 #endif 3682 DBG_COUNTER_INC(tx_frees); 3683 } 3684 if (__predict_false(++cidx == qsize)) { 3685 cidx = 0; 3686 gen = 0; 3687 } 3688 } 3689 txq->ift_cidx = cidx; 3690 txq->ift_gen = gen; 3691 } 3692 3693 static __inline int 3694 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3695 { 3696 int reclaim; 3697 if_ctx_t ctx = txq->ift_ctx; 3698 3699 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3700 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3701 3702 /* 3703 * Need a rate-limiting check so that this isn't called every time 3704 */ 3705 iflib_tx_credits_update(ctx, txq); 3706 reclaim = DESC_RECLAIMABLE(txq); 3707 3708 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3709 #ifdef INVARIANTS 3710 if (iflib_verbose_debug) { 3711 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3712 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3713 reclaim, thresh); 3714 } 3715 #endif 3716 return (0); 3717 } 3718 iflib_tx_desc_free(txq, reclaim); 3719 txq->ift_cleaned += reclaim; 3720 txq->ift_in_use -= reclaim; 3721 3722 return (reclaim); 3723 } 3724 3725 static struct mbuf ** 3726 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3727 { 3728 int next, size; 3729 struct mbuf **items; 3730 3731 size = r->size; 3732 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3733 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3734 3735 prefetch(items[(cidx + offset) & (size-1)]); 3736 if (remaining > 1) { 3737 prefetch2cachelines(&items[next]); 3738 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3739 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3740 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3741 } 3742 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3743 } 3744 3745 static void 3746 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3747 { 3748 3749 ifmp_ring_check_drainage(txq->ift_br, budget); 3750 } 3751 3752 static uint32_t 3753 iflib_txq_can_drain(struct ifmp_ring *r) 3754 { 3755 iflib_txq_t txq = r->cookie; 3756 if_ctx_t ctx = txq->ift_ctx; 3757 3758 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3759 return (1); 3760 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3761 BUS_DMASYNC_POSTREAD); 3762 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3763 false)); 3764 } 3765 3766 static uint32_t 3767 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3768 { 3769 iflib_txq_t txq = r->cookie; 3770 if_ctx_t ctx = txq->ift_ctx; 3771 if_t ifp = ctx->ifc_ifp; 3772 struct mbuf *m, **mp; 3773 int avail, bytes_sent, skipped, count, err, i; 3774 int mcast_sent, pkt_sent, reclaimed; 3775 bool do_prefetch, rang, ring; 3776 3777 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3778 !LINK_ACTIVE(ctx))) { 3779 DBG_COUNTER_INC(txq_drain_notready); 3780 return (0); 3781 } 3782 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3783 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3784 avail = IDXDIFF(pidx, cidx, r->size); 3785 3786 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3787 /* 3788 * The driver is unloading so we need to free all pending packets. 3789 */ 3790 DBG_COUNTER_INC(txq_drain_flushing); 3791 for (i = 0; i < avail; i++) { 3792 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3793 m_freem(r->items[(cidx + i) & (r->size-1)]); 3794 r->items[(cidx + i) & (r->size-1)] = NULL; 3795 } 3796 return (avail); 3797 } 3798 3799 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3800 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3801 CALLOUT_LOCK(txq); 3802 callout_stop(&txq->ift_timer); 3803 CALLOUT_UNLOCK(txq); 3804 DBG_COUNTER_INC(txq_drain_oactive); 3805 return (0); 3806 } 3807 3808 /* 3809 * If we've reclaimed any packets this queue cannot be hung. 3810 */ 3811 if (reclaimed) 3812 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3813 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3814 count = MIN(avail, TX_BATCH_SIZE); 3815 #ifdef INVARIANTS 3816 if (iflib_verbose_debug) 3817 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3818 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3819 #endif 3820 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3821 err = 0; 3822 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3823 int rem = do_prefetch ? count - i : 0; 3824 3825 mp = _ring_peek_one(r, cidx, i, rem); 3826 MPASS(mp != NULL && *mp != NULL); 3827 3828 /* 3829 * Completion interrupts will use the address of the txq 3830 * as a sentinel to enqueue _something_ in order to acquire 3831 * the lock on the mp_ring (there's no direct lock call). 3832 * We obviously whave to check for these sentinel cases 3833 * and skip them. 3834 */ 3835 if (__predict_false(*mp == (struct mbuf *)txq)) { 3836 skipped++; 3837 continue; 3838 } 3839 err = iflib_encap(txq, mp); 3840 if (__predict_false(err)) { 3841 /* no room - bail out */ 3842 if (err == ENOBUFS) 3843 break; 3844 skipped++; 3845 /* we can't send this packet - skip it */ 3846 continue; 3847 } 3848 pkt_sent++; 3849 m = *mp; 3850 DBG_COUNTER_INC(tx_sent); 3851 bytes_sent += m->m_pkthdr.len; 3852 mcast_sent += !!(m->m_flags & M_MCAST); 3853 3854 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3855 break; 3856 ETHER_BPF_MTAP(ifp, m); 3857 rang = iflib_txd_db_check(txq, false); 3858 } 3859 3860 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3861 ring = rang ? false : (iflib_min_tx_latency | err); 3862 iflib_txd_db_check(txq, ring); 3863 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3864 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3865 if (mcast_sent) 3866 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3867 #ifdef INVARIANTS 3868 if (iflib_verbose_debug) 3869 printf("consumed=%d\n", skipped + pkt_sent); 3870 #endif 3871 return (skipped + pkt_sent); 3872 } 3873 3874 static uint32_t 3875 iflib_txq_drain_always(struct ifmp_ring *r) 3876 { 3877 return (1); 3878 } 3879 3880 static uint32_t 3881 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3882 { 3883 int i, avail; 3884 struct mbuf **mp; 3885 iflib_txq_t txq; 3886 3887 txq = r->cookie; 3888 3889 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3890 CALLOUT_LOCK(txq); 3891 callout_stop(&txq->ift_timer); 3892 CALLOUT_UNLOCK(txq); 3893 3894 avail = IDXDIFF(pidx, cidx, r->size); 3895 for (i = 0; i < avail; i++) { 3896 mp = _ring_peek_one(r, cidx, i, avail - i); 3897 if (__predict_false(*mp == (struct mbuf *)txq)) 3898 continue; 3899 m_freem(*mp); 3900 DBG_COUNTER_INC(tx_frees); 3901 } 3902 MPASS(ifmp_ring_is_stalled(r) == 0); 3903 return (avail); 3904 } 3905 3906 static void 3907 iflib_ifmp_purge(iflib_txq_t txq) 3908 { 3909 struct ifmp_ring *r; 3910 3911 r = txq->ift_br; 3912 r->drain = iflib_txq_drain_free; 3913 r->can_drain = iflib_txq_drain_always; 3914 3915 ifmp_ring_check_drainage(r, r->size); 3916 3917 r->drain = iflib_txq_drain; 3918 r->can_drain = iflib_txq_can_drain; 3919 } 3920 3921 static void 3922 _task_fn_tx(void *context) 3923 { 3924 iflib_txq_t txq = context; 3925 if_ctx_t ctx = txq->ift_ctx; 3926 if_t ifp = ctx->ifc_ifp; 3927 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3928 3929 #ifdef IFLIB_DIAGNOSTICS 3930 txq->ift_cpu_exec_count[curcpu]++; 3931 #endif 3932 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3933 return; 3934 #ifdef DEV_NETMAP 3935 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3936 netmap_tx_irq(ifp, txq->ift_id)) 3937 goto skip_ifmp; 3938 #endif 3939 #ifdef ALTQ 3940 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3941 iflib_altq_if_start(ifp); 3942 #endif 3943 if (txq->ift_db_pending) 3944 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3945 else if (!abdicate) 3946 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3947 /* 3948 * When abdicating, we always need to check drainage, not just when we don't enqueue 3949 */ 3950 if (abdicate) 3951 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3952 #ifdef DEV_NETMAP 3953 skip_ifmp: 3954 #endif 3955 if (ctx->ifc_flags & IFC_LEGACY) 3956 IFDI_INTR_ENABLE(ctx); 3957 else 3958 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3959 } 3960 3961 static void 3962 _task_fn_rx(void *context) 3963 { 3964 iflib_rxq_t rxq = context; 3965 if_ctx_t ctx = rxq->ifr_ctx; 3966 uint8_t more; 3967 uint16_t budget; 3968 #ifdef DEV_NETMAP 3969 u_int work = 0; 3970 int nmirq; 3971 #endif 3972 3973 #ifdef IFLIB_DIAGNOSTICS 3974 rxq->ifr_cpu_exec_count[curcpu]++; 3975 #endif 3976 DBG_COUNTER_INC(task_fn_rxs); 3977 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3978 return; 3979 #ifdef DEV_NETMAP 3980 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 3981 if (nmirq != NM_IRQ_PASS) { 3982 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 3983 goto skip_rxeof; 3984 } 3985 #endif 3986 budget = ctx->ifc_sysctl_rx_budget; 3987 if (budget == 0) 3988 budget = 16; /* XXX */ 3989 more = iflib_rxeof(rxq, budget); 3990 #ifdef DEV_NETMAP 3991 skip_rxeof: 3992 #endif 3993 if ((more & IFLIB_RXEOF_MORE) == 0) { 3994 if (ctx->ifc_flags & IFC_LEGACY) 3995 IFDI_INTR_ENABLE(ctx); 3996 else 3997 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3998 DBG_COUNTER_INC(rx_intr_enables); 3999 } 4000 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4001 return; 4002 4003 if (more & IFLIB_RXEOF_MORE) 4004 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4005 else if (more & IFLIB_RXEOF_EMPTY) 4006 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4007 } 4008 4009 static void 4010 _task_fn_admin(void *context) 4011 { 4012 if_ctx_t ctx = context; 4013 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4014 iflib_txq_t txq; 4015 int i; 4016 bool oactive, running, do_reset, do_watchdog, in_detach; 4017 4018 STATE_LOCK(ctx); 4019 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4020 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4021 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4022 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4023 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4024 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 4025 STATE_UNLOCK(ctx); 4026 4027 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4028 return; 4029 if (in_detach) 4030 return; 4031 4032 CTX_LOCK(ctx); 4033 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4034 CALLOUT_LOCK(txq); 4035 callout_stop(&txq->ift_timer); 4036 CALLOUT_UNLOCK(txq); 4037 } 4038 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4039 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4040 if (do_watchdog) { 4041 ctx->ifc_watchdog_events++; 4042 IFDI_WATCHDOG_RESET(ctx); 4043 } 4044 IFDI_UPDATE_ADMIN_STATUS(ctx); 4045 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4046 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4047 txq->ift_timer.c_cpu); 4048 } 4049 IFDI_LINK_INTR_ENABLE(ctx); 4050 if (do_reset) 4051 iflib_if_init_locked(ctx); 4052 CTX_UNLOCK(ctx); 4053 4054 if (LINK_ACTIVE(ctx) == 0) 4055 return; 4056 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4057 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4058 } 4059 4060 static void 4061 _task_fn_iov(void *context) 4062 { 4063 if_ctx_t ctx = context; 4064 4065 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4066 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4067 return; 4068 4069 CTX_LOCK(ctx); 4070 IFDI_VFLR_HANDLE(ctx); 4071 CTX_UNLOCK(ctx); 4072 } 4073 4074 static int 4075 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4076 { 4077 int err; 4078 if_int_delay_info_t info; 4079 if_ctx_t ctx; 4080 4081 info = (if_int_delay_info_t)arg1; 4082 ctx = info->iidi_ctx; 4083 info->iidi_req = req; 4084 info->iidi_oidp = oidp; 4085 CTX_LOCK(ctx); 4086 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4087 CTX_UNLOCK(ctx); 4088 return (err); 4089 } 4090 4091 /********************************************************************* 4092 * 4093 * IFNET FUNCTIONS 4094 * 4095 **********************************************************************/ 4096 4097 static void 4098 iflib_if_init_locked(if_ctx_t ctx) 4099 { 4100 iflib_stop(ctx); 4101 iflib_init_locked(ctx); 4102 } 4103 4104 static void 4105 iflib_if_init(void *arg) 4106 { 4107 if_ctx_t ctx = arg; 4108 4109 CTX_LOCK(ctx); 4110 iflib_if_init_locked(ctx); 4111 CTX_UNLOCK(ctx); 4112 } 4113 4114 static int 4115 iflib_if_transmit(if_t ifp, struct mbuf *m) 4116 { 4117 if_ctx_t ctx = if_getsoftc(ifp); 4118 4119 iflib_txq_t txq; 4120 int err, qidx; 4121 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4122 4123 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4124 DBG_COUNTER_INC(tx_frees); 4125 m_freem(m); 4126 return (ENETDOWN); 4127 } 4128 4129 MPASS(m->m_nextpkt == NULL); 4130 /* ALTQ-enabled interfaces always use queue 0. */ 4131 qidx = 0; 4132 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 4133 qidx = QIDX(ctx, m); 4134 /* 4135 * XXX calculate buf_ring based on flowid (divvy up bits?) 4136 */ 4137 txq = &ctx->ifc_txqs[qidx]; 4138 4139 #ifdef DRIVER_BACKPRESSURE 4140 if (txq->ift_closed) { 4141 while (m != NULL) { 4142 next = m->m_nextpkt; 4143 m->m_nextpkt = NULL; 4144 m_freem(m); 4145 DBG_COUNTER_INC(tx_frees); 4146 m = next; 4147 } 4148 return (ENOBUFS); 4149 } 4150 #endif 4151 #ifdef notyet 4152 qidx = count = 0; 4153 mp = marr; 4154 next = m; 4155 do { 4156 count++; 4157 next = next->m_nextpkt; 4158 } while (next != NULL); 4159 4160 if (count > nitems(marr)) 4161 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4162 /* XXX check nextpkt */ 4163 m_freem(m); 4164 /* XXX simplify for now */ 4165 DBG_COUNTER_INC(tx_frees); 4166 return (ENOBUFS); 4167 } 4168 for (next = m, i = 0; next != NULL; i++) { 4169 mp[i] = next; 4170 next = next->m_nextpkt; 4171 mp[i]->m_nextpkt = NULL; 4172 } 4173 #endif 4174 DBG_COUNTER_INC(tx_seen); 4175 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4176 4177 if (abdicate) 4178 GROUPTASK_ENQUEUE(&txq->ift_task); 4179 if (err) { 4180 if (!abdicate) 4181 GROUPTASK_ENQUEUE(&txq->ift_task); 4182 /* support forthcoming later */ 4183 #ifdef DRIVER_BACKPRESSURE 4184 txq->ift_closed = TRUE; 4185 #endif 4186 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4187 m_freem(m); 4188 DBG_COUNTER_INC(tx_frees); 4189 } 4190 4191 return (err); 4192 } 4193 4194 #ifdef ALTQ 4195 /* 4196 * The overall approach to integrating iflib with ALTQ is to continue to use 4197 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4198 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4199 * is redundant/unnecessary, but doing so minimizes the amount of 4200 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4201 * redundantly queueing to an intermediate mp_ring is swamped by the 4202 * performance limitations inherent in using ALTQ. 4203 * 4204 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4205 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4206 * given interface. If ALTQ is enabled for an interface, then all 4207 * transmitted packets for that interface will be submitted to the ALTQ 4208 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4209 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4210 * update stats that the iflib machinery handles, and which is sensitve to 4211 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4212 * will be installed as the start routine for use by ALTQ facilities that 4213 * need to trigger queue drains on a scheduled basis. 4214 * 4215 */ 4216 static void 4217 iflib_altq_if_start(if_t ifp) 4218 { 4219 struct ifaltq *ifq = &ifp->if_snd; 4220 struct mbuf *m; 4221 4222 IFQ_LOCK(ifq); 4223 IFQ_DEQUEUE_NOLOCK(ifq, m); 4224 while (m != NULL) { 4225 iflib_if_transmit(ifp, m); 4226 IFQ_DEQUEUE_NOLOCK(ifq, m); 4227 } 4228 IFQ_UNLOCK(ifq); 4229 } 4230 4231 static int 4232 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4233 { 4234 int err; 4235 4236 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4237 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4238 if (err == 0) 4239 iflib_altq_if_start(ifp); 4240 } else 4241 err = iflib_if_transmit(ifp, m); 4242 4243 return (err); 4244 } 4245 #endif /* ALTQ */ 4246 4247 static void 4248 iflib_if_qflush(if_t ifp) 4249 { 4250 if_ctx_t ctx = if_getsoftc(ifp); 4251 iflib_txq_t txq = ctx->ifc_txqs; 4252 int i; 4253 4254 STATE_LOCK(ctx); 4255 ctx->ifc_flags |= IFC_QFLUSH; 4256 STATE_UNLOCK(ctx); 4257 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4258 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4259 iflib_txq_check_drain(txq, 0); 4260 STATE_LOCK(ctx); 4261 ctx->ifc_flags &= ~IFC_QFLUSH; 4262 STATE_UNLOCK(ctx); 4263 4264 /* 4265 * When ALTQ is enabled, this will also take care of purging the 4266 * ALTQ queue(s). 4267 */ 4268 if_qflush(ifp); 4269 } 4270 4271 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4272 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4273 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4274 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4275 4276 static int 4277 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4278 { 4279 if_ctx_t ctx = if_getsoftc(ifp); 4280 struct ifreq *ifr = (struct ifreq *)data; 4281 #if defined(INET) || defined(INET6) 4282 struct ifaddr *ifa = (struct ifaddr *)data; 4283 #endif 4284 bool avoid_reset = false; 4285 int err = 0, reinit = 0, bits; 4286 4287 switch (command) { 4288 case SIOCSIFADDR: 4289 #ifdef INET 4290 if (ifa->ifa_addr->sa_family == AF_INET) 4291 avoid_reset = true; 4292 #endif 4293 #ifdef INET6 4294 if (ifa->ifa_addr->sa_family == AF_INET6) 4295 avoid_reset = true; 4296 #endif 4297 /* 4298 ** Calling init results in link renegotiation, 4299 ** so we avoid doing it when possible. 4300 */ 4301 if (avoid_reset) { 4302 if_setflagbits(ifp, IFF_UP,0); 4303 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4304 reinit = 1; 4305 #ifdef INET 4306 if (!(if_getflags(ifp) & IFF_NOARP)) 4307 arp_ifinit(ifp, ifa); 4308 #endif 4309 } else 4310 err = ether_ioctl(ifp, command, data); 4311 break; 4312 case SIOCSIFMTU: 4313 CTX_LOCK(ctx); 4314 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4315 CTX_UNLOCK(ctx); 4316 break; 4317 } 4318 bits = if_getdrvflags(ifp); 4319 /* stop the driver and free any clusters before proceeding */ 4320 iflib_stop(ctx); 4321 4322 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4323 STATE_LOCK(ctx); 4324 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4325 ctx->ifc_flags |= IFC_MULTISEG; 4326 else 4327 ctx->ifc_flags &= ~IFC_MULTISEG; 4328 STATE_UNLOCK(ctx); 4329 err = if_setmtu(ifp, ifr->ifr_mtu); 4330 } 4331 iflib_init_locked(ctx); 4332 STATE_LOCK(ctx); 4333 if_setdrvflags(ifp, bits); 4334 STATE_UNLOCK(ctx); 4335 CTX_UNLOCK(ctx); 4336 break; 4337 case SIOCSIFFLAGS: 4338 CTX_LOCK(ctx); 4339 if (if_getflags(ifp) & IFF_UP) { 4340 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4341 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4342 (IFF_PROMISC | IFF_ALLMULTI)) { 4343 CTX_UNLOCK(ctx); 4344 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4345 CTX_LOCK(ctx); 4346 } 4347 } else 4348 reinit = 1; 4349 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4350 iflib_stop(ctx); 4351 } 4352 ctx->ifc_if_flags = if_getflags(ifp); 4353 CTX_UNLOCK(ctx); 4354 break; 4355 case SIOCADDMULTI: 4356 case SIOCDELMULTI: 4357 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4358 CTX_LOCK(ctx); 4359 IFDI_INTR_DISABLE(ctx); 4360 IFDI_MULTI_SET(ctx); 4361 IFDI_INTR_ENABLE(ctx); 4362 CTX_UNLOCK(ctx); 4363 } 4364 break; 4365 case SIOCSIFMEDIA: 4366 CTX_LOCK(ctx); 4367 IFDI_MEDIA_SET(ctx); 4368 CTX_UNLOCK(ctx); 4369 /* FALLTHROUGH */ 4370 case SIOCGIFMEDIA: 4371 case SIOCGIFXMEDIA: 4372 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4373 break; 4374 case SIOCGI2C: 4375 { 4376 struct ifi2creq i2c; 4377 4378 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4379 if (err != 0) 4380 break; 4381 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4382 err = EINVAL; 4383 break; 4384 } 4385 if (i2c.len > sizeof(i2c.data)) { 4386 err = EINVAL; 4387 break; 4388 } 4389 4390 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4391 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4392 sizeof(i2c)); 4393 break; 4394 } 4395 case SIOCSIFCAP: 4396 { 4397 int mask, setmask, oldmask; 4398 4399 oldmask = if_getcapenable(ifp); 4400 mask = ifr->ifr_reqcap ^ oldmask; 4401 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4402 setmask = 0; 4403 #ifdef TCP_OFFLOAD 4404 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4405 #endif 4406 setmask |= (mask & IFCAP_FLAGS); 4407 setmask |= (mask & IFCAP_WOL); 4408 4409 /* 4410 * If any RX csum has changed, change all the ones that 4411 * are supported by the driver. 4412 */ 4413 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4414 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4415 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4416 } 4417 4418 /* 4419 * want to ensure that traffic has stopped before we change any of the flags 4420 */ 4421 if (setmask) { 4422 CTX_LOCK(ctx); 4423 bits = if_getdrvflags(ifp); 4424 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4425 iflib_stop(ctx); 4426 STATE_LOCK(ctx); 4427 if_togglecapenable(ifp, setmask); 4428 STATE_UNLOCK(ctx); 4429 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4430 iflib_init_locked(ctx); 4431 STATE_LOCK(ctx); 4432 if_setdrvflags(ifp, bits); 4433 STATE_UNLOCK(ctx); 4434 CTX_UNLOCK(ctx); 4435 } 4436 if_vlancap(ifp); 4437 break; 4438 } 4439 case SIOCGPRIVATE_0: 4440 case SIOCSDRVSPEC: 4441 case SIOCGDRVSPEC: 4442 CTX_LOCK(ctx); 4443 err = IFDI_PRIV_IOCTL(ctx, command, data); 4444 CTX_UNLOCK(ctx); 4445 break; 4446 default: 4447 err = ether_ioctl(ifp, command, data); 4448 break; 4449 } 4450 if (reinit) 4451 iflib_if_init(ctx); 4452 return (err); 4453 } 4454 4455 static uint64_t 4456 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4457 { 4458 if_ctx_t ctx = if_getsoftc(ifp); 4459 4460 return (IFDI_GET_COUNTER(ctx, cnt)); 4461 } 4462 4463 /********************************************************************* 4464 * 4465 * OTHER FUNCTIONS EXPORTED TO THE STACK 4466 * 4467 **********************************************************************/ 4468 4469 static void 4470 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4471 { 4472 if_ctx_t ctx = if_getsoftc(ifp); 4473 4474 if ((void *)ctx != arg) 4475 return; 4476 4477 if ((vtag == 0) || (vtag > 4095)) 4478 return; 4479 4480 if (iflib_in_detach(ctx)) 4481 return; 4482 4483 CTX_LOCK(ctx); 4484 /* Driver may need all untagged packets to be flushed */ 4485 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4486 iflib_stop(ctx); 4487 IFDI_VLAN_REGISTER(ctx, vtag); 4488 /* Re-init to load the changes, if required */ 4489 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4490 iflib_init_locked(ctx); 4491 CTX_UNLOCK(ctx); 4492 } 4493 4494 static void 4495 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4496 { 4497 if_ctx_t ctx = if_getsoftc(ifp); 4498 4499 if ((void *)ctx != arg) 4500 return; 4501 4502 if ((vtag == 0) || (vtag > 4095)) 4503 return; 4504 4505 CTX_LOCK(ctx); 4506 /* Driver may need all tagged packets to be flushed */ 4507 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4508 iflib_stop(ctx); 4509 IFDI_VLAN_UNREGISTER(ctx, vtag); 4510 /* Re-init to load the changes, if required */ 4511 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4512 iflib_init_locked(ctx); 4513 CTX_UNLOCK(ctx); 4514 } 4515 4516 static void 4517 iflib_led_func(void *arg, int onoff) 4518 { 4519 if_ctx_t ctx = arg; 4520 4521 CTX_LOCK(ctx); 4522 IFDI_LED_FUNC(ctx, onoff); 4523 CTX_UNLOCK(ctx); 4524 } 4525 4526 /********************************************************************* 4527 * 4528 * BUS FUNCTION DEFINITIONS 4529 * 4530 **********************************************************************/ 4531 4532 int 4533 iflib_device_probe(device_t dev) 4534 { 4535 const pci_vendor_info_t *ent; 4536 if_shared_ctx_t sctx; 4537 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4538 uint16_t pci_vendor_id; 4539 4540 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4541 return (ENOTSUP); 4542 4543 pci_vendor_id = pci_get_vendor(dev); 4544 pci_device_id = pci_get_device(dev); 4545 pci_subvendor_id = pci_get_subvendor(dev); 4546 pci_subdevice_id = pci_get_subdevice(dev); 4547 pci_rev_id = pci_get_revid(dev); 4548 if (sctx->isc_parse_devinfo != NULL) 4549 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4550 4551 ent = sctx->isc_vendor_info; 4552 while (ent->pvi_vendor_id != 0) { 4553 if (pci_vendor_id != ent->pvi_vendor_id) { 4554 ent++; 4555 continue; 4556 } 4557 if ((pci_device_id == ent->pvi_device_id) && 4558 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4559 (ent->pvi_subvendor_id == 0)) && 4560 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4561 (ent->pvi_subdevice_id == 0)) && 4562 ((pci_rev_id == ent->pvi_rev_id) || 4563 (ent->pvi_rev_id == 0))) { 4564 device_set_desc_copy(dev, ent->pvi_name); 4565 /* this needs to be changed to zero if the bus probing code 4566 * ever stops re-probing on best match because the sctx 4567 * may have its values over written by register calls 4568 * in subsequent probes 4569 */ 4570 return (BUS_PROBE_DEFAULT); 4571 } 4572 ent++; 4573 } 4574 return (ENXIO); 4575 } 4576 4577 int 4578 iflib_device_probe_vendor(device_t dev) 4579 { 4580 int probe; 4581 4582 probe = iflib_device_probe(dev); 4583 if (probe == BUS_PROBE_DEFAULT) 4584 return (BUS_PROBE_VENDOR); 4585 else 4586 return (probe); 4587 } 4588 4589 static void 4590 iflib_reset_qvalues(if_ctx_t ctx) 4591 { 4592 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4593 if_shared_ctx_t sctx = ctx->ifc_sctx; 4594 device_t dev = ctx->ifc_dev; 4595 int i; 4596 4597 if (ctx->ifc_sysctl_ntxqs != 0) 4598 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4599 if (ctx->ifc_sysctl_nrxqs != 0) 4600 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4601 4602 for (i = 0; i < sctx->isc_ntxqs; i++) { 4603 if (ctx->ifc_sysctl_ntxds[i] != 0) 4604 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4605 else 4606 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4607 } 4608 4609 for (i = 0; i < sctx->isc_nrxqs; i++) { 4610 if (ctx->ifc_sysctl_nrxds[i] != 0) 4611 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4612 else 4613 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4614 } 4615 4616 for (i = 0; i < sctx->isc_nrxqs; i++) { 4617 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4618 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4619 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4620 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4621 } 4622 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4623 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4624 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4625 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4626 } 4627 if (!powerof2(scctx->isc_nrxd[i])) { 4628 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4629 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4630 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4631 } 4632 } 4633 4634 for (i = 0; i < sctx->isc_ntxqs; i++) { 4635 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4636 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4637 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4638 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4639 } 4640 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4641 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4642 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4643 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4644 } 4645 if (!powerof2(scctx->isc_ntxd[i])) { 4646 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4647 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4648 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4649 } 4650 } 4651 } 4652 4653 static void 4654 iflib_add_pfil(if_ctx_t ctx) 4655 { 4656 struct pfil_head *pfil; 4657 struct pfil_head_args pa; 4658 iflib_rxq_t rxq; 4659 int i; 4660 4661 pa.pa_version = PFIL_VERSION; 4662 pa.pa_flags = PFIL_IN; 4663 pa.pa_type = PFIL_TYPE_ETHERNET; 4664 pa.pa_headname = ctx->ifc_ifp->if_xname; 4665 pfil = pfil_head_register(&pa); 4666 4667 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4668 rxq->pfil = pfil; 4669 } 4670 } 4671 4672 static void 4673 iflib_rem_pfil(if_ctx_t ctx) 4674 { 4675 struct pfil_head *pfil; 4676 iflib_rxq_t rxq; 4677 int i; 4678 4679 rxq = ctx->ifc_rxqs; 4680 pfil = rxq->pfil; 4681 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4682 rxq->pfil = NULL; 4683 } 4684 pfil_head_unregister(pfil); 4685 } 4686 4687 4688 /* 4689 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4690 * cpuid and wrapping as necessary. 4691 */ 4692 static unsigned int 4693 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4694 { 4695 unsigned int first_valid; 4696 unsigned int last_valid; 4697 4698 /* cpuid should always be in the valid set */ 4699 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4700 4701 /* valid set should never be empty */ 4702 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4703 4704 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4705 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4706 n = n % CPU_COUNT(&ctx->ifc_cpus); 4707 while (n > 0) { 4708 do { 4709 cpuid++; 4710 if (cpuid > last_valid) 4711 cpuid = first_valid; 4712 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4713 n--; 4714 } 4715 4716 return (cpuid); 4717 } 4718 4719 #if defined(SMP) && defined(SCHED_ULE) 4720 extern struct cpu_group *cpu_top; /* CPU topology */ 4721 4722 static int 4723 find_child_with_core(int cpu, struct cpu_group *grp) 4724 { 4725 int i; 4726 4727 if (grp->cg_children == 0) 4728 return -1; 4729 4730 MPASS(grp->cg_child); 4731 for (i = 0; i < grp->cg_children; i++) { 4732 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 4733 return i; 4734 } 4735 4736 return -1; 4737 } 4738 4739 4740 /* 4741 * Find an L2 neighbor of the given CPU or return -1 if none found. This 4742 * does not distinguish among multiple L2 neighbors if the given CPU has 4743 * more than one (it will always return the same result in that case). 4744 */ 4745 static int 4746 find_l2_neighbor(int cpu) 4747 { 4748 struct cpu_group *grp; 4749 int i; 4750 4751 grp = cpu_top; 4752 if (grp == NULL) 4753 return -1; 4754 4755 /* 4756 * Find the smallest CPU group that contains the given core. 4757 */ 4758 i = 0; 4759 while ((i = find_child_with_core(cpu, grp)) != -1) { 4760 /* 4761 * If the smallest group containing the given CPU has less 4762 * than two members, we conclude the given CPU has no 4763 * L2 neighbor. 4764 */ 4765 if (grp->cg_child[i].cg_count <= 1) 4766 return (-1); 4767 grp = &grp->cg_child[i]; 4768 } 4769 4770 /* Must share L2. */ 4771 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 4772 return -1; 4773 4774 /* 4775 * Select the first member of the set that isn't the reference 4776 * CPU, which at this point is guaranteed to exist. 4777 */ 4778 for (i = 0; i < CPU_SETSIZE; i++) { 4779 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu) 4780 return (i); 4781 } 4782 4783 /* Should never be reached */ 4784 return (-1); 4785 } 4786 4787 #else 4788 static int 4789 find_l2_neighbor(int cpu) 4790 { 4791 4792 return (-1); 4793 } 4794 #endif 4795 4796 /* 4797 * CPU mapping behaviors 4798 * --------------------- 4799 * 'separate txrx' refers to the separate_txrx sysctl 4800 * 'use logical' refers to the use_logical_cores sysctl 4801 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4802 * 4803 * separate use INTR 4804 * txrx logical CPUS result 4805 * ---------- --------- ------ ------------------------------------------------ 4806 * - - X RX and TX queues mapped to consecutive physical 4807 * cores with RX/TX pairs on same core and excess 4808 * of either following 4809 * - X X RX and TX queues mapped to consecutive cores 4810 * of any type with RX/TX pairs on same core and 4811 * excess of either following 4812 * X - X RX and TX queues mapped to consecutive physical 4813 * cores; all RX then all TX 4814 * X X X RX queues mapped to consecutive physical cores 4815 * first, then TX queues mapped to L2 neighbor of 4816 * the corresponding RX queue if one exists, 4817 * otherwise to consecutive physical cores 4818 * - n/a - RX and TX queues mapped to consecutive cores of 4819 * any type with RX/TX pairs on same core and excess 4820 * of either following 4821 * X n/a - RX and TX queues mapped to consecutive cores of 4822 * any type; all RX then all TX 4823 */ 4824 static unsigned int 4825 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 4826 bool is_tx) 4827 { 4828 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4829 unsigned int core_index; 4830 4831 if (ctx->ifc_sysctl_separate_txrx) { 4832 /* 4833 * When using separate CPUs for TX and RX, the assignment 4834 * will always be of a consecutive CPU out of the set of 4835 * context CPUs, except for the specific case where the 4836 * context CPUs are phsyical cores, the use of logical cores 4837 * has been enabled, the assignment is for TX, the TX qid 4838 * corresponds to an RX qid, and the CPU assigned to the 4839 * corresponding RX queue has an L2 neighbor. 4840 */ 4841 if (ctx->ifc_sysctl_use_logical_cores && 4842 ctx->ifc_cpus_are_physical_cores && 4843 is_tx && qid < scctx->isc_nrxqsets) { 4844 int l2_neighbor; 4845 unsigned int rx_cpuid; 4846 4847 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 4848 l2_neighbor = find_l2_neighbor(rx_cpuid); 4849 if (l2_neighbor != -1) { 4850 return (l2_neighbor); 4851 } 4852 /* 4853 * ... else fall through to the normal 4854 * consecutive-after-RX assignment scheme. 4855 * 4856 * Note that we are assuming that all RX queue CPUs 4857 * have an L2 neighbor, or all do not. If a mixed 4858 * scenario is possible, we will have to keep track 4859 * separately of how many queues prior to this one 4860 * were not able to be assigned to an L2 neighbor. 4861 */ 4862 } 4863 if (is_tx) 4864 core_index = scctx->isc_nrxqsets + qid; 4865 else 4866 core_index = qid; 4867 } else { 4868 core_index = qid; 4869 } 4870 4871 return (cpuid_advance(ctx, base_cpuid, core_index)); 4872 } 4873 4874 static uint16_t 4875 get_ctx_core_offset(if_ctx_t ctx) 4876 { 4877 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4878 struct cpu_offset *op; 4879 cpuset_t assigned_cpus; 4880 unsigned int cores_consumed; 4881 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 4882 unsigned int first_valid; 4883 unsigned int last_valid; 4884 unsigned int i; 4885 4886 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4887 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4888 4889 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 4890 /* 4891 * Align the user-chosen base CPU ID to the next valid CPU 4892 * for this device. If the chosen base CPU ID is smaller 4893 * than the first valid CPU or larger than the last valid 4894 * CPU, we assume the user does not know what the valid 4895 * range is for this device and is thinking in terms of a 4896 * zero-based reference frame, and so we shift the given 4897 * value into the valid range (and wrap accordingly) so the 4898 * intent is translated to the proper frame of reference. 4899 * If the base CPU ID is within the valid first/last, but 4900 * does not correspond to a valid CPU, it is advanced to the 4901 * next valid CPU (wrapping if necessary). 4902 */ 4903 if (base_cpuid < first_valid || base_cpuid > last_valid) { 4904 /* shift from zero-based to first_valid-based */ 4905 base_cpuid += first_valid; 4906 /* wrap to range [first_valid, last_valid] */ 4907 base_cpuid = (base_cpuid - first_valid) % 4908 (last_valid - first_valid + 1); 4909 } 4910 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 4911 /* 4912 * base_cpuid is in [first_valid, last_valid], but 4913 * not a member of the valid set. In this case, 4914 * there will always be a member of the valid set 4915 * with a CPU ID that is greater than base_cpuid, 4916 * and we simply advance to it. 4917 */ 4918 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 4919 base_cpuid++; 4920 } 4921 return (base_cpuid); 4922 } 4923 4924 /* 4925 * Determine how many cores will be consumed by performing the CPU 4926 * assignments and counting how many of the assigned CPUs correspond 4927 * to CPUs in the set of context CPUs. This is done using the CPU 4928 * ID first_valid as the base CPU ID, as the base CPU must be within 4929 * the set of context CPUs. 4930 * 4931 * Note not all assigned CPUs will be in the set of context CPUs 4932 * when separate CPUs are being allocated to TX and RX queues, 4933 * assignment to logical cores has been enabled, the set of context 4934 * CPUs contains only physical CPUs, and TX queues are mapped to L2 4935 * neighbors of CPUs that RX queues have been mapped to - in this 4936 * case we do only want to count how many CPUs in the set of context 4937 * CPUs have been consumed, as that determines the next CPU in that 4938 * set to start allocating at for the next device for which 4939 * core_offset is not set. 4940 */ 4941 CPU_ZERO(&assigned_cpus); 4942 for (i = 0; i < scctx->isc_ntxqsets; i++) 4943 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 4944 &assigned_cpus); 4945 for (i = 0; i < scctx->isc_nrxqsets; i++) 4946 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 4947 &assigned_cpus); 4948 CPU_AND(&assigned_cpus, &ctx->ifc_cpus); 4949 cores_consumed = CPU_COUNT(&assigned_cpus); 4950 4951 mtx_lock(&cpu_offset_mtx); 4952 SLIST_FOREACH(op, &cpu_offsets, entries) { 4953 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4954 base_cpuid = op->next_cpuid; 4955 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 4956 cores_consumed); 4957 MPASS(op->refcount < UINT_MAX); 4958 op->refcount++; 4959 break; 4960 } 4961 } 4962 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 4963 base_cpuid = first_valid; 4964 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4965 M_NOWAIT | M_ZERO); 4966 if (op == NULL) { 4967 device_printf(ctx->ifc_dev, 4968 "allocation for cpu offset failed.\n"); 4969 } else { 4970 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 4971 cores_consumed); 4972 op->refcount = 1; 4973 CPU_COPY(&ctx->ifc_cpus, &op->set); 4974 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4975 } 4976 } 4977 mtx_unlock(&cpu_offset_mtx); 4978 4979 return (base_cpuid); 4980 } 4981 4982 static void 4983 unref_ctx_core_offset(if_ctx_t ctx) 4984 { 4985 struct cpu_offset *op, *top; 4986 4987 mtx_lock(&cpu_offset_mtx); 4988 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4989 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4990 MPASS(op->refcount > 0); 4991 op->refcount--; 4992 if (op->refcount == 0) { 4993 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4994 free(op, M_IFLIB); 4995 } 4996 break; 4997 } 4998 } 4999 mtx_unlock(&cpu_offset_mtx); 5000 } 5001 5002 int 5003 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5004 { 5005 if_ctx_t ctx; 5006 if_t ifp; 5007 if_softc_ctx_t scctx; 5008 kobjop_desc_t kobj_desc; 5009 kobj_method_t *kobj_method; 5010 int err, msix, rid; 5011 int num_txd, num_rxd; 5012 5013 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 5014 5015 if (sc == NULL) { 5016 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5017 device_set_softc(dev, ctx); 5018 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5019 } 5020 5021 ctx->ifc_sctx = sctx; 5022 ctx->ifc_dev = dev; 5023 ctx->ifc_softc = sc; 5024 5025 if ((err = iflib_register(ctx)) != 0) { 5026 device_printf(dev, "iflib_register failed %d\n", err); 5027 goto fail_ctx_free; 5028 } 5029 iflib_add_device_sysctl_pre(ctx); 5030 5031 scctx = &ctx->ifc_softc_ctx; 5032 ifp = ctx->ifc_ifp; 5033 5034 iflib_reset_qvalues(ctx); 5035 CTX_LOCK(ctx); 5036 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5037 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5038 goto fail_unlock; 5039 } 5040 _iflib_pre_assert(scctx); 5041 ctx->ifc_txrx = *scctx->isc_txrx; 5042 5043 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5044 5045 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5046 ctx->ifc_mediap = scctx->isc_media; 5047 5048 #ifdef INVARIANTS 5049 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5050 MPASS(scctx->isc_tx_csum_flags); 5051 #endif 5052 5053 if_setcapabilities(ifp, 5054 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5055 if_setcapenable(ifp, 5056 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5057 5058 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5059 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5060 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5061 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5062 5063 num_txd = iflib_num_tx_descs(ctx); 5064 num_rxd = iflib_num_rx_descs(ctx); 5065 5066 /* XXX change for per-queue sizes */ 5067 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5068 num_txd, num_rxd); 5069 5070 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5071 scctx->isc_tx_nsegments = max(1, num_txd / 5072 MAX_SINGLE_PACKET_FRACTION); 5073 if (scctx->isc_tx_tso_segments_max > num_txd / 5074 MAX_SINGLE_PACKET_FRACTION) 5075 scctx->isc_tx_tso_segments_max = max(1, 5076 num_txd / MAX_SINGLE_PACKET_FRACTION); 5077 5078 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5079 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5080 /* 5081 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5082 * but some MACs do. 5083 */ 5084 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5085 IP_MAXPACKET)); 5086 /* 5087 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5088 * into account. In the worst case, each of these calls will 5089 * add another mbuf and, thus, the requirement for another DMA 5090 * segment. So for best performance, it doesn't make sense to 5091 * advertize a maximum of TSO segments that typically will 5092 * require defragmentation in iflib_encap(). 5093 */ 5094 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5095 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5096 } 5097 if (scctx->isc_rss_table_size == 0) 5098 scctx->isc_rss_table_size = 64; 5099 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5100 5101 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5102 /* XXX format name */ 5103 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5104 NULL, NULL, "admin"); 5105 5106 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5107 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5108 device_printf(dev, "Unable to fetch CPU list\n"); 5109 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5110 ctx->ifc_cpus_are_physical_cores = false; 5111 } else 5112 ctx->ifc_cpus_are_physical_cores = true; 5113 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5114 5115 /* 5116 ** Now set up MSI or MSI-X, should return us the number of supported 5117 ** vectors (will be 1 for a legacy interrupt and MSI). 5118 */ 5119 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5120 msix = scctx->isc_vectors; 5121 } else if (scctx->isc_msix_bar != 0) 5122 /* 5123 * The simple fact that isc_msix_bar is not 0 does not mean we 5124 * we have a good value there that is known to work. 5125 */ 5126 msix = iflib_msix_init(ctx); 5127 else { 5128 scctx->isc_vectors = 1; 5129 scctx->isc_ntxqsets = 1; 5130 scctx->isc_nrxqsets = 1; 5131 scctx->isc_intr = IFLIB_INTR_LEGACY; 5132 msix = 0; 5133 } 5134 /* Get memory for the station queues */ 5135 if ((err = iflib_queues_alloc(ctx))) { 5136 device_printf(dev, "Unable to allocate queue memory\n"); 5137 goto fail_intr_free; 5138 } 5139 5140 if ((err = iflib_qset_structures_setup(ctx))) 5141 goto fail_queues; 5142 5143 /* 5144 * Now that we know how many queues there are, get the core offset. 5145 */ 5146 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5147 5148 if (msix > 1) { 5149 /* 5150 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5151 * aren't the default NULL implementation. 5152 */ 5153 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5154 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5155 kobj_desc); 5156 if (kobj_method == &kobj_desc->deflt) { 5157 device_printf(dev, 5158 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5159 err = EOPNOTSUPP; 5160 goto fail_queues; 5161 } 5162 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5163 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5164 kobj_desc); 5165 if (kobj_method == &kobj_desc->deflt) { 5166 device_printf(dev, 5167 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5168 err = EOPNOTSUPP; 5169 goto fail_queues; 5170 } 5171 5172 /* 5173 * Assign the MSI-X vectors. 5174 * Note that the default NULL ifdi_msix_intr_assign method will 5175 * fail here, too. 5176 */ 5177 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5178 if (err != 0) { 5179 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5180 err); 5181 goto fail_queues; 5182 } 5183 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5184 rid = 0; 5185 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5186 MPASS(msix == 1); 5187 rid = 1; 5188 } 5189 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5190 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5191 goto fail_queues; 5192 } 5193 } else { 5194 device_printf(dev, 5195 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5196 err = ENODEV; 5197 goto fail_queues; 5198 } 5199 5200 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5201 5202 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5203 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5204 goto fail_detach; 5205 } 5206 5207 /* 5208 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5209 * This must appear after the call to ether_ifattach() because 5210 * ether_ifattach() sets if_hdrlen to the default value. 5211 */ 5212 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5213 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5214 5215 if ((err = iflib_netmap_attach(ctx))) { 5216 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5217 goto fail_detach; 5218 } 5219 *ctxp = ctx; 5220 5221 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5222 5223 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5224 iflib_add_device_sysctl_post(ctx); 5225 iflib_add_pfil(ctx); 5226 ctx->ifc_flags |= IFC_INIT_DONE; 5227 CTX_UNLOCK(ctx); 5228 5229 return (0); 5230 5231 fail_detach: 5232 ether_ifdetach(ctx->ifc_ifp); 5233 fail_queues: 5234 iflib_tqg_detach(ctx); 5235 iflib_tx_structures_free(ctx); 5236 iflib_rx_structures_free(ctx); 5237 IFDI_DETACH(ctx); 5238 IFDI_QUEUES_FREE(ctx); 5239 fail_intr_free: 5240 iflib_free_intr_mem(ctx); 5241 fail_unlock: 5242 CTX_UNLOCK(ctx); 5243 iflib_deregister(ctx); 5244 fail_ctx_free: 5245 device_set_softc(ctx->ifc_dev, NULL); 5246 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5247 free(ctx->ifc_softc, M_IFLIB); 5248 free(ctx, M_IFLIB); 5249 return (err); 5250 } 5251 5252 int 5253 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 5254 struct iflib_cloneattach_ctx *clctx) 5255 { 5256 int num_txd, num_rxd; 5257 int err; 5258 if_ctx_t ctx; 5259 if_t ifp; 5260 if_softc_ctx_t scctx; 5261 int i; 5262 void *sc; 5263 5264 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 5265 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5266 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5267 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 5268 ctx->ifc_flags |= IFC_PSEUDO; 5269 5270 ctx->ifc_sctx = sctx; 5271 ctx->ifc_softc = sc; 5272 ctx->ifc_dev = dev; 5273 5274 if ((err = iflib_register(ctx)) != 0) { 5275 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 5276 goto fail_ctx_free; 5277 } 5278 iflib_add_device_sysctl_pre(ctx); 5279 5280 scctx = &ctx->ifc_softc_ctx; 5281 ifp = ctx->ifc_ifp; 5282 5283 iflib_reset_qvalues(ctx); 5284 CTX_LOCK(ctx); 5285 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5286 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5287 goto fail_unlock; 5288 } 5289 if (sctx->isc_flags & IFLIB_GEN_MAC) 5290 ether_gen_addr(ifp, &ctx->ifc_mac); 5291 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 5292 clctx->cc_params)) != 0) { 5293 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 5294 goto fail_unlock; 5295 } 5296 #ifdef INVARIANTS 5297 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5298 MPASS(scctx->isc_tx_csum_flags); 5299 #endif 5300 5301 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5302 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5303 5304 ifp->if_flags |= IFF_NOGROUP; 5305 if (sctx->isc_flags & IFLIB_PSEUDO) { 5306 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5307 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5308 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 5309 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5310 } else { 5311 if_attach(ctx->ifc_ifp); 5312 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 5313 } 5314 5315 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5316 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5317 goto fail_detach; 5318 } 5319 *ctxp = ctx; 5320 5321 /* 5322 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5323 * This must appear after the call to ether_ifattach() because 5324 * ether_ifattach() sets if_hdrlen to the default value. 5325 */ 5326 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5327 if_setifheaderlen(ifp, 5328 sizeof(struct ether_vlan_header)); 5329 5330 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5331 iflib_add_device_sysctl_post(ctx); 5332 ctx->ifc_flags |= IFC_INIT_DONE; 5333 CTX_UNLOCK(ctx); 5334 return (0); 5335 } 5336 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 5337 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5338 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5339 5340 _iflib_pre_assert(scctx); 5341 ctx->ifc_txrx = *scctx->isc_txrx; 5342 5343 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5344 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5345 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5346 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5347 5348 num_txd = iflib_num_tx_descs(ctx); 5349 num_rxd = iflib_num_rx_descs(ctx); 5350 5351 /* XXX change for per-queue sizes */ 5352 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5353 num_txd, num_rxd); 5354 5355 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5356 scctx->isc_tx_nsegments = max(1, num_txd / 5357 MAX_SINGLE_PACKET_FRACTION); 5358 if (scctx->isc_tx_tso_segments_max > num_txd / 5359 MAX_SINGLE_PACKET_FRACTION) 5360 scctx->isc_tx_tso_segments_max = max(1, 5361 num_txd / MAX_SINGLE_PACKET_FRACTION); 5362 5363 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5364 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5365 /* 5366 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5367 * but some MACs do. 5368 */ 5369 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5370 IP_MAXPACKET)); 5371 /* 5372 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5373 * into account. In the worst case, each of these calls will 5374 * add another mbuf and, thus, the requirement for another DMA 5375 * segment. So for best performance, it doesn't make sense to 5376 * advertize a maximum of TSO segments that typically will 5377 * require defragmentation in iflib_encap(). 5378 */ 5379 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5380 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5381 } 5382 if (scctx->isc_rss_table_size == 0) 5383 scctx->isc_rss_table_size = 64; 5384 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5385 5386 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5387 /* XXX format name */ 5388 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5389 NULL, NULL, "admin"); 5390 5391 /* XXX --- can support > 1 -- but keep it simple for now */ 5392 scctx->isc_intr = IFLIB_INTR_LEGACY; 5393 5394 /* Get memory for the station queues */ 5395 if ((err = iflib_queues_alloc(ctx))) { 5396 device_printf(dev, "Unable to allocate queue memory\n"); 5397 goto fail_iflib_detach; 5398 } 5399 5400 if ((err = iflib_qset_structures_setup(ctx))) { 5401 device_printf(dev, "qset structure setup failed %d\n", err); 5402 goto fail_queues; 5403 } 5404 5405 /* 5406 * XXX What if anything do we want to do about interrupts? 5407 */ 5408 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5409 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5410 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5411 goto fail_detach; 5412 } 5413 5414 /* 5415 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5416 * This must appear after the call to ether_ifattach() because 5417 * ether_ifattach() sets if_hdrlen to the default value. 5418 */ 5419 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5420 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5421 5422 /* XXX handle more than one queue */ 5423 for (i = 0; i < scctx->isc_nrxqsets; i++) 5424 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5425 5426 *ctxp = ctx; 5427 5428 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5429 iflib_add_device_sysctl_post(ctx); 5430 ctx->ifc_flags |= IFC_INIT_DONE; 5431 CTX_UNLOCK(ctx); 5432 5433 return (0); 5434 fail_detach: 5435 ether_ifdetach(ctx->ifc_ifp); 5436 fail_queues: 5437 iflib_tqg_detach(ctx); 5438 iflib_tx_structures_free(ctx); 5439 iflib_rx_structures_free(ctx); 5440 fail_iflib_detach: 5441 IFDI_DETACH(ctx); 5442 IFDI_QUEUES_FREE(ctx); 5443 fail_unlock: 5444 CTX_UNLOCK(ctx); 5445 iflib_deregister(ctx); 5446 fail_ctx_free: 5447 free(ctx->ifc_softc, M_IFLIB); 5448 free(ctx, M_IFLIB); 5449 return (err); 5450 } 5451 5452 int 5453 iflib_pseudo_deregister(if_ctx_t ctx) 5454 { 5455 if_t ifp = ctx->ifc_ifp; 5456 if_shared_ctx_t sctx = ctx->ifc_sctx; 5457 5458 /* Unregister VLAN event handlers early */ 5459 iflib_unregister_vlan_handlers(ctx); 5460 5461 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5462 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5463 bpfdetach(ifp); 5464 if_detach(ifp); 5465 } else { 5466 ether_ifdetach(ifp); 5467 } 5468 5469 iflib_tqg_detach(ctx); 5470 iflib_tx_structures_free(ctx); 5471 iflib_rx_structures_free(ctx); 5472 IFDI_DETACH(ctx); 5473 IFDI_QUEUES_FREE(ctx); 5474 5475 iflib_deregister(ctx); 5476 5477 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5478 free(ctx->ifc_softc, M_IFLIB); 5479 free(ctx, M_IFLIB); 5480 return (0); 5481 } 5482 5483 int 5484 iflib_device_attach(device_t dev) 5485 { 5486 if_ctx_t ctx; 5487 if_shared_ctx_t sctx; 5488 5489 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5490 return (ENOTSUP); 5491 5492 pci_enable_busmaster(dev); 5493 5494 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5495 } 5496 5497 int 5498 iflib_device_deregister(if_ctx_t ctx) 5499 { 5500 if_t ifp = ctx->ifc_ifp; 5501 device_t dev = ctx->ifc_dev; 5502 5503 /* Make sure VLANS are not using driver */ 5504 if (if_vlantrunkinuse(ifp)) { 5505 device_printf(dev, "Vlan in use, detach first\n"); 5506 return (EBUSY); 5507 } 5508 #ifdef PCI_IOV 5509 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5510 device_printf(dev, "SR-IOV in use; detach first.\n"); 5511 return (EBUSY); 5512 } 5513 #endif 5514 5515 STATE_LOCK(ctx); 5516 ctx->ifc_flags |= IFC_IN_DETACH; 5517 STATE_UNLOCK(ctx); 5518 5519 /* Unregister VLAN handlers before calling iflib_stop() */ 5520 iflib_unregister_vlan_handlers(ctx); 5521 5522 iflib_netmap_detach(ifp); 5523 ether_ifdetach(ifp); 5524 5525 CTX_LOCK(ctx); 5526 iflib_stop(ctx); 5527 CTX_UNLOCK(ctx); 5528 5529 iflib_rem_pfil(ctx); 5530 if (ctx->ifc_led_dev != NULL) 5531 led_destroy(ctx->ifc_led_dev); 5532 5533 iflib_tqg_detach(ctx); 5534 iflib_tx_structures_free(ctx); 5535 iflib_rx_structures_free(ctx); 5536 5537 CTX_LOCK(ctx); 5538 IFDI_DETACH(ctx); 5539 IFDI_QUEUES_FREE(ctx); 5540 CTX_UNLOCK(ctx); 5541 5542 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5543 iflib_free_intr_mem(ctx); 5544 5545 bus_generic_detach(dev); 5546 5547 iflib_deregister(ctx); 5548 5549 device_set_softc(ctx->ifc_dev, NULL); 5550 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5551 free(ctx->ifc_softc, M_IFLIB); 5552 unref_ctx_core_offset(ctx); 5553 free(ctx, M_IFLIB); 5554 return (0); 5555 } 5556 5557 static void 5558 iflib_tqg_detach(if_ctx_t ctx) 5559 { 5560 iflib_txq_t txq; 5561 iflib_rxq_t rxq; 5562 int i; 5563 struct taskqgroup *tqg; 5564 5565 /* XXX drain any dependent tasks */ 5566 tqg = qgroup_if_io_tqg; 5567 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5568 callout_drain(&txq->ift_timer); 5569 #ifdef DEV_NETMAP 5570 callout_drain(&txq->ift_netmap_timer); 5571 #endif /* DEV_NETMAP */ 5572 if (txq->ift_task.gt_uniq != NULL) 5573 taskqgroup_detach(tqg, &txq->ift_task); 5574 } 5575 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5576 if (rxq->ifr_task.gt_uniq != NULL) 5577 taskqgroup_detach(tqg, &rxq->ifr_task); 5578 } 5579 tqg = qgroup_if_config_tqg; 5580 if (ctx->ifc_admin_task.gt_uniq != NULL) 5581 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5582 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5583 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5584 } 5585 5586 static void 5587 iflib_free_intr_mem(if_ctx_t ctx) 5588 { 5589 5590 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5591 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5592 } 5593 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5594 pci_release_msi(ctx->ifc_dev); 5595 } 5596 if (ctx->ifc_msix_mem != NULL) { 5597 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5598 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5599 ctx->ifc_msix_mem = NULL; 5600 } 5601 } 5602 5603 int 5604 iflib_device_detach(device_t dev) 5605 { 5606 if_ctx_t ctx = device_get_softc(dev); 5607 5608 return (iflib_device_deregister(ctx)); 5609 } 5610 5611 int 5612 iflib_device_suspend(device_t dev) 5613 { 5614 if_ctx_t ctx = device_get_softc(dev); 5615 5616 CTX_LOCK(ctx); 5617 IFDI_SUSPEND(ctx); 5618 CTX_UNLOCK(ctx); 5619 5620 return bus_generic_suspend(dev); 5621 } 5622 int 5623 iflib_device_shutdown(device_t dev) 5624 { 5625 if_ctx_t ctx = device_get_softc(dev); 5626 5627 CTX_LOCK(ctx); 5628 IFDI_SHUTDOWN(ctx); 5629 CTX_UNLOCK(ctx); 5630 5631 return bus_generic_suspend(dev); 5632 } 5633 5634 int 5635 iflib_device_resume(device_t dev) 5636 { 5637 if_ctx_t ctx = device_get_softc(dev); 5638 iflib_txq_t txq = ctx->ifc_txqs; 5639 5640 CTX_LOCK(ctx); 5641 IFDI_RESUME(ctx); 5642 iflib_if_init_locked(ctx); 5643 CTX_UNLOCK(ctx); 5644 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5645 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5646 5647 return (bus_generic_resume(dev)); 5648 } 5649 5650 int 5651 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5652 { 5653 int error; 5654 if_ctx_t ctx = device_get_softc(dev); 5655 5656 CTX_LOCK(ctx); 5657 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5658 CTX_UNLOCK(ctx); 5659 5660 return (error); 5661 } 5662 5663 void 5664 iflib_device_iov_uninit(device_t dev) 5665 { 5666 if_ctx_t ctx = device_get_softc(dev); 5667 5668 CTX_LOCK(ctx); 5669 IFDI_IOV_UNINIT(ctx); 5670 CTX_UNLOCK(ctx); 5671 } 5672 5673 int 5674 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5675 { 5676 int error; 5677 if_ctx_t ctx = device_get_softc(dev); 5678 5679 CTX_LOCK(ctx); 5680 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5681 CTX_UNLOCK(ctx); 5682 5683 return (error); 5684 } 5685 5686 /********************************************************************* 5687 * 5688 * MODULE FUNCTION DEFINITIONS 5689 * 5690 **********************************************************************/ 5691 5692 /* 5693 * - Start a fast taskqueue thread for each core 5694 * - Start a taskqueue for control operations 5695 */ 5696 static int 5697 iflib_module_init(void) 5698 { 5699 iflib_timer_default = hz / 2; 5700 return (0); 5701 } 5702 5703 static int 5704 iflib_module_event_handler(module_t mod, int what, void *arg) 5705 { 5706 int err; 5707 5708 switch (what) { 5709 case MOD_LOAD: 5710 if ((err = iflib_module_init()) != 0) 5711 return (err); 5712 break; 5713 case MOD_UNLOAD: 5714 return (EBUSY); 5715 default: 5716 return (EOPNOTSUPP); 5717 } 5718 5719 return (0); 5720 } 5721 5722 /********************************************************************* 5723 * 5724 * PUBLIC FUNCTION DEFINITIONS 5725 * ordered as in iflib.h 5726 * 5727 **********************************************************************/ 5728 5729 static void 5730 _iflib_assert(if_shared_ctx_t sctx) 5731 { 5732 int i; 5733 5734 MPASS(sctx->isc_tx_maxsize); 5735 MPASS(sctx->isc_tx_maxsegsize); 5736 5737 MPASS(sctx->isc_rx_maxsize); 5738 MPASS(sctx->isc_rx_nsegments); 5739 MPASS(sctx->isc_rx_maxsegsize); 5740 5741 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5742 for (i = 0; i < sctx->isc_nrxqs; i++) { 5743 MPASS(sctx->isc_nrxd_min[i]); 5744 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5745 MPASS(sctx->isc_nrxd_max[i]); 5746 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5747 MPASS(sctx->isc_nrxd_default[i]); 5748 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5749 } 5750 5751 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5752 for (i = 0; i < sctx->isc_ntxqs; i++) { 5753 MPASS(sctx->isc_ntxd_min[i]); 5754 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5755 MPASS(sctx->isc_ntxd_max[i]); 5756 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5757 MPASS(sctx->isc_ntxd_default[i]); 5758 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5759 } 5760 } 5761 5762 static void 5763 _iflib_pre_assert(if_softc_ctx_t scctx) 5764 { 5765 5766 MPASS(scctx->isc_txrx->ift_txd_encap); 5767 MPASS(scctx->isc_txrx->ift_txd_flush); 5768 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5769 MPASS(scctx->isc_txrx->ift_rxd_available); 5770 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5771 MPASS(scctx->isc_txrx->ift_rxd_refill); 5772 MPASS(scctx->isc_txrx->ift_rxd_flush); 5773 } 5774 5775 static int 5776 iflib_register(if_ctx_t ctx) 5777 { 5778 if_shared_ctx_t sctx = ctx->ifc_sctx; 5779 driver_t *driver = sctx->isc_driver; 5780 device_t dev = ctx->ifc_dev; 5781 if_t ifp; 5782 u_char type; 5783 int iflags; 5784 5785 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5786 _iflib_assert(sctx); 5787 5788 CTX_LOCK_INIT(ctx); 5789 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5790 if (sctx->isc_flags & IFLIB_PSEUDO) { 5791 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5792 type = IFT_ETHER; 5793 else 5794 type = IFT_PPP; 5795 } else 5796 type = IFT_ETHER; 5797 ifp = ctx->ifc_ifp = if_alloc(type); 5798 if (ifp == NULL) { 5799 device_printf(dev, "can not allocate ifnet structure\n"); 5800 return (ENOMEM); 5801 } 5802 5803 /* 5804 * Initialize our context's device specific methods 5805 */ 5806 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5807 kobj_class_compile((kobj_class_t) driver); 5808 5809 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5810 if_setsoftc(ifp, ctx); 5811 if_setdev(ifp, dev); 5812 if_setinitfn(ifp, iflib_if_init); 5813 if_setioctlfn(ifp, iflib_if_ioctl); 5814 #ifdef ALTQ 5815 if_setstartfn(ifp, iflib_altq_if_start); 5816 if_settransmitfn(ifp, iflib_altq_if_transmit); 5817 if_setsendqready(ifp); 5818 #else 5819 if_settransmitfn(ifp, iflib_if_transmit); 5820 #endif 5821 if_setqflushfn(ifp, iflib_if_qflush); 5822 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5823 5824 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5825 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5826 iflags |= IFF_POINTOPOINT; 5827 else 5828 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5829 if_setflags(ifp, iflags); 5830 ctx->ifc_vlan_attach_event = 5831 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5832 EVENTHANDLER_PRI_FIRST); 5833 ctx->ifc_vlan_detach_event = 5834 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5835 EVENTHANDLER_PRI_FIRST); 5836 5837 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5838 ctx->ifc_mediap = &ctx->ifc_media; 5839 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5840 iflib_media_change, iflib_media_status); 5841 } 5842 return (0); 5843 } 5844 5845 static void 5846 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5847 { 5848 /* Unregister VLAN events */ 5849 if (ctx->ifc_vlan_attach_event != NULL) { 5850 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5851 ctx->ifc_vlan_attach_event = NULL; 5852 } 5853 if (ctx->ifc_vlan_detach_event != NULL) { 5854 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5855 ctx->ifc_vlan_detach_event = NULL; 5856 } 5857 5858 } 5859 5860 static void 5861 iflib_deregister(if_ctx_t ctx) 5862 { 5863 if_t ifp = ctx->ifc_ifp; 5864 5865 /* Remove all media */ 5866 ifmedia_removeall(&ctx->ifc_media); 5867 5868 /* Ensure that VLAN event handlers are unregistered */ 5869 iflib_unregister_vlan_handlers(ctx); 5870 5871 /* Release kobject reference */ 5872 kobj_delete((kobj_t) ctx, NULL); 5873 5874 /* Free the ifnet structure */ 5875 if_free(ifp); 5876 5877 STATE_LOCK_DESTROY(ctx); 5878 5879 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5880 CTX_LOCK_DESTROY(ctx); 5881 } 5882 5883 static int 5884 iflib_queues_alloc(if_ctx_t ctx) 5885 { 5886 if_shared_ctx_t sctx = ctx->ifc_sctx; 5887 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5888 device_t dev = ctx->ifc_dev; 5889 int nrxqsets = scctx->isc_nrxqsets; 5890 int ntxqsets = scctx->isc_ntxqsets; 5891 iflib_txq_t txq; 5892 iflib_rxq_t rxq; 5893 iflib_fl_t fl = NULL; 5894 int i, j, cpu, err, txconf, rxconf; 5895 iflib_dma_info_t ifdip; 5896 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5897 uint32_t *txqsizes = scctx->isc_txqsizes; 5898 uint8_t nrxqs = sctx->isc_nrxqs; 5899 uint8_t ntxqs = sctx->isc_ntxqs; 5900 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5901 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5902 caddr_t *vaddrs; 5903 uint64_t *paddrs; 5904 5905 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5906 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5907 KASSERT(nrxqs >= fl_offset + nfree_lists, 5908 ("there must be at least a rxq for each free list")); 5909 5910 /* Allocate the TX ring struct memory */ 5911 if (!(ctx->ifc_txqs = 5912 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5913 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5914 device_printf(dev, "Unable to allocate TX ring memory\n"); 5915 err = ENOMEM; 5916 goto fail; 5917 } 5918 5919 /* Now allocate the RX */ 5920 if (!(ctx->ifc_rxqs = 5921 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5922 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5923 device_printf(dev, "Unable to allocate RX ring memory\n"); 5924 err = ENOMEM; 5925 goto rx_fail; 5926 } 5927 5928 txq = ctx->ifc_txqs; 5929 rxq = ctx->ifc_rxqs; 5930 5931 /* 5932 * XXX handle allocation failure 5933 */ 5934 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5935 /* Set up some basics */ 5936 5937 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5938 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5939 device_printf(dev, 5940 "Unable to allocate TX DMA info memory\n"); 5941 err = ENOMEM; 5942 goto err_tx_desc; 5943 } 5944 txq->ift_ifdi = ifdip; 5945 for (j = 0; j < ntxqs; j++, ifdip++) { 5946 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5947 device_printf(dev, 5948 "Unable to allocate TX descriptors\n"); 5949 err = ENOMEM; 5950 goto err_tx_desc; 5951 } 5952 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5953 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5954 } 5955 txq->ift_ctx = ctx; 5956 txq->ift_id = i; 5957 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5958 txq->ift_br_offset = 1; 5959 } else { 5960 txq->ift_br_offset = 0; 5961 } 5962 5963 if (iflib_txsd_alloc(txq)) { 5964 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5965 err = ENOMEM; 5966 goto err_tx_desc; 5967 } 5968 5969 /* Initialize the TX lock */ 5970 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5971 device_get_nameunit(dev), txq->ift_id); 5972 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5973 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5974 txq->ift_timer.c_cpu = cpu; 5975 #ifdef DEV_NETMAP 5976 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5977 txq->ift_netmap_timer.c_cpu = cpu; 5978 #endif /* DEV_NETMAP */ 5979 5980 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5981 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5982 if (err) { 5983 /* XXX free any allocated rings */ 5984 device_printf(dev, "Unable to allocate buf_ring\n"); 5985 goto err_tx_desc; 5986 } 5987 } 5988 5989 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5990 /* Set up some basics */ 5991 callout_init(&rxq->ifr_watchdog, 1); 5992 5993 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5994 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5995 device_printf(dev, 5996 "Unable to allocate RX DMA info memory\n"); 5997 err = ENOMEM; 5998 goto err_tx_desc; 5999 } 6000 6001 rxq->ifr_ifdi = ifdip; 6002 /* XXX this needs to be changed if #rx queues != #tx queues */ 6003 rxq->ifr_ntxqirq = 1; 6004 rxq->ifr_txqid[0] = i; 6005 for (j = 0; j < nrxqs; j++, ifdip++) { 6006 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 6007 device_printf(dev, 6008 "Unable to allocate RX descriptors\n"); 6009 err = ENOMEM; 6010 goto err_tx_desc; 6011 } 6012 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 6013 } 6014 rxq->ifr_ctx = ctx; 6015 rxq->ifr_id = i; 6016 rxq->ifr_fl_offset = fl_offset; 6017 rxq->ifr_nfl = nfree_lists; 6018 if (!(fl = 6019 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 6020 device_printf(dev, "Unable to allocate free list memory\n"); 6021 err = ENOMEM; 6022 goto err_tx_desc; 6023 } 6024 rxq->ifr_fl = fl; 6025 for (j = 0; j < nfree_lists; j++) { 6026 fl[j].ifl_rxq = rxq; 6027 fl[j].ifl_id = j; 6028 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 6029 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 6030 } 6031 /* Allocate receive buffers for the ring */ 6032 if (iflib_rxsd_alloc(rxq)) { 6033 device_printf(dev, 6034 "Critical Failure setting up receive buffers\n"); 6035 err = ENOMEM; 6036 goto err_rx_desc; 6037 } 6038 6039 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 6040 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 6041 M_WAITOK); 6042 } 6043 6044 /* TXQs */ 6045 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6046 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6047 for (i = 0; i < ntxqsets; i++) { 6048 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 6049 6050 for (j = 0; j < ntxqs; j++, di++) { 6051 vaddrs[i*ntxqs + j] = di->idi_vaddr; 6052 paddrs[i*ntxqs + j] = di->idi_paddr; 6053 } 6054 } 6055 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 6056 device_printf(ctx->ifc_dev, 6057 "Unable to allocate device TX queue\n"); 6058 iflib_tx_structures_free(ctx); 6059 free(vaddrs, M_IFLIB); 6060 free(paddrs, M_IFLIB); 6061 goto err_rx_desc; 6062 } 6063 free(vaddrs, M_IFLIB); 6064 free(paddrs, M_IFLIB); 6065 6066 /* RXQs */ 6067 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6068 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6069 for (i = 0; i < nrxqsets; i++) { 6070 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6071 6072 for (j = 0; j < nrxqs; j++, di++) { 6073 vaddrs[i*nrxqs + j] = di->idi_vaddr; 6074 paddrs[i*nrxqs + j] = di->idi_paddr; 6075 } 6076 } 6077 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6078 device_printf(ctx->ifc_dev, 6079 "Unable to allocate device RX queue\n"); 6080 iflib_tx_structures_free(ctx); 6081 free(vaddrs, M_IFLIB); 6082 free(paddrs, M_IFLIB); 6083 goto err_rx_desc; 6084 } 6085 free(vaddrs, M_IFLIB); 6086 free(paddrs, M_IFLIB); 6087 6088 return (0); 6089 6090 /* XXX handle allocation failure changes */ 6091 err_rx_desc: 6092 err_tx_desc: 6093 rx_fail: 6094 if (ctx->ifc_rxqs != NULL) 6095 free(ctx->ifc_rxqs, M_IFLIB); 6096 ctx->ifc_rxqs = NULL; 6097 if (ctx->ifc_txqs != NULL) 6098 free(ctx->ifc_txqs, M_IFLIB); 6099 ctx->ifc_txqs = NULL; 6100 fail: 6101 return (err); 6102 } 6103 6104 static int 6105 iflib_tx_structures_setup(if_ctx_t ctx) 6106 { 6107 iflib_txq_t txq = ctx->ifc_txqs; 6108 int i; 6109 6110 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6111 iflib_txq_setup(txq); 6112 6113 return (0); 6114 } 6115 6116 static void 6117 iflib_tx_structures_free(if_ctx_t ctx) 6118 { 6119 iflib_txq_t txq = ctx->ifc_txqs; 6120 if_shared_ctx_t sctx = ctx->ifc_sctx; 6121 int i, j; 6122 6123 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6124 for (j = 0; j < sctx->isc_ntxqs; j++) 6125 iflib_dma_free(&txq->ift_ifdi[j]); 6126 iflib_txq_destroy(txq); 6127 } 6128 free(ctx->ifc_txqs, M_IFLIB); 6129 ctx->ifc_txqs = NULL; 6130 } 6131 6132 /********************************************************************* 6133 * 6134 * Initialize all receive rings. 6135 * 6136 **********************************************************************/ 6137 static int 6138 iflib_rx_structures_setup(if_ctx_t ctx) 6139 { 6140 iflib_rxq_t rxq = ctx->ifc_rxqs; 6141 int q; 6142 #if defined(INET6) || defined(INET) 6143 int err, i; 6144 #endif 6145 6146 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6147 #if defined(INET6) || defined(INET) 6148 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6149 TCP_LRO_ENTRIES, min(1024, 6150 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6151 if (err != 0) { 6152 device_printf(ctx->ifc_dev, 6153 "LRO Initialization failed!\n"); 6154 goto fail; 6155 } 6156 #endif 6157 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6158 } 6159 return (0); 6160 #if defined(INET6) || defined(INET) 6161 fail: 6162 /* 6163 * Free LRO resources allocated so far, we will only handle 6164 * the rings that completed, the failing case will have 6165 * cleaned up for itself. 'q' failed, so its the terminus. 6166 */ 6167 rxq = ctx->ifc_rxqs; 6168 for (i = 0; i < q; ++i, rxq++) { 6169 tcp_lro_free(&rxq->ifr_lc); 6170 } 6171 return (err); 6172 #endif 6173 } 6174 6175 /********************************************************************* 6176 * 6177 * Free all receive rings. 6178 * 6179 **********************************************************************/ 6180 static void 6181 iflib_rx_structures_free(if_ctx_t ctx) 6182 { 6183 iflib_rxq_t rxq = ctx->ifc_rxqs; 6184 if_shared_ctx_t sctx = ctx->ifc_sctx; 6185 int i, j; 6186 6187 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6188 for (j = 0; j < sctx->isc_nrxqs; j++) 6189 iflib_dma_free(&rxq->ifr_ifdi[j]); 6190 iflib_rx_sds_free(rxq); 6191 #if defined(INET6) || defined(INET) 6192 tcp_lro_free(&rxq->ifr_lc); 6193 #endif 6194 } 6195 free(ctx->ifc_rxqs, M_IFLIB); 6196 ctx->ifc_rxqs = NULL; 6197 } 6198 6199 static int 6200 iflib_qset_structures_setup(if_ctx_t ctx) 6201 { 6202 int err; 6203 6204 /* 6205 * It is expected that the caller takes care of freeing queues if this 6206 * fails. 6207 */ 6208 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6209 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6210 return (err); 6211 } 6212 6213 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6214 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6215 6216 return (err); 6217 } 6218 6219 int 6220 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6221 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6222 { 6223 6224 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6225 } 6226 6227 /* Just to avoid copy/paste */ 6228 static inline int 6229 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6230 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6231 const char *name) 6232 { 6233 device_t dev; 6234 unsigned int base_cpuid, cpuid; 6235 int err; 6236 6237 dev = ctx->ifc_dev; 6238 base_cpuid = ctx->ifc_sysctl_core_offset; 6239 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6240 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6241 irq ? irq->ii_res : NULL, name); 6242 if (err) { 6243 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6244 return (err); 6245 } 6246 #ifdef notyet 6247 if (cpuid > ctx->ifc_cpuid_highest) 6248 ctx->ifc_cpuid_highest = cpuid; 6249 #endif 6250 return (0); 6251 } 6252 6253 int 6254 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6255 iflib_intr_type_t type, driver_filter_t *filter, 6256 void *filter_arg, int qid, const char *name) 6257 { 6258 device_t dev; 6259 struct grouptask *gtask; 6260 struct taskqgroup *tqg; 6261 iflib_filter_info_t info; 6262 gtask_fn_t *fn; 6263 int tqrid, err; 6264 driver_filter_t *intr_fast; 6265 void *q; 6266 6267 info = &ctx->ifc_filter_info; 6268 tqrid = rid; 6269 6270 switch (type) { 6271 /* XXX merge tx/rx for netmap? */ 6272 case IFLIB_INTR_TX: 6273 q = &ctx->ifc_txqs[qid]; 6274 info = &ctx->ifc_txqs[qid].ift_filter_info; 6275 gtask = &ctx->ifc_txqs[qid].ift_task; 6276 tqg = qgroup_if_io_tqg; 6277 fn = _task_fn_tx; 6278 intr_fast = iflib_fast_intr; 6279 GROUPTASK_INIT(gtask, 0, fn, q); 6280 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6281 break; 6282 case IFLIB_INTR_RX: 6283 q = &ctx->ifc_rxqs[qid]; 6284 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6285 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6286 tqg = qgroup_if_io_tqg; 6287 fn = _task_fn_rx; 6288 intr_fast = iflib_fast_intr; 6289 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6290 break; 6291 case IFLIB_INTR_RXTX: 6292 q = &ctx->ifc_rxqs[qid]; 6293 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6294 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6295 tqg = qgroup_if_io_tqg; 6296 fn = _task_fn_rx; 6297 intr_fast = iflib_fast_intr_rxtx; 6298 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6299 break; 6300 case IFLIB_INTR_ADMIN: 6301 q = ctx; 6302 tqrid = -1; 6303 info = &ctx->ifc_filter_info; 6304 gtask = &ctx->ifc_admin_task; 6305 tqg = qgroup_if_config_tqg; 6306 fn = _task_fn_admin; 6307 intr_fast = iflib_fast_intr_ctx; 6308 break; 6309 default: 6310 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6311 __func__); 6312 return (EINVAL); 6313 } 6314 6315 info->ifi_filter = filter; 6316 info->ifi_filter_arg = filter_arg; 6317 info->ifi_task = gtask; 6318 info->ifi_ctx = q; 6319 6320 dev = ctx->ifc_dev; 6321 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6322 if (err != 0) { 6323 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6324 return (err); 6325 } 6326 if (type == IFLIB_INTR_ADMIN) 6327 return (0); 6328 6329 if (tqrid != -1) { 6330 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6331 name); 6332 if (err) 6333 return (err); 6334 } else { 6335 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6336 } 6337 6338 return (0); 6339 } 6340 6341 void 6342 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6343 { 6344 device_t dev; 6345 struct grouptask *gtask; 6346 struct taskqgroup *tqg; 6347 gtask_fn_t *fn; 6348 void *q; 6349 int err; 6350 6351 switch (type) { 6352 case IFLIB_INTR_TX: 6353 q = &ctx->ifc_txqs[qid]; 6354 gtask = &ctx->ifc_txqs[qid].ift_task; 6355 tqg = qgroup_if_io_tqg; 6356 fn = _task_fn_tx; 6357 GROUPTASK_INIT(gtask, 0, fn, q); 6358 break; 6359 case IFLIB_INTR_RX: 6360 q = &ctx->ifc_rxqs[qid]; 6361 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6362 tqg = qgroup_if_io_tqg; 6363 fn = _task_fn_rx; 6364 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6365 break; 6366 case IFLIB_INTR_IOV: 6367 q = ctx; 6368 gtask = &ctx->ifc_vflr_task; 6369 tqg = qgroup_if_config_tqg; 6370 fn = _task_fn_iov; 6371 GROUPTASK_INIT(gtask, 0, fn, q); 6372 break; 6373 default: 6374 panic("unknown net intr type"); 6375 } 6376 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6377 if (err) { 6378 dev = ctx->ifc_dev; 6379 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6380 name); 6381 } 6382 } 6383 6384 void 6385 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6386 { 6387 6388 if (irq->ii_tag) 6389 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6390 6391 if (irq->ii_res) 6392 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6393 rman_get_rid(irq->ii_res), irq->ii_res); 6394 } 6395 6396 static int 6397 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6398 { 6399 iflib_txq_t txq = ctx->ifc_txqs; 6400 iflib_rxq_t rxq = ctx->ifc_rxqs; 6401 if_irq_t irq = &ctx->ifc_legacy_irq; 6402 iflib_filter_info_t info; 6403 device_t dev; 6404 struct grouptask *gtask; 6405 struct resource *res; 6406 struct taskqgroup *tqg; 6407 void *q; 6408 int err, tqrid; 6409 bool rx_only; 6410 6411 q = &ctx->ifc_rxqs[0]; 6412 info = &rxq[0].ifr_filter_info; 6413 gtask = &rxq[0].ifr_task; 6414 tqg = qgroup_if_io_tqg; 6415 tqrid = *rid; 6416 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6417 6418 ctx->ifc_flags |= IFC_LEGACY; 6419 info->ifi_filter = filter; 6420 info->ifi_filter_arg = filter_arg; 6421 info->ifi_task = gtask; 6422 info->ifi_ctx = rx_only ? ctx : q; 6423 6424 dev = ctx->ifc_dev; 6425 /* We allocate a single interrupt resource */ 6426 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6427 iflib_fast_intr_rxtx, NULL, info, name); 6428 if (err != 0) 6429 return (err); 6430 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6431 res = irq->ii_res; 6432 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6433 6434 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6435 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6436 "tx"); 6437 return (0); 6438 } 6439 6440 void 6441 iflib_led_create(if_ctx_t ctx) 6442 { 6443 6444 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6445 device_get_nameunit(ctx->ifc_dev)); 6446 } 6447 6448 void 6449 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6450 { 6451 6452 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6453 } 6454 6455 void 6456 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6457 { 6458 6459 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6460 } 6461 6462 void 6463 iflib_admin_intr_deferred(if_ctx_t ctx) 6464 { 6465 6466 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6467 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6468 } 6469 6470 void 6471 iflib_iov_intr_deferred(if_ctx_t ctx) 6472 { 6473 6474 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6475 } 6476 6477 void 6478 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6479 { 6480 6481 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6482 name); 6483 } 6484 6485 void 6486 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6487 const char *name) 6488 { 6489 6490 GROUPTASK_INIT(gtask, 0, fn, ctx); 6491 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6492 name); 6493 } 6494 6495 void 6496 iflib_config_gtask_deinit(struct grouptask *gtask) 6497 { 6498 6499 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6500 } 6501 6502 void 6503 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6504 { 6505 if_t ifp = ctx->ifc_ifp; 6506 iflib_txq_t txq = ctx->ifc_txqs; 6507 6508 if_setbaudrate(ifp, baudrate); 6509 if (baudrate >= IF_Gbps(10)) { 6510 STATE_LOCK(ctx); 6511 ctx->ifc_flags |= IFC_PREFETCH; 6512 STATE_UNLOCK(ctx); 6513 } 6514 /* If link down, disable watchdog */ 6515 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6516 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6517 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6518 } 6519 ctx->ifc_link_state = link_state; 6520 if_link_state_change(ifp, link_state); 6521 } 6522 6523 static int 6524 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6525 { 6526 int credits; 6527 #ifdef INVARIANTS 6528 int credits_pre = txq->ift_cidx_processed; 6529 #endif 6530 6531 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6532 BUS_DMASYNC_POSTREAD); 6533 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6534 return (0); 6535 6536 txq->ift_processed += credits; 6537 txq->ift_cidx_processed += credits; 6538 6539 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6540 if (txq->ift_cidx_processed >= txq->ift_size) 6541 txq->ift_cidx_processed -= txq->ift_size; 6542 return (credits); 6543 } 6544 6545 static int 6546 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6547 { 6548 iflib_fl_t fl; 6549 u_int i; 6550 6551 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6552 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6553 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6554 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6555 budget)); 6556 } 6557 6558 void 6559 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6560 const char *description, if_int_delay_info_t info, 6561 int offset, int value) 6562 { 6563 info->iidi_ctx = ctx; 6564 info->iidi_offset = offset; 6565 info->iidi_value = value; 6566 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6567 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6568 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6569 info, 0, iflib_sysctl_int_delay, "I", description); 6570 } 6571 6572 struct sx * 6573 iflib_ctx_lock_get(if_ctx_t ctx) 6574 { 6575 6576 return (&ctx->ifc_ctx_sx); 6577 } 6578 6579 static int 6580 iflib_msix_init(if_ctx_t ctx) 6581 { 6582 device_t dev = ctx->ifc_dev; 6583 if_shared_ctx_t sctx = ctx->ifc_sctx; 6584 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6585 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6586 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6587 6588 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6589 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6590 6591 if (bootverbose) 6592 device_printf(dev, "msix_init qsets capped at %d\n", 6593 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6594 6595 /* Override by tuneable */ 6596 if (scctx->isc_disable_msix) 6597 goto msi; 6598 6599 /* First try MSI-X */ 6600 if ((msgs = pci_msix_count(dev)) == 0) { 6601 if (bootverbose) 6602 device_printf(dev, "MSI-X not supported or disabled\n"); 6603 goto msi; 6604 } 6605 6606 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6607 /* 6608 * bar == -1 => "trust me I know what I'm doing" 6609 * Some drivers are for hardware that is so shoddily 6610 * documented that no one knows which bars are which 6611 * so the developer has to map all bars. This hack 6612 * allows shoddy garbage to use MSI-X in this framework. 6613 */ 6614 if (bar != -1) { 6615 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6616 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6617 if (ctx->ifc_msix_mem == NULL) { 6618 device_printf(dev, "Unable to map MSI-X table\n"); 6619 goto msi; 6620 } 6621 } 6622 6623 admincnt = sctx->isc_admin_intrcnt; 6624 #if IFLIB_DEBUG 6625 /* use only 1 qset in debug mode */ 6626 queuemsgs = min(msgs - admincnt, 1); 6627 #else 6628 queuemsgs = msgs - admincnt; 6629 #endif 6630 #ifdef RSS 6631 queues = imin(queuemsgs, rss_getnumbuckets()); 6632 #else 6633 queues = queuemsgs; 6634 #endif 6635 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6636 if (bootverbose) 6637 device_printf(dev, 6638 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6639 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6640 #ifdef RSS 6641 /* If we're doing RSS, clamp at the number of RSS buckets */ 6642 if (queues > rss_getnumbuckets()) 6643 queues = rss_getnumbuckets(); 6644 #endif 6645 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6646 rx_queues = iflib_num_rx_queues; 6647 else 6648 rx_queues = queues; 6649 6650 if (rx_queues > scctx->isc_nrxqsets) 6651 rx_queues = scctx->isc_nrxqsets; 6652 6653 /* 6654 * We want this to be all logical CPUs by default 6655 */ 6656 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6657 tx_queues = iflib_num_tx_queues; 6658 else 6659 tx_queues = mp_ncpus; 6660 6661 if (tx_queues > scctx->isc_ntxqsets) 6662 tx_queues = scctx->isc_ntxqsets; 6663 6664 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6665 #ifdef INVARIANTS 6666 if (tx_queues != rx_queues) 6667 device_printf(dev, 6668 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6669 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6670 #endif 6671 tx_queues = min(rx_queues, tx_queues); 6672 rx_queues = min(rx_queues, tx_queues); 6673 } 6674 6675 vectors = rx_queues + admincnt; 6676 if (msgs < vectors) { 6677 device_printf(dev, 6678 "insufficient number of MSI-X vectors " 6679 "(supported %d, need %d)\n", msgs, vectors); 6680 goto msi; 6681 } 6682 6683 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6684 tx_queues); 6685 msgs = vectors; 6686 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6687 if (vectors != msgs) { 6688 device_printf(dev, 6689 "Unable to allocate sufficient MSI-X vectors " 6690 "(got %d, need %d)\n", vectors, msgs); 6691 pci_release_msi(dev); 6692 if (bar != -1) { 6693 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6694 ctx->ifc_msix_mem); 6695 ctx->ifc_msix_mem = NULL; 6696 } 6697 goto msi; 6698 } 6699 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6700 vectors); 6701 scctx->isc_vectors = vectors; 6702 scctx->isc_nrxqsets = rx_queues; 6703 scctx->isc_ntxqsets = tx_queues; 6704 scctx->isc_intr = IFLIB_INTR_MSIX; 6705 6706 return (vectors); 6707 } else { 6708 device_printf(dev, 6709 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6710 err); 6711 if (bar != -1) { 6712 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6713 ctx->ifc_msix_mem); 6714 ctx->ifc_msix_mem = NULL; 6715 } 6716 } 6717 6718 msi: 6719 vectors = pci_msi_count(dev); 6720 scctx->isc_nrxqsets = 1; 6721 scctx->isc_ntxqsets = 1; 6722 scctx->isc_vectors = vectors; 6723 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6724 device_printf(dev,"Using an MSI interrupt\n"); 6725 scctx->isc_intr = IFLIB_INTR_MSI; 6726 } else { 6727 scctx->isc_vectors = 1; 6728 device_printf(dev,"Using a Legacy interrupt\n"); 6729 scctx->isc_intr = IFLIB_INTR_LEGACY; 6730 } 6731 6732 return (vectors); 6733 } 6734 6735 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6736 6737 static int 6738 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6739 { 6740 int rc; 6741 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6742 struct sbuf *sb; 6743 const char *ring_state = "UNKNOWN"; 6744 6745 /* XXX needed ? */ 6746 rc = sysctl_wire_old_buffer(req, 0); 6747 MPASS(rc == 0); 6748 if (rc != 0) 6749 return (rc); 6750 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6751 MPASS(sb != NULL); 6752 if (sb == NULL) 6753 return (ENOMEM); 6754 if (state[3] <= 3) 6755 ring_state = ring_states[state[3]]; 6756 6757 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6758 state[0], state[1], state[2], ring_state); 6759 rc = sbuf_finish(sb); 6760 sbuf_delete(sb); 6761 return(rc); 6762 } 6763 6764 enum iflib_ndesc_handler { 6765 IFLIB_NTXD_HANDLER, 6766 IFLIB_NRXD_HANDLER, 6767 }; 6768 6769 static int 6770 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6771 { 6772 if_ctx_t ctx = (void *)arg1; 6773 enum iflib_ndesc_handler type = arg2; 6774 char buf[256] = {0}; 6775 qidx_t *ndesc; 6776 char *p, *next; 6777 int nqs, rc, i; 6778 6779 nqs = 8; 6780 switch(type) { 6781 case IFLIB_NTXD_HANDLER: 6782 ndesc = ctx->ifc_sysctl_ntxds; 6783 if (ctx->ifc_sctx) 6784 nqs = ctx->ifc_sctx->isc_ntxqs; 6785 break; 6786 case IFLIB_NRXD_HANDLER: 6787 ndesc = ctx->ifc_sysctl_nrxds; 6788 if (ctx->ifc_sctx) 6789 nqs = ctx->ifc_sctx->isc_nrxqs; 6790 break; 6791 default: 6792 printf("%s: unhandled type\n", __func__); 6793 return (EINVAL); 6794 } 6795 if (nqs == 0) 6796 nqs = 8; 6797 6798 for (i=0; i<8; i++) { 6799 if (i >= nqs) 6800 break; 6801 if (i) 6802 strcat(buf, ","); 6803 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6804 } 6805 6806 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6807 if (rc || req->newptr == NULL) 6808 return rc; 6809 6810 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6811 i++, p = strsep(&next, " ,")) { 6812 ndesc[i] = strtoul(p, NULL, 10); 6813 } 6814 6815 return(rc); 6816 } 6817 6818 #define NAME_BUFLEN 32 6819 static void 6820 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6821 { 6822 device_t dev = iflib_get_dev(ctx); 6823 struct sysctl_oid_list *child, *oid_list; 6824 struct sysctl_ctx_list *ctx_list; 6825 struct sysctl_oid *node; 6826 6827 ctx_list = device_get_sysctl_ctx(dev); 6828 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6829 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6830 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6831 oid_list = SYSCTL_CHILDREN(node); 6832 6833 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6834 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6835 "driver version"); 6836 6837 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6838 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6839 "# of txqs to use, 0 => use default #"); 6840 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6841 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6842 "# of rxqs to use, 0 => use default #"); 6843 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6844 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6845 "permit #txq != #rxq"); 6846 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6847 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6848 "disable MSI-X (default 0)"); 6849 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6850 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6851 "set the RX budget"); 6852 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6853 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6854 "cause TX to abdicate instead of running to completion"); 6855 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6856 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6857 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6858 "offset to start using cores at"); 6859 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6860 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6861 "use separate cores for TX and RX"); 6862 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores", 6863 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 6864 "try to make use of logical cores for TX and RX"); 6865 6866 /* XXX change for per-queue sizes */ 6867 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6868 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6869 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6870 "list of # of TX descriptors to use, 0 = use default #"); 6871 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6872 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6873 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6874 "list of # of RX descriptors to use, 0 = use default #"); 6875 } 6876 6877 static void 6878 iflib_add_device_sysctl_post(if_ctx_t ctx) 6879 { 6880 if_shared_ctx_t sctx = ctx->ifc_sctx; 6881 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6882 device_t dev = iflib_get_dev(ctx); 6883 struct sysctl_oid_list *child; 6884 struct sysctl_ctx_list *ctx_list; 6885 iflib_fl_t fl; 6886 iflib_txq_t txq; 6887 iflib_rxq_t rxq; 6888 int i, j; 6889 char namebuf[NAME_BUFLEN]; 6890 char *qfmt; 6891 struct sysctl_oid *queue_node, *fl_node, *node; 6892 struct sysctl_oid_list *queue_list, *fl_list; 6893 ctx_list = device_get_sysctl_ctx(dev); 6894 6895 node = ctx->ifc_sysctl_node; 6896 child = SYSCTL_CHILDREN(node); 6897 6898 if (scctx->isc_ntxqsets > 100) 6899 qfmt = "txq%03d"; 6900 else if (scctx->isc_ntxqsets > 10) 6901 qfmt = "txq%02d"; 6902 else 6903 qfmt = "txq%d"; 6904 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6905 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6906 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6907 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6908 queue_list = SYSCTL_CHILDREN(queue_node); 6909 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6910 CTLFLAG_RD, 6911 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to"); 6912 #if MEMORY_LOGGING 6913 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6914 CTLFLAG_RD, 6915 &txq->ift_dequeued, "total mbufs freed"); 6916 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6917 CTLFLAG_RD, 6918 &txq->ift_enqueued, "total mbufs enqueued"); 6919 #endif 6920 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6921 CTLFLAG_RD, 6922 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6923 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6924 CTLFLAG_RD, 6925 &txq->ift_pullups, "# of times m_pullup was called"); 6926 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6927 CTLFLAG_RD, 6928 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6929 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6930 CTLFLAG_RD, 6931 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6932 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6933 CTLFLAG_RD, 6934 &txq->ift_map_failed, "# of times DMA map failed"); 6935 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6936 CTLFLAG_RD, 6937 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6938 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6939 CTLFLAG_RD, 6940 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6941 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6942 CTLFLAG_RD, 6943 &txq->ift_pidx, 1, "Producer Index"); 6944 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6945 CTLFLAG_RD, 6946 &txq->ift_cidx, 1, "Consumer Index"); 6947 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6948 CTLFLAG_RD, 6949 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6950 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6951 CTLFLAG_RD, 6952 &txq->ift_in_use, 1, "descriptors in use"); 6953 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6954 CTLFLAG_RD, 6955 &txq->ift_processed, "descriptors procesed for clean"); 6956 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6957 CTLFLAG_RD, 6958 &txq->ift_cleaned, "total cleaned"); 6959 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6960 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6961 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6962 mp_ring_state_handler, "A", "soft ring state"); 6963 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6964 CTLFLAG_RD, &txq->ift_br->enqueues, 6965 "# of enqueues to the mp_ring for this queue"); 6966 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6967 CTLFLAG_RD, &txq->ift_br->drops, 6968 "# of drops in the mp_ring for this queue"); 6969 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6970 CTLFLAG_RD, &txq->ift_br->starts, 6971 "# of normal consumer starts in the mp_ring for this queue"); 6972 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6973 CTLFLAG_RD, &txq->ift_br->stalls, 6974 "# of consumer stalls in the mp_ring for this queue"); 6975 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6976 CTLFLAG_RD, &txq->ift_br->restarts, 6977 "# of consumer restarts in the mp_ring for this queue"); 6978 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6979 CTLFLAG_RD, &txq->ift_br->abdications, 6980 "# of consumer abdications in the mp_ring for this queue"); 6981 } 6982 6983 if (scctx->isc_nrxqsets > 100) 6984 qfmt = "rxq%03d"; 6985 else if (scctx->isc_nrxqsets > 10) 6986 qfmt = "rxq%02d"; 6987 else 6988 qfmt = "rxq%d"; 6989 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6990 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6991 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6992 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6993 queue_list = SYSCTL_CHILDREN(queue_node); 6994 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6995 CTLFLAG_RD, 6996 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to"); 6997 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6998 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6999 CTLFLAG_RD, 7000 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 7001 } 7002 7003 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7004 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7005 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 7006 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 7007 fl_list = SYSCTL_CHILDREN(fl_node); 7008 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7009 CTLFLAG_RD, 7010 &fl->ifl_pidx, 1, "Producer Index"); 7011 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7012 CTLFLAG_RD, 7013 &fl->ifl_cidx, 1, "Consumer Index"); 7014 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7015 CTLFLAG_RD, 7016 &fl->ifl_credits, 1, "credits available"); 7017 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7018 CTLFLAG_RD, 7019 &fl->ifl_buf_size, 1, "buffer size"); 7020 #if MEMORY_LOGGING 7021 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 7022 CTLFLAG_RD, 7023 &fl->ifl_m_enqueued, "mbufs allocated"); 7024 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 7025 CTLFLAG_RD, 7026 &fl->ifl_m_dequeued, "mbufs freed"); 7027 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 7028 CTLFLAG_RD, 7029 &fl->ifl_cl_enqueued, "clusters allocated"); 7030 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 7031 CTLFLAG_RD, 7032 &fl->ifl_cl_dequeued, "clusters freed"); 7033 #endif 7034 } 7035 } 7036 7037 } 7038 7039 void 7040 iflib_request_reset(if_ctx_t ctx) 7041 { 7042 7043 STATE_LOCK(ctx); 7044 ctx->ifc_flags |= IFC_DO_RESET; 7045 STATE_UNLOCK(ctx); 7046 } 7047 7048 #ifndef __NO_STRICT_ALIGNMENT 7049 static struct mbuf * 7050 iflib_fixup_rx(struct mbuf *m) 7051 { 7052 struct mbuf *n; 7053 7054 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7055 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7056 m->m_data += ETHER_HDR_LEN; 7057 n = m; 7058 } else { 7059 MGETHDR(n, M_NOWAIT, MT_DATA); 7060 if (n == NULL) { 7061 m_freem(m); 7062 return (NULL); 7063 } 7064 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7065 m->m_data += ETHER_HDR_LEN; 7066 m->m_len -= ETHER_HDR_LEN; 7067 n->m_len = ETHER_HDR_LEN; 7068 M_MOVE_PKTHDR(n, m); 7069 n->m_next = m; 7070 } 7071 return (n); 7072 } 7073 #endif 7074 7075 #ifdef DEBUGNET 7076 static void 7077 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7078 { 7079 if_ctx_t ctx; 7080 7081 ctx = if_getsoftc(ifp); 7082 CTX_LOCK(ctx); 7083 *nrxr = NRXQSETS(ctx); 7084 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7085 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7086 CTX_UNLOCK(ctx); 7087 } 7088 7089 static void 7090 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7091 { 7092 if_ctx_t ctx; 7093 if_softc_ctx_t scctx; 7094 iflib_fl_t fl; 7095 iflib_rxq_t rxq; 7096 int i, j; 7097 7098 ctx = if_getsoftc(ifp); 7099 scctx = &ctx->ifc_softc_ctx; 7100 7101 switch (event) { 7102 case DEBUGNET_START: 7103 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7104 rxq = &ctx->ifc_rxqs[i]; 7105 for (j = 0; j < rxq->ifr_nfl; j++) { 7106 fl = rxq->ifr_fl; 7107 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7108 } 7109 } 7110 iflib_no_tx_batch = 1; 7111 break; 7112 default: 7113 break; 7114 } 7115 } 7116 7117 static int 7118 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7119 { 7120 if_ctx_t ctx; 7121 iflib_txq_t txq; 7122 int error; 7123 7124 ctx = if_getsoftc(ifp); 7125 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7126 IFF_DRV_RUNNING) 7127 return (EBUSY); 7128 7129 txq = &ctx->ifc_txqs[0]; 7130 error = iflib_encap(txq, &m); 7131 if (error == 0) 7132 (void)iflib_txd_db_check(txq, true); 7133 return (error); 7134 } 7135 7136 static int 7137 iflib_debugnet_poll(if_t ifp, int count) 7138 { 7139 struct epoch_tracker et; 7140 if_ctx_t ctx; 7141 if_softc_ctx_t scctx; 7142 iflib_txq_t txq; 7143 int i; 7144 7145 ctx = if_getsoftc(ifp); 7146 scctx = &ctx->ifc_softc_ctx; 7147 7148 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7149 IFF_DRV_RUNNING) 7150 return (EBUSY); 7151 7152 txq = &ctx->ifc_txqs[0]; 7153 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 7154 7155 NET_EPOCH_ENTER(et); 7156 for (i = 0; i < scctx->isc_nrxqsets; i++) 7157 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7158 NET_EPOCH_EXIT(et); 7159 return (0); 7160 } 7161 #endif /* DEBUGNET */ 7162