1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 #define IFLIB_RXEOF_MORE (1U << 0) 133 #define IFLIB_RXEOF_EMPTY (2U << 0) 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 static void iflib_timer(void *arg); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 199 qidx_t ifc_sysctl_ntxds[8]; 200 qidx_t ifc_sysctl_nrxds[8]; 201 struct if_txrx ifc_txrx; 202 #define isc_txd_encap ifc_txrx.ift_txd_encap 203 #define isc_txd_flush ifc_txrx.ift_txd_flush 204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 205 #define isc_rxd_available ifc_txrx.ift_rxd_available 206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 212 eventhandler_tag ifc_vlan_attach_event; 213 eventhandler_tag ifc_vlan_detach_event; 214 struct ether_addr ifc_mac; 215 }; 216 217 void * 218 iflib_get_softc(if_ctx_t ctx) 219 { 220 221 return (ctx->ifc_softc); 222 } 223 224 device_t 225 iflib_get_dev(if_ctx_t ctx) 226 { 227 228 return (ctx->ifc_dev); 229 } 230 231 if_t 232 iflib_get_ifp(if_ctx_t ctx) 233 { 234 235 return (ctx->ifc_ifp); 236 } 237 238 struct ifmedia * 239 iflib_get_media(if_ctx_t ctx) 240 { 241 242 return (ctx->ifc_mediap); 243 } 244 245 uint32_t 246 iflib_get_flags(if_ctx_t ctx) 247 { 248 return (ctx->ifc_flags); 249 } 250 251 void 252 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 253 { 254 255 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 256 } 257 258 if_softc_ctx_t 259 iflib_get_softc_ctx(if_ctx_t ctx) 260 { 261 262 return (&ctx->ifc_softc_ctx); 263 } 264 265 if_shared_ctx_t 266 iflib_get_sctx(if_ctx_t ctx) 267 { 268 269 return (ctx->ifc_sctx); 270 } 271 272 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 273 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 274 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 275 276 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 277 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 289 struct mbuf **ifsd_m; /* pkthdr mbufs */ 290 } if_txsd_vec_t; 291 292 /* magic number that should be high enough for any hardware */ 293 #define IFLIB_MAX_TX_SEGS 128 294 #define IFLIB_RX_COPY_THRESH 128 295 #define IFLIB_MAX_RX_REFRESH 32 296 /* The minimum descriptors per second before we start coalescing */ 297 #define IFLIB_MIN_DESC_SEC 16384 298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 299 #define IFLIB_QUEUE_IDLE 0 300 #define IFLIB_QUEUE_HUNG 1 301 #define IFLIB_QUEUE_WORKING 2 302 /* maximum number of txqs that can share an rx interrupt */ 303 #define IFLIB_MAX_TX_SHARED_INTR 4 304 305 /* this should really scale with ring size - this is a fairly arbitrary value */ 306 #define TX_BATCH_SIZE 32 307 308 #define IFLIB_RESTART_BUDGET 8 309 310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 313 314 struct iflib_txq { 315 qidx_t ift_in_use; 316 qidx_t ift_cidx; 317 qidx_t ift_cidx_processed; 318 qidx_t ift_pidx; 319 uint8_t ift_gen; 320 uint8_t ift_br_offset; 321 uint16_t ift_npending; 322 uint16_t ift_db_pending; 323 uint16_t ift_rs_pending; 324 /* implicit pad */ 325 uint8_t ift_txd_size[8]; 326 uint64_t ift_processed; 327 uint64_t ift_cleaned; 328 uint64_t ift_cleaned_prev; 329 #if MEMORY_LOGGING 330 uint64_t ift_enqueued; 331 uint64_t ift_dequeued; 332 #endif 333 uint64_t ift_no_tx_dma_setup; 334 uint64_t ift_no_desc_avail; 335 uint64_t ift_mbuf_defrag_failed; 336 uint64_t ift_mbuf_defrag; 337 uint64_t ift_map_failed; 338 uint64_t ift_txd_encap_efbig; 339 uint64_t ift_pullups; 340 uint64_t ift_last_timer_tick; 341 342 struct mtx ift_mtx; 343 struct mtx ift_db_mtx; 344 345 /* constant values */ 346 if_ctx_t ift_ctx; 347 struct ifmp_ring *ift_br; 348 struct grouptask ift_task; 349 qidx_t ift_size; 350 uint16_t ift_id; 351 struct callout ift_timer; 352 353 if_txsd_vec_t ift_sds; 354 uint8_t ift_qstatus; 355 uint8_t ift_closed; 356 uint8_t ift_update_freq; 357 struct iflib_filter_info ift_filter_info; 358 bus_dma_tag_t ift_buf_tag; 359 bus_dma_tag_t ift_tso_buf_tag; 360 iflib_dma_info_t ift_ifdi; 361 #define MTX_NAME_LEN 16 362 char ift_mtx_name[MTX_NAME_LEN]; 363 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 364 #ifdef IFLIB_DIAGNOSTICS 365 uint64_t ift_cpu_exec_count[256]; 366 #endif 367 } __aligned(CACHE_LINE_SIZE); 368 369 struct iflib_fl { 370 qidx_t ifl_cidx; 371 qidx_t ifl_pidx; 372 qidx_t ifl_credits; 373 uint8_t ifl_gen; 374 uint8_t ifl_rxd_size; 375 #if MEMORY_LOGGING 376 uint64_t ifl_m_enqueued; 377 uint64_t ifl_m_dequeued; 378 uint64_t ifl_cl_enqueued; 379 uint64_t ifl_cl_dequeued; 380 #endif 381 /* implicit pad */ 382 bitstr_t *ifl_rx_bitmap; 383 qidx_t ifl_fragidx; 384 /* constant */ 385 qidx_t ifl_size; 386 uint16_t ifl_buf_size; 387 uint16_t ifl_cltype; 388 uma_zone_t ifl_zone; 389 iflib_rxsd_array_t ifl_sds; 390 iflib_rxq_t ifl_rxq; 391 uint8_t ifl_id; 392 bus_dma_tag_t ifl_buf_tag; 393 iflib_dma_info_t ifl_ifdi; 394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 395 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 397 } __aligned(CACHE_LINE_SIZE); 398 399 static inline qidx_t 400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 401 { 402 qidx_t used; 403 404 if (pidx > cidx) 405 used = pidx - cidx; 406 else if (pidx < cidx) 407 used = size - cidx + pidx; 408 else if (gen == 0 && pidx == cidx) 409 used = 0; 410 else if (gen == 1 && pidx == cidx) 411 used = size; 412 else 413 panic("bad state"); 414 415 return (used); 416 } 417 418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 419 420 #define IDXDIFF(head, tail, wrap) \ 421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 422 423 struct iflib_rxq { 424 if_ctx_t ifr_ctx; 425 iflib_fl_t ifr_fl; 426 uint64_t ifr_rx_irq; 427 struct pfil_head *pfil; 428 /* 429 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 430 * the command queue consumer index. Otherwise it's unused. 431 */ 432 qidx_t ifr_cq_cidx; 433 uint16_t ifr_id; 434 uint8_t ifr_nfl; 435 uint8_t ifr_ntxqirq; 436 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 437 uint8_t ifr_fl_offset; 438 struct lro_ctrl ifr_lc; 439 struct grouptask ifr_task; 440 struct callout ifr_watchdog; 441 struct iflib_filter_info ifr_filter_info; 442 iflib_dma_info_t ifr_ifdi; 443 444 /* dynamically allocate if any drivers need a value substantially larger than this */ 445 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 446 #ifdef IFLIB_DIAGNOSTICS 447 uint64_t ifr_cpu_exec_count[256]; 448 #endif 449 } __aligned(CACHE_LINE_SIZE); 450 451 typedef struct if_rxsd { 452 caddr_t *ifsd_cl; 453 iflib_fl_t ifsd_fl; 454 qidx_t ifsd_cidx; 455 } *if_rxsd_t; 456 457 /* multiple of word size */ 458 #ifdef __LP64__ 459 #define PKT_INFO_SIZE 6 460 #define RXD_INFO_SIZE 5 461 #define PKT_TYPE uint64_t 462 #else 463 #define PKT_INFO_SIZE 11 464 #define RXD_INFO_SIZE 8 465 #define PKT_TYPE uint32_t 466 #endif 467 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 468 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 469 470 typedef struct if_pkt_info_pad { 471 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 472 } *if_pkt_info_pad_t; 473 typedef struct if_rxd_info_pad { 474 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 475 } *if_rxd_info_pad_t; 476 477 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 478 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 479 480 481 static inline void 482 pkt_info_zero(if_pkt_info_t pi) 483 { 484 if_pkt_info_pad_t pi_pad; 485 486 pi_pad = (if_pkt_info_pad_t)pi; 487 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 488 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 489 #ifndef __LP64__ 490 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 491 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 492 #endif 493 } 494 495 static device_method_t iflib_pseudo_methods[] = { 496 DEVMETHOD(device_attach, noop_attach), 497 DEVMETHOD(device_detach, iflib_pseudo_detach), 498 DEVMETHOD_END 499 }; 500 501 driver_t iflib_pseudodriver = { 502 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 503 }; 504 505 static inline void 506 rxd_info_zero(if_rxd_info_t ri) 507 { 508 if_rxd_info_pad_t ri_pad; 509 int i; 510 511 ri_pad = (if_rxd_info_pad_t)ri; 512 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 513 ri_pad->rxd_val[i] = 0; 514 ri_pad->rxd_val[i+1] = 0; 515 ri_pad->rxd_val[i+2] = 0; 516 ri_pad->rxd_val[i+3] = 0; 517 } 518 #ifdef __LP64__ 519 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 520 #endif 521 } 522 523 /* 524 * Only allow a single packet to take up most 1/nth of the tx ring 525 */ 526 #define MAX_SINGLE_PACKET_FRACTION 12 527 #define IF_BAD_DMA (bus_addr_t)-1 528 529 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 530 531 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 532 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 533 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 534 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 535 536 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 537 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 538 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 539 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 540 541 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 542 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 543 544 void 545 iflib_set_detach(if_ctx_t ctx) 546 { 547 STATE_LOCK(ctx); 548 ctx->ifc_flags |= IFC_IN_DETACH; 549 STATE_UNLOCK(ctx); 550 } 551 552 /* Our boot-time initialization hook */ 553 static int iflib_module_event_handler(module_t, int, void *); 554 555 static moduledata_t iflib_moduledata = { 556 "iflib", 557 iflib_module_event_handler, 558 NULL 559 }; 560 561 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 562 MODULE_VERSION(iflib, 1); 563 564 MODULE_DEPEND(iflib, pci, 1, 1, 1); 565 MODULE_DEPEND(iflib, ether, 1, 1, 1); 566 567 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 568 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 569 570 #ifndef IFLIB_DEBUG_COUNTERS 571 #ifdef INVARIANTS 572 #define IFLIB_DEBUG_COUNTERS 1 573 #else 574 #define IFLIB_DEBUG_COUNTERS 0 575 #endif /* !INVARIANTS */ 576 #endif 577 578 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 579 "iflib driver parameters"); 580 581 /* 582 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 583 */ 584 static int iflib_min_tx_latency = 0; 585 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 586 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 587 static int iflib_no_tx_batch = 0; 588 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 589 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 590 591 592 #if IFLIB_DEBUG_COUNTERS 593 594 static int iflib_tx_seen; 595 static int iflib_tx_sent; 596 static int iflib_tx_encap; 597 static int iflib_rx_allocs; 598 static int iflib_fl_refills; 599 static int iflib_fl_refills_large; 600 static int iflib_tx_frees; 601 602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 603 &iflib_tx_seen, 0, "# TX mbufs seen"); 604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 605 &iflib_tx_sent, 0, "# TX mbufs sent"); 606 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 607 &iflib_tx_encap, 0, "# TX mbufs encapped"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 609 &iflib_tx_frees, 0, "# TX frees"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 611 &iflib_rx_allocs, 0, "# RX allocations"); 612 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 613 &iflib_fl_refills, 0, "# refills"); 614 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 615 &iflib_fl_refills_large, 0, "# large refills"); 616 617 618 static int iflib_txq_drain_flushing; 619 static int iflib_txq_drain_oactive; 620 static int iflib_txq_drain_notready; 621 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 623 &iflib_txq_drain_flushing, 0, "# drain flushes"); 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 625 &iflib_txq_drain_oactive, 0, "# drain oactives"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 627 &iflib_txq_drain_notready, 0, "# drain notready"); 628 629 630 static int iflib_encap_load_mbuf_fail; 631 static int iflib_encap_pad_mbuf_fail; 632 static int iflib_encap_txq_avail_fail; 633 static int iflib_encap_txd_encap_fail; 634 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 636 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 638 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 639 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 640 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 641 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 642 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 643 644 static int iflib_task_fn_rxs; 645 static int iflib_rx_intr_enables; 646 static int iflib_fast_intrs; 647 static int iflib_rx_unavail; 648 static int iflib_rx_ctx_inactive; 649 static int iflib_rx_if_input; 650 static int iflib_rxd_flush; 651 652 static int iflib_verbose_debug; 653 654 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 655 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 657 &iflib_rx_intr_enables, 0, "# RX intr enables"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 659 &iflib_fast_intrs, 0, "# fast_intr calls"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 661 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 663 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 665 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 667 &iflib_rxd_flush, 0, "# times rxd_flush called"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 669 &iflib_verbose_debug, 0, "enable verbose debugging"); 670 671 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 672 static void 673 iflib_debug_reset(void) 674 { 675 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 676 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 677 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 678 iflib_txq_drain_notready = 679 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 680 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 681 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 682 iflib_rx_unavail = 683 iflib_rx_ctx_inactive = iflib_rx_if_input = 684 iflib_rxd_flush = 0; 685 } 686 687 #else 688 #define DBG_COUNTER_INC(name) 689 static void iflib_debug_reset(void) {} 690 #endif 691 692 #define IFLIB_DEBUG 0 693 694 static void iflib_tx_structures_free(if_ctx_t ctx); 695 static void iflib_rx_structures_free(if_ctx_t ctx); 696 static int iflib_queues_alloc(if_ctx_t ctx); 697 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 698 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 699 static int iflib_qset_structures_setup(if_ctx_t ctx); 700 static int iflib_msix_init(if_ctx_t ctx); 701 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 702 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 703 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 704 #ifdef ALTQ 705 static void iflib_altq_if_start(if_t ifp); 706 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 707 #endif 708 static int iflib_register(if_ctx_t); 709 static void iflib_deregister(if_ctx_t); 710 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 711 static void iflib_init_locked(if_ctx_t ctx); 712 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 713 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 714 static void iflib_ifmp_purge(iflib_txq_t txq); 715 static void _iflib_pre_assert(if_softc_ctx_t scctx); 716 static void iflib_if_init_locked(if_ctx_t ctx); 717 static void iflib_free_intr_mem(if_ctx_t ctx); 718 #ifndef __NO_STRICT_ALIGNMENT 719 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 720 #endif 721 722 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 723 SLIST_HEAD_INITIALIZER(cpu_offsets); 724 struct cpu_offset { 725 SLIST_ENTRY(cpu_offset) entries; 726 cpuset_t set; 727 unsigned int refcount; 728 uint16_t offset; 729 }; 730 static struct mtx cpu_offset_mtx; 731 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 732 MTX_DEF); 733 734 DEBUGNET_DEFINE(iflib); 735 736 #ifdef DEV_NETMAP 737 #include <sys/selinfo.h> 738 #include <net/netmap.h> 739 #include <dev/netmap/netmap_kern.h> 740 741 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 742 743 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 744 745 /* 746 * device-specific sysctl variables: 747 * 748 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 749 * During regular operations the CRC is stripped, but on some 750 * hardware reception of frames not multiple of 64 is slower, 751 * so using crcstrip=0 helps in benchmarks. 752 * 753 * iflib_rx_miss, iflib_rx_miss_bufs: 754 * count packets that might be missed due to lost interrupts. 755 */ 756 SYSCTL_DECL(_dev_netmap); 757 /* 758 * The xl driver by default strips CRCs and we do not override it. 759 */ 760 761 int iflib_crcstrip = 1; 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 763 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 764 765 int iflib_rx_miss, iflib_rx_miss_bufs; 766 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 767 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 768 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 769 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 770 771 /* 772 * Register/unregister. We are already under netmap lock. 773 * Only called on the first register or the last unregister. 774 */ 775 static int 776 iflib_netmap_register(struct netmap_adapter *na, int onoff) 777 { 778 if_t ifp = na->ifp; 779 if_ctx_t ctx = ifp->if_softc; 780 int status; 781 782 CTX_LOCK(ctx); 783 IFDI_INTR_DISABLE(ctx); 784 785 /* Tell the stack that the interface is no longer active */ 786 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 787 788 if (!CTX_IS_VF(ctx)) 789 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 790 791 /* enable or disable flags and callbacks in na and ifp */ 792 if (onoff) { 793 nm_set_native_flags(na); 794 } else { 795 nm_clear_native_flags(na); 796 } 797 iflib_stop(ctx); 798 iflib_init_locked(ctx); 799 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 800 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 801 if (status) 802 nm_clear_native_flags(na); 803 CTX_UNLOCK(ctx); 804 return (status); 805 } 806 807 static int 808 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 809 { 810 struct netmap_adapter *na = kring->na; 811 u_int const lim = kring->nkr_num_slots - 1; 812 u_int head = kring->rhead; 813 struct netmap_ring *ring = kring->ring; 814 bus_dmamap_t *map; 815 struct if_rxd_update iru; 816 if_ctx_t ctx = rxq->ifr_ctx; 817 iflib_fl_t fl = &rxq->ifr_fl[0]; 818 uint32_t refill_pidx, nic_i; 819 #if IFLIB_DEBUG_COUNTERS 820 int rf_count = 0; 821 #endif 822 823 if (nm_i == head && __predict_true(!init)) 824 return 0; 825 iru_init(&iru, rxq, 0 /* flid */); 826 map = fl->ifl_sds.ifsd_map; 827 refill_pidx = netmap_idx_k2n(kring, nm_i); 828 /* 829 * IMPORTANT: we must leave one free slot in the ring, 830 * so move head back by one unit 831 */ 832 head = nm_prev(head, lim); 833 nic_i = UINT_MAX; 834 DBG_COUNTER_INC(fl_refills); 835 while (nm_i != head) { 836 #if IFLIB_DEBUG_COUNTERS 837 if (++rf_count == 9) 838 DBG_COUNTER_INC(fl_refills_large); 839 #endif 840 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 841 struct netmap_slot *slot = &ring->slot[nm_i]; 842 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 843 uint32_t nic_i_dma = refill_pidx; 844 nic_i = netmap_idx_k2n(kring, nm_i); 845 846 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 847 848 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 849 return netmap_ring_reinit(kring); 850 851 fl->ifl_vm_addrs[tmp_pidx] = addr; 852 if (__predict_false(init)) { 853 netmap_load_map(na, fl->ifl_buf_tag, 854 map[nic_i], addr); 855 } else if (slot->flags & NS_BUF_CHANGED) { 856 /* buffer has changed, reload map */ 857 netmap_reload_map(na, fl->ifl_buf_tag, 858 map[nic_i], addr); 859 } 860 slot->flags &= ~NS_BUF_CHANGED; 861 862 nm_i = nm_next(nm_i, lim); 863 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 864 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 865 continue; 866 867 iru.iru_pidx = refill_pidx; 868 iru.iru_count = tmp_pidx+1; 869 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 870 refill_pidx = nic_i; 871 for (int n = 0; n < iru.iru_count; n++) { 872 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 873 BUS_DMASYNC_PREREAD); 874 /* XXX - change this to not use the netmap func*/ 875 nic_i_dma = nm_next(nic_i_dma, lim); 876 } 877 } 878 } 879 kring->nr_hwcur = head; 880 881 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 882 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 883 if (__predict_true(nic_i != UINT_MAX)) { 884 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 885 DBG_COUNTER_INC(rxd_flush); 886 } 887 return (0); 888 } 889 890 /* 891 * Reconcile kernel and user view of the transmit ring. 892 * 893 * All information is in the kring. 894 * Userspace wants to send packets up to the one before kring->rhead, 895 * kernel knows kring->nr_hwcur is the first unsent packet. 896 * 897 * Here we push packets out (as many as possible), and possibly 898 * reclaim buffers from previously completed transmission. 899 * 900 * The caller (netmap) guarantees that there is only one instance 901 * running at any time. Any interference with other driver 902 * methods should be handled by the individual drivers. 903 */ 904 static int 905 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 906 { 907 struct netmap_adapter *na = kring->na; 908 if_t ifp = na->ifp; 909 struct netmap_ring *ring = kring->ring; 910 u_int nm_i; /* index into the netmap kring */ 911 u_int nic_i; /* index into the NIC ring */ 912 u_int n; 913 u_int const lim = kring->nkr_num_slots - 1; 914 u_int const head = kring->rhead; 915 struct if_pkt_info pi; 916 917 /* 918 * interrupts on every tx packet are expensive so request 919 * them every half ring, or where NS_REPORT is set 920 */ 921 u_int report_frequency = kring->nkr_num_slots >> 1; 922 /* device-specific */ 923 if_ctx_t ctx = ifp->if_softc; 924 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 925 926 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 927 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 928 929 /* 930 * First part: process new packets to send. 931 * nm_i is the current index in the netmap kring, 932 * nic_i is the corresponding index in the NIC ring. 933 * 934 * If we have packets to send (nm_i != head) 935 * iterate over the netmap ring, fetch length and update 936 * the corresponding slot in the NIC ring. Some drivers also 937 * need to update the buffer's physical address in the NIC slot 938 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 939 * 940 * The netmap_reload_map() calls is especially expensive, 941 * even when (as in this case) the tag is 0, so do only 942 * when the buffer has actually changed. 943 * 944 * If possible do not set the report/intr bit on all slots, 945 * but only a few times per ring or when NS_REPORT is set. 946 * 947 * Finally, on 10G and faster drivers, it might be useful 948 * to prefetch the next slot and txr entry. 949 */ 950 951 nm_i = kring->nr_hwcur; 952 if (nm_i != head) { /* we have new packets to send */ 953 pkt_info_zero(&pi); 954 pi.ipi_segs = txq->ift_segs; 955 pi.ipi_qsidx = kring->ring_id; 956 nic_i = netmap_idx_k2n(kring, nm_i); 957 958 __builtin_prefetch(&ring->slot[nm_i]); 959 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 960 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 961 962 for (n = 0; nm_i != head; n++) { 963 struct netmap_slot *slot = &ring->slot[nm_i]; 964 u_int len = slot->len; 965 uint64_t paddr; 966 void *addr = PNMB(na, slot, &paddr); 967 int flags = (slot->flags & NS_REPORT || 968 nic_i == 0 || nic_i == report_frequency) ? 969 IPI_TX_INTR : 0; 970 971 /* device-specific */ 972 pi.ipi_len = len; 973 pi.ipi_segs[0].ds_addr = paddr; 974 pi.ipi_segs[0].ds_len = len; 975 pi.ipi_nsegs = 1; 976 pi.ipi_ndescs = 0; 977 pi.ipi_pidx = nic_i; 978 pi.ipi_flags = flags; 979 980 /* Fill the slot in the NIC ring. */ 981 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 982 DBG_COUNTER_INC(tx_encap); 983 984 /* prefetch for next round */ 985 __builtin_prefetch(&ring->slot[nm_i + 1]); 986 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 987 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 988 989 NM_CHECK_ADDR_LEN(na, addr, len); 990 991 if (slot->flags & NS_BUF_CHANGED) { 992 /* buffer has changed, reload map */ 993 netmap_reload_map(na, txq->ift_buf_tag, 994 txq->ift_sds.ifsd_map[nic_i], addr); 995 } 996 /* make sure changes to the buffer are synced */ 997 bus_dmamap_sync(txq->ift_buf_tag, 998 txq->ift_sds.ifsd_map[nic_i], 999 BUS_DMASYNC_PREWRITE); 1000 1001 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1002 nm_i = nm_next(nm_i, lim); 1003 nic_i = nm_next(nic_i, lim); 1004 } 1005 kring->nr_hwcur = nm_i; 1006 1007 /* synchronize the NIC ring */ 1008 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1009 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1010 1011 /* (re)start the tx unit up to slot nic_i (excluded) */ 1012 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1013 } 1014 1015 /* 1016 * Second part: reclaim buffers for completed transmissions. 1017 * 1018 * If there are unclaimed buffers, attempt to reclaim them. 1019 * If none are reclaimed, and TX IRQs are not in use, do an initial 1020 * minimal delay, then trigger the tx handler which will spin in the 1021 * group task queue. 1022 */ 1023 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1024 if (iflib_tx_credits_update(ctx, txq)) { 1025 /* some tx completed, increment avail */ 1026 nic_i = txq->ift_cidx_processed; 1027 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1028 } 1029 } 1030 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1031 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1032 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1033 iflib_timer, txq, txq->ift_timer.c_cpu); 1034 } 1035 return (0); 1036 } 1037 1038 /* 1039 * Reconcile kernel and user view of the receive ring. 1040 * Same as for the txsync, this routine must be efficient. 1041 * The caller guarantees a single invocations, but races against 1042 * the rest of the driver should be handled here. 1043 * 1044 * On call, kring->rhead is the first packet that userspace wants 1045 * to keep, and kring->rcur is the wakeup point. 1046 * The kernel has previously reported packets up to kring->rtail. 1047 * 1048 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1049 * of whether or not we received an interrupt. 1050 */ 1051 static int 1052 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1053 { 1054 struct netmap_adapter *na = kring->na; 1055 struct netmap_ring *ring = kring->ring; 1056 if_t ifp = na->ifp; 1057 iflib_fl_t fl; 1058 uint32_t nm_i; /* index into the netmap ring */ 1059 uint32_t nic_i; /* index into the NIC ring */ 1060 u_int i, n; 1061 u_int const lim = kring->nkr_num_slots - 1; 1062 u_int const head = kring->rhead; 1063 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1064 struct if_rxd_info ri; 1065 1066 if_ctx_t ctx = ifp->if_softc; 1067 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1068 if (head > lim) 1069 return netmap_ring_reinit(kring); 1070 1071 /* 1072 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1073 */ 1074 1075 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1076 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1077 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1078 } 1079 1080 /* 1081 * First part: import newly received packets. 1082 * 1083 * nm_i is the index of the next free slot in the netmap ring, 1084 * nic_i is the index of the next received packet in the NIC ring, 1085 * and they may differ in case if_init() has been called while 1086 * in netmap mode. For the receive ring we have 1087 * 1088 * nic_i = rxr->next_check; 1089 * nm_i = kring->nr_hwtail (previous) 1090 * and 1091 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1092 * 1093 * rxr->next_check is set to 0 on a ring reinit 1094 */ 1095 if (netmap_no_pendintr || force_update) { 1096 int crclen = iflib_crcstrip ? 0 : 4; 1097 int error, avail; 1098 1099 for (i = 0; i < rxq->ifr_nfl; i++) { 1100 fl = &rxq->ifr_fl[i]; 1101 nic_i = fl->ifl_cidx; 1102 nm_i = netmap_idx_n2k(kring, nic_i); 1103 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1104 rxq->ifr_id, nic_i, USHRT_MAX); 1105 for (n = 0; avail > 0; n++, avail--) { 1106 rxd_info_zero(&ri); 1107 ri.iri_frags = rxq->ifr_frags; 1108 ri.iri_qsidx = kring->ring_id; 1109 ri.iri_ifp = ctx->ifc_ifp; 1110 ri.iri_cidx = nic_i; 1111 1112 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1113 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1114 ring->slot[nm_i].flags = 0; 1115 bus_dmamap_sync(fl->ifl_buf_tag, 1116 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1117 nm_i = nm_next(nm_i, lim); 1118 nic_i = nm_next(nic_i, lim); 1119 } 1120 if (n) { /* update the state variables */ 1121 if (netmap_no_pendintr && !force_update) { 1122 /* diagnostics */ 1123 iflib_rx_miss ++; 1124 iflib_rx_miss_bufs += n; 1125 } 1126 fl->ifl_cidx = nic_i; 1127 kring->nr_hwtail = nm_i; 1128 } 1129 kring->nr_kflags &= ~NKR_PENDINTR; 1130 } 1131 } 1132 /* 1133 * Second part: skip past packets that userspace has released. 1134 * (kring->nr_hwcur to head excluded), 1135 * and make the buffers available for reception. 1136 * As usual nm_i is the index in the netmap ring, 1137 * nic_i is the index in the NIC ring, and 1138 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1139 */ 1140 /* XXX not sure how this will work with multiple free lists */ 1141 nm_i = kring->nr_hwcur; 1142 1143 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1144 } 1145 1146 static void 1147 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1148 { 1149 if_ctx_t ctx = na->ifp->if_softc; 1150 1151 CTX_LOCK(ctx); 1152 if (onoff) { 1153 IFDI_INTR_ENABLE(ctx); 1154 } else { 1155 IFDI_INTR_DISABLE(ctx); 1156 } 1157 CTX_UNLOCK(ctx); 1158 } 1159 1160 1161 static int 1162 iflib_netmap_attach(if_ctx_t ctx) 1163 { 1164 struct netmap_adapter na; 1165 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1166 1167 bzero(&na, sizeof(na)); 1168 1169 na.ifp = ctx->ifc_ifp; 1170 na.na_flags = NAF_BDG_MAYSLEEP; 1171 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1172 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1173 1174 na.num_tx_desc = scctx->isc_ntxd[0]; 1175 na.num_rx_desc = scctx->isc_nrxd[0]; 1176 na.nm_txsync = iflib_netmap_txsync; 1177 na.nm_rxsync = iflib_netmap_rxsync; 1178 na.nm_register = iflib_netmap_register; 1179 na.nm_intr = iflib_netmap_intr; 1180 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1181 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1182 return (netmap_attach(&na)); 1183 } 1184 1185 static void 1186 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1187 { 1188 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1189 struct netmap_slot *slot; 1190 1191 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1192 if (slot == NULL) 1193 return; 1194 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1195 1196 /* 1197 * In netmap mode, set the map for the packet buffer. 1198 * NOTE: Some drivers (not this one) also need to set 1199 * the physical buffer address in the NIC ring. 1200 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1201 * netmap slot index, si 1202 */ 1203 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1204 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1205 NMB(na, slot + si)); 1206 } 1207 } 1208 1209 static void 1210 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1211 { 1212 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1213 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1214 struct netmap_slot *slot; 1215 uint32_t nm_i; 1216 1217 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1218 if (slot == NULL) 1219 return; 1220 nm_i = netmap_idx_n2k(kring, 0); 1221 netmap_fl_refill(rxq, kring, nm_i, true); 1222 } 1223 1224 static void 1225 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1226 { 1227 struct netmap_kring *kring; 1228 uint16_t txqid; 1229 1230 txqid = txq->ift_id; 1231 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1232 1233 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1234 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1235 BUS_DMASYNC_POSTREAD); 1236 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1237 netmap_tx_irq(ctx->ifc_ifp, txqid); 1238 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1239 if (hz < 2000) 1240 *reset_on = 1; 1241 else 1242 *reset_on = hz / 1000; 1243 } 1244 } 1245 } 1246 1247 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1248 1249 #else 1250 #define iflib_netmap_txq_init(ctx, txq) 1251 #define iflib_netmap_rxq_init(ctx, rxq) 1252 #define iflib_netmap_detach(ifp) 1253 1254 #define iflib_netmap_attach(ctx) (0) 1255 #define netmap_rx_irq(ifp, qid, budget) (0) 1256 #define netmap_tx_irq(ifp, qid) do {} while (0) 1257 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1258 #endif 1259 1260 #if defined(__i386__) || defined(__amd64__) 1261 static __inline void 1262 prefetch(void *x) 1263 { 1264 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1265 } 1266 static __inline void 1267 prefetch2cachelines(void *x) 1268 { 1269 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1270 #if (CACHE_LINE_SIZE < 128) 1271 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1272 #endif 1273 } 1274 #else 1275 #define prefetch(x) 1276 #define prefetch2cachelines(x) 1277 #endif 1278 1279 static void 1280 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1281 { 1282 iflib_fl_t fl; 1283 1284 fl = &rxq->ifr_fl[flid]; 1285 iru->iru_paddrs = fl->ifl_bus_addrs; 1286 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1287 iru->iru_idxs = fl->ifl_rxd_idxs; 1288 iru->iru_qsidx = rxq->ifr_id; 1289 iru->iru_buf_size = fl->ifl_buf_size; 1290 iru->iru_flidx = fl->ifl_id; 1291 } 1292 1293 static void 1294 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1295 { 1296 if (err) 1297 return; 1298 *(bus_addr_t *) arg = segs[0].ds_addr; 1299 } 1300 1301 int 1302 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1303 { 1304 int err; 1305 device_t dev = ctx->ifc_dev; 1306 1307 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1308 align, 0, /* alignment, bounds */ 1309 BUS_SPACE_MAXADDR, /* lowaddr */ 1310 BUS_SPACE_MAXADDR, /* highaddr */ 1311 NULL, NULL, /* filter, filterarg */ 1312 size, /* maxsize */ 1313 1, /* nsegments */ 1314 size, /* maxsegsize */ 1315 BUS_DMA_ALLOCNOW, /* flags */ 1316 NULL, /* lockfunc */ 1317 NULL, /* lockarg */ 1318 &dma->idi_tag); 1319 if (err) { 1320 device_printf(dev, 1321 "%s: bus_dma_tag_create failed: %d\n", 1322 __func__, err); 1323 goto fail_0; 1324 } 1325 1326 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1327 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1328 if (err) { 1329 device_printf(dev, 1330 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1331 __func__, (uintmax_t)size, err); 1332 goto fail_1; 1333 } 1334 1335 dma->idi_paddr = IF_BAD_DMA; 1336 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1337 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1338 if (err || dma->idi_paddr == IF_BAD_DMA) { 1339 device_printf(dev, 1340 "%s: bus_dmamap_load failed: %d\n", 1341 __func__, err); 1342 goto fail_2; 1343 } 1344 1345 dma->idi_size = size; 1346 return (0); 1347 1348 fail_2: 1349 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1350 fail_1: 1351 bus_dma_tag_destroy(dma->idi_tag); 1352 fail_0: 1353 dma->idi_tag = NULL; 1354 1355 return (err); 1356 } 1357 1358 int 1359 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1360 { 1361 if_shared_ctx_t sctx = ctx->ifc_sctx; 1362 1363 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1364 1365 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1366 } 1367 1368 int 1369 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1370 { 1371 int i, err; 1372 iflib_dma_info_t *dmaiter; 1373 1374 dmaiter = dmalist; 1375 for (i = 0; i < count; i++, dmaiter++) { 1376 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1377 break; 1378 } 1379 if (err) 1380 iflib_dma_free_multi(dmalist, i); 1381 return (err); 1382 } 1383 1384 void 1385 iflib_dma_free(iflib_dma_info_t dma) 1386 { 1387 if (dma->idi_tag == NULL) 1388 return; 1389 if (dma->idi_paddr != IF_BAD_DMA) { 1390 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1391 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1392 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1393 dma->idi_paddr = IF_BAD_DMA; 1394 } 1395 if (dma->idi_vaddr != NULL) { 1396 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1397 dma->idi_vaddr = NULL; 1398 } 1399 bus_dma_tag_destroy(dma->idi_tag); 1400 dma->idi_tag = NULL; 1401 } 1402 1403 void 1404 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1405 { 1406 int i; 1407 iflib_dma_info_t *dmaiter = dmalist; 1408 1409 for (i = 0; i < count; i++, dmaiter++) 1410 iflib_dma_free(*dmaiter); 1411 } 1412 1413 #ifdef EARLY_AP_STARTUP 1414 static const int iflib_started = 1; 1415 #else 1416 /* 1417 * We used to abuse the smp_started flag to decide if the queues have been 1418 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1419 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1420 * is set. Run a SYSINIT() strictly after that to just set a usable 1421 * completion flag. 1422 */ 1423 1424 static int iflib_started; 1425 1426 static void 1427 iflib_record_started(void *arg) 1428 { 1429 iflib_started = 1; 1430 } 1431 1432 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1433 iflib_record_started, NULL); 1434 #endif 1435 1436 static int 1437 iflib_fast_intr(void *arg) 1438 { 1439 iflib_filter_info_t info = arg; 1440 struct grouptask *gtask = info->ifi_task; 1441 int result; 1442 1443 if (!iflib_started) 1444 return (FILTER_STRAY); 1445 1446 DBG_COUNTER_INC(fast_intrs); 1447 if (info->ifi_filter != NULL) { 1448 result = info->ifi_filter(info->ifi_filter_arg); 1449 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1450 return (result); 1451 } 1452 1453 GROUPTASK_ENQUEUE(gtask); 1454 return (FILTER_HANDLED); 1455 } 1456 1457 static int 1458 iflib_fast_intr_rxtx(void *arg) 1459 { 1460 iflib_filter_info_t info = arg; 1461 struct grouptask *gtask = info->ifi_task; 1462 if_ctx_t ctx; 1463 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1464 iflib_txq_t txq; 1465 void *sc; 1466 int i, cidx, result; 1467 qidx_t txqid; 1468 bool intr_enable, intr_legacy; 1469 1470 if (!iflib_started) 1471 return (FILTER_STRAY); 1472 1473 DBG_COUNTER_INC(fast_intrs); 1474 if (info->ifi_filter != NULL) { 1475 result = info->ifi_filter(info->ifi_filter_arg); 1476 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1477 return (result); 1478 } 1479 1480 ctx = rxq->ifr_ctx; 1481 sc = ctx->ifc_softc; 1482 intr_enable = false; 1483 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1484 MPASS(rxq->ifr_ntxqirq); 1485 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1486 txqid = rxq->ifr_txqid[i]; 1487 txq = &ctx->ifc_txqs[txqid]; 1488 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1489 BUS_DMASYNC_POSTREAD); 1490 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1491 if (intr_legacy) 1492 intr_enable = true; 1493 else 1494 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1495 continue; 1496 } 1497 GROUPTASK_ENQUEUE(&txq->ift_task); 1498 } 1499 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1500 cidx = rxq->ifr_cq_cidx; 1501 else 1502 cidx = rxq->ifr_fl[0].ifl_cidx; 1503 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1504 GROUPTASK_ENQUEUE(gtask); 1505 else { 1506 if (intr_legacy) 1507 intr_enable = true; 1508 else 1509 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1510 DBG_COUNTER_INC(rx_intr_enables); 1511 } 1512 if (intr_enable) 1513 IFDI_INTR_ENABLE(ctx); 1514 return (FILTER_HANDLED); 1515 } 1516 1517 1518 static int 1519 iflib_fast_intr_ctx(void *arg) 1520 { 1521 iflib_filter_info_t info = arg; 1522 struct grouptask *gtask = info->ifi_task; 1523 int result; 1524 1525 if (!iflib_started) 1526 return (FILTER_STRAY); 1527 1528 DBG_COUNTER_INC(fast_intrs); 1529 if (info->ifi_filter != NULL) { 1530 result = info->ifi_filter(info->ifi_filter_arg); 1531 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1532 return (result); 1533 } 1534 1535 GROUPTASK_ENQUEUE(gtask); 1536 return (FILTER_HANDLED); 1537 } 1538 1539 static int 1540 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1541 driver_filter_t filter, driver_intr_t handler, void *arg, 1542 const char *name) 1543 { 1544 struct resource *res; 1545 void *tag = NULL; 1546 device_t dev = ctx->ifc_dev; 1547 int flags, i, rc; 1548 1549 flags = RF_ACTIVE; 1550 if (ctx->ifc_flags & IFC_LEGACY) 1551 flags |= RF_SHAREABLE; 1552 MPASS(rid < 512); 1553 i = rid; 1554 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1555 if (res == NULL) { 1556 device_printf(dev, 1557 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1558 return (ENOMEM); 1559 } 1560 irq->ii_res = res; 1561 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1562 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1563 filter, handler, arg, &tag); 1564 if (rc != 0) { 1565 device_printf(dev, 1566 "failed to setup interrupt for rid %d, name %s: %d\n", 1567 rid, name ? name : "unknown", rc); 1568 return (rc); 1569 } else if (name) 1570 bus_describe_intr(dev, res, tag, "%s", name); 1571 1572 irq->ii_tag = tag; 1573 return (0); 1574 } 1575 1576 /********************************************************************* 1577 * 1578 * Allocate DMA resources for TX buffers as well as memory for the TX 1579 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1580 * iflib_sw_tx_desc_array structure, storing all the information that 1581 * is needed to transmit a packet on the wire. This is called only 1582 * once at attach, setup is done every reset. 1583 * 1584 **********************************************************************/ 1585 static int 1586 iflib_txsd_alloc(iflib_txq_t txq) 1587 { 1588 if_ctx_t ctx = txq->ift_ctx; 1589 if_shared_ctx_t sctx = ctx->ifc_sctx; 1590 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1591 device_t dev = ctx->ifc_dev; 1592 bus_size_t tsomaxsize; 1593 int err, nsegments, ntsosegments; 1594 bool tso; 1595 1596 nsegments = scctx->isc_tx_nsegments; 1597 ntsosegments = scctx->isc_tx_tso_segments_max; 1598 tsomaxsize = scctx->isc_tx_tso_size_max; 1599 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1600 tsomaxsize += sizeof(struct ether_vlan_header); 1601 MPASS(scctx->isc_ntxd[0] > 0); 1602 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1603 MPASS(nsegments > 0); 1604 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1605 MPASS(ntsosegments > 0); 1606 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1607 } 1608 1609 /* 1610 * Set up DMA tags for TX buffers. 1611 */ 1612 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1613 1, 0, /* alignment, bounds */ 1614 BUS_SPACE_MAXADDR, /* lowaddr */ 1615 BUS_SPACE_MAXADDR, /* highaddr */ 1616 NULL, NULL, /* filter, filterarg */ 1617 sctx->isc_tx_maxsize, /* maxsize */ 1618 nsegments, /* nsegments */ 1619 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1620 0, /* flags */ 1621 NULL, /* lockfunc */ 1622 NULL, /* lockfuncarg */ 1623 &txq->ift_buf_tag))) { 1624 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1625 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1626 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1627 goto fail; 1628 } 1629 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1630 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1631 1, 0, /* alignment, bounds */ 1632 BUS_SPACE_MAXADDR, /* lowaddr */ 1633 BUS_SPACE_MAXADDR, /* highaddr */ 1634 NULL, NULL, /* filter, filterarg */ 1635 tsomaxsize, /* maxsize */ 1636 ntsosegments, /* nsegments */ 1637 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1638 0, /* flags */ 1639 NULL, /* lockfunc */ 1640 NULL, /* lockfuncarg */ 1641 &txq->ift_tso_buf_tag))) { 1642 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1643 err); 1644 goto fail; 1645 } 1646 1647 /* Allocate memory for the TX mbuf map. */ 1648 if (!(txq->ift_sds.ifsd_m = 1649 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1650 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1651 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1652 err = ENOMEM; 1653 goto fail; 1654 } 1655 1656 /* 1657 * Create the DMA maps for TX buffers. 1658 */ 1659 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1660 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1661 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1662 device_printf(dev, 1663 "Unable to allocate TX buffer DMA map memory\n"); 1664 err = ENOMEM; 1665 goto fail; 1666 } 1667 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1668 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1669 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1670 device_printf(dev, 1671 "Unable to allocate TSO TX buffer map memory\n"); 1672 err = ENOMEM; 1673 goto fail; 1674 } 1675 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1676 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1677 &txq->ift_sds.ifsd_map[i]); 1678 if (err != 0) { 1679 device_printf(dev, "Unable to create TX DMA map\n"); 1680 goto fail; 1681 } 1682 if (!tso) 1683 continue; 1684 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1685 &txq->ift_sds.ifsd_tso_map[i]); 1686 if (err != 0) { 1687 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1688 goto fail; 1689 } 1690 } 1691 return (0); 1692 fail: 1693 /* We free all, it handles case where we are in the middle */ 1694 iflib_tx_structures_free(ctx); 1695 return (err); 1696 } 1697 1698 static void 1699 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1700 { 1701 bus_dmamap_t map; 1702 1703 if (txq->ift_sds.ifsd_map != NULL) { 1704 map = txq->ift_sds.ifsd_map[i]; 1705 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1706 bus_dmamap_unload(txq->ift_buf_tag, map); 1707 bus_dmamap_destroy(txq->ift_buf_tag, map); 1708 txq->ift_sds.ifsd_map[i] = NULL; 1709 } 1710 1711 if (txq->ift_sds.ifsd_tso_map != NULL) { 1712 map = txq->ift_sds.ifsd_tso_map[i]; 1713 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1714 BUS_DMASYNC_POSTWRITE); 1715 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1716 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1717 txq->ift_sds.ifsd_tso_map[i] = NULL; 1718 } 1719 } 1720 1721 static void 1722 iflib_txq_destroy(iflib_txq_t txq) 1723 { 1724 if_ctx_t ctx = txq->ift_ctx; 1725 1726 for (int i = 0; i < txq->ift_size; i++) 1727 iflib_txsd_destroy(ctx, txq, i); 1728 1729 if (txq->ift_br != NULL) { 1730 ifmp_ring_free(txq->ift_br); 1731 txq->ift_br = NULL; 1732 } 1733 1734 mtx_destroy(&txq->ift_mtx); 1735 1736 if (txq->ift_sds.ifsd_map != NULL) { 1737 free(txq->ift_sds.ifsd_map, M_IFLIB); 1738 txq->ift_sds.ifsd_map = NULL; 1739 } 1740 if (txq->ift_sds.ifsd_tso_map != NULL) { 1741 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1742 txq->ift_sds.ifsd_tso_map = NULL; 1743 } 1744 if (txq->ift_sds.ifsd_m != NULL) { 1745 free(txq->ift_sds.ifsd_m, M_IFLIB); 1746 txq->ift_sds.ifsd_m = NULL; 1747 } 1748 if (txq->ift_buf_tag != NULL) { 1749 bus_dma_tag_destroy(txq->ift_buf_tag); 1750 txq->ift_buf_tag = NULL; 1751 } 1752 if (txq->ift_tso_buf_tag != NULL) { 1753 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1754 txq->ift_tso_buf_tag = NULL; 1755 } 1756 if (txq->ift_ifdi != NULL) { 1757 free(txq->ift_ifdi, M_IFLIB); 1758 } 1759 } 1760 1761 static void 1762 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1763 { 1764 struct mbuf **mp; 1765 1766 mp = &txq->ift_sds.ifsd_m[i]; 1767 if (*mp == NULL) 1768 return; 1769 1770 if (txq->ift_sds.ifsd_map != NULL) { 1771 bus_dmamap_sync(txq->ift_buf_tag, 1772 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1773 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1774 } 1775 if (txq->ift_sds.ifsd_tso_map != NULL) { 1776 bus_dmamap_sync(txq->ift_tso_buf_tag, 1777 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1778 bus_dmamap_unload(txq->ift_tso_buf_tag, 1779 txq->ift_sds.ifsd_tso_map[i]); 1780 } 1781 m_free(*mp); 1782 DBG_COUNTER_INC(tx_frees); 1783 *mp = NULL; 1784 } 1785 1786 static int 1787 iflib_txq_setup(iflib_txq_t txq) 1788 { 1789 if_ctx_t ctx = txq->ift_ctx; 1790 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1791 if_shared_ctx_t sctx = ctx->ifc_sctx; 1792 iflib_dma_info_t di; 1793 int i; 1794 1795 /* Set number of descriptors available */ 1796 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1797 /* XXX make configurable */ 1798 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1799 1800 /* Reset indices */ 1801 txq->ift_cidx_processed = 0; 1802 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1803 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1804 1805 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1806 bzero((void *)di->idi_vaddr, di->idi_size); 1807 1808 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1809 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1810 bus_dmamap_sync(di->idi_tag, di->idi_map, 1811 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1812 return (0); 1813 } 1814 1815 /********************************************************************* 1816 * 1817 * Allocate DMA resources for RX buffers as well as memory for the RX 1818 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1819 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1820 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1821 * Since we use use one entry in iflib_sw_rx_desc_array per received 1822 * packet, the maximum number of entries we'll need is equal to the 1823 * number of hardware receive descriptors that we've allocated. 1824 * 1825 **********************************************************************/ 1826 static int 1827 iflib_rxsd_alloc(iflib_rxq_t rxq) 1828 { 1829 if_ctx_t ctx = rxq->ifr_ctx; 1830 if_shared_ctx_t sctx = ctx->ifc_sctx; 1831 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1832 device_t dev = ctx->ifc_dev; 1833 iflib_fl_t fl; 1834 int err; 1835 1836 MPASS(scctx->isc_nrxd[0] > 0); 1837 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1838 1839 fl = rxq->ifr_fl; 1840 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1841 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1842 /* Set up DMA tag for RX buffers. */ 1843 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1844 1, 0, /* alignment, bounds */ 1845 BUS_SPACE_MAXADDR, /* lowaddr */ 1846 BUS_SPACE_MAXADDR, /* highaddr */ 1847 NULL, NULL, /* filter, filterarg */ 1848 sctx->isc_rx_maxsize, /* maxsize */ 1849 sctx->isc_rx_nsegments, /* nsegments */ 1850 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1851 0, /* flags */ 1852 NULL, /* lockfunc */ 1853 NULL, /* lockarg */ 1854 &fl->ifl_buf_tag); 1855 if (err) { 1856 device_printf(dev, 1857 "Unable to allocate RX DMA tag: %d\n", err); 1858 goto fail; 1859 } 1860 1861 /* Allocate memory for the RX mbuf map. */ 1862 if (!(fl->ifl_sds.ifsd_m = 1863 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1864 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1865 device_printf(dev, 1866 "Unable to allocate RX mbuf map memory\n"); 1867 err = ENOMEM; 1868 goto fail; 1869 } 1870 1871 /* Allocate memory for the direct RX cluster pointer map. */ 1872 if (!(fl->ifl_sds.ifsd_cl = 1873 (caddr_t *) malloc(sizeof(caddr_t) * 1874 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1875 device_printf(dev, 1876 "Unable to allocate RX cluster map memory\n"); 1877 err = ENOMEM; 1878 goto fail; 1879 } 1880 1881 /* Allocate memory for the RX cluster bus address map. */ 1882 if (!(fl->ifl_sds.ifsd_ba = 1883 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1884 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1885 device_printf(dev, 1886 "Unable to allocate RX bus address map memory\n"); 1887 err = ENOMEM; 1888 goto fail; 1889 } 1890 1891 /* 1892 * Create the DMA maps for RX buffers. 1893 */ 1894 if (!(fl->ifl_sds.ifsd_map = 1895 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1896 device_printf(dev, 1897 "Unable to allocate RX buffer DMA map memory\n"); 1898 err = ENOMEM; 1899 goto fail; 1900 } 1901 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1902 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1903 &fl->ifl_sds.ifsd_map[i]); 1904 if (err != 0) { 1905 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1906 goto fail; 1907 } 1908 } 1909 } 1910 return (0); 1911 1912 fail: 1913 iflib_rx_structures_free(ctx); 1914 return (err); 1915 } 1916 1917 1918 /* 1919 * Internal service routines 1920 */ 1921 1922 struct rxq_refill_cb_arg { 1923 int error; 1924 bus_dma_segment_t seg; 1925 int nseg; 1926 }; 1927 1928 static void 1929 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1930 { 1931 struct rxq_refill_cb_arg *cb_arg = arg; 1932 1933 cb_arg->error = error; 1934 cb_arg->seg = segs[0]; 1935 cb_arg->nseg = nseg; 1936 } 1937 1938 /** 1939 * _iflib_fl_refill - refill an rxq free-buffer list 1940 * @ctx: the iflib context 1941 * @fl: the free list to refill 1942 * @count: the number of new buffers to allocate 1943 * 1944 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1945 * The caller must assure that @count does not exceed the queue's capacity. 1946 */ 1947 static uint8_t 1948 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1949 { 1950 struct if_rxd_update iru; 1951 struct rxq_refill_cb_arg cb_arg; 1952 struct mbuf *m; 1953 caddr_t cl, *sd_cl; 1954 struct mbuf **sd_m; 1955 bus_dmamap_t *sd_map; 1956 bus_addr_t bus_addr, *sd_ba; 1957 int err, frag_idx, i, idx, n, pidx; 1958 qidx_t credits; 1959 1960 sd_m = fl->ifl_sds.ifsd_m; 1961 sd_map = fl->ifl_sds.ifsd_map; 1962 sd_cl = fl->ifl_sds.ifsd_cl; 1963 sd_ba = fl->ifl_sds.ifsd_ba; 1964 pidx = fl->ifl_pidx; 1965 idx = pidx; 1966 frag_idx = fl->ifl_fragidx; 1967 credits = fl->ifl_credits; 1968 1969 i = 0; 1970 n = count; 1971 MPASS(n > 0); 1972 MPASS(credits + n <= fl->ifl_size); 1973 1974 if (pidx < fl->ifl_cidx) 1975 MPASS(pidx + n <= fl->ifl_cidx); 1976 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1977 MPASS(fl->ifl_gen == 0); 1978 if (pidx > fl->ifl_cidx) 1979 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1980 1981 DBG_COUNTER_INC(fl_refills); 1982 if (n > 8) 1983 DBG_COUNTER_INC(fl_refills_large); 1984 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1985 while (n--) { 1986 /* 1987 * We allocate an uninitialized mbuf + cluster, mbuf is 1988 * initialized after rx. 1989 * 1990 * If the cluster is still set then we know a minimum sized packet was received 1991 */ 1992 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1993 &frag_idx); 1994 if (frag_idx < 0) 1995 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1996 MPASS(frag_idx >= 0); 1997 if ((cl = sd_cl[frag_idx]) == NULL) { 1998 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1999 break; 2000 2001 cb_arg.error = 0; 2002 MPASS(sd_map != NULL); 2003 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2004 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2005 BUS_DMA_NOWAIT); 2006 if (err != 0 || cb_arg.error) { 2007 /* 2008 * !zone_pack ? 2009 */ 2010 if (fl->ifl_zone == zone_pack) 2011 uma_zfree(fl->ifl_zone, cl); 2012 break; 2013 } 2014 2015 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2016 sd_cl[frag_idx] = cl; 2017 #if MEMORY_LOGGING 2018 fl->ifl_cl_enqueued++; 2019 #endif 2020 } else { 2021 bus_addr = sd_ba[frag_idx]; 2022 } 2023 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2024 BUS_DMASYNC_PREREAD); 2025 2026 if (sd_m[frag_idx] == NULL) { 2027 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2028 break; 2029 } 2030 sd_m[frag_idx] = m; 2031 } 2032 bit_set(fl->ifl_rx_bitmap, frag_idx); 2033 #if MEMORY_LOGGING 2034 fl->ifl_m_enqueued++; 2035 #endif 2036 2037 DBG_COUNTER_INC(rx_allocs); 2038 fl->ifl_rxd_idxs[i] = frag_idx; 2039 fl->ifl_bus_addrs[i] = bus_addr; 2040 fl->ifl_vm_addrs[i] = cl; 2041 credits++; 2042 i++; 2043 MPASS(credits <= fl->ifl_size); 2044 if (++idx == fl->ifl_size) { 2045 fl->ifl_gen = 1; 2046 idx = 0; 2047 } 2048 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2049 iru.iru_pidx = pidx; 2050 iru.iru_count = i; 2051 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2052 i = 0; 2053 pidx = idx; 2054 fl->ifl_pidx = idx; 2055 fl->ifl_credits = credits; 2056 } 2057 } 2058 2059 if (i) { 2060 iru.iru_pidx = pidx; 2061 iru.iru_count = i; 2062 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2063 fl->ifl_pidx = idx; 2064 fl->ifl_credits = credits; 2065 } 2066 DBG_COUNTER_INC(rxd_flush); 2067 if (fl->ifl_pidx == 0) 2068 pidx = fl->ifl_size - 1; 2069 else 2070 pidx = fl->ifl_pidx - 1; 2071 2072 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2073 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2074 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2075 fl->ifl_fragidx = frag_idx; 2076 2077 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2078 } 2079 2080 static __inline uint8_t 2081 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2082 { 2083 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2084 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2085 #ifdef INVARIANTS 2086 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2087 #endif 2088 2089 MPASS(fl->ifl_credits <= fl->ifl_size); 2090 MPASS(reclaimable == delta); 2091 2092 if (reclaimable > 0) 2093 return (_iflib_fl_refill(ctx, fl, min(max, reclaimable))); 2094 return (0); 2095 } 2096 2097 uint8_t 2098 iflib_in_detach(if_ctx_t ctx) 2099 { 2100 bool in_detach; 2101 2102 STATE_LOCK(ctx); 2103 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2104 STATE_UNLOCK(ctx); 2105 return (in_detach); 2106 } 2107 2108 static void 2109 iflib_fl_bufs_free(iflib_fl_t fl) 2110 { 2111 iflib_dma_info_t idi = fl->ifl_ifdi; 2112 bus_dmamap_t sd_map; 2113 uint32_t i; 2114 2115 for (i = 0; i < fl->ifl_size; i++) { 2116 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2117 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2118 2119 if (*sd_cl != NULL) { 2120 sd_map = fl->ifl_sds.ifsd_map[i]; 2121 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2122 BUS_DMASYNC_POSTREAD); 2123 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2124 if (*sd_cl != NULL) 2125 uma_zfree(fl->ifl_zone, *sd_cl); 2126 if (*sd_m != NULL) { 2127 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2128 uma_zfree(zone_mbuf, *sd_m); 2129 } 2130 } else { 2131 MPASS(*sd_cl == NULL); 2132 MPASS(*sd_m == NULL); 2133 } 2134 #if MEMORY_LOGGING 2135 fl->ifl_m_dequeued++; 2136 fl->ifl_cl_dequeued++; 2137 #endif 2138 *sd_cl = NULL; 2139 *sd_m = NULL; 2140 } 2141 #ifdef INVARIANTS 2142 for (i = 0; i < fl->ifl_size; i++) { 2143 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2144 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2145 } 2146 #endif 2147 /* 2148 * Reset free list values 2149 */ 2150 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2151 bzero(idi->idi_vaddr, idi->idi_size); 2152 } 2153 2154 /********************************************************************* 2155 * 2156 * Initialize a free list and its buffers. 2157 * 2158 **********************************************************************/ 2159 static int 2160 iflib_fl_setup(iflib_fl_t fl) 2161 { 2162 iflib_rxq_t rxq = fl->ifl_rxq; 2163 if_ctx_t ctx = rxq->ifr_ctx; 2164 2165 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2166 /* 2167 ** Free current RX buffer structs and their mbufs 2168 */ 2169 iflib_fl_bufs_free(fl); 2170 /* Now replenish the mbufs */ 2171 MPASS(fl->ifl_credits == 0); 2172 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2173 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2174 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2175 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2176 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2177 2178 2179 /* avoid pre-allocating zillions of clusters to an idle card 2180 * potentially speeding up attach 2181 */ 2182 (void) _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2183 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2184 if (min(128, fl->ifl_size) != fl->ifl_credits) 2185 return (ENOBUFS); 2186 /* 2187 * handle failure 2188 */ 2189 MPASS(rxq != NULL); 2190 MPASS(fl->ifl_ifdi != NULL); 2191 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2192 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2193 return (0); 2194 } 2195 2196 /********************************************************************* 2197 * 2198 * Free receive ring data structures 2199 * 2200 **********************************************************************/ 2201 static void 2202 iflib_rx_sds_free(iflib_rxq_t rxq) 2203 { 2204 iflib_fl_t fl; 2205 int i, j; 2206 2207 if (rxq->ifr_fl != NULL) { 2208 for (i = 0; i < rxq->ifr_nfl; i++) { 2209 fl = &rxq->ifr_fl[i]; 2210 if (fl->ifl_buf_tag != NULL) { 2211 if (fl->ifl_sds.ifsd_map != NULL) { 2212 for (j = 0; j < fl->ifl_size; j++) { 2213 bus_dmamap_sync( 2214 fl->ifl_buf_tag, 2215 fl->ifl_sds.ifsd_map[j], 2216 BUS_DMASYNC_POSTREAD); 2217 bus_dmamap_unload( 2218 fl->ifl_buf_tag, 2219 fl->ifl_sds.ifsd_map[j]); 2220 bus_dmamap_destroy( 2221 fl->ifl_buf_tag, 2222 fl->ifl_sds.ifsd_map[j]); 2223 } 2224 } 2225 bus_dma_tag_destroy(fl->ifl_buf_tag); 2226 fl->ifl_buf_tag = NULL; 2227 } 2228 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2229 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2230 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2231 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2232 fl->ifl_sds.ifsd_m = NULL; 2233 fl->ifl_sds.ifsd_cl = NULL; 2234 fl->ifl_sds.ifsd_ba = NULL; 2235 fl->ifl_sds.ifsd_map = NULL; 2236 } 2237 free(rxq->ifr_fl, M_IFLIB); 2238 rxq->ifr_fl = NULL; 2239 free(rxq->ifr_ifdi, M_IFLIB); 2240 rxq->ifr_ifdi = NULL; 2241 rxq->ifr_cq_cidx = 0; 2242 } 2243 } 2244 2245 /* 2246 * Timer routine 2247 */ 2248 static void 2249 iflib_timer(void *arg) 2250 { 2251 iflib_txq_t txq = arg; 2252 if_ctx_t ctx = txq->ift_ctx; 2253 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2254 uint64_t this_tick = ticks; 2255 uint32_t reset_on = hz / 2; 2256 2257 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2258 return; 2259 2260 /* 2261 ** Check on the state of the TX queue(s), this 2262 ** can be done without the lock because its RO 2263 ** and the HUNG state will be static if set. 2264 */ 2265 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2266 txq->ift_last_timer_tick = this_tick; 2267 IFDI_TIMER(ctx, txq->ift_id); 2268 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2269 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2270 (sctx->isc_pause_frames == 0))) 2271 goto hung; 2272 2273 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2274 ifmp_ring_is_stalled(txq->ift_br)) { 2275 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down")); 2276 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2277 } 2278 txq->ift_cleaned_prev = txq->ift_cleaned; 2279 } 2280 #ifdef DEV_NETMAP 2281 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2282 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2283 #endif 2284 /* handle any laggards */ 2285 if (txq->ift_db_pending) 2286 GROUPTASK_ENQUEUE(&txq->ift_task); 2287 2288 sctx->isc_pause_frames = 0; 2289 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2290 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2291 return; 2292 2293 hung: 2294 device_printf(ctx->ifc_dev, 2295 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2296 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2297 STATE_LOCK(ctx); 2298 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2299 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2300 iflib_admin_intr_deferred(ctx); 2301 STATE_UNLOCK(ctx); 2302 } 2303 2304 static void 2305 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2306 { 2307 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2308 2309 /* 2310 * XXX don't set the max_frame_size to larger 2311 * than the hardware can handle 2312 */ 2313 if (sctx->isc_max_frame_size <= MCLBYTES) 2314 ctx->ifc_rx_mbuf_sz = MCLBYTES; 2315 else 2316 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE; 2317 } 2318 2319 uint32_t 2320 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2321 { 2322 2323 return (ctx->ifc_rx_mbuf_sz); 2324 } 2325 2326 static void 2327 iflib_init_locked(if_ctx_t ctx) 2328 { 2329 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2330 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2331 if_t ifp = ctx->ifc_ifp; 2332 iflib_fl_t fl; 2333 iflib_txq_t txq; 2334 iflib_rxq_t rxq; 2335 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2336 2337 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2338 IFDI_INTR_DISABLE(ctx); 2339 2340 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2341 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2342 /* Set hardware offload abilities */ 2343 if_clearhwassist(ifp); 2344 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2345 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2346 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2347 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2348 if (if_getcapenable(ifp) & IFCAP_TSO4) 2349 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2350 if (if_getcapenable(ifp) & IFCAP_TSO6) 2351 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2352 2353 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2354 CALLOUT_LOCK(txq); 2355 callout_stop(&txq->ift_timer); 2356 CALLOUT_UNLOCK(txq); 2357 iflib_netmap_txq_init(ctx, txq); 2358 } 2359 2360 /* 2361 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2362 * that drivers can use the value when setting up the hardware receive 2363 * buffers. 2364 */ 2365 iflib_calc_rx_mbuf_sz(ctx); 2366 2367 #ifdef INVARIANTS 2368 i = if_getdrvflags(ifp); 2369 #endif 2370 IFDI_INIT(ctx); 2371 MPASS(if_getdrvflags(ifp) == i); 2372 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2373 /* XXX this should really be done on a per-queue basis */ 2374 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2375 MPASS(rxq->ifr_id == i); 2376 iflib_netmap_rxq_init(ctx, rxq); 2377 continue; 2378 } 2379 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2380 if (iflib_fl_setup(fl)) { 2381 device_printf(ctx->ifc_dev, 2382 "setting up free list %d failed - " 2383 "check cluster settings\n", j); 2384 goto done; 2385 } 2386 } 2387 } 2388 done: 2389 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2390 IFDI_INTR_ENABLE(ctx); 2391 txq = ctx->ifc_txqs; 2392 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2393 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2394 txq->ift_timer.c_cpu); 2395 } 2396 2397 static int 2398 iflib_media_change(if_t ifp) 2399 { 2400 if_ctx_t ctx = if_getsoftc(ifp); 2401 int err; 2402 2403 CTX_LOCK(ctx); 2404 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2405 iflib_init_locked(ctx); 2406 CTX_UNLOCK(ctx); 2407 return (err); 2408 } 2409 2410 static void 2411 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2412 { 2413 if_ctx_t ctx = if_getsoftc(ifp); 2414 2415 CTX_LOCK(ctx); 2416 IFDI_UPDATE_ADMIN_STATUS(ctx); 2417 IFDI_MEDIA_STATUS(ctx, ifmr); 2418 CTX_UNLOCK(ctx); 2419 } 2420 2421 void 2422 iflib_stop(if_ctx_t ctx) 2423 { 2424 iflib_txq_t txq = ctx->ifc_txqs; 2425 iflib_rxq_t rxq = ctx->ifc_rxqs; 2426 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2427 if_shared_ctx_t sctx = ctx->ifc_sctx; 2428 iflib_dma_info_t di; 2429 iflib_fl_t fl; 2430 int i, j; 2431 2432 /* Tell the stack that the interface is no longer active */ 2433 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2434 2435 IFDI_INTR_DISABLE(ctx); 2436 DELAY(1000); 2437 IFDI_STOP(ctx); 2438 DELAY(1000); 2439 2440 iflib_debug_reset(); 2441 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2442 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2443 /* make sure all transmitters have completed before proceeding XXX */ 2444 2445 CALLOUT_LOCK(txq); 2446 callout_stop(&txq->ift_timer); 2447 CALLOUT_UNLOCK(txq); 2448 2449 /* clean any enqueued buffers */ 2450 iflib_ifmp_purge(txq); 2451 /* Free any existing tx buffers. */ 2452 for (j = 0; j < txq->ift_size; j++) { 2453 iflib_txsd_free(ctx, txq, j); 2454 } 2455 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2456 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2457 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2458 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2459 txq->ift_pullups = 0; 2460 ifmp_ring_reset_stats(txq->ift_br); 2461 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2462 bzero((void *)di->idi_vaddr, di->idi_size); 2463 } 2464 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2465 /* make sure all transmitters have completed before proceeding XXX */ 2466 2467 rxq->ifr_cq_cidx = 0; 2468 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2469 bzero((void *)di->idi_vaddr, di->idi_size); 2470 /* also resets the free lists pidx/cidx */ 2471 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2472 iflib_fl_bufs_free(fl); 2473 } 2474 } 2475 2476 static inline caddr_t 2477 calc_next_rxd(iflib_fl_t fl, int cidx) 2478 { 2479 qidx_t size; 2480 int nrxd; 2481 caddr_t start, end, cur, next; 2482 2483 nrxd = fl->ifl_size; 2484 size = fl->ifl_rxd_size; 2485 start = fl->ifl_ifdi->idi_vaddr; 2486 2487 if (__predict_false(size == 0)) 2488 return (start); 2489 cur = start + size*cidx; 2490 end = start + size*nrxd; 2491 next = CACHE_PTR_NEXT(cur); 2492 return (next < end ? next : start); 2493 } 2494 2495 static inline void 2496 prefetch_pkts(iflib_fl_t fl, int cidx) 2497 { 2498 int nextptr; 2499 int nrxd = fl->ifl_size; 2500 caddr_t next_rxd; 2501 2502 2503 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2504 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2505 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2506 next_rxd = calc_next_rxd(fl, cidx); 2507 prefetch(next_rxd); 2508 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2509 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2510 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2511 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2512 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2513 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2514 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2515 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2516 } 2517 2518 static struct mbuf * 2519 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2520 int *pf_rv, if_rxd_info_t ri) 2521 { 2522 bus_dmamap_t map; 2523 iflib_fl_t fl; 2524 caddr_t payload; 2525 struct mbuf *m; 2526 int flid, cidx, len, next; 2527 2528 map = NULL; 2529 flid = irf->irf_flid; 2530 cidx = irf->irf_idx; 2531 fl = &rxq->ifr_fl[flid]; 2532 sd->ifsd_fl = fl; 2533 sd->ifsd_cidx = cidx; 2534 m = fl->ifl_sds.ifsd_m[cidx]; 2535 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2536 fl->ifl_credits--; 2537 #if MEMORY_LOGGING 2538 fl->ifl_m_dequeued++; 2539 #endif 2540 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2541 prefetch_pkts(fl, cidx); 2542 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2543 prefetch(&fl->ifl_sds.ifsd_map[next]); 2544 map = fl->ifl_sds.ifsd_map[cidx]; 2545 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2546 2547 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2548 MPASS(fl->ifl_cidx == cidx); 2549 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2550 2551 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) { 2552 payload = *sd->ifsd_cl; 2553 payload += ri->iri_pad; 2554 len = ri->iri_len - ri->iri_pad; 2555 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2556 len | PFIL_MEMPTR | PFIL_IN, NULL); 2557 switch (*pf_rv) { 2558 case PFIL_DROPPED: 2559 case PFIL_CONSUMED: 2560 /* 2561 * The filter ate it. Everything is recycled. 2562 */ 2563 m = NULL; 2564 unload = 0; 2565 break; 2566 case PFIL_REALLOCED: 2567 /* 2568 * The filter copied it. Everything is recycled. 2569 */ 2570 m = pfil_mem2mbuf(payload); 2571 unload = 0; 2572 break; 2573 case PFIL_PASS: 2574 /* 2575 * Filter said it was OK, so receive like 2576 * normal 2577 */ 2578 fl->ifl_sds.ifsd_m[cidx] = NULL; 2579 break; 2580 default: 2581 MPASS(0); 2582 } 2583 } else { 2584 fl->ifl_sds.ifsd_m[cidx] = NULL; 2585 *pf_rv = PFIL_PASS; 2586 } 2587 2588 if (unload) 2589 bus_dmamap_unload(fl->ifl_buf_tag, map); 2590 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2591 if (__predict_false(fl->ifl_cidx == 0)) 2592 fl->ifl_gen = 0; 2593 bit_clear(fl->ifl_rx_bitmap, cidx); 2594 return (m); 2595 } 2596 2597 static struct mbuf * 2598 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2599 { 2600 struct mbuf *m, *mh, *mt; 2601 caddr_t cl; 2602 int *pf_rv_ptr, flags, i, padlen; 2603 bool consumed; 2604 2605 i = 0; 2606 mh = NULL; 2607 consumed = false; 2608 *pf_rv = PFIL_PASS; 2609 pf_rv_ptr = pf_rv; 2610 do { 2611 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2612 pf_rv_ptr, ri); 2613 2614 MPASS(*sd->ifsd_cl != NULL); 2615 2616 /* 2617 * Exclude zero-length frags & frags from 2618 * packets the filter has consumed or dropped 2619 */ 2620 if (ri->iri_frags[i].irf_len == 0 || consumed || 2621 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2622 if (mh == NULL) { 2623 /* everything saved here */ 2624 consumed = true; 2625 pf_rv_ptr = NULL; 2626 continue; 2627 } 2628 /* XXX we can save the cluster here, but not the mbuf */ 2629 m_init(m, M_NOWAIT, MT_DATA, 0); 2630 m_free(m); 2631 continue; 2632 } 2633 if (mh == NULL) { 2634 flags = M_PKTHDR|M_EXT; 2635 mh = mt = m; 2636 padlen = ri->iri_pad; 2637 } else { 2638 flags = M_EXT; 2639 mt->m_next = m; 2640 mt = m; 2641 /* assuming padding is only on the first fragment */ 2642 padlen = 0; 2643 } 2644 cl = *sd->ifsd_cl; 2645 *sd->ifsd_cl = NULL; 2646 2647 /* Can these two be made one ? */ 2648 m_init(m, M_NOWAIT, MT_DATA, flags); 2649 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2650 /* 2651 * These must follow m_init and m_cljset 2652 */ 2653 m->m_data += padlen; 2654 ri->iri_len -= padlen; 2655 m->m_len = ri->iri_frags[i].irf_len; 2656 } while (++i < ri->iri_nfrags); 2657 2658 return (mh); 2659 } 2660 2661 /* 2662 * Process one software descriptor 2663 */ 2664 static struct mbuf * 2665 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2666 { 2667 struct if_rxsd sd; 2668 struct mbuf *m; 2669 int pf_rv; 2670 2671 /* should I merge this back in now that the two paths are basically duplicated? */ 2672 if (ri->iri_nfrags == 1 && 2673 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2674 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2675 &pf_rv, ri); 2676 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2677 return (m); 2678 if (pf_rv == PFIL_PASS) { 2679 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2680 #ifndef __NO_STRICT_ALIGNMENT 2681 if (!IP_ALIGNED(m)) 2682 m->m_data += 2; 2683 #endif 2684 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2685 m->m_len = ri->iri_frags[0].irf_len; 2686 } 2687 } else { 2688 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2689 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2690 return (m); 2691 } 2692 m->m_pkthdr.len = ri->iri_len; 2693 m->m_pkthdr.rcvif = ri->iri_ifp; 2694 m->m_flags |= ri->iri_flags; 2695 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2696 m->m_pkthdr.flowid = ri->iri_flowid; 2697 M_HASHTYPE_SET(m, ri->iri_rsstype); 2698 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2699 m->m_pkthdr.csum_data = ri->iri_csum_data; 2700 return (m); 2701 } 2702 2703 #if defined(INET6) || defined(INET) 2704 static void 2705 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2706 { 2707 CURVNET_SET(lc->ifp->if_vnet); 2708 #if defined(INET6) 2709 *v6 = V_ip6_forwarding; 2710 #endif 2711 #if defined(INET) 2712 *v4 = V_ipforwarding; 2713 #endif 2714 CURVNET_RESTORE(); 2715 } 2716 2717 /* 2718 * Returns true if it's possible this packet could be LROed. 2719 * if it returns false, it is guaranteed that tcp_lro_rx() 2720 * would not return zero. 2721 */ 2722 static bool 2723 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2724 { 2725 struct ether_header *eh; 2726 2727 eh = mtod(m, struct ether_header *); 2728 switch (eh->ether_type) { 2729 #if defined(INET6) 2730 case htons(ETHERTYPE_IPV6): 2731 return (!v6_forwarding); 2732 #endif 2733 #if defined (INET) 2734 case htons(ETHERTYPE_IP): 2735 return (!v4_forwarding); 2736 #endif 2737 } 2738 2739 return false; 2740 } 2741 #else 2742 static void 2743 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2744 { 2745 } 2746 #endif 2747 2748 static void 2749 _task_fn_rx_watchdog(void *context) 2750 { 2751 iflib_rxq_t rxq = context; 2752 2753 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2754 } 2755 2756 static uint8_t 2757 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2758 { 2759 if_t ifp; 2760 if_ctx_t ctx = rxq->ifr_ctx; 2761 if_shared_ctx_t sctx = ctx->ifc_sctx; 2762 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2763 int avail, i; 2764 qidx_t *cidxp; 2765 struct if_rxd_info ri; 2766 int err, budget_left, rx_bytes, rx_pkts; 2767 iflib_fl_t fl; 2768 int lro_enabled; 2769 bool v4_forwarding, v6_forwarding, lro_possible; 2770 uint8_t retval = 0; 2771 2772 /* 2773 * XXX early demux data packets so that if_input processing only handles 2774 * acks in interrupt context 2775 */ 2776 struct mbuf *m, *mh, *mt, *mf; 2777 2778 NET_EPOCH_ASSERT(); 2779 2780 lro_possible = v4_forwarding = v6_forwarding = false; 2781 ifp = ctx->ifc_ifp; 2782 mh = mt = NULL; 2783 MPASS(budget > 0); 2784 rx_pkts = rx_bytes = 0; 2785 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2786 cidxp = &rxq->ifr_cq_cidx; 2787 else 2788 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2789 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2790 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2791 retval |= __iflib_fl_refill_lt(ctx, fl, budget + 8); 2792 DBG_COUNTER_INC(rx_unavail); 2793 return (retval); 2794 } 2795 2796 /* pfil needs the vnet to be set */ 2797 CURVNET_SET_QUIET(ifp->if_vnet); 2798 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2799 if (__predict_false(!CTX_ACTIVE(ctx))) { 2800 DBG_COUNTER_INC(rx_ctx_inactive); 2801 break; 2802 } 2803 /* 2804 * Reset client set fields to their default values 2805 */ 2806 rxd_info_zero(&ri); 2807 ri.iri_qsidx = rxq->ifr_id; 2808 ri.iri_cidx = *cidxp; 2809 ri.iri_ifp = ifp; 2810 ri.iri_frags = rxq->ifr_frags; 2811 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2812 2813 if (err) 2814 goto err; 2815 rx_pkts += 1; 2816 rx_bytes += ri.iri_len; 2817 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2818 *cidxp = ri.iri_cidx; 2819 /* Update our consumer index */ 2820 /* XXX NB: shurd - check if this is still safe */ 2821 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2822 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2823 /* was this only a completion queue message? */ 2824 if (__predict_false(ri.iri_nfrags == 0)) 2825 continue; 2826 } 2827 MPASS(ri.iri_nfrags != 0); 2828 MPASS(ri.iri_len != 0); 2829 2830 /* will advance the cidx on the corresponding free lists */ 2831 m = iflib_rxd_pkt_get(rxq, &ri); 2832 avail--; 2833 budget_left--; 2834 if (avail == 0 && budget_left) 2835 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2836 2837 if (__predict_false(m == NULL)) 2838 continue; 2839 2840 /* imm_pkt: -- cxgb */ 2841 if (mh == NULL) 2842 mh = mt = m; 2843 else { 2844 mt->m_nextpkt = m; 2845 mt = m; 2846 } 2847 } 2848 CURVNET_RESTORE(); 2849 /* make sure that we can refill faster than drain */ 2850 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2851 retval |= __iflib_fl_refill_lt(ctx, fl, budget + 8); 2852 2853 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2854 if (lro_enabled) 2855 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2856 mt = mf = NULL; 2857 while (mh != NULL) { 2858 m = mh; 2859 mh = mh->m_nextpkt; 2860 m->m_nextpkt = NULL; 2861 #ifndef __NO_STRICT_ALIGNMENT 2862 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2863 continue; 2864 #endif 2865 rx_bytes += m->m_pkthdr.len; 2866 rx_pkts++; 2867 #if defined(INET6) || defined(INET) 2868 if (lro_enabled) { 2869 if (!lro_possible) { 2870 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2871 if (lro_possible && mf != NULL) { 2872 ifp->if_input(ifp, mf); 2873 DBG_COUNTER_INC(rx_if_input); 2874 mt = mf = NULL; 2875 } 2876 } 2877 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2878 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2879 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2880 continue; 2881 } 2882 } 2883 #endif 2884 if (lro_possible) { 2885 ifp->if_input(ifp, m); 2886 DBG_COUNTER_INC(rx_if_input); 2887 continue; 2888 } 2889 2890 if (mf == NULL) 2891 mf = m; 2892 if (mt != NULL) 2893 mt->m_nextpkt = m; 2894 mt = m; 2895 } 2896 if (mf != NULL) { 2897 ifp->if_input(ifp, mf); 2898 DBG_COUNTER_INC(rx_if_input); 2899 } 2900 2901 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2902 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2903 2904 /* 2905 * Flush any outstanding LRO work 2906 */ 2907 #if defined(INET6) || defined(INET) 2908 tcp_lro_flush_all(&rxq->ifr_lc); 2909 #endif 2910 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 2911 retval |= IFLIB_RXEOF_MORE; 2912 return (retval); 2913 err: 2914 STATE_LOCK(ctx); 2915 ctx->ifc_flags |= IFC_DO_RESET; 2916 iflib_admin_intr_deferred(ctx); 2917 STATE_UNLOCK(ctx); 2918 return (0); 2919 } 2920 2921 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2922 static inline qidx_t 2923 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2924 { 2925 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2926 qidx_t minthresh = txq->ift_size / 8; 2927 if (in_use > 4*minthresh) 2928 return (notify_count); 2929 if (in_use > 2*minthresh) 2930 return (notify_count >> 1); 2931 if (in_use > minthresh) 2932 return (notify_count >> 3); 2933 return (0); 2934 } 2935 2936 static inline qidx_t 2937 txq_max_rs_deferred(iflib_txq_t txq) 2938 { 2939 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2940 qidx_t minthresh = txq->ift_size / 8; 2941 if (txq->ift_in_use > 4*minthresh) 2942 return (notify_count); 2943 if (txq->ift_in_use > 2*minthresh) 2944 return (notify_count >> 1); 2945 if (txq->ift_in_use > minthresh) 2946 return (notify_count >> 2); 2947 return (2); 2948 } 2949 2950 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2951 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2952 2953 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2954 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2955 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2956 2957 /* forward compatibility for cxgb */ 2958 #define FIRST_QSET(ctx) 0 2959 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2960 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2961 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2962 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2963 2964 /* XXX we should be setting this to something other than zero */ 2965 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2966 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2967 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2968 2969 static inline bool 2970 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2971 { 2972 qidx_t dbval, max; 2973 bool rang; 2974 2975 rang = false; 2976 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2977 if (ring || txq->ift_db_pending >= max) { 2978 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2979 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2980 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2981 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2982 txq->ift_db_pending = txq->ift_npending = 0; 2983 rang = true; 2984 } 2985 return (rang); 2986 } 2987 2988 #ifdef PKT_DEBUG 2989 static void 2990 print_pkt(if_pkt_info_t pi) 2991 { 2992 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2993 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2994 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2995 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2996 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2997 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2998 } 2999 #endif 3000 3001 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3002 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3003 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3004 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3005 3006 static int 3007 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3008 { 3009 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3010 struct ether_vlan_header *eh; 3011 struct mbuf *m; 3012 3013 m = *mp; 3014 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3015 M_WRITABLE(m) == 0) { 3016 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3017 return (ENOMEM); 3018 } else { 3019 m_freem(*mp); 3020 DBG_COUNTER_INC(tx_frees); 3021 *mp = m; 3022 } 3023 } 3024 3025 /* 3026 * Determine where frame payload starts. 3027 * Jump over vlan headers if already present, 3028 * helpful for QinQ too. 3029 */ 3030 if (__predict_false(m->m_len < sizeof(*eh))) { 3031 txq->ift_pullups++; 3032 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3033 return (ENOMEM); 3034 } 3035 eh = mtod(m, struct ether_vlan_header *); 3036 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3037 pi->ipi_etype = ntohs(eh->evl_proto); 3038 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3039 } else { 3040 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3041 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3042 } 3043 3044 switch (pi->ipi_etype) { 3045 #ifdef INET 3046 case ETHERTYPE_IP: 3047 { 3048 struct mbuf *n; 3049 struct ip *ip = NULL; 3050 struct tcphdr *th = NULL; 3051 int minthlen; 3052 3053 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3054 if (__predict_false(m->m_len < minthlen)) { 3055 /* 3056 * if this code bloat is causing too much of a hit 3057 * move it to a separate function and mark it noinline 3058 */ 3059 if (m->m_len == pi->ipi_ehdrlen) { 3060 n = m->m_next; 3061 MPASS(n); 3062 if (n->m_len >= sizeof(*ip)) { 3063 ip = (struct ip *)n->m_data; 3064 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3065 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3066 } else { 3067 txq->ift_pullups++; 3068 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3069 return (ENOMEM); 3070 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3071 } 3072 } else { 3073 txq->ift_pullups++; 3074 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3075 return (ENOMEM); 3076 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3077 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3078 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3079 } 3080 } else { 3081 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3082 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3083 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3084 } 3085 pi->ipi_ip_hlen = ip->ip_hl << 2; 3086 pi->ipi_ipproto = ip->ip_p; 3087 pi->ipi_flags |= IPI_TX_IPV4; 3088 3089 /* TCP checksum offload may require TCP header length */ 3090 if (IS_TX_OFFLOAD4(pi)) { 3091 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3092 if (__predict_false(th == NULL)) { 3093 txq->ift_pullups++; 3094 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3095 return (ENOMEM); 3096 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3097 } 3098 pi->ipi_tcp_hflags = th->th_flags; 3099 pi->ipi_tcp_hlen = th->th_off << 2; 3100 pi->ipi_tcp_seq = th->th_seq; 3101 } 3102 if (IS_TSO4(pi)) { 3103 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3104 return (ENXIO); 3105 /* 3106 * TSO always requires hardware checksum offload. 3107 */ 3108 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3109 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3110 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3111 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3112 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3113 ip->ip_sum = 0; 3114 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3115 } 3116 } 3117 } 3118 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3119 ip->ip_sum = 0; 3120 3121 break; 3122 } 3123 #endif 3124 #ifdef INET6 3125 case ETHERTYPE_IPV6: 3126 { 3127 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3128 struct tcphdr *th; 3129 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3130 3131 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3132 txq->ift_pullups++; 3133 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3134 return (ENOMEM); 3135 } 3136 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3137 3138 /* XXX-BZ this will go badly in case of ext hdrs. */ 3139 pi->ipi_ipproto = ip6->ip6_nxt; 3140 pi->ipi_flags |= IPI_TX_IPV6; 3141 3142 /* TCP checksum offload may require TCP header length */ 3143 if (IS_TX_OFFLOAD6(pi)) { 3144 if (pi->ipi_ipproto == IPPROTO_TCP) { 3145 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3146 txq->ift_pullups++; 3147 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3148 return (ENOMEM); 3149 } 3150 pi->ipi_tcp_hflags = th->th_flags; 3151 pi->ipi_tcp_hlen = th->th_off << 2; 3152 pi->ipi_tcp_seq = th->th_seq; 3153 } 3154 if (IS_TSO6(pi)) { 3155 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3156 return (ENXIO); 3157 /* 3158 * TSO always requires hardware checksum offload. 3159 */ 3160 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3161 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3162 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3163 } 3164 } 3165 break; 3166 } 3167 #endif 3168 default: 3169 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3170 pi->ipi_ip_hlen = 0; 3171 break; 3172 } 3173 *mp = m; 3174 3175 return (0); 3176 } 3177 3178 /* 3179 * If dodgy hardware rejects the scatter gather chain we've handed it 3180 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3181 * m_defrag'd mbufs 3182 */ 3183 static __noinline struct mbuf * 3184 iflib_remove_mbuf(iflib_txq_t txq) 3185 { 3186 int ntxd, pidx; 3187 struct mbuf *m, **ifsd_m; 3188 3189 ifsd_m = txq->ift_sds.ifsd_m; 3190 ntxd = txq->ift_size; 3191 pidx = txq->ift_pidx & (ntxd - 1); 3192 ifsd_m = txq->ift_sds.ifsd_m; 3193 m = ifsd_m[pidx]; 3194 ifsd_m[pidx] = NULL; 3195 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3196 if (txq->ift_sds.ifsd_tso_map != NULL) 3197 bus_dmamap_unload(txq->ift_tso_buf_tag, 3198 txq->ift_sds.ifsd_tso_map[pidx]); 3199 #if MEMORY_LOGGING 3200 txq->ift_dequeued++; 3201 #endif 3202 return (m); 3203 } 3204 3205 static inline caddr_t 3206 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3207 { 3208 qidx_t size; 3209 int ntxd; 3210 caddr_t start, end, cur, next; 3211 3212 ntxd = txq->ift_size; 3213 size = txq->ift_txd_size[qid]; 3214 start = txq->ift_ifdi[qid].idi_vaddr; 3215 3216 if (__predict_false(size == 0)) 3217 return (start); 3218 cur = start + size*cidx; 3219 end = start + size*ntxd; 3220 next = CACHE_PTR_NEXT(cur); 3221 return (next < end ? next : start); 3222 } 3223 3224 /* 3225 * Pad an mbuf to ensure a minimum ethernet frame size. 3226 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3227 */ 3228 static __noinline int 3229 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3230 { 3231 /* 3232 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3233 * and ARP message is the smallest common payload I can think of 3234 */ 3235 static char pad[18]; /* just zeros */ 3236 int n; 3237 struct mbuf *new_head; 3238 3239 if (!M_WRITABLE(*m_head)) { 3240 new_head = m_dup(*m_head, M_NOWAIT); 3241 if (new_head == NULL) { 3242 m_freem(*m_head); 3243 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3244 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3245 DBG_COUNTER_INC(tx_frees); 3246 return ENOMEM; 3247 } 3248 m_freem(*m_head); 3249 *m_head = new_head; 3250 } 3251 3252 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3253 n > 0; n -= sizeof(pad)) 3254 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3255 break; 3256 3257 if (n > 0) { 3258 m_freem(*m_head); 3259 device_printf(dev, "cannot pad short frame\n"); 3260 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3261 DBG_COUNTER_INC(tx_frees); 3262 return (ENOBUFS); 3263 } 3264 3265 return 0; 3266 } 3267 3268 static int 3269 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3270 { 3271 if_ctx_t ctx; 3272 if_shared_ctx_t sctx; 3273 if_softc_ctx_t scctx; 3274 bus_dma_tag_t buf_tag; 3275 bus_dma_segment_t *segs; 3276 struct mbuf *m_head, **ifsd_m; 3277 void *next_txd; 3278 bus_dmamap_t map; 3279 struct if_pkt_info pi; 3280 int remap = 0; 3281 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3282 3283 ctx = txq->ift_ctx; 3284 sctx = ctx->ifc_sctx; 3285 scctx = &ctx->ifc_softc_ctx; 3286 segs = txq->ift_segs; 3287 ntxd = txq->ift_size; 3288 m_head = *m_headp; 3289 map = NULL; 3290 3291 /* 3292 * If we're doing TSO the next descriptor to clean may be quite far ahead 3293 */ 3294 cidx = txq->ift_cidx; 3295 pidx = txq->ift_pidx; 3296 if (ctx->ifc_flags & IFC_PREFETCH) { 3297 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3298 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3299 next_txd = calc_next_txd(txq, cidx, 0); 3300 prefetch(next_txd); 3301 } 3302 3303 /* prefetch the next cache line of mbuf pointers and flags */ 3304 prefetch(&txq->ift_sds.ifsd_m[next]); 3305 prefetch(&txq->ift_sds.ifsd_map[next]); 3306 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3307 } 3308 map = txq->ift_sds.ifsd_map[pidx]; 3309 ifsd_m = txq->ift_sds.ifsd_m; 3310 3311 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3312 buf_tag = txq->ift_tso_buf_tag; 3313 max_segs = scctx->isc_tx_tso_segments_max; 3314 map = txq->ift_sds.ifsd_tso_map[pidx]; 3315 MPASS(buf_tag != NULL); 3316 MPASS(max_segs > 0); 3317 } else { 3318 buf_tag = txq->ift_buf_tag; 3319 max_segs = scctx->isc_tx_nsegments; 3320 map = txq->ift_sds.ifsd_map[pidx]; 3321 } 3322 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3323 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3324 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3325 if (err) { 3326 DBG_COUNTER_INC(encap_txd_encap_fail); 3327 return err; 3328 } 3329 } 3330 m_head = *m_headp; 3331 3332 pkt_info_zero(&pi); 3333 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3334 pi.ipi_pidx = pidx; 3335 pi.ipi_qsidx = txq->ift_id; 3336 pi.ipi_len = m_head->m_pkthdr.len; 3337 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3338 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3339 3340 /* deliberate bitwise OR to make one condition */ 3341 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3342 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3343 DBG_COUNTER_INC(encap_txd_encap_fail); 3344 return (err); 3345 } 3346 m_head = *m_headp; 3347 } 3348 3349 retry: 3350 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3351 BUS_DMA_NOWAIT); 3352 defrag: 3353 if (__predict_false(err)) { 3354 switch (err) { 3355 case EFBIG: 3356 /* try collapse once and defrag once */ 3357 if (remap == 0) { 3358 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3359 /* try defrag if collapsing fails */ 3360 if (m_head == NULL) 3361 remap++; 3362 } 3363 if (remap == 1) { 3364 txq->ift_mbuf_defrag++; 3365 m_head = m_defrag(*m_headp, M_NOWAIT); 3366 } 3367 /* 3368 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3369 * failed to map an mbuf that was run through m_defrag 3370 */ 3371 MPASS(remap <= 1); 3372 if (__predict_false(m_head == NULL || remap > 1)) 3373 goto defrag_failed; 3374 remap++; 3375 *m_headp = m_head; 3376 goto retry; 3377 break; 3378 case ENOMEM: 3379 txq->ift_no_tx_dma_setup++; 3380 break; 3381 default: 3382 txq->ift_no_tx_dma_setup++; 3383 m_freem(*m_headp); 3384 DBG_COUNTER_INC(tx_frees); 3385 *m_headp = NULL; 3386 break; 3387 } 3388 txq->ift_map_failed++; 3389 DBG_COUNTER_INC(encap_load_mbuf_fail); 3390 DBG_COUNTER_INC(encap_txd_encap_fail); 3391 return (err); 3392 } 3393 ifsd_m[pidx] = m_head; 3394 /* 3395 * XXX assumes a 1 to 1 relationship between segments and 3396 * descriptors - this does not hold true on all drivers, e.g. 3397 * cxgb 3398 */ 3399 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3400 txq->ift_no_desc_avail++; 3401 bus_dmamap_unload(buf_tag, map); 3402 DBG_COUNTER_INC(encap_txq_avail_fail); 3403 DBG_COUNTER_INC(encap_txd_encap_fail); 3404 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3405 GROUPTASK_ENQUEUE(&txq->ift_task); 3406 return (ENOBUFS); 3407 } 3408 /* 3409 * On Intel cards we can greatly reduce the number of TX interrupts 3410 * we see by only setting report status on every Nth descriptor. 3411 * However, this also means that the driver will need to keep track 3412 * of the descriptors that RS was set on to check them for the DD bit. 3413 */ 3414 txq->ift_rs_pending += nsegs + 1; 3415 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3416 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3417 pi.ipi_flags |= IPI_TX_INTR; 3418 txq->ift_rs_pending = 0; 3419 } 3420 3421 pi.ipi_segs = segs; 3422 pi.ipi_nsegs = nsegs; 3423 3424 MPASS(pidx >= 0 && pidx < txq->ift_size); 3425 #ifdef PKT_DEBUG 3426 print_pkt(&pi); 3427 #endif 3428 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3429 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3430 DBG_COUNTER_INC(tx_encap); 3431 MPASS(pi.ipi_new_pidx < txq->ift_size); 3432 3433 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3434 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3435 ndesc += txq->ift_size; 3436 txq->ift_gen = 1; 3437 } 3438 /* 3439 * drivers can need as many as 3440 * two sentinels 3441 */ 3442 MPASS(ndesc <= pi.ipi_nsegs + 2); 3443 MPASS(pi.ipi_new_pidx != pidx); 3444 MPASS(ndesc > 0); 3445 txq->ift_in_use += ndesc; 3446 3447 /* 3448 * We update the last software descriptor again here because there may 3449 * be a sentinel and/or there may be more mbufs than segments 3450 */ 3451 txq->ift_pidx = pi.ipi_new_pidx; 3452 txq->ift_npending += pi.ipi_ndescs; 3453 } else { 3454 *m_headp = m_head = iflib_remove_mbuf(txq); 3455 if (err == EFBIG) { 3456 txq->ift_txd_encap_efbig++; 3457 if (remap < 2) { 3458 remap = 1; 3459 goto defrag; 3460 } 3461 } 3462 goto defrag_failed; 3463 } 3464 /* 3465 * err can't possibly be non-zero here, so we don't neet to test it 3466 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3467 */ 3468 return (err); 3469 3470 defrag_failed: 3471 txq->ift_mbuf_defrag_failed++; 3472 txq->ift_map_failed++; 3473 m_freem(*m_headp); 3474 DBG_COUNTER_INC(tx_frees); 3475 *m_headp = NULL; 3476 DBG_COUNTER_INC(encap_txd_encap_fail); 3477 return (ENOMEM); 3478 } 3479 3480 static void 3481 iflib_tx_desc_free(iflib_txq_t txq, int n) 3482 { 3483 uint32_t qsize, cidx, mask, gen; 3484 struct mbuf *m, **ifsd_m; 3485 bool do_prefetch; 3486 3487 cidx = txq->ift_cidx; 3488 gen = txq->ift_gen; 3489 qsize = txq->ift_size; 3490 mask = qsize-1; 3491 ifsd_m = txq->ift_sds.ifsd_m; 3492 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3493 3494 while (n-- > 0) { 3495 if (do_prefetch) { 3496 prefetch(ifsd_m[(cidx + 3) & mask]); 3497 prefetch(ifsd_m[(cidx + 4) & mask]); 3498 } 3499 if ((m = ifsd_m[cidx]) != NULL) { 3500 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3501 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3502 bus_dmamap_sync(txq->ift_tso_buf_tag, 3503 txq->ift_sds.ifsd_tso_map[cidx], 3504 BUS_DMASYNC_POSTWRITE); 3505 bus_dmamap_unload(txq->ift_tso_buf_tag, 3506 txq->ift_sds.ifsd_tso_map[cidx]); 3507 } else { 3508 bus_dmamap_sync(txq->ift_buf_tag, 3509 txq->ift_sds.ifsd_map[cidx], 3510 BUS_DMASYNC_POSTWRITE); 3511 bus_dmamap_unload(txq->ift_buf_tag, 3512 txq->ift_sds.ifsd_map[cidx]); 3513 } 3514 /* XXX we don't support any drivers that batch packets yet */ 3515 MPASS(m->m_nextpkt == NULL); 3516 m_freem(m); 3517 ifsd_m[cidx] = NULL; 3518 #if MEMORY_LOGGING 3519 txq->ift_dequeued++; 3520 #endif 3521 DBG_COUNTER_INC(tx_frees); 3522 } 3523 if (__predict_false(++cidx == qsize)) { 3524 cidx = 0; 3525 gen = 0; 3526 } 3527 } 3528 txq->ift_cidx = cidx; 3529 txq->ift_gen = gen; 3530 } 3531 3532 static __inline int 3533 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3534 { 3535 int reclaim; 3536 if_ctx_t ctx = txq->ift_ctx; 3537 3538 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3539 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3540 3541 /* 3542 * Need a rate-limiting check so that this isn't called every time 3543 */ 3544 iflib_tx_credits_update(ctx, txq); 3545 reclaim = DESC_RECLAIMABLE(txq); 3546 3547 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3548 #ifdef INVARIANTS 3549 if (iflib_verbose_debug) { 3550 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3551 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3552 reclaim, thresh); 3553 3554 } 3555 #endif 3556 return (0); 3557 } 3558 iflib_tx_desc_free(txq, reclaim); 3559 txq->ift_cleaned += reclaim; 3560 txq->ift_in_use -= reclaim; 3561 3562 return (reclaim); 3563 } 3564 3565 static struct mbuf ** 3566 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3567 { 3568 int next, size; 3569 struct mbuf **items; 3570 3571 size = r->size; 3572 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3573 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3574 3575 prefetch(items[(cidx + offset) & (size-1)]); 3576 if (remaining > 1) { 3577 prefetch2cachelines(&items[next]); 3578 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3579 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3580 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3581 } 3582 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3583 } 3584 3585 static void 3586 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3587 { 3588 3589 ifmp_ring_check_drainage(txq->ift_br, budget); 3590 } 3591 3592 static uint32_t 3593 iflib_txq_can_drain(struct ifmp_ring *r) 3594 { 3595 iflib_txq_t txq = r->cookie; 3596 if_ctx_t ctx = txq->ift_ctx; 3597 3598 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3599 return (1); 3600 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3601 BUS_DMASYNC_POSTREAD); 3602 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3603 false)); 3604 } 3605 3606 static uint32_t 3607 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3608 { 3609 iflib_txq_t txq = r->cookie; 3610 if_ctx_t ctx = txq->ift_ctx; 3611 if_t ifp = ctx->ifc_ifp; 3612 struct mbuf *m, **mp; 3613 int avail, bytes_sent, consumed, count, err, i, in_use_prev; 3614 int mcast_sent, pkt_sent, reclaimed, txq_avail; 3615 bool do_prefetch, rang, ring; 3616 3617 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3618 !LINK_ACTIVE(ctx))) { 3619 DBG_COUNTER_INC(txq_drain_notready); 3620 return (0); 3621 } 3622 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3623 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3624 avail = IDXDIFF(pidx, cidx, r->size); 3625 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3626 DBG_COUNTER_INC(txq_drain_flushing); 3627 for (i = 0; i < avail; i++) { 3628 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3629 m_free(r->items[(cidx + i) & (r->size-1)]); 3630 r->items[(cidx + i) & (r->size-1)] = NULL; 3631 } 3632 return (avail); 3633 } 3634 3635 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3636 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3637 CALLOUT_LOCK(txq); 3638 callout_stop(&txq->ift_timer); 3639 CALLOUT_UNLOCK(txq); 3640 DBG_COUNTER_INC(txq_drain_oactive); 3641 return (0); 3642 } 3643 if (reclaimed) 3644 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3645 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3646 count = MIN(avail, TX_BATCH_SIZE); 3647 #ifdef INVARIANTS 3648 if (iflib_verbose_debug) 3649 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3650 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3651 #endif 3652 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3653 txq_avail = TXQ_AVAIL(txq); 3654 err = 0; 3655 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) { 3656 int rem = do_prefetch ? count - i : 0; 3657 3658 mp = _ring_peek_one(r, cidx, i, rem); 3659 MPASS(mp != NULL && *mp != NULL); 3660 if (__predict_false(*mp == (struct mbuf *)txq)) { 3661 consumed++; 3662 continue; 3663 } 3664 in_use_prev = txq->ift_in_use; 3665 err = iflib_encap(txq, mp); 3666 if (__predict_false(err)) { 3667 /* no room - bail out */ 3668 if (err == ENOBUFS) 3669 break; 3670 consumed++; 3671 /* we can't send this packet - skip it */ 3672 continue; 3673 } 3674 consumed++; 3675 pkt_sent++; 3676 m = *mp; 3677 DBG_COUNTER_INC(tx_sent); 3678 bytes_sent += m->m_pkthdr.len; 3679 mcast_sent += !!(m->m_flags & M_MCAST); 3680 txq_avail = TXQ_AVAIL(txq); 3681 3682 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3683 ETHER_BPF_MTAP(ifp, m); 3684 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3685 break; 3686 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3687 } 3688 3689 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3690 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3691 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3692 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3693 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3694 if (mcast_sent) 3695 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3696 #ifdef INVARIANTS 3697 if (iflib_verbose_debug) 3698 printf("consumed=%d\n", consumed); 3699 #endif 3700 return (consumed); 3701 } 3702 3703 static uint32_t 3704 iflib_txq_drain_always(struct ifmp_ring *r) 3705 { 3706 return (1); 3707 } 3708 3709 static uint32_t 3710 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3711 { 3712 int i, avail; 3713 struct mbuf **mp; 3714 iflib_txq_t txq; 3715 3716 txq = r->cookie; 3717 3718 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3719 CALLOUT_LOCK(txq); 3720 callout_stop(&txq->ift_timer); 3721 CALLOUT_UNLOCK(txq); 3722 3723 avail = IDXDIFF(pidx, cidx, r->size); 3724 for (i = 0; i < avail; i++) { 3725 mp = _ring_peek_one(r, cidx, i, avail - i); 3726 if (__predict_false(*mp == (struct mbuf *)txq)) 3727 continue; 3728 m_freem(*mp); 3729 DBG_COUNTER_INC(tx_frees); 3730 } 3731 MPASS(ifmp_ring_is_stalled(r) == 0); 3732 return (avail); 3733 } 3734 3735 static void 3736 iflib_ifmp_purge(iflib_txq_t txq) 3737 { 3738 struct ifmp_ring *r; 3739 3740 r = txq->ift_br; 3741 r->drain = iflib_txq_drain_free; 3742 r->can_drain = iflib_txq_drain_always; 3743 3744 ifmp_ring_check_drainage(r, r->size); 3745 3746 r->drain = iflib_txq_drain; 3747 r->can_drain = iflib_txq_can_drain; 3748 } 3749 3750 static void 3751 _task_fn_tx(void *context) 3752 { 3753 iflib_txq_t txq = context; 3754 if_ctx_t ctx = txq->ift_ctx; 3755 #if defined(ALTQ) || defined(DEV_NETMAP) 3756 if_t ifp = ctx->ifc_ifp; 3757 #endif 3758 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3759 3760 #ifdef IFLIB_DIAGNOSTICS 3761 txq->ift_cpu_exec_count[curcpu]++; 3762 #endif 3763 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3764 return; 3765 #ifdef DEV_NETMAP 3766 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3767 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3768 BUS_DMASYNC_POSTREAD); 3769 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3770 netmap_tx_irq(ifp, txq->ift_id); 3771 if (ctx->ifc_flags & IFC_LEGACY) 3772 IFDI_INTR_ENABLE(ctx); 3773 else 3774 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3775 return; 3776 } 3777 #endif 3778 #ifdef ALTQ 3779 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3780 iflib_altq_if_start(ifp); 3781 #endif 3782 if (txq->ift_db_pending) 3783 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3784 else if (!abdicate) 3785 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3786 /* 3787 * When abdicating, we always need to check drainage, not just when we don't enqueue 3788 */ 3789 if (abdicate) 3790 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3791 if (ctx->ifc_flags & IFC_LEGACY) 3792 IFDI_INTR_ENABLE(ctx); 3793 else 3794 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3795 } 3796 3797 static void 3798 _task_fn_rx(void *context) 3799 { 3800 iflib_rxq_t rxq = context; 3801 if_ctx_t ctx = rxq->ifr_ctx; 3802 uint8_t more; 3803 uint16_t budget; 3804 3805 #ifdef IFLIB_DIAGNOSTICS 3806 rxq->ifr_cpu_exec_count[curcpu]++; 3807 #endif 3808 DBG_COUNTER_INC(task_fn_rxs); 3809 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3810 return; 3811 #ifdef DEV_NETMAP 3812 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3813 u_int work = 0; 3814 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3815 more = 0; 3816 goto skip_rxeof; 3817 } 3818 } 3819 #endif 3820 budget = ctx->ifc_sysctl_rx_budget; 3821 if (budget == 0) 3822 budget = 16; /* XXX */ 3823 more = iflib_rxeof(rxq, budget); 3824 #ifdef DEV_NETMAP 3825 skip_rxeof: 3826 #endif 3827 if ((more & IFLIB_RXEOF_MORE) == 0) { 3828 if (ctx->ifc_flags & IFC_LEGACY) 3829 IFDI_INTR_ENABLE(ctx); 3830 else 3831 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3832 DBG_COUNTER_INC(rx_intr_enables); 3833 } 3834 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3835 return; 3836 3837 if (more & IFLIB_RXEOF_MORE) 3838 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3839 else if (more & IFLIB_RXEOF_EMPTY) 3840 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 3841 } 3842 3843 static void 3844 _task_fn_admin(void *context) 3845 { 3846 if_ctx_t ctx = context; 3847 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3848 iflib_txq_t txq; 3849 int i; 3850 bool oactive, running, do_reset, do_watchdog, in_detach; 3851 uint32_t reset_on = hz / 2; 3852 3853 STATE_LOCK(ctx); 3854 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3855 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3856 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3857 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3858 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3859 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3860 STATE_UNLOCK(ctx); 3861 3862 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3863 return; 3864 if (in_detach) 3865 return; 3866 3867 CTX_LOCK(ctx); 3868 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3869 CALLOUT_LOCK(txq); 3870 callout_stop(&txq->ift_timer); 3871 CALLOUT_UNLOCK(txq); 3872 } 3873 if (do_watchdog) { 3874 ctx->ifc_watchdog_events++; 3875 IFDI_WATCHDOG_RESET(ctx); 3876 } 3877 IFDI_UPDATE_ADMIN_STATUS(ctx); 3878 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3879 #ifdef DEV_NETMAP 3880 reset_on = hz / 2; 3881 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3882 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3883 #endif 3884 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3885 } 3886 IFDI_LINK_INTR_ENABLE(ctx); 3887 if (do_reset) 3888 iflib_if_init_locked(ctx); 3889 CTX_UNLOCK(ctx); 3890 3891 if (LINK_ACTIVE(ctx) == 0) 3892 return; 3893 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3894 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3895 } 3896 3897 3898 static void 3899 _task_fn_iov(void *context) 3900 { 3901 if_ctx_t ctx = context; 3902 3903 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3904 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3905 return; 3906 3907 CTX_LOCK(ctx); 3908 IFDI_VFLR_HANDLE(ctx); 3909 CTX_UNLOCK(ctx); 3910 } 3911 3912 static int 3913 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3914 { 3915 int err; 3916 if_int_delay_info_t info; 3917 if_ctx_t ctx; 3918 3919 info = (if_int_delay_info_t)arg1; 3920 ctx = info->iidi_ctx; 3921 info->iidi_req = req; 3922 info->iidi_oidp = oidp; 3923 CTX_LOCK(ctx); 3924 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3925 CTX_UNLOCK(ctx); 3926 return (err); 3927 } 3928 3929 /********************************************************************* 3930 * 3931 * IFNET FUNCTIONS 3932 * 3933 **********************************************************************/ 3934 3935 static void 3936 iflib_if_init_locked(if_ctx_t ctx) 3937 { 3938 iflib_stop(ctx); 3939 iflib_init_locked(ctx); 3940 } 3941 3942 3943 static void 3944 iflib_if_init(void *arg) 3945 { 3946 if_ctx_t ctx = arg; 3947 3948 CTX_LOCK(ctx); 3949 iflib_if_init_locked(ctx); 3950 CTX_UNLOCK(ctx); 3951 } 3952 3953 static int 3954 iflib_if_transmit(if_t ifp, struct mbuf *m) 3955 { 3956 if_ctx_t ctx = if_getsoftc(ifp); 3957 3958 iflib_txq_t txq; 3959 int err, qidx; 3960 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3961 3962 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3963 DBG_COUNTER_INC(tx_frees); 3964 m_freem(m); 3965 return (ENETDOWN); 3966 } 3967 3968 MPASS(m->m_nextpkt == NULL); 3969 /* ALTQ-enabled interfaces always use queue 0. */ 3970 qidx = 0; 3971 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3972 qidx = QIDX(ctx, m); 3973 /* 3974 * XXX calculate buf_ring based on flowid (divvy up bits?) 3975 */ 3976 txq = &ctx->ifc_txqs[qidx]; 3977 3978 #ifdef DRIVER_BACKPRESSURE 3979 if (txq->ift_closed) { 3980 while (m != NULL) { 3981 next = m->m_nextpkt; 3982 m->m_nextpkt = NULL; 3983 m_freem(m); 3984 DBG_COUNTER_INC(tx_frees); 3985 m = next; 3986 } 3987 return (ENOBUFS); 3988 } 3989 #endif 3990 #ifdef notyet 3991 qidx = count = 0; 3992 mp = marr; 3993 next = m; 3994 do { 3995 count++; 3996 next = next->m_nextpkt; 3997 } while (next != NULL); 3998 3999 if (count > nitems(marr)) 4000 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4001 /* XXX check nextpkt */ 4002 m_freem(m); 4003 /* XXX simplify for now */ 4004 DBG_COUNTER_INC(tx_frees); 4005 return (ENOBUFS); 4006 } 4007 for (next = m, i = 0; next != NULL; i++) { 4008 mp[i] = next; 4009 next = next->m_nextpkt; 4010 mp[i]->m_nextpkt = NULL; 4011 } 4012 #endif 4013 DBG_COUNTER_INC(tx_seen); 4014 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4015 4016 if (abdicate) 4017 GROUPTASK_ENQUEUE(&txq->ift_task); 4018 if (err) { 4019 if (!abdicate) 4020 GROUPTASK_ENQUEUE(&txq->ift_task); 4021 /* support forthcoming later */ 4022 #ifdef DRIVER_BACKPRESSURE 4023 txq->ift_closed = TRUE; 4024 #endif 4025 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4026 m_freem(m); 4027 DBG_COUNTER_INC(tx_frees); 4028 } 4029 4030 return (err); 4031 } 4032 4033 #ifdef ALTQ 4034 /* 4035 * The overall approach to integrating iflib with ALTQ is to continue to use 4036 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4037 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4038 * is redundant/unnecessary, but doing so minimizes the amount of 4039 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4040 * redundantly queueing to an intermediate mp_ring is swamped by the 4041 * performance limitations inherent in using ALTQ. 4042 * 4043 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4044 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4045 * given interface. If ALTQ is enabled for an interface, then all 4046 * transmitted packets for that interface will be submitted to the ALTQ 4047 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4048 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4049 * update stats that the iflib machinery handles, and which is sensitve to 4050 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4051 * will be installed as the start routine for use by ALTQ facilities that 4052 * need to trigger queue drains on a scheduled basis. 4053 * 4054 */ 4055 static void 4056 iflib_altq_if_start(if_t ifp) 4057 { 4058 struct ifaltq *ifq = &ifp->if_snd; 4059 struct mbuf *m; 4060 4061 IFQ_LOCK(ifq); 4062 IFQ_DEQUEUE_NOLOCK(ifq, m); 4063 while (m != NULL) { 4064 iflib_if_transmit(ifp, m); 4065 IFQ_DEQUEUE_NOLOCK(ifq, m); 4066 } 4067 IFQ_UNLOCK(ifq); 4068 } 4069 4070 static int 4071 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4072 { 4073 int err; 4074 4075 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4076 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4077 if (err == 0) 4078 iflib_altq_if_start(ifp); 4079 } else 4080 err = iflib_if_transmit(ifp, m); 4081 4082 return (err); 4083 } 4084 #endif /* ALTQ */ 4085 4086 static void 4087 iflib_if_qflush(if_t ifp) 4088 { 4089 if_ctx_t ctx = if_getsoftc(ifp); 4090 iflib_txq_t txq = ctx->ifc_txqs; 4091 int i; 4092 4093 STATE_LOCK(ctx); 4094 ctx->ifc_flags |= IFC_QFLUSH; 4095 STATE_UNLOCK(ctx); 4096 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4097 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4098 iflib_txq_check_drain(txq, 0); 4099 STATE_LOCK(ctx); 4100 ctx->ifc_flags &= ~IFC_QFLUSH; 4101 STATE_UNLOCK(ctx); 4102 4103 /* 4104 * When ALTQ is enabled, this will also take care of purging the 4105 * ALTQ queue(s). 4106 */ 4107 if_qflush(ifp); 4108 } 4109 4110 4111 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4112 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4113 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4114 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4115 4116 static int 4117 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4118 { 4119 if_ctx_t ctx = if_getsoftc(ifp); 4120 struct ifreq *ifr = (struct ifreq *)data; 4121 #if defined(INET) || defined(INET6) 4122 struct ifaddr *ifa = (struct ifaddr *)data; 4123 #endif 4124 bool avoid_reset = false; 4125 int err = 0, reinit = 0, bits; 4126 4127 switch (command) { 4128 case SIOCSIFADDR: 4129 #ifdef INET 4130 if (ifa->ifa_addr->sa_family == AF_INET) 4131 avoid_reset = true; 4132 #endif 4133 #ifdef INET6 4134 if (ifa->ifa_addr->sa_family == AF_INET6) 4135 avoid_reset = true; 4136 #endif 4137 /* 4138 ** Calling init results in link renegotiation, 4139 ** so we avoid doing it when possible. 4140 */ 4141 if (avoid_reset) { 4142 if_setflagbits(ifp, IFF_UP,0); 4143 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4144 reinit = 1; 4145 #ifdef INET 4146 if (!(if_getflags(ifp) & IFF_NOARP)) 4147 arp_ifinit(ifp, ifa); 4148 #endif 4149 } else 4150 err = ether_ioctl(ifp, command, data); 4151 break; 4152 case SIOCSIFMTU: 4153 CTX_LOCK(ctx); 4154 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4155 CTX_UNLOCK(ctx); 4156 break; 4157 } 4158 bits = if_getdrvflags(ifp); 4159 /* stop the driver and free any clusters before proceeding */ 4160 iflib_stop(ctx); 4161 4162 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4163 STATE_LOCK(ctx); 4164 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4165 ctx->ifc_flags |= IFC_MULTISEG; 4166 else 4167 ctx->ifc_flags &= ~IFC_MULTISEG; 4168 STATE_UNLOCK(ctx); 4169 err = if_setmtu(ifp, ifr->ifr_mtu); 4170 } 4171 iflib_init_locked(ctx); 4172 STATE_LOCK(ctx); 4173 if_setdrvflags(ifp, bits); 4174 STATE_UNLOCK(ctx); 4175 CTX_UNLOCK(ctx); 4176 break; 4177 case SIOCSIFFLAGS: 4178 CTX_LOCK(ctx); 4179 if (if_getflags(ifp) & IFF_UP) { 4180 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4181 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4182 (IFF_PROMISC | IFF_ALLMULTI)) { 4183 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4184 } 4185 } else 4186 reinit = 1; 4187 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4188 iflib_stop(ctx); 4189 } 4190 ctx->ifc_if_flags = if_getflags(ifp); 4191 CTX_UNLOCK(ctx); 4192 break; 4193 case SIOCADDMULTI: 4194 case SIOCDELMULTI: 4195 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4196 CTX_LOCK(ctx); 4197 IFDI_INTR_DISABLE(ctx); 4198 IFDI_MULTI_SET(ctx); 4199 IFDI_INTR_ENABLE(ctx); 4200 CTX_UNLOCK(ctx); 4201 } 4202 break; 4203 case SIOCSIFMEDIA: 4204 CTX_LOCK(ctx); 4205 IFDI_MEDIA_SET(ctx); 4206 CTX_UNLOCK(ctx); 4207 /* FALLTHROUGH */ 4208 case SIOCGIFMEDIA: 4209 case SIOCGIFXMEDIA: 4210 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4211 break; 4212 case SIOCGI2C: 4213 { 4214 struct ifi2creq i2c; 4215 4216 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4217 if (err != 0) 4218 break; 4219 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4220 err = EINVAL; 4221 break; 4222 } 4223 if (i2c.len > sizeof(i2c.data)) { 4224 err = EINVAL; 4225 break; 4226 } 4227 4228 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4229 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4230 sizeof(i2c)); 4231 break; 4232 } 4233 case SIOCSIFCAP: 4234 { 4235 int mask, setmask, oldmask; 4236 4237 oldmask = if_getcapenable(ifp); 4238 mask = ifr->ifr_reqcap ^ oldmask; 4239 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4240 setmask = 0; 4241 #ifdef TCP_OFFLOAD 4242 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4243 #endif 4244 setmask |= (mask & IFCAP_FLAGS); 4245 setmask |= (mask & IFCAP_WOL); 4246 4247 /* 4248 * If any RX csum has changed, change all the ones that 4249 * are supported by the driver. 4250 */ 4251 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4252 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4253 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4254 } 4255 4256 /* 4257 * want to ensure that traffic has stopped before we change any of the flags 4258 */ 4259 if (setmask) { 4260 CTX_LOCK(ctx); 4261 bits = if_getdrvflags(ifp); 4262 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4263 iflib_stop(ctx); 4264 STATE_LOCK(ctx); 4265 if_togglecapenable(ifp, setmask); 4266 STATE_UNLOCK(ctx); 4267 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4268 iflib_init_locked(ctx); 4269 STATE_LOCK(ctx); 4270 if_setdrvflags(ifp, bits); 4271 STATE_UNLOCK(ctx); 4272 CTX_UNLOCK(ctx); 4273 } 4274 if_vlancap(ifp); 4275 break; 4276 } 4277 case SIOCGPRIVATE_0: 4278 case SIOCSDRVSPEC: 4279 case SIOCGDRVSPEC: 4280 CTX_LOCK(ctx); 4281 err = IFDI_PRIV_IOCTL(ctx, command, data); 4282 CTX_UNLOCK(ctx); 4283 break; 4284 default: 4285 err = ether_ioctl(ifp, command, data); 4286 break; 4287 } 4288 if (reinit) 4289 iflib_if_init(ctx); 4290 return (err); 4291 } 4292 4293 static uint64_t 4294 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4295 { 4296 if_ctx_t ctx = if_getsoftc(ifp); 4297 4298 return (IFDI_GET_COUNTER(ctx, cnt)); 4299 } 4300 4301 /********************************************************************* 4302 * 4303 * OTHER FUNCTIONS EXPORTED TO THE STACK 4304 * 4305 **********************************************************************/ 4306 4307 static void 4308 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4309 { 4310 if_ctx_t ctx = if_getsoftc(ifp); 4311 4312 if ((void *)ctx != arg) 4313 return; 4314 4315 if ((vtag == 0) || (vtag > 4095)) 4316 return; 4317 4318 if (iflib_in_detach(ctx)) 4319 return; 4320 4321 CTX_LOCK(ctx); 4322 IFDI_VLAN_REGISTER(ctx, vtag); 4323 /* Re-init to load the changes */ 4324 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4325 iflib_if_init_locked(ctx); 4326 CTX_UNLOCK(ctx); 4327 } 4328 4329 static void 4330 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4331 { 4332 if_ctx_t ctx = if_getsoftc(ifp); 4333 4334 if ((void *)ctx != arg) 4335 return; 4336 4337 if ((vtag == 0) || (vtag > 4095)) 4338 return; 4339 4340 CTX_LOCK(ctx); 4341 IFDI_VLAN_UNREGISTER(ctx, vtag); 4342 /* Re-init to load the changes */ 4343 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4344 iflib_if_init_locked(ctx); 4345 CTX_UNLOCK(ctx); 4346 } 4347 4348 static void 4349 iflib_led_func(void *arg, int onoff) 4350 { 4351 if_ctx_t ctx = arg; 4352 4353 CTX_LOCK(ctx); 4354 IFDI_LED_FUNC(ctx, onoff); 4355 CTX_UNLOCK(ctx); 4356 } 4357 4358 /********************************************************************* 4359 * 4360 * BUS FUNCTION DEFINITIONS 4361 * 4362 **********************************************************************/ 4363 4364 int 4365 iflib_device_probe(device_t dev) 4366 { 4367 const pci_vendor_info_t *ent; 4368 if_shared_ctx_t sctx; 4369 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4370 uint16_t pci_vendor_id; 4371 4372 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4373 return (ENOTSUP); 4374 4375 pci_vendor_id = pci_get_vendor(dev); 4376 pci_device_id = pci_get_device(dev); 4377 pci_subvendor_id = pci_get_subvendor(dev); 4378 pci_subdevice_id = pci_get_subdevice(dev); 4379 pci_rev_id = pci_get_revid(dev); 4380 if (sctx->isc_parse_devinfo != NULL) 4381 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4382 4383 ent = sctx->isc_vendor_info; 4384 while (ent->pvi_vendor_id != 0) { 4385 if (pci_vendor_id != ent->pvi_vendor_id) { 4386 ent++; 4387 continue; 4388 } 4389 if ((pci_device_id == ent->pvi_device_id) && 4390 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4391 (ent->pvi_subvendor_id == 0)) && 4392 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4393 (ent->pvi_subdevice_id == 0)) && 4394 ((pci_rev_id == ent->pvi_rev_id) || 4395 (ent->pvi_rev_id == 0))) { 4396 4397 device_set_desc_copy(dev, ent->pvi_name); 4398 /* this needs to be changed to zero if the bus probing code 4399 * ever stops re-probing on best match because the sctx 4400 * may have its values over written by register calls 4401 * in subsequent probes 4402 */ 4403 return (BUS_PROBE_DEFAULT); 4404 } 4405 ent++; 4406 } 4407 return (ENXIO); 4408 } 4409 4410 int 4411 iflib_device_probe_vendor(device_t dev) 4412 { 4413 int probe; 4414 4415 probe = iflib_device_probe(dev); 4416 if (probe == BUS_PROBE_DEFAULT) 4417 return (BUS_PROBE_VENDOR); 4418 else 4419 return (probe); 4420 } 4421 4422 static void 4423 iflib_reset_qvalues(if_ctx_t ctx) 4424 { 4425 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4426 if_shared_ctx_t sctx = ctx->ifc_sctx; 4427 device_t dev = ctx->ifc_dev; 4428 int i; 4429 4430 if (ctx->ifc_sysctl_ntxqs != 0) 4431 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4432 if (ctx->ifc_sysctl_nrxqs != 0) 4433 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4434 4435 for (i = 0; i < sctx->isc_ntxqs; i++) { 4436 if (ctx->ifc_sysctl_ntxds[i] != 0) 4437 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4438 else 4439 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4440 } 4441 4442 for (i = 0; i < sctx->isc_nrxqs; i++) { 4443 if (ctx->ifc_sysctl_nrxds[i] != 0) 4444 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4445 else 4446 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4447 } 4448 4449 for (i = 0; i < sctx->isc_nrxqs; i++) { 4450 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4451 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4452 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4453 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4454 } 4455 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4456 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4457 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4458 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4459 } 4460 if (!powerof2(scctx->isc_nrxd[i])) { 4461 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4462 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4463 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4464 } 4465 } 4466 4467 for (i = 0; i < sctx->isc_ntxqs; i++) { 4468 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4469 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4470 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4471 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4472 } 4473 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4474 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4475 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4476 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4477 } 4478 if (!powerof2(scctx->isc_ntxd[i])) { 4479 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4480 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4481 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4482 } 4483 } 4484 } 4485 4486 static void 4487 iflib_add_pfil(if_ctx_t ctx) 4488 { 4489 struct pfil_head *pfil; 4490 struct pfil_head_args pa; 4491 iflib_rxq_t rxq; 4492 int i; 4493 4494 pa.pa_version = PFIL_VERSION; 4495 pa.pa_flags = PFIL_IN; 4496 pa.pa_type = PFIL_TYPE_ETHERNET; 4497 pa.pa_headname = ctx->ifc_ifp->if_xname; 4498 pfil = pfil_head_register(&pa); 4499 4500 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4501 rxq->pfil = pfil; 4502 } 4503 } 4504 4505 static void 4506 iflib_rem_pfil(if_ctx_t ctx) 4507 { 4508 struct pfil_head *pfil; 4509 iflib_rxq_t rxq; 4510 int i; 4511 4512 rxq = ctx->ifc_rxqs; 4513 pfil = rxq->pfil; 4514 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4515 rxq->pfil = NULL; 4516 } 4517 pfil_head_unregister(pfil); 4518 } 4519 4520 static uint16_t 4521 get_ctx_core_offset(if_ctx_t ctx) 4522 { 4523 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4524 struct cpu_offset *op; 4525 uint16_t qc; 4526 uint16_t ret = ctx->ifc_sysctl_core_offset; 4527 4528 if (ret != CORE_OFFSET_UNSPECIFIED) 4529 return (ret); 4530 4531 if (ctx->ifc_sysctl_separate_txrx) 4532 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4533 else 4534 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4535 4536 mtx_lock(&cpu_offset_mtx); 4537 SLIST_FOREACH(op, &cpu_offsets, entries) { 4538 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4539 ret = op->offset; 4540 op->offset += qc; 4541 MPASS(op->refcount < UINT_MAX); 4542 op->refcount++; 4543 break; 4544 } 4545 } 4546 if (ret == CORE_OFFSET_UNSPECIFIED) { 4547 ret = 0; 4548 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4549 M_NOWAIT | M_ZERO); 4550 if (op == NULL) { 4551 device_printf(ctx->ifc_dev, 4552 "allocation for cpu offset failed.\n"); 4553 } else { 4554 op->offset = qc; 4555 op->refcount = 1; 4556 CPU_COPY(&ctx->ifc_cpus, &op->set); 4557 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4558 } 4559 } 4560 mtx_unlock(&cpu_offset_mtx); 4561 4562 return (ret); 4563 } 4564 4565 static void 4566 unref_ctx_core_offset(if_ctx_t ctx) 4567 { 4568 struct cpu_offset *op, *top; 4569 4570 mtx_lock(&cpu_offset_mtx); 4571 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4572 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4573 MPASS(op->refcount > 0); 4574 op->refcount--; 4575 if (op->refcount == 0) { 4576 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4577 free(op, M_IFLIB); 4578 } 4579 break; 4580 } 4581 } 4582 mtx_unlock(&cpu_offset_mtx); 4583 } 4584 4585 int 4586 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4587 { 4588 if_ctx_t ctx; 4589 if_t ifp; 4590 if_softc_ctx_t scctx; 4591 kobjop_desc_t kobj_desc; 4592 kobj_method_t *kobj_method; 4593 int err, msix, rid; 4594 uint16_t main_rxq, main_txq; 4595 4596 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4597 4598 if (sc == NULL) { 4599 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4600 device_set_softc(dev, ctx); 4601 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4602 } 4603 4604 ctx->ifc_sctx = sctx; 4605 ctx->ifc_dev = dev; 4606 ctx->ifc_softc = sc; 4607 4608 if ((err = iflib_register(ctx)) != 0) { 4609 device_printf(dev, "iflib_register failed %d\n", err); 4610 goto fail_ctx_free; 4611 } 4612 iflib_add_device_sysctl_pre(ctx); 4613 4614 scctx = &ctx->ifc_softc_ctx; 4615 ifp = ctx->ifc_ifp; 4616 4617 iflib_reset_qvalues(ctx); 4618 CTX_LOCK(ctx); 4619 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4620 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4621 goto fail_unlock; 4622 } 4623 _iflib_pre_assert(scctx); 4624 ctx->ifc_txrx = *scctx->isc_txrx; 4625 4626 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4627 ctx->ifc_mediap = scctx->isc_media; 4628 4629 #ifdef INVARIANTS 4630 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4631 MPASS(scctx->isc_tx_csum_flags); 4632 #endif 4633 4634 if_setcapabilities(ifp, 4635 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4636 if_setcapenable(ifp, 4637 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4638 4639 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4640 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4641 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4642 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4643 4644 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4645 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4646 4647 /* XXX change for per-queue sizes */ 4648 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4649 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4650 4651 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4652 MAX_SINGLE_PACKET_FRACTION) 4653 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4654 MAX_SINGLE_PACKET_FRACTION); 4655 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4656 MAX_SINGLE_PACKET_FRACTION) 4657 scctx->isc_tx_tso_segments_max = max(1, 4658 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4659 4660 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4661 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4662 /* 4663 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4664 * but some MACs do. 4665 */ 4666 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4667 IP_MAXPACKET)); 4668 /* 4669 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4670 * into account. In the worst case, each of these calls will 4671 * add another mbuf and, thus, the requirement for another DMA 4672 * segment. So for best performance, it doesn't make sense to 4673 * advertize a maximum of TSO segments that typically will 4674 * require defragmentation in iflib_encap(). 4675 */ 4676 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4677 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4678 } 4679 if (scctx->isc_rss_table_size == 0) 4680 scctx->isc_rss_table_size = 64; 4681 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4682 4683 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4684 /* XXX format name */ 4685 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4686 NULL, NULL, "admin"); 4687 4688 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4689 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4690 device_printf(dev, "Unable to fetch CPU list\n"); 4691 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4692 } 4693 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4694 4695 /* 4696 ** Now set up MSI or MSI-X, should return us the number of supported 4697 ** vectors (will be 1 for a legacy interrupt and MSI). 4698 */ 4699 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4700 msix = scctx->isc_vectors; 4701 } else if (scctx->isc_msix_bar != 0) 4702 /* 4703 * The simple fact that isc_msix_bar is not 0 does not mean we 4704 * we have a good value there that is known to work. 4705 */ 4706 msix = iflib_msix_init(ctx); 4707 else { 4708 scctx->isc_vectors = 1; 4709 scctx->isc_ntxqsets = 1; 4710 scctx->isc_nrxqsets = 1; 4711 scctx->isc_intr = IFLIB_INTR_LEGACY; 4712 msix = 0; 4713 } 4714 /* Get memory for the station queues */ 4715 if ((err = iflib_queues_alloc(ctx))) { 4716 device_printf(dev, "Unable to allocate queue memory\n"); 4717 goto fail_intr_free; 4718 } 4719 4720 if ((err = iflib_qset_structures_setup(ctx))) 4721 goto fail_queues; 4722 4723 /* 4724 * Now that we know how many queues there are, get the core offset. 4725 */ 4726 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4727 4728 /* 4729 * Group taskqueues aren't properly set up until SMP is started, 4730 * so we disable interrupts until we can handle them post 4731 * SI_SUB_SMP. 4732 * 4733 * XXX: disabling interrupts doesn't actually work, at least for 4734 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4735 * we do null handling and depend on this not causing too large an 4736 * interrupt storm. 4737 */ 4738 IFDI_INTR_DISABLE(ctx); 4739 4740 if (msix > 1) { 4741 /* 4742 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4743 * aren't the default NULL implementation. 4744 */ 4745 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4746 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4747 kobj_desc); 4748 if (kobj_method == &kobj_desc->deflt) { 4749 device_printf(dev, 4750 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4751 err = EOPNOTSUPP; 4752 goto fail_queues; 4753 } 4754 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4755 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4756 kobj_desc); 4757 if (kobj_method == &kobj_desc->deflt) { 4758 device_printf(dev, 4759 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4760 err = EOPNOTSUPP; 4761 goto fail_queues; 4762 } 4763 4764 /* 4765 * Assign the MSI-X vectors. 4766 * Note that the default NULL ifdi_msix_intr_assign method will 4767 * fail here, too. 4768 */ 4769 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4770 if (err != 0) { 4771 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4772 err); 4773 goto fail_queues; 4774 } 4775 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4776 rid = 0; 4777 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4778 MPASS(msix == 1); 4779 rid = 1; 4780 } 4781 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4782 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4783 goto fail_queues; 4784 } 4785 } else { 4786 device_printf(dev, 4787 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4788 err = ENODEV; 4789 goto fail_intr_free; 4790 } 4791 4792 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4793 4794 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4795 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4796 goto fail_detach; 4797 } 4798 4799 /* 4800 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4801 * This must appear after the call to ether_ifattach() because 4802 * ether_ifattach() sets if_hdrlen to the default value. 4803 */ 4804 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4805 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4806 4807 if ((err = iflib_netmap_attach(ctx))) { 4808 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4809 goto fail_detach; 4810 } 4811 *ctxp = ctx; 4812 4813 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4814 4815 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4816 iflib_add_device_sysctl_post(ctx); 4817 iflib_add_pfil(ctx); 4818 ctx->ifc_flags |= IFC_INIT_DONE; 4819 CTX_UNLOCK(ctx); 4820 4821 return (0); 4822 4823 fail_detach: 4824 ether_ifdetach(ctx->ifc_ifp); 4825 fail_intr_free: 4826 iflib_free_intr_mem(ctx); 4827 fail_queues: 4828 iflib_tx_structures_free(ctx); 4829 iflib_rx_structures_free(ctx); 4830 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4831 IFDI_DETACH(ctx); 4832 fail_unlock: 4833 CTX_UNLOCK(ctx); 4834 iflib_deregister(ctx); 4835 fail_ctx_free: 4836 device_set_softc(ctx->ifc_dev, NULL); 4837 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4838 free(ctx->ifc_softc, M_IFLIB); 4839 free(ctx, M_IFLIB); 4840 return (err); 4841 } 4842 4843 int 4844 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4845 struct iflib_cloneattach_ctx *clctx) 4846 { 4847 int err; 4848 if_ctx_t ctx; 4849 if_t ifp; 4850 if_softc_ctx_t scctx; 4851 int i; 4852 void *sc; 4853 uint16_t main_txq; 4854 uint16_t main_rxq; 4855 4856 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4857 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4858 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4859 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4860 ctx->ifc_flags |= IFC_PSEUDO; 4861 4862 ctx->ifc_sctx = sctx; 4863 ctx->ifc_softc = sc; 4864 ctx->ifc_dev = dev; 4865 4866 if ((err = iflib_register(ctx)) != 0) { 4867 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4868 goto fail_ctx_free; 4869 } 4870 iflib_add_device_sysctl_pre(ctx); 4871 4872 scctx = &ctx->ifc_softc_ctx; 4873 ifp = ctx->ifc_ifp; 4874 4875 iflib_reset_qvalues(ctx); 4876 CTX_LOCK(ctx); 4877 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4878 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4879 goto fail_unlock; 4880 } 4881 if (sctx->isc_flags & IFLIB_GEN_MAC) 4882 ether_gen_addr(ifp, &ctx->ifc_mac); 4883 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4884 clctx->cc_params)) != 0) { 4885 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4886 goto fail_ctx_free; 4887 } 4888 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4889 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4890 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4891 4892 #ifdef INVARIANTS 4893 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4894 MPASS(scctx->isc_tx_csum_flags); 4895 #endif 4896 4897 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4898 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4899 4900 ifp->if_flags |= IFF_NOGROUP; 4901 if (sctx->isc_flags & IFLIB_PSEUDO) { 4902 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4903 4904 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4905 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4906 goto fail_detach; 4907 } 4908 *ctxp = ctx; 4909 4910 /* 4911 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4912 * This must appear after the call to ether_ifattach() because 4913 * ether_ifattach() sets if_hdrlen to the default value. 4914 */ 4915 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4916 if_setifheaderlen(ifp, 4917 sizeof(struct ether_vlan_header)); 4918 4919 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4920 iflib_add_device_sysctl_post(ctx); 4921 ctx->ifc_flags |= IFC_INIT_DONE; 4922 return (0); 4923 } 4924 _iflib_pre_assert(scctx); 4925 ctx->ifc_txrx = *scctx->isc_txrx; 4926 4927 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4928 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4929 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4930 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4931 4932 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4933 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4934 4935 /* XXX change for per-queue sizes */ 4936 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4937 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4938 4939 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4940 MAX_SINGLE_PACKET_FRACTION) 4941 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4942 MAX_SINGLE_PACKET_FRACTION); 4943 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4944 MAX_SINGLE_PACKET_FRACTION) 4945 scctx->isc_tx_tso_segments_max = max(1, 4946 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4947 4948 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4949 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4950 /* 4951 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4952 * but some MACs do. 4953 */ 4954 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4955 IP_MAXPACKET)); 4956 /* 4957 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4958 * into account. In the worst case, each of these calls will 4959 * add another mbuf and, thus, the requirement for another DMA 4960 * segment. So for best performance, it doesn't make sense to 4961 * advertize a maximum of TSO segments that typically will 4962 * require defragmentation in iflib_encap(). 4963 */ 4964 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4965 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4966 } 4967 if (scctx->isc_rss_table_size == 0) 4968 scctx->isc_rss_table_size = 64; 4969 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4970 4971 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4972 /* XXX format name */ 4973 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4974 NULL, NULL, "admin"); 4975 4976 /* XXX --- can support > 1 -- but keep it simple for now */ 4977 scctx->isc_intr = IFLIB_INTR_LEGACY; 4978 4979 /* Get memory for the station queues */ 4980 if ((err = iflib_queues_alloc(ctx))) { 4981 device_printf(dev, "Unable to allocate queue memory\n"); 4982 goto fail_iflib_detach; 4983 } 4984 4985 if ((err = iflib_qset_structures_setup(ctx))) { 4986 device_printf(dev, "qset structure setup failed %d\n", err); 4987 goto fail_queues; 4988 } 4989 4990 /* 4991 * XXX What if anything do we want to do about interrupts? 4992 */ 4993 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4994 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4995 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4996 goto fail_detach; 4997 } 4998 4999 /* 5000 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5001 * This must appear after the call to ether_ifattach() because 5002 * ether_ifattach() sets if_hdrlen to the default value. 5003 */ 5004 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5005 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5006 5007 /* XXX handle more than one queue */ 5008 for (i = 0; i < scctx->isc_nrxqsets; i++) 5009 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5010 5011 *ctxp = ctx; 5012 5013 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5014 iflib_add_device_sysctl_post(ctx); 5015 ctx->ifc_flags |= IFC_INIT_DONE; 5016 CTX_UNLOCK(ctx); 5017 5018 return (0); 5019 fail_detach: 5020 ether_ifdetach(ctx->ifc_ifp); 5021 fail_queues: 5022 iflib_tx_structures_free(ctx); 5023 iflib_rx_structures_free(ctx); 5024 fail_iflib_detach: 5025 IFDI_DETACH(ctx); 5026 fail_unlock: 5027 CTX_UNLOCK(ctx); 5028 iflib_deregister(ctx); 5029 fail_ctx_free: 5030 free(ctx->ifc_softc, M_IFLIB); 5031 free(ctx, M_IFLIB); 5032 return (err); 5033 } 5034 5035 int 5036 iflib_pseudo_deregister(if_ctx_t ctx) 5037 { 5038 if_t ifp = ctx->ifc_ifp; 5039 iflib_txq_t txq; 5040 iflib_rxq_t rxq; 5041 int i, j; 5042 struct taskqgroup *tqg; 5043 iflib_fl_t fl; 5044 5045 /* Unregister VLAN event handlers early */ 5046 iflib_unregister_vlan_handlers(ctx); 5047 5048 ether_ifdetach(ifp); 5049 /* XXX drain any dependent tasks */ 5050 tqg = qgroup_if_io_tqg; 5051 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5052 callout_drain(&txq->ift_timer); 5053 if (txq->ift_task.gt_uniq != NULL) 5054 taskqgroup_detach(tqg, &txq->ift_task); 5055 } 5056 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5057 callout_drain(&rxq->ifr_watchdog); 5058 if (rxq->ifr_task.gt_uniq != NULL) 5059 taskqgroup_detach(tqg, &rxq->ifr_task); 5060 5061 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5062 free(fl->ifl_rx_bitmap, M_IFLIB); 5063 } 5064 tqg = qgroup_if_config_tqg; 5065 if (ctx->ifc_admin_task.gt_uniq != NULL) 5066 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5067 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5068 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5069 5070 iflib_tx_structures_free(ctx); 5071 iflib_rx_structures_free(ctx); 5072 5073 iflib_deregister(ctx); 5074 5075 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5076 free(ctx->ifc_softc, M_IFLIB); 5077 free(ctx, M_IFLIB); 5078 return (0); 5079 } 5080 5081 int 5082 iflib_device_attach(device_t dev) 5083 { 5084 if_ctx_t ctx; 5085 if_shared_ctx_t sctx; 5086 5087 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5088 return (ENOTSUP); 5089 5090 pci_enable_busmaster(dev); 5091 5092 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5093 } 5094 5095 int 5096 iflib_device_deregister(if_ctx_t ctx) 5097 { 5098 if_t ifp = ctx->ifc_ifp; 5099 iflib_txq_t txq; 5100 iflib_rxq_t rxq; 5101 device_t dev = ctx->ifc_dev; 5102 int i, j; 5103 struct taskqgroup *tqg; 5104 iflib_fl_t fl; 5105 5106 /* Make sure VLANS are not using driver */ 5107 if (if_vlantrunkinuse(ifp)) { 5108 device_printf(dev, "Vlan in use, detach first\n"); 5109 return (EBUSY); 5110 } 5111 #ifdef PCI_IOV 5112 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5113 device_printf(dev, "SR-IOV in use; detach first.\n"); 5114 return (EBUSY); 5115 } 5116 #endif 5117 5118 STATE_LOCK(ctx); 5119 ctx->ifc_flags |= IFC_IN_DETACH; 5120 STATE_UNLOCK(ctx); 5121 5122 /* Unregister VLAN handlers before calling iflib_stop() */ 5123 iflib_unregister_vlan_handlers(ctx); 5124 5125 iflib_netmap_detach(ifp); 5126 ether_ifdetach(ifp); 5127 5128 CTX_LOCK(ctx); 5129 iflib_stop(ctx); 5130 CTX_UNLOCK(ctx); 5131 5132 iflib_rem_pfil(ctx); 5133 if (ctx->ifc_led_dev != NULL) 5134 led_destroy(ctx->ifc_led_dev); 5135 /* XXX drain any dependent tasks */ 5136 tqg = qgroup_if_io_tqg; 5137 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5138 callout_drain(&txq->ift_timer); 5139 if (txq->ift_task.gt_uniq != NULL) 5140 taskqgroup_detach(tqg, &txq->ift_task); 5141 } 5142 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5143 if (rxq->ifr_task.gt_uniq != NULL) 5144 taskqgroup_detach(tqg, &rxq->ifr_task); 5145 5146 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5147 free(fl->ifl_rx_bitmap, M_IFLIB); 5148 } 5149 tqg = qgroup_if_config_tqg; 5150 if (ctx->ifc_admin_task.gt_uniq != NULL) 5151 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5152 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5153 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5154 CTX_LOCK(ctx); 5155 IFDI_DETACH(ctx); 5156 CTX_UNLOCK(ctx); 5157 5158 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5159 iflib_free_intr_mem(ctx); 5160 5161 bus_generic_detach(dev); 5162 5163 iflib_tx_structures_free(ctx); 5164 iflib_rx_structures_free(ctx); 5165 5166 iflib_deregister(ctx); 5167 5168 device_set_softc(ctx->ifc_dev, NULL); 5169 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5170 free(ctx->ifc_softc, M_IFLIB); 5171 unref_ctx_core_offset(ctx); 5172 free(ctx, M_IFLIB); 5173 return (0); 5174 } 5175 5176 static void 5177 iflib_free_intr_mem(if_ctx_t ctx) 5178 { 5179 5180 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5181 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5182 } 5183 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5184 pci_release_msi(ctx->ifc_dev); 5185 } 5186 if (ctx->ifc_msix_mem != NULL) { 5187 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5188 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5189 ctx->ifc_msix_mem = NULL; 5190 } 5191 } 5192 5193 int 5194 iflib_device_detach(device_t dev) 5195 { 5196 if_ctx_t ctx = device_get_softc(dev); 5197 5198 return (iflib_device_deregister(ctx)); 5199 } 5200 5201 int 5202 iflib_device_suspend(device_t dev) 5203 { 5204 if_ctx_t ctx = device_get_softc(dev); 5205 5206 CTX_LOCK(ctx); 5207 IFDI_SUSPEND(ctx); 5208 CTX_UNLOCK(ctx); 5209 5210 return bus_generic_suspend(dev); 5211 } 5212 int 5213 iflib_device_shutdown(device_t dev) 5214 { 5215 if_ctx_t ctx = device_get_softc(dev); 5216 5217 CTX_LOCK(ctx); 5218 IFDI_SHUTDOWN(ctx); 5219 CTX_UNLOCK(ctx); 5220 5221 return bus_generic_suspend(dev); 5222 } 5223 5224 5225 int 5226 iflib_device_resume(device_t dev) 5227 { 5228 if_ctx_t ctx = device_get_softc(dev); 5229 iflib_txq_t txq = ctx->ifc_txqs; 5230 5231 CTX_LOCK(ctx); 5232 IFDI_RESUME(ctx); 5233 iflib_if_init_locked(ctx); 5234 CTX_UNLOCK(ctx); 5235 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5236 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5237 5238 return (bus_generic_resume(dev)); 5239 } 5240 5241 int 5242 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5243 { 5244 int error; 5245 if_ctx_t ctx = device_get_softc(dev); 5246 5247 CTX_LOCK(ctx); 5248 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5249 CTX_UNLOCK(ctx); 5250 5251 return (error); 5252 } 5253 5254 void 5255 iflib_device_iov_uninit(device_t dev) 5256 { 5257 if_ctx_t ctx = device_get_softc(dev); 5258 5259 CTX_LOCK(ctx); 5260 IFDI_IOV_UNINIT(ctx); 5261 CTX_UNLOCK(ctx); 5262 } 5263 5264 int 5265 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5266 { 5267 int error; 5268 if_ctx_t ctx = device_get_softc(dev); 5269 5270 CTX_LOCK(ctx); 5271 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5272 CTX_UNLOCK(ctx); 5273 5274 return (error); 5275 } 5276 5277 /********************************************************************* 5278 * 5279 * MODULE FUNCTION DEFINITIONS 5280 * 5281 **********************************************************************/ 5282 5283 /* 5284 * - Start a fast taskqueue thread for each core 5285 * - Start a taskqueue for control operations 5286 */ 5287 static int 5288 iflib_module_init(void) 5289 { 5290 return (0); 5291 } 5292 5293 static int 5294 iflib_module_event_handler(module_t mod, int what, void *arg) 5295 { 5296 int err; 5297 5298 switch (what) { 5299 case MOD_LOAD: 5300 if ((err = iflib_module_init()) != 0) 5301 return (err); 5302 break; 5303 case MOD_UNLOAD: 5304 return (EBUSY); 5305 default: 5306 return (EOPNOTSUPP); 5307 } 5308 5309 return (0); 5310 } 5311 5312 /********************************************************************* 5313 * 5314 * PUBLIC FUNCTION DEFINITIONS 5315 * ordered as in iflib.h 5316 * 5317 **********************************************************************/ 5318 5319 5320 static void 5321 _iflib_assert(if_shared_ctx_t sctx) 5322 { 5323 int i; 5324 5325 MPASS(sctx->isc_tx_maxsize); 5326 MPASS(sctx->isc_tx_maxsegsize); 5327 5328 MPASS(sctx->isc_rx_maxsize); 5329 MPASS(sctx->isc_rx_nsegments); 5330 MPASS(sctx->isc_rx_maxsegsize); 5331 5332 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5333 for (i = 0; i < sctx->isc_nrxqs; i++) { 5334 MPASS(sctx->isc_nrxd_min[i]); 5335 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5336 MPASS(sctx->isc_nrxd_max[i]); 5337 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5338 MPASS(sctx->isc_nrxd_default[i]); 5339 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5340 } 5341 5342 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5343 for (i = 0; i < sctx->isc_ntxqs; i++) { 5344 MPASS(sctx->isc_ntxd_min[i]); 5345 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5346 MPASS(sctx->isc_ntxd_max[i]); 5347 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5348 MPASS(sctx->isc_ntxd_default[i]); 5349 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5350 } 5351 } 5352 5353 static void 5354 _iflib_pre_assert(if_softc_ctx_t scctx) 5355 { 5356 5357 MPASS(scctx->isc_txrx->ift_txd_encap); 5358 MPASS(scctx->isc_txrx->ift_txd_flush); 5359 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5360 MPASS(scctx->isc_txrx->ift_rxd_available); 5361 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5362 MPASS(scctx->isc_txrx->ift_rxd_refill); 5363 MPASS(scctx->isc_txrx->ift_rxd_flush); 5364 } 5365 5366 static int 5367 iflib_register(if_ctx_t ctx) 5368 { 5369 if_shared_ctx_t sctx = ctx->ifc_sctx; 5370 driver_t *driver = sctx->isc_driver; 5371 device_t dev = ctx->ifc_dev; 5372 if_t ifp; 5373 5374 _iflib_assert(sctx); 5375 5376 CTX_LOCK_INIT(ctx); 5377 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5378 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5379 if (ifp == NULL) { 5380 device_printf(dev, "can not allocate ifnet structure\n"); 5381 return (ENOMEM); 5382 } 5383 5384 /* 5385 * Initialize our context's device specific methods 5386 */ 5387 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5388 kobj_class_compile((kobj_class_t) driver); 5389 5390 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5391 if_setsoftc(ifp, ctx); 5392 if_setdev(ifp, dev); 5393 if_setinitfn(ifp, iflib_if_init); 5394 if_setioctlfn(ifp, iflib_if_ioctl); 5395 #ifdef ALTQ 5396 if_setstartfn(ifp, iflib_altq_if_start); 5397 if_settransmitfn(ifp, iflib_altq_if_transmit); 5398 if_setsendqready(ifp); 5399 #else 5400 if_settransmitfn(ifp, iflib_if_transmit); 5401 #endif 5402 if_setqflushfn(ifp, iflib_if_qflush); 5403 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5404 5405 ctx->ifc_vlan_attach_event = 5406 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5407 EVENTHANDLER_PRI_FIRST); 5408 ctx->ifc_vlan_detach_event = 5409 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5410 EVENTHANDLER_PRI_FIRST); 5411 5412 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5413 ctx->ifc_mediap = &ctx->ifc_media; 5414 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5415 iflib_media_change, iflib_media_status); 5416 } 5417 return (0); 5418 } 5419 5420 static void 5421 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5422 { 5423 /* Unregister VLAN events */ 5424 if (ctx->ifc_vlan_attach_event != NULL) { 5425 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5426 ctx->ifc_vlan_attach_event = NULL; 5427 } 5428 if (ctx->ifc_vlan_detach_event != NULL) { 5429 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5430 ctx->ifc_vlan_detach_event = NULL; 5431 } 5432 5433 } 5434 5435 static void 5436 iflib_deregister(if_ctx_t ctx) 5437 { 5438 if_t ifp = ctx->ifc_ifp; 5439 5440 /* Remove all media */ 5441 ifmedia_removeall(&ctx->ifc_media); 5442 5443 /* Ensure that VLAN event handlers are unregistered */ 5444 iflib_unregister_vlan_handlers(ctx); 5445 5446 /* Release kobject reference */ 5447 kobj_delete((kobj_t) ctx, NULL); 5448 5449 /* Free the ifnet structure */ 5450 if_free(ifp); 5451 5452 STATE_LOCK_DESTROY(ctx); 5453 5454 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5455 CTX_LOCK_DESTROY(ctx); 5456 } 5457 5458 static int 5459 iflib_queues_alloc(if_ctx_t ctx) 5460 { 5461 if_shared_ctx_t sctx = ctx->ifc_sctx; 5462 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5463 device_t dev = ctx->ifc_dev; 5464 int nrxqsets = scctx->isc_nrxqsets; 5465 int ntxqsets = scctx->isc_ntxqsets; 5466 iflib_txq_t txq; 5467 iflib_rxq_t rxq; 5468 iflib_fl_t fl = NULL; 5469 int i, j, cpu, err, txconf, rxconf; 5470 iflib_dma_info_t ifdip; 5471 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5472 uint32_t *txqsizes = scctx->isc_txqsizes; 5473 uint8_t nrxqs = sctx->isc_nrxqs; 5474 uint8_t ntxqs = sctx->isc_ntxqs; 5475 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5476 caddr_t *vaddrs; 5477 uint64_t *paddrs; 5478 5479 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5480 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5481 5482 /* Allocate the TX ring struct memory */ 5483 if (!(ctx->ifc_txqs = 5484 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5485 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5486 device_printf(dev, "Unable to allocate TX ring memory\n"); 5487 err = ENOMEM; 5488 goto fail; 5489 } 5490 5491 /* Now allocate the RX */ 5492 if (!(ctx->ifc_rxqs = 5493 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5494 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5495 device_printf(dev, "Unable to allocate RX ring memory\n"); 5496 err = ENOMEM; 5497 goto rx_fail; 5498 } 5499 5500 txq = ctx->ifc_txqs; 5501 rxq = ctx->ifc_rxqs; 5502 5503 /* 5504 * XXX handle allocation failure 5505 */ 5506 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5507 /* Set up some basics */ 5508 5509 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5510 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5511 device_printf(dev, 5512 "Unable to allocate TX DMA info memory\n"); 5513 err = ENOMEM; 5514 goto err_tx_desc; 5515 } 5516 txq->ift_ifdi = ifdip; 5517 for (j = 0; j < ntxqs; j++, ifdip++) { 5518 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5519 device_printf(dev, 5520 "Unable to allocate TX descriptors\n"); 5521 err = ENOMEM; 5522 goto err_tx_desc; 5523 } 5524 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5525 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5526 } 5527 txq->ift_ctx = ctx; 5528 txq->ift_id = i; 5529 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5530 txq->ift_br_offset = 1; 5531 } else { 5532 txq->ift_br_offset = 0; 5533 } 5534 /* XXX fix this */ 5535 txq->ift_timer.c_cpu = cpu; 5536 5537 if (iflib_txsd_alloc(txq)) { 5538 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5539 err = ENOMEM; 5540 goto err_tx_desc; 5541 } 5542 5543 /* Initialize the TX lock */ 5544 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5545 device_get_nameunit(dev), txq->ift_id); 5546 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5547 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5548 5549 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5550 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5551 if (err) { 5552 /* XXX free any allocated rings */ 5553 device_printf(dev, "Unable to allocate buf_ring\n"); 5554 goto err_tx_desc; 5555 } 5556 } 5557 5558 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5559 /* Set up some basics */ 5560 callout_init(&rxq->ifr_watchdog, 1); 5561 5562 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5563 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5564 device_printf(dev, 5565 "Unable to allocate RX DMA info memory\n"); 5566 err = ENOMEM; 5567 goto err_tx_desc; 5568 } 5569 5570 rxq->ifr_ifdi = ifdip; 5571 /* XXX this needs to be changed if #rx queues != #tx queues */ 5572 rxq->ifr_ntxqirq = 1; 5573 rxq->ifr_txqid[0] = i; 5574 for (j = 0; j < nrxqs; j++, ifdip++) { 5575 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5576 device_printf(dev, 5577 "Unable to allocate RX descriptors\n"); 5578 err = ENOMEM; 5579 goto err_tx_desc; 5580 } 5581 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5582 } 5583 rxq->ifr_ctx = ctx; 5584 rxq->ifr_id = i; 5585 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5586 rxq->ifr_fl_offset = 1; 5587 } else { 5588 rxq->ifr_fl_offset = 0; 5589 } 5590 rxq->ifr_nfl = nfree_lists; 5591 if (!(fl = 5592 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5593 device_printf(dev, "Unable to allocate free list memory\n"); 5594 err = ENOMEM; 5595 goto err_tx_desc; 5596 } 5597 rxq->ifr_fl = fl; 5598 for (j = 0; j < nfree_lists; j++) { 5599 fl[j].ifl_rxq = rxq; 5600 fl[j].ifl_id = j; 5601 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5602 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5603 } 5604 /* Allocate receive buffers for the ring */ 5605 if (iflib_rxsd_alloc(rxq)) { 5606 device_printf(dev, 5607 "Critical Failure setting up receive buffers\n"); 5608 err = ENOMEM; 5609 goto err_rx_desc; 5610 } 5611 5612 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5613 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5614 M_WAITOK); 5615 } 5616 5617 /* TXQs */ 5618 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5619 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5620 for (i = 0; i < ntxqsets; i++) { 5621 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5622 5623 for (j = 0; j < ntxqs; j++, di++) { 5624 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5625 paddrs[i*ntxqs + j] = di->idi_paddr; 5626 } 5627 } 5628 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5629 device_printf(ctx->ifc_dev, 5630 "Unable to allocate device TX queue\n"); 5631 iflib_tx_structures_free(ctx); 5632 free(vaddrs, M_IFLIB); 5633 free(paddrs, M_IFLIB); 5634 goto err_rx_desc; 5635 } 5636 free(vaddrs, M_IFLIB); 5637 free(paddrs, M_IFLIB); 5638 5639 /* RXQs */ 5640 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5641 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5642 for (i = 0; i < nrxqsets; i++) { 5643 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5644 5645 for (j = 0; j < nrxqs; j++, di++) { 5646 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5647 paddrs[i*nrxqs + j] = di->idi_paddr; 5648 } 5649 } 5650 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5651 device_printf(ctx->ifc_dev, 5652 "Unable to allocate device RX queue\n"); 5653 iflib_tx_structures_free(ctx); 5654 free(vaddrs, M_IFLIB); 5655 free(paddrs, M_IFLIB); 5656 goto err_rx_desc; 5657 } 5658 free(vaddrs, M_IFLIB); 5659 free(paddrs, M_IFLIB); 5660 5661 return (0); 5662 5663 /* XXX handle allocation failure changes */ 5664 err_rx_desc: 5665 err_tx_desc: 5666 rx_fail: 5667 if (ctx->ifc_rxqs != NULL) 5668 free(ctx->ifc_rxqs, M_IFLIB); 5669 ctx->ifc_rxqs = NULL; 5670 if (ctx->ifc_txqs != NULL) 5671 free(ctx->ifc_txqs, M_IFLIB); 5672 ctx->ifc_txqs = NULL; 5673 fail: 5674 return (err); 5675 } 5676 5677 static int 5678 iflib_tx_structures_setup(if_ctx_t ctx) 5679 { 5680 iflib_txq_t txq = ctx->ifc_txqs; 5681 int i; 5682 5683 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5684 iflib_txq_setup(txq); 5685 5686 return (0); 5687 } 5688 5689 static void 5690 iflib_tx_structures_free(if_ctx_t ctx) 5691 { 5692 iflib_txq_t txq = ctx->ifc_txqs; 5693 if_shared_ctx_t sctx = ctx->ifc_sctx; 5694 int i, j; 5695 5696 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5697 for (j = 0; j < sctx->isc_ntxqs; j++) 5698 iflib_dma_free(&txq->ift_ifdi[j]); 5699 iflib_txq_destroy(txq); 5700 } 5701 free(ctx->ifc_txqs, M_IFLIB); 5702 ctx->ifc_txqs = NULL; 5703 IFDI_QUEUES_FREE(ctx); 5704 } 5705 5706 /********************************************************************* 5707 * 5708 * Initialize all receive rings. 5709 * 5710 **********************************************************************/ 5711 static int 5712 iflib_rx_structures_setup(if_ctx_t ctx) 5713 { 5714 iflib_rxq_t rxq = ctx->ifc_rxqs; 5715 int q; 5716 #if defined(INET6) || defined(INET) 5717 int err, i; 5718 #endif 5719 5720 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5721 #if defined(INET6) || defined(INET) 5722 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5723 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5724 TCP_LRO_ENTRIES, min(1024, 5725 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5726 if (err != 0) { 5727 device_printf(ctx->ifc_dev, 5728 "LRO Initialization failed!\n"); 5729 goto fail; 5730 } 5731 } 5732 #endif 5733 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5734 } 5735 return (0); 5736 #if defined(INET6) || defined(INET) 5737 fail: 5738 /* 5739 * Free LRO resources allocated so far, we will only handle 5740 * the rings that completed, the failing case will have 5741 * cleaned up for itself. 'q' failed, so its the terminus. 5742 */ 5743 rxq = ctx->ifc_rxqs; 5744 for (i = 0; i < q; ++i, rxq++) { 5745 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5746 tcp_lro_free(&rxq->ifr_lc); 5747 } 5748 return (err); 5749 #endif 5750 } 5751 5752 /********************************************************************* 5753 * 5754 * Free all receive rings. 5755 * 5756 **********************************************************************/ 5757 static void 5758 iflib_rx_structures_free(if_ctx_t ctx) 5759 { 5760 iflib_rxq_t rxq = ctx->ifc_rxqs; 5761 if_shared_ctx_t sctx = ctx->ifc_sctx; 5762 int i, j; 5763 5764 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5765 for (j = 0; j < sctx->isc_nrxqs; j++) 5766 iflib_dma_free(&rxq->ifr_ifdi[j]); 5767 iflib_rx_sds_free(rxq); 5768 #if defined(INET6) || defined(INET) 5769 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5770 tcp_lro_free(&rxq->ifr_lc); 5771 #endif 5772 } 5773 free(ctx->ifc_rxqs, M_IFLIB); 5774 ctx->ifc_rxqs = NULL; 5775 } 5776 5777 static int 5778 iflib_qset_structures_setup(if_ctx_t ctx) 5779 { 5780 int err; 5781 5782 /* 5783 * It is expected that the caller takes care of freeing queues if this 5784 * fails. 5785 */ 5786 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5787 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5788 return (err); 5789 } 5790 5791 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5792 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5793 5794 return (err); 5795 } 5796 5797 int 5798 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5799 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5800 { 5801 5802 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5803 } 5804 5805 #ifdef SMP 5806 static int 5807 find_nth(if_ctx_t ctx, int qid) 5808 { 5809 cpuset_t cpus; 5810 int i, cpuid, eqid, count; 5811 5812 CPU_COPY(&ctx->ifc_cpus, &cpus); 5813 count = CPU_COUNT(&cpus); 5814 eqid = qid % count; 5815 /* clear up to the qid'th bit */ 5816 for (i = 0; i < eqid; i++) { 5817 cpuid = CPU_FFS(&cpus); 5818 MPASS(cpuid != 0); 5819 CPU_CLR(cpuid-1, &cpus); 5820 } 5821 cpuid = CPU_FFS(&cpus); 5822 MPASS(cpuid != 0); 5823 return (cpuid-1); 5824 } 5825 5826 #ifdef SCHED_ULE 5827 extern struct cpu_group *cpu_top; /* CPU topology */ 5828 5829 static int 5830 find_child_with_core(int cpu, struct cpu_group *grp) 5831 { 5832 int i; 5833 5834 if (grp->cg_children == 0) 5835 return -1; 5836 5837 MPASS(grp->cg_child); 5838 for (i = 0; i < grp->cg_children; i++) { 5839 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5840 return i; 5841 } 5842 5843 return -1; 5844 } 5845 5846 /* 5847 * Find the nth "close" core to the specified core 5848 * "close" is defined as the deepest level that shares 5849 * at least an L2 cache. With threads, this will be 5850 * threads on the same core. If the shared cache is L3 5851 * or higher, simply returns the same core. 5852 */ 5853 static int 5854 find_close_core(int cpu, int core_offset) 5855 { 5856 struct cpu_group *grp; 5857 int i; 5858 int fcpu; 5859 cpuset_t cs; 5860 5861 grp = cpu_top; 5862 if (grp == NULL) 5863 return cpu; 5864 i = 0; 5865 while ((i = find_child_with_core(cpu, grp)) != -1) { 5866 /* If the child only has one cpu, don't descend */ 5867 if (grp->cg_child[i].cg_count <= 1) 5868 break; 5869 grp = &grp->cg_child[i]; 5870 } 5871 5872 /* If they don't share at least an L2 cache, use the same CPU */ 5873 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5874 return cpu; 5875 5876 /* Now pick one */ 5877 CPU_COPY(&grp->cg_mask, &cs); 5878 5879 /* Add the selected CPU offset to core offset. */ 5880 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5881 if (fcpu - 1 == cpu) 5882 break; 5883 CPU_CLR(fcpu - 1, &cs); 5884 } 5885 MPASS(fcpu); 5886 5887 core_offset += i; 5888 5889 CPU_COPY(&grp->cg_mask, &cs); 5890 for (i = core_offset % grp->cg_count; i > 0; i--) { 5891 MPASS(CPU_FFS(&cs)); 5892 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5893 } 5894 MPASS(CPU_FFS(&cs)); 5895 return CPU_FFS(&cs) - 1; 5896 } 5897 #else 5898 static int 5899 find_close_core(int cpu, int core_offset __unused) 5900 { 5901 return cpu; 5902 } 5903 #endif 5904 5905 static int 5906 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5907 { 5908 switch (type) { 5909 case IFLIB_INTR_TX: 5910 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5911 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5912 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5913 case IFLIB_INTR_RX: 5914 case IFLIB_INTR_RXTX: 5915 /* RX queues get the specified core */ 5916 return qid / CPU_COUNT(&ctx->ifc_cpus); 5917 default: 5918 return -1; 5919 } 5920 } 5921 #else 5922 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5923 #define find_close_core(cpuid, tid) CPU_FIRST() 5924 #define find_nth(ctx, gid) CPU_FIRST() 5925 #endif 5926 5927 /* Just to avoid copy/paste */ 5928 static inline int 5929 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5930 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5931 const char *name) 5932 { 5933 device_t dev; 5934 int co, cpuid, err, tid; 5935 5936 dev = ctx->ifc_dev; 5937 co = ctx->ifc_sysctl_core_offset; 5938 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5939 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5940 cpuid = find_nth(ctx, qid + co); 5941 tid = get_core_offset(ctx, type, qid); 5942 if (tid < 0) { 5943 device_printf(dev, "get_core_offset failed\n"); 5944 return (EOPNOTSUPP); 5945 } 5946 cpuid = find_close_core(cpuid, tid); 5947 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5948 name); 5949 if (err) { 5950 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5951 return (err); 5952 } 5953 #ifdef notyet 5954 if (cpuid > ctx->ifc_cpuid_highest) 5955 ctx->ifc_cpuid_highest = cpuid; 5956 #endif 5957 return (0); 5958 } 5959 5960 int 5961 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5962 iflib_intr_type_t type, driver_filter_t *filter, 5963 void *filter_arg, int qid, const char *name) 5964 { 5965 device_t dev; 5966 struct grouptask *gtask; 5967 struct taskqgroup *tqg; 5968 iflib_filter_info_t info; 5969 gtask_fn_t *fn; 5970 int tqrid, err; 5971 driver_filter_t *intr_fast; 5972 void *q; 5973 5974 info = &ctx->ifc_filter_info; 5975 tqrid = rid; 5976 5977 switch (type) { 5978 /* XXX merge tx/rx for netmap? */ 5979 case IFLIB_INTR_TX: 5980 q = &ctx->ifc_txqs[qid]; 5981 info = &ctx->ifc_txqs[qid].ift_filter_info; 5982 gtask = &ctx->ifc_txqs[qid].ift_task; 5983 tqg = qgroup_if_io_tqg; 5984 fn = _task_fn_tx; 5985 intr_fast = iflib_fast_intr; 5986 GROUPTASK_INIT(gtask, 0, fn, q); 5987 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5988 break; 5989 case IFLIB_INTR_RX: 5990 q = &ctx->ifc_rxqs[qid]; 5991 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5992 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5993 tqg = qgroup_if_io_tqg; 5994 fn = _task_fn_rx; 5995 intr_fast = iflib_fast_intr; 5996 NET_GROUPTASK_INIT(gtask, 0, fn, q); 5997 break; 5998 case IFLIB_INTR_RXTX: 5999 q = &ctx->ifc_rxqs[qid]; 6000 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6001 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6002 tqg = qgroup_if_io_tqg; 6003 fn = _task_fn_rx; 6004 intr_fast = iflib_fast_intr_rxtx; 6005 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6006 break; 6007 case IFLIB_INTR_ADMIN: 6008 q = ctx; 6009 tqrid = -1; 6010 info = &ctx->ifc_filter_info; 6011 gtask = &ctx->ifc_admin_task; 6012 tqg = qgroup_if_config_tqg; 6013 fn = _task_fn_admin; 6014 intr_fast = iflib_fast_intr_ctx; 6015 break; 6016 default: 6017 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6018 __func__); 6019 return (EINVAL); 6020 } 6021 6022 info->ifi_filter = filter; 6023 info->ifi_filter_arg = filter_arg; 6024 info->ifi_task = gtask; 6025 info->ifi_ctx = q; 6026 6027 dev = ctx->ifc_dev; 6028 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6029 if (err != 0) { 6030 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6031 return (err); 6032 } 6033 if (type == IFLIB_INTR_ADMIN) 6034 return (0); 6035 6036 if (tqrid != -1) { 6037 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6038 q, name); 6039 if (err) 6040 return (err); 6041 } else { 6042 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6043 } 6044 6045 return (0); 6046 } 6047 6048 void 6049 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6050 { 6051 struct grouptask *gtask; 6052 struct taskqgroup *tqg; 6053 gtask_fn_t *fn; 6054 void *q; 6055 int err; 6056 6057 switch (type) { 6058 case IFLIB_INTR_TX: 6059 q = &ctx->ifc_txqs[qid]; 6060 gtask = &ctx->ifc_txqs[qid].ift_task; 6061 tqg = qgroup_if_io_tqg; 6062 fn = _task_fn_tx; 6063 GROUPTASK_INIT(gtask, 0, fn, q); 6064 break; 6065 case IFLIB_INTR_RX: 6066 q = &ctx->ifc_rxqs[qid]; 6067 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6068 tqg = qgroup_if_io_tqg; 6069 fn = _task_fn_rx; 6070 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6071 break; 6072 case IFLIB_INTR_IOV: 6073 q = ctx; 6074 gtask = &ctx->ifc_vflr_task; 6075 tqg = qgroup_if_config_tqg; 6076 fn = _task_fn_iov; 6077 GROUPTASK_INIT(gtask, 0, fn, q); 6078 break; 6079 default: 6080 panic("unknown net intr type"); 6081 } 6082 if (irq != NULL) { 6083 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6084 q, name); 6085 if (err) 6086 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6087 irq->ii_res, name); 6088 } else { 6089 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6090 } 6091 } 6092 6093 void 6094 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6095 { 6096 6097 if (irq->ii_tag) 6098 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6099 6100 if (irq->ii_res) 6101 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6102 rman_get_rid(irq->ii_res), irq->ii_res); 6103 } 6104 6105 static int 6106 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6107 { 6108 iflib_txq_t txq = ctx->ifc_txqs; 6109 iflib_rxq_t rxq = ctx->ifc_rxqs; 6110 if_irq_t irq = &ctx->ifc_legacy_irq; 6111 iflib_filter_info_t info; 6112 device_t dev; 6113 struct grouptask *gtask; 6114 struct resource *res; 6115 struct taskqgroup *tqg; 6116 void *q; 6117 int err, tqrid; 6118 bool rx_only; 6119 6120 q = &ctx->ifc_rxqs[0]; 6121 info = &rxq[0].ifr_filter_info; 6122 gtask = &rxq[0].ifr_task; 6123 tqg = qgroup_if_io_tqg; 6124 tqrid = *rid; 6125 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6126 6127 ctx->ifc_flags |= IFC_LEGACY; 6128 info->ifi_filter = filter; 6129 info->ifi_filter_arg = filter_arg; 6130 info->ifi_task = gtask; 6131 info->ifi_ctx = rx_only ? ctx : q; 6132 6133 dev = ctx->ifc_dev; 6134 /* We allocate a single interrupt resource */ 6135 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6136 iflib_fast_intr_rxtx, NULL, info, name); 6137 if (err != 0) 6138 return (err); 6139 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6140 res = irq->ii_res; 6141 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6142 6143 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6144 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6145 "tx"); 6146 return (0); 6147 } 6148 6149 void 6150 iflib_led_create(if_ctx_t ctx) 6151 { 6152 6153 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6154 device_get_nameunit(ctx->ifc_dev)); 6155 } 6156 6157 void 6158 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6159 { 6160 6161 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6162 } 6163 6164 void 6165 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6166 { 6167 6168 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6169 } 6170 6171 void 6172 iflib_admin_intr_deferred(if_ctx_t ctx) 6173 { 6174 #ifdef INVARIANTS 6175 struct grouptask *gtask; 6176 6177 gtask = &ctx->ifc_admin_task; 6178 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 6179 #endif 6180 6181 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6182 } 6183 6184 void 6185 iflib_iov_intr_deferred(if_ctx_t ctx) 6186 { 6187 6188 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6189 } 6190 6191 void 6192 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6193 { 6194 6195 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6196 name); 6197 } 6198 6199 void 6200 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6201 const char *name) 6202 { 6203 6204 GROUPTASK_INIT(gtask, 0, fn, ctx); 6205 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6206 name); 6207 } 6208 6209 void 6210 iflib_config_gtask_deinit(struct grouptask *gtask) 6211 { 6212 6213 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6214 } 6215 6216 void 6217 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6218 { 6219 if_t ifp = ctx->ifc_ifp; 6220 iflib_txq_t txq = ctx->ifc_txqs; 6221 6222 if_setbaudrate(ifp, baudrate); 6223 if (baudrate >= IF_Gbps(10)) { 6224 STATE_LOCK(ctx); 6225 ctx->ifc_flags |= IFC_PREFETCH; 6226 STATE_UNLOCK(ctx); 6227 } 6228 /* If link down, disable watchdog */ 6229 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6230 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6231 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6232 } 6233 ctx->ifc_link_state = link_state; 6234 if_link_state_change(ifp, link_state); 6235 } 6236 6237 static int 6238 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6239 { 6240 int credits; 6241 #ifdef INVARIANTS 6242 int credits_pre = txq->ift_cidx_processed; 6243 #endif 6244 6245 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6246 BUS_DMASYNC_POSTREAD); 6247 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6248 return (0); 6249 6250 txq->ift_processed += credits; 6251 txq->ift_cidx_processed += credits; 6252 6253 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6254 if (txq->ift_cidx_processed >= txq->ift_size) 6255 txq->ift_cidx_processed -= txq->ift_size; 6256 return (credits); 6257 } 6258 6259 static int 6260 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6261 { 6262 iflib_fl_t fl; 6263 u_int i; 6264 6265 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6266 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6267 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6268 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6269 budget)); 6270 } 6271 6272 void 6273 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6274 const char *description, if_int_delay_info_t info, 6275 int offset, int value) 6276 { 6277 info->iidi_ctx = ctx; 6278 info->iidi_offset = offset; 6279 info->iidi_value = value; 6280 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6281 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6282 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 6283 info, 0, iflib_sysctl_int_delay, "I", description); 6284 } 6285 6286 struct sx * 6287 iflib_ctx_lock_get(if_ctx_t ctx) 6288 { 6289 6290 return (&ctx->ifc_ctx_sx); 6291 } 6292 6293 static int 6294 iflib_msix_init(if_ctx_t ctx) 6295 { 6296 device_t dev = ctx->ifc_dev; 6297 if_shared_ctx_t sctx = ctx->ifc_sctx; 6298 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6299 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6300 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6301 6302 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6303 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6304 6305 if (bootverbose) 6306 device_printf(dev, "msix_init qsets capped at %d\n", 6307 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6308 6309 /* Override by tuneable */ 6310 if (scctx->isc_disable_msix) 6311 goto msi; 6312 6313 /* First try MSI-X */ 6314 if ((msgs = pci_msix_count(dev)) == 0) { 6315 if (bootverbose) 6316 device_printf(dev, "MSI-X not supported or disabled\n"); 6317 goto msi; 6318 } 6319 6320 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6321 /* 6322 * bar == -1 => "trust me I know what I'm doing" 6323 * Some drivers are for hardware that is so shoddily 6324 * documented that no one knows which bars are which 6325 * so the developer has to map all bars. This hack 6326 * allows shoddy garbage to use MSI-X in this framework. 6327 */ 6328 if (bar != -1) { 6329 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6330 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6331 if (ctx->ifc_msix_mem == NULL) { 6332 device_printf(dev, "Unable to map MSI-X table\n"); 6333 goto msi; 6334 } 6335 } 6336 6337 admincnt = sctx->isc_admin_intrcnt; 6338 #if IFLIB_DEBUG 6339 /* use only 1 qset in debug mode */ 6340 queuemsgs = min(msgs - admincnt, 1); 6341 #else 6342 queuemsgs = msgs - admincnt; 6343 #endif 6344 #ifdef RSS 6345 queues = imin(queuemsgs, rss_getnumbuckets()); 6346 #else 6347 queues = queuemsgs; 6348 #endif 6349 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6350 if (bootverbose) 6351 device_printf(dev, 6352 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6353 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6354 #ifdef RSS 6355 /* If we're doing RSS, clamp at the number of RSS buckets */ 6356 if (queues > rss_getnumbuckets()) 6357 queues = rss_getnumbuckets(); 6358 #endif 6359 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6360 rx_queues = iflib_num_rx_queues; 6361 else 6362 rx_queues = queues; 6363 6364 if (rx_queues > scctx->isc_nrxqsets) 6365 rx_queues = scctx->isc_nrxqsets; 6366 6367 /* 6368 * We want this to be all logical CPUs by default 6369 */ 6370 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6371 tx_queues = iflib_num_tx_queues; 6372 else 6373 tx_queues = mp_ncpus; 6374 6375 if (tx_queues > scctx->isc_ntxqsets) 6376 tx_queues = scctx->isc_ntxqsets; 6377 6378 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6379 #ifdef INVARIANTS 6380 if (tx_queues != rx_queues) 6381 device_printf(dev, 6382 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6383 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6384 #endif 6385 tx_queues = min(rx_queues, tx_queues); 6386 rx_queues = min(rx_queues, tx_queues); 6387 } 6388 6389 vectors = rx_queues + admincnt; 6390 if (msgs < vectors) { 6391 device_printf(dev, 6392 "insufficient number of MSI-X vectors " 6393 "(supported %d, need %d)\n", msgs, vectors); 6394 goto msi; 6395 } 6396 6397 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6398 tx_queues); 6399 msgs = vectors; 6400 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6401 if (vectors != msgs) { 6402 device_printf(dev, 6403 "Unable to allocate sufficient MSI-X vectors " 6404 "(got %d, need %d)\n", vectors, msgs); 6405 pci_release_msi(dev); 6406 if (bar != -1) { 6407 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6408 ctx->ifc_msix_mem); 6409 ctx->ifc_msix_mem = NULL; 6410 } 6411 goto msi; 6412 } 6413 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6414 vectors); 6415 scctx->isc_vectors = vectors; 6416 scctx->isc_nrxqsets = rx_queues; 6417 scctx->isc_ntxqsets = tx_queues; 6418 scctx->isc_intr = IFLIB_INTR_MSIX; 6419 6420 return (vectors); 6421 } else { 6422 device_printf(dev, 6423 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6424 err); 6425 if (bar != -1) { 6426 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6427 ctx->ifc_msix_mem); 6428 ctx->ifc_msix_mem = NULL; 6429 } 6430 } 6431 6432 msi: 6433 vectors = pci_msi_count(dev); 6434 scctx->isc_nrxqsets = 1; 6435 scctx->isc_ntxqsets = 1; 6436 scctx->isc_vectors = vectors; 6437 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6438 device_printf(dev,"Using an MSI interrupt\n"); 6439 scctx->isc_intr = IFLIB_INTR_MSI; 6440 } else { 6441 scctx->isc_vectors = 1; 6442 device_printf(dev,"Using a Legacy interrupt\n"); 6443 scctx->isc_intr = IFLIB_INTR_LEGACY; 6444 } 6445 6446 return (vectors); 6447 } 6448 6449 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6450 6451 static int 6452 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6453 { 6454 int rc; 6455 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6456 struct sbuf *sb; 6457 const char *ring_state = "UNKNOWN"; 6458 6459 /* XXX needed ? */ 6460 rc = sysctl_wire_old_buffer(req, 0); 6461 MPASS(rc == 0); 6462 if (rc != 0) 6463 return (rc); 6464 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6465 MPASS(sb != NULL); 6466 if (sb == NULL) 6467 return (ENOMEM); 6468 if (state[3] <= 3) 6469 ring_state = ring_states[state[3]]; 6470 6471 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6472 state[0], state[1], state[2], ring_state); 6473 rc = sbuf_finish(sb); 6474 sbuf_delete(sb); 6475 return(rc); 6476 } 6477 6478 enum iflib_ndesc_handler { 6479 IFLIB_NTXD_HANDLER, 6480 IFLIB_NRXD_HANDLER, 6481 }; 6482 6483 static int 6484 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6485 { 6486 if_ctx_t ctx = (void *)arg1; 6487 enum iflib_ndesc_handler type = arg2; 6488 char buf[256] = {0}; 6489 qidx_t *ndesc; 6490 char *p, *next; 6491 int nqs, rc, i; 6492 6493 nqs = 8; 6494 switch(type) { 6495 case IFLIB_NTXD_HANDLER: 6496 ndesc = ctx->ifc_sysctl_ntxds; 6497 if (ctx->ifc_sctx) 6498 nqs = ctx->ifc_sctx->isc_ntxqs; 6499 break; 6500 case IFLIB_NRXD_HANDLER: 6501 ndesc = ctx->ifc_sysctl_nrxds; 6502 if (ctx->ifc_sctx) 6503 nqs = ctx->ifc_sctx->isc_nrxqs; 6504 break; 6505 default: 6506 printf("%s: unhandled type\n", __func__); 6507 return (EINVAL); 6508 } 6509 if (nqs == 0) 6510 nqs = 8; 6511 6512 for (i=0; i<8; i++) { 6513 if (i >= nqs) 6514 break; 6515 if (i) 6516 strcat(buf, ","); 6517 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6518 } 6519 6520 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6521 if (rc || req->newptr == NULL) 6522 return rc; 6523 6524 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6525 i++, p = strsep(&next, " ,")) { 6526 ndesc[i] = strtoul(p, NULL, 10); 6527 } 6528 6529 return(rc); 6530 } 6531 6532 #define NAME_BUFLEN 32 6533 static void 6534 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6535 { 6536 device_t dev = iflib_get_dev(ctx); 6537 struct sysctl_oid_list *child, *oid_list; 6538 struct sysctl_ctx_list *ctx_list; 6539 struct sysctl_oid *node; 6540 6541 ctx_list = device_get_sysctl_ctx(dev); 6542 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6543 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6544 CTLFLAG_RD, NULL, "IFLIB fields"); 6545 oid_list = SYSCTL_CHILDREN(node); 6546 6547 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6548 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6549 "driver version"); 6550 6551 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6552 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6553 "# of txqs to use, 0 => use default #"); 6554 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6555 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6556 "# of rxqs to use, 0 => use default #"); 6557 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6558 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6559 "permit #txq != #rxq"); 6560 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6561 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6562 "disable MSI-X (default 0)"); 6563 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6564 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6565 "set the RX budget"); 6566 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6567 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6568 "cause TX to abdicate instead of running to completion"); 6569 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6570 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6571 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6572 "offset to start using cores at"); 6573 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6574 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6575 "use separate cores for TX and RX"); 6576 6577 /* XXX change for per-queue sizes */ 6578 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6579 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6580 mp_ndesc_handler, "A", 6581 "list of # of TX descriptors to use, 0 = use default #"); 6582 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6583 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6584 mp_ndesc_handler, "A", 6585 "list of # of RX descriptors to use, 0 = use default #"); 6586 } 6587 6588 static void 6589 iflib_add_device_sysctl_post(if_ctx_t ctx) 6590 { 6591 if_shared_ctx_t sctx = ctx->ifc_sctx; 6592 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6593 device_t dev = iflib_get_dev(ctx); 6594 struct sysctl_oid_list *child; 6595 struct sysctl_ctx_list *ctx_list; 6596 iflib_fl_t fl; 6597 iflib_txq_t txq; 6598 iflib_rxq_t rxq; 6599 int i, j; 6600 char namebuf[NAME_BUFLEN]; 6601 char *qfmt; 6602 struct sysctl_oid *queue_node, *fl_node, *node; 6603 struct sysctl_oid_list *queue_list, *fl_list; 6604 ctx_list = device_get_sysctl_ctx(dev); 6605 6606 node = ctx->ifc_sysctl_node; 6607 child = SYSCTL_CHILDREN(node); 6608 6609 if (scctx->isc_ntxqsets > 100) 6610 qfmt = "txq%03d"; 6611 else if (scctx->isc_ntxqsets > 10) 6612 qfmt = "txq%02d"; 6613 else 6614 qfmt = "txq%d"; 6615 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6616 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6617 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6618 CTLFLAG_RD, NULL, "Queue Name"); 6619 queue_list = SYSCTL_CHILDREN(queue_node); 6620 #if MEMORY_LOGGING 6621 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6622 CTLFLAG_RD, 6623 &txq->ift_dequeued, "total mbufs freed"); 6624 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6625 CTLFLAG_RD, 6626 &txq->ift_enqueued, "total mbufs enqueued"); 6627 #endif 6628 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6629 CTLFLAG_RD, 6630 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6631 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6632 CTLFLAG_RD, 6633 &txq->ift_pullups, "# of times m_pullup was called"); 6634 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6635 CTLFLAG_RD, 6636 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6637 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6638 CTLFLAG_RD, 6639 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6640 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6641 CTLFLAG_RD, 6642 &txq->ift_map_failed, "# of times DMA map failed"); 6643 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6644 CTLFLAG_RD, 6645 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6646 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6647 CTLFLAG_RD, 6648 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6649 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6650 CTLFLAG_RD, 6651 &txq->ift_pidx, 1, "Producer Index"); 6652 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6653 CTLFLAG_RD, 6654 &txq->ift_cidx, 1, "Consumer Index"); 6655 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6656 CTLFLAG_RD, 6657 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6658 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6659 CTLFLAG_RD, 6660 &txq->ift_in_use, 1, "descriptors in use"); 6661 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6662 CTLFLAG_RD, 6663 &txq->ift_processed, "descriptors procesed for clean"); 6664 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6665 CTLFLAG_RD, 6666 &txq->ift_cleaned, "total cleaned"); 6667 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6668 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6669 0, mp_ring_state_handler, "A", "soft ring state"); 6670 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6671 CTLFLAG_RD, &txq->ift_br->enqueues, 6672 "# of enqueues to the mp_ring for this queue"); 6673 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6674 CTLFLAG_RD, &txq->ift_br->drops, 6675 "# of drops in the mp_ring for this queue"); 6676 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6677 CTLFLAG_RD, &txq->ift_br->starts, 6678 "# of normal consumer starts in the mp_ring for this queue"); 6679 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6680 CTLFLAG_RD, &txq->ift_br->stalls, 6681 "# of consumer stalls in the mp_ring for this queue"); 6682 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6683 CTLFLAG_RD, &txq->ift_br->restarts, 6684 "# of consumer restarts in the mp_ring for this queue"); 6685 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6686 CTLFLAG_RD, &txq->ift_br->abdications, 6687 "# of consumer abdications in the mp_ring for this queue"); 6688 } 6689 6690 if (scctx->isc_nrxqsets > 100) 6691 qfmt = "rxq%03d"; 6692 else if (scctx->isc_nrxqsets > 10) 6693 qfmt = "rxq%02d"; 6694 else 6695 qfmt = "rxq%d"; 6696 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6697 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6698 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6699 CTLFLAG_RD, NULL, "Queue Name"); 6700 queue_list = SYSCTL_CHILDREN(queue_node); 6701 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6702 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6703 CTLFLAG_RD, 6704 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6705 } 6706 6707 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6708 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6709 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6710 CTLFLAG_RD, NULL, "freelist Name"); 6711 fl_list = SYSCTL_CHILDREN(fl_node); 6712 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6713 CTLFLAG_RD, 6714 &fl->ifl_pidx, 1, "Producer Index"); 6715 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6716 CTLFLAG_RD, 6717 &fl->ifl_cidx, 1, "Consumer Index"); 6718 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6719 CTLFLAG_RD, 6720 &fl->ifl_credits, 1, "credits available"); 6721 #if MEMORY_LOGGING 6722 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6723 CTLFLAG_RD, 6724 &fl->ifl_m_enqueued, "mbufs allocated"); 6725 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6726 CTLFLAG_RD, 6727 &fl->ifl_m_dequeued, "mbufs freed"); 6728 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6729 CTLFLAG_RD, 6730 &fl->ifl_cl_enqueued, "clusters allocated"); 6731 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6732 CTLFLAG_RD, 6733 &fl->ifl_cl_dequeued, "clusters freed"); 6734 #endif 6735 6736 } 6737 } 6738 6739 } 6740 6741 void 6742 iflib_request_reset(if_ctx_t ctx) 6743 { 6744 6745 STATE_LOCK(ctx); 6746 ctx->ifc_flags |= IFC_DO_RESET; 6747 STATE_UNLOCK(ctx); 6748 } 6749 6750 #ifndef __NO_STRICT_ALIGNMENT 6751 static struct mbuf * 6752 iflib_fixup_rx(struct mbuf *m) 6753 { 6754 struct mbuf *n; 6755 6756 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6757 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6758 m->m_data += ETHER_HDR_LEN; 6759 n = m; 6760 } else { 6761 MGETHDR(n, M_NOWAIT, MT_DATA); 6762 if (n == NULL) { 6763 m_freem(m); 6764 return (NULL); 6765 } 6766 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6767 m->m_data += ETHER_HDR_LEN; 6768 m->m_len -= ETHER_HDR_LEN; 6769 n->m_len = ETHER_HDR_LEN; 6770 M_MOVE_PKTHDR(n, m); 6771 n->m_next = m; 6772 } 6773 return (n); 6774 } 6775 #endif 6776 6777 #ifdef DEBUGNET 6778 static void 6779 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6780 { 6781 if_ctx_t ctx; 6782 6783 ctx = if_getsoftc(ifp); 6784 CTX_LOCK(ctx); 6785 *nrxr = NRXQSETS(ctx); 6786 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6787 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6788 CTX_UNLOCK(ctx); 6789 } 6790 6791 static void 6792 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6793 { 6794 if_ctx_t ctx; 6795 if_softc_ctx_t scctx; 6796 iflib_fl_t fl; 6797 iflib_rxq_t rxq; 6798 int i, j; 6799 6800 ctx = if_getsoftc(ifp); 6801 scctx = &ctx->ifc_softc_ctx; 6802 6803 switch (event) { 6804 case DEBUGNET_START: 6805 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6806 rxq = &ctx->ifc_rxqs[i]; 6807 for (j = 0; j < rxq->ifr_nfl; j++) { 6808 fl = rxq->ifr_fl; 6809 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6810 } 6811 } 6812 iflib_no_tx_batch = 1; 6813 break; 6814 default: 6815 break; 6816 } 6817 } 6818 6819 static int 6820 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6821 { 6822 if_ctx_t ctx; 6823 iflib_txq_t txq; 6824 int error; 6825 6826 ctx = if_getsoftc(ifp); 6827 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6828 IFF_DRV_RUNNING) 6829 return (EBUSY); 6830 6831 txq = &ctx->ifc_txqs[0]; 6832 error = iflib_encap(txq, &m); 6833 if (error == 0) 6834 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6835 return (error); 6836 } 6837 6838 static int 6839 iflib_debugnet_poll(if_t ifp, int count) 6840 { 6841 struct epoch_tracker et; 6842 if_ctx_t ctx; 6843 if_softc_ctx_t scctx; 6844 iflib_txq_t txq; 6845 int i; 6846 6847 ctx = if_getsoftc(ifp); 6848 scctx = &ctx->ifc_softc_ctx; 6849 6850 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6851 IFF_DRV_RUNNING) 6852 return (EBUSY); 6853 6854 txq = &ctx->ifc_txqs[0]; 6855 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6856 6857 NET_EPOCH_ENTER(et); 6858 for (i = 0; i < scctx->isc_nrxqsets; i++) 6859 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6860 NET_EPOCH_EXIT(et); 6861 return (0); 6862 } 6863 #endif /* DEBUGNET */ 6864