1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/jail.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/md5.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/kobj.h> 47 #include <sys/rman.h> 48 #include <sys/proc.h> 49 #include <sys/sbuf.h> 50 #include <sys/smp.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/syslog.h> 55 #include <sys/taskqueue.h> 56 #include <sys/limits.h> 57 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet/netdump/netdump.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 #include <net/iflib_private.h> 92 93 #include "ifdi_if.h" 94 95 #ifdef PCI_IOV 96 #include <dev/pci/pci_iov.h> 97 #endif 98 99 #include <sys/bitstring.h> 100 /* 101 * enable accounting of every mbuf as it comes in to and goes out of 102 * iflib's software descriptor references 103 */ 104 #define MEMORY_LOGGING 0 105 /* 106 * Enable mbuf vectors for compressing long mbuf chains 107 */ 108 109 /* 110 * NB: 111 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 112 * we prefetch needs to be determined by the time spent in m_free vis a vis 113 * the cost of a prefetch. This will of course vary based on the workload: 114 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 115 * is quite expensive, thus suggesting very little prefetch. 116 * - small packet forwarding which is just returning a single mbuf to 117 * UMA will typically be very fast vis a vis the cost of a memory 118 * access. 119 */ 120 121 122 /* 123 * File organization: 124 * - private structures 125 * - iflib private utility functions 126 * - ifnet functions 127 * - vlan registry and other exported functions 128 * - iflib public core functions 129 * 130 * 131 */ 132 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct sx ifc_ctx_sx; 167 struct mtx ifc_state_mtx; 168 169 iflib_txq_t ifc_txqs; 170 iflib_rxq_t ifc_rxqs; 171 uint32_t ifc_if_flags; 172 uint32_t ifc_flags; 173 uint32_t ifc_max_fl_buf_size; 174 uint32_t ifc_rx_mbuf_sz; 175 176 int ifc_link_state; 177 int ifc_link_irq; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 188 struct sysctl_oid *ifc_sysctl_node; 189 uint16_t ifc_sysctl_ntxqs; 190 uint16_t ifc_sysctl_nrxqs; 191 uint16_t ifc_sysctl_qs_eq_override; 192 uint16_t ifc_sysctl_rx_budget; 193 uint16_t ifc_sysctl_tx_abdicate; 194 195 qidx_t ifc_sysctl_ntxds[8]; 196 qidx_t ifc_sysctl_nrxds[8]; 197 struct if_txrx ifc_txrx; 198 #define isc_txd_encap ifc_txrx.ift_txd_encap 199 #define isc_txd_flush ifc_txrx.ift_txd_flush 200 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 201 #define isc_rxd_available ifc_txrx.ift_rxd_available 202 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 203 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 204 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 208 eventhandler_tag ifc_vlan_attach_event; 209 eventhandler_tag ifc_vlan_detach_event; 210 uint8_t ifc_mac[ETHER_ADDR_LEN]; 211 char ifc_mtx_name[16]; 212 }; 213 214 215 void * 216 iflib_get_softc(if_ctx_t ctx) 217 { 218 219 return (ctx->ifc_softc); 220 } 221 222 device_t 223 iflib_get_dev(if_ctx_t ctx) 224 { 225 226 return (ctx->ifc_dev); 227 } 228 229 if_t 230 iflib_get_ifp(if_ctx_t ctx) 231 { 232 233 return (ctx->ifc_ifp); 234 } 235 236 struct ifmedia * 237 iflib_get_media(if_ctx_t ctx) 238 { 239 240 return (&ctx->ifc_media); 241 } 242 243 uint32_t 244 iflib_get_flags(if_ctx_t ctx) 245 { 246 return (ctx->ifc_flags); 247 } 248 249 void 250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 251 { 252 253 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 254 } 255 256 if_softc_ctx_t 257 iflib_get_softc_ctx(if_ctx_t ctx) 258 { 259 260 return (&ctx->ifc_softc_ctx); 261 } 262 263 if_shared_ctx_t 264 iflib_get_sctx(if_ctx_t ctx) 265 { 266 267 return (ctx->ifc_sctx); 268 } 269 270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 273 274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 276 277 typedef struct iflib_sw_rx_desc_array { 278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 279 struct mbuf **ifsd_m; /* pkthdr mbufs */ 280 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 281 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 282 } iflib_rxsd_array_t; 283 284 typedef struct iflib_sw_tx_desc_array { 285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 286 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 287 struct mbuf **ifsd_m; /* pkthdr mbufs */ 288 } if_txsd_vec_t; 289 290 291 /* magic number that should be high enough for any hardware */ 292 #define IFLIB_MAX_TX_SEGS 128 293 #define IFLIB_RX_COPY_THRESH 128 294 #define IFLIB_MAX_RX_REFRESH 32 295 /* The minimum descriptors per second before we start coalescing */ 296 #define IFLIB_MIN_DESC_SEC 16384 297 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 298 #define IFLIB_QUEUE_IDLE 0 299 #define IFLIB_QUEUE_HUNG 1 300 #define IFLIB_QUEUE_WORKING 2 301 /* maximum number of txqs that can share an rx interrupt */ 302 #define IFLIB_MAX_TX_SHARED_INTR 4 303 304 /* this should really scale with ring size - this is a fairly arbitrary value */ 305 #define TX_BATCH_SIZE 32 306 307 #define IFLIB_RESTART_BUDGET 8 308 309 310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 313 struct iflib_txq { 314 qidx_t ift_in_use; 315 qidx_t ift_cidx; 316 qidx_t ift_cidx_processed; 317 qidx_t ift_pidx; 318 uint8_t ift_gen; 319 uint8_t ift_br_offset; 320 uint16_t ift_npending; 321 uint16_t ift_db_pending; 322 uint16_t ift_rs_pending; 323 /* implicit pad */ 324 uint8_t ift_txd_size[8]; 325 uint64_t ift_processed; 326 uint64_t ift_cleaned; 327 uint64_t ift_cleaned_prev; 328 #if MEMORY_LOGGING 329 uint64_t ift_enqueued; 330 uint64_t ift_dequeued; 331 #endif 332 uint64_t ift_no_tx_dma_setup; 333 uint64_t ift_no_desc_avail; 334 uint64_t ift_mbuf_defrag_failed; 335 uint64_t ift_mbuf_defrag; 336 uint64_t ift_map_failed; 337 uint64_t ift_txd_encap_efbig; 338 uint64_t ift_pullups; 339 uint64_t ift_last_timer_tick; 340 341 struct mtx ift_mtx; 342 struct mtx ift_db_mtx; 343 344 /* constant values */ 345 if_ctx_t ift_ctx; 346 struct ifmp_ring *ift_br; 347 struct grouptask ift_task; 348 qidx_t ift_size; 349 uint16_t ift_id; 350 struct callout ift_timer; 351 352 if_txsd_vec_t ift_sds; 353 uint8_t ift_qstatus; 354 uint8_t ift_closed; 355 uint8_t ift_update_freq; 356 struct iflib_filter_info ift_filter_info; 357 bus_dma_tag_t ift_buf_tag; 358 bus_dma_tag_t ift_tso_buf_tag; 359 iflib_dma_info_t ift_ifdi; 360 #define MTX_NAME_LEN 16 361 char ift_mtx_name[MTX_NAME_LEN]; 362 char ift_db_mtx_name[MTX_NAME_LEN]; 363 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 364 #ifdef IFLIB_DIAGNOSTICS 365 uint64_t ift_cpu_exec_count[256]; 366 #endif 367 } __aligned(CACHE_LINE_SIZE); 368 369 struct iflib_fl { 370 qidx_t ifl_cidx; 371 qidx_t ifl_pidx; 372 qidx_t ifl_credits; 373 uint8_t ifl_gen; 374 uint8_t ifl_rxd_size; 375 #if MEMORY_LOGGING 376 uint64_t ifl_m_enqueued; 377 uint64_t ifl_m_dequeued; 378 uint64_t ifl_cl_enqueued; 379 uint64_t ifl_cl_dequeued; 380 #endif 381 /* implicit pad */ 382 383 bitstr_t *ifl_rx_bitmap; 384 qidx_t ifl_fragidx; 385 /* constant */ 386 qidx_t ifl_size; 387 uint16_t ifl_buf_size; 388 uint16_t ifl_cltype; 389 uma_zone_t ifl_zone; 390 iflib_rxsd_array_t ifl_sds; 391 iflib_rxq_t ifl_rxq; 392 uint8_t ifl_id; 393 bus_dma_tag_t ifl_buf_tag; 394 iflib_dma_info_t ifl_ifdi; 395 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 396 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 397 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 398 } __aligned(CACHE_LINE_SIZE); 399 400 static inline qidx_t 401 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 402 { 403 qidx_t used; 404 405 if (pidx > cidx) 406 used = pidx - cidx; 407 else if (pidx < cidx) 408 used = size - cidx + pidx; 409 else if (gen == 0 && pidx == cidx) 410 used = 0; 411 else if (gen == 1 && pidx == cidx) 412 used = size; 413 else 414 panic("bad state"); 415 416 return (used); 417 } 418 419 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 420 421 #define IDXDIFF(head, tail, wrap) \ 422 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 423 424 struct iflib_rxq { 425 /* If there is a separate completion queue - 426 * these are the cq cidx and pidx. Otherwise 427 * these are unused. 428 */ 429 qidx_t ifr_size; 430 qidx_t ifr_cq_cidx; 431 qidx_t ifr_cq_pidx; 432 uint8_t ifr_cq_gen; 433 uint8_t ifr_fl_offset; 434 435 if_ctx_t ifr_ctx; 436 iflib_fl_t ifr_fl; 437 uint64_t ifr_rx_irq; 438 uint16_t ifr_id; 439 uint8_t ifr_lro_enabled; 440 uint8_t ifr_nfl; 441 uint8_t ifr_ntxqirq; 442 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 443 struct lro_ctrl ifr_lc; 444 struct grouptask ifr_task; 445 struct iflib_filter_info ifr_filter_info; 446 iflib_dma_info_t ifr_ifdi; 447 448 /* dynamically allocate if any drivers need a value substantially larger than this */ 449 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 450 #ifdef IFLIB_DIAGNOSTICS 451 uint64_t ifr_cpu_exec_count[256]; 452 #endif 453 } __aligned(CACHE_LINE_SIZE); 454 455 typedef struct if_rxsd { 456 caddr_t *ifsd_cl; 457 struct mbuf **ifsd_m; 458 iflib_fl_t ifsd_fl; 459 qidx_t ifsd_cidx; 460 } *if_rxsd_t; 461 462 /* multiple of word size */ 463 #ifdef __LP64__ 464 #define PKT_INFO_SIZE 6 465 #define RXD_INFO_SIZE 5 466 #define PKT_TYPE uint64_t 467 #else 468 #define PKT_INFO_SIZE 11 469 #define RXD_INFO_SIZE 8 470 #define PKT_TYPE uint32_t 471 #endif 472 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 473 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 474 475 typedef struct if_pkt_info_pad { 476 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 477 } *if_pkt_info_pad_t; 478 typedef struct if_rxd_info_pad { 479 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 480 } *if_rxd_info_pad_t; 481 482 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 483 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 484 485 486 static inline void 487 pkt_info_zero(if_pkt_info_t pi) 488 { 489 if_pkt_info_pad_t pi_pad; 490 491 pi_pad = (if_pkt_info_pad_t)pi; 492 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 493 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 494 #ifndef __LP64__ 495 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 496 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 497 #endif 498 } 499 500 static device_method_t iflib_pseudo_methods[] = { 501 DEVMETHOD(device_attach, noop_attach), 502 DEVMETHOD(device_detach, iflib_pseudo_detach), 503 DEVMETHOD_END 504 }; 505 506 driver_t iflib_pseudodriver = { 507 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 508 }; 509 510 static inline void 511 rxd_info_zero(if_rxd_info_t ri) 512 { 513 if_rxd_info_pad_t ri_pad; 514 int i; 515 516 ri_pad = (if_rxd_info_pad_t)ri; 517 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 518 ri_pad->rxd_val[i] = 0; 519 ri_pad->rxd_val[i+1] = 0; 520 ri_pad->rxd_val[i+2] = 0; 521 ri_pad->rxd_val[i+3] = 0; 522 } 523 #ifdef __LP64__ 524 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 525 #endif 526 } 527 528 /* 529 * Only allow a single packet to take up most 1/nth of the tx ring 530 */ 531 #define MAX_SINGLE_PACKET_FRACTION 12 532 #define IF_BAD_DMA (bus_addr_t)-1 533 534 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 535 536 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 537 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 538 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 539 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 540 541 542 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 543 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 544 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 545 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 546 547 548 549 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 550 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 551 552 void 553 iflib_set_detach(if_ctx_t ctx) 554 { 555 STATE_LOCK(ctx); 556 ctx->ifc_flags |= IFC_IN_DETACH; 557 STATE_UNLOCK(ctx); 558 } 559 560 /* Our boot-time initialization hook */ 561 static int iflib_module_event_handler(module_t, int, void *); 562 563 static moduledata_t iflib_moduledata = { 564 "iflib", 565 iflib_module_event_handler, 566 NULL 567 }; 568 569 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 570 MODULE_VERSION(iflib, 1); 571 572 MODULE_DEPEND(iflib, pci, 1, 1, 1); 573 MODULE_DEPEND(iflib, ether, 1, 1, 1); 574 575 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 576 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 577 578 #ifndef IFLIB_DEBUG_COUNTERS 579 #ifdef INVARIANTS 580 #define IFLIB_DEBUG_COUNTERS 1 581 #else 582 #define IFLIB_DEBUG_COUNTERS 0 583 #endif /* !INVARIANTS */ 584 #endif 585 586 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 587 "iflib driver parameters"); 588 589 /* 590 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 591 */ 592 static int iflib_min_tx_latency = 0; 593 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 594 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 595 static int iflib_no_tx_batch = 0; 596 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 597 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 598 599 600 #if IFLIB_DEBUG_COUNTERS 601 602 static int iflib_tx_seen; 603 static int iflib_tx_sent; 604 static int iflib_tx_encap; 605 static int iflib_rx_allocs; 606 static int iflib_fl_refills; 607 static int iflib_fl_refills_large; 608 static int iflib_tx_frees; 609 610 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 611 &iflib_tx_seen, 0, "# tx mbufs seen"); 612 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 613 &iflib_tx_sent, 0, "# tx mbufs sent"); 614 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 615 &iflib_tx_encap, 0, "# tx mbufs encapped"); 616 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 617 &iflib_tx_frees, 0, "# tx frees"); 618 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 619 &iflib_rx_allocs, 0, "# rx allocations"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 621 &iflib_fl_refills, 0, "# refills"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 623 &iflib_fl_refills_large, 0, "# large refills"); 624 625 626 static int iflib_txq_drain_flushing; 627 static int iflib_txq_drain_oactive; 628 static int iflib_txq_drain_notready; 629 630 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 631 &iflib_txq_drain_flushing, 0, "# drain flushes"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 633 &iflib_txq_drain_oactive, 0, "# drain oactives"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 635 &iflib_txq_drain_notready, 0, "# drain notready"); 636 637 638 static int iflib_encap_load_mbuf_fail; 639 static int iflib_encap_pad_mbuf_fail; 640 static int iflib_encap_txq_avail_fail; 641 static int iflib_encap_txd_encap_fail; 642 643 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 644 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 645 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 646 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 648 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 650 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 651 652 static int iflib_task_fn_rxs; 653 static int iflib_rx_intr_enables; 654 static int iflib_fast_intrs; 655 static int iflib_rx_unavail; 656 static int iflib_rx_ctx_inactive; 657 static int iflib_rx_if_input; 658 static int iflib_rx_mbuf_null; 659 static int iflib_rxd_flush; 660 661 static int iflib_verbose_debug; 662 663 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 664 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 666 &iflib_rx_intr_enables, 0, "# rx intr enables"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 668 &iflib_fast_intrs, 0, "# fast_intr calls"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 670 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 671 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 672 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 673 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 674 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 675 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 676 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 677 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 678 &iflib_rxd_flush, 0, "# times rxd_flush called"); 679 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 680 &iflib_verbose_debug, 0, "enable verbose debugging"); 681 682 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 683 static void 684 iflib_debug_reset(void) 685 { 686 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 687 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 688 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 689 iflib_txq_drain_notready = 690 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 691 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 692 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 693 iflib_rx_unavail = 694 iflib_rx_ctx_inactive = iflib_rx_if_input = 695 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 696 } 697 698 #else 699 #define DBG_COUNTER_INC(name) 700 static void iflib_debug_reset(void) {} 701 #endif 702 703 #define IFLIB_DEBUG 0 704 705 static void iflib_tx_structures_free(if_ctx_t ctx); 706 static void iflib_rx_structures_free(if_ctx_t ctx); 707 static int iflib_queues_alloc(if_ctx_t ctx); 708 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 709 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 710 static int iflib_qset_structures_setup(if_ctx_t ctx); 711 static int iflib_msix_init(if_ctx_t ctx); 712 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 713 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 714 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 715 #ifdef ALTQ 716 static void iflib_altq_if_start(if_t ifp); 717 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 718 #endif 719 static int iflib_register(if_ctx_t); 720 static void iflib_init_locked(if_ctx_t ctx); 721 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 722 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 723 static void iflib_ifmp_purge(iflib_txq_t txq); 724 static void _iflib_pre_assert(if_softc_ctx_t scctx); 725 static void iflib_if_init_locked(if_ctx_t ctx); 726 static void iflib_free_intr_mem(if_ctx_t ctx); 727 #ifndef __NO_STRICT_ALIGNMENT 728 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 729 #endif 730 731 NETDUMP_DEFINE(iflib); 732 733 #ifdef DEV_NETMAP 734 #include <sys/selinfo.h> 735 #include <net/netmap.h> 736 #include <dev/netmap/netmap_kern.h> 737 738 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 739 740 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 741 742 /* 743 * device-specific sysctl variables: 744 * 745 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 746 * During regular operations the CRC is stripped, but on some 747 * hardware reception of frames not multiple of 64 is slower, 748 * so using crcstrip=0 helps in benchmarks. 749 * 750 * iflib_rx_miss, iflib_rx_miss_bufs: 751 * count packets that might be missed due to lost interrupts. 752 */ 753 SYSCTL_DECL(_dev_netmap); 754 /* 755 * The xl driver by default strips CRCs and we do not override it. 756 */ 757 758 int iflib_crcstrip = 1; 759 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 760 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 761 762 int iflib_rx_miss, iflib_rx_miss_bufs; 763 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 764 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 765 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 766 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 767 768 /* 769 * Register/unregister. We are already under netmap lock. 770 * Only called on the first register or the last unregister. 771 */ 772 static int 773 iflib_netmap_register(struct netmap_adapter *na, int onoff) 774 { 775 struct ifnet *ifp = na->ifp; 776 if_ctx_t ctx = ifp->if_softc; 777 int status; 778 779 CTX_LOCK(ctx); 780 IFDI_INTR_DISABLE(ctx); 781 782 /* Tell the stack that the interface is no longer active */ 783 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 784 785 if (!CTX_IS_VF(ctx)) 786 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 787 788 /* enable or disable flags and callbacks in na and ifp */ 789 if (onoff) { 790 nm_set_native_flags(na); 791 } else { 792 nm_clear_native_flags(na); 793 } 794 iflib_stop(ctx); 795 iflib_init_locked(ctx); 796 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 797 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 798 if (status) 799 nm_clear_native_flags(na); 800 CTX_UNLOCK(ctx); 801 return (status); 802 } 803 804 static int 805 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 806 { 807 struct netmap_adapter *na = kring->na; 808 u_int const lim = kring->nkr_num_slots - 1; 809 u_int head = kring->rhead; 810 struct netmap_ring *ring = kring->ring; 811 bus_dmamap_t *map; 812 struct if_rxd_update iru; 813 if_ctx_t ctx = rxq->ifr_ctx; 814 iflib_fl_t fl = &rxq->ifr_fl[0]; 815 uint32_t refill_pidx, nic_i; 816 #if IFLIB_DEBUG_COUNTERS 817 int rf_count = 0; 818 #endif 819 820 if (nm_i == head && __predict_true(!init)) 821 return 0; 822 iru_init(&iru, rxq, 0 /* flid */); 823 map = fl->ifl_sds.ifsd_map; 824 refill_pidx = netmap_idx_k2n(kring, nm_i); 825 /* 826 * IMPORTANT: we must leave one free slot in the ring, 827 * so move head back by one unit 828 */ 829 head = nm_prev(head, lim); 830 nic_i = UINT_MAX; 831 DBG_COUNTER_INC(fl_refills); 832 while (nm_i != head) { 833 #if IFLIB_DEBUG_COUNTERS 834 if (++rf_count == 9) 835 DBG_COUNTER_INC(fl_refills_large); 836 #endif 837 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 838 struct netmap_slot *slot = &ring->slot[nm_i]; 839 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 840 uint32_t nic_i_dma = refill_pidx; 841 nic_i = netmap_idx_k2n(kring, nm_i); 842 843 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 844 845 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 846 return netmap_ring_reinit(kring); 847 848 fl->ifl_vm_addrs[tmp_pidx] = addr; 849 if (__predict_false(init)) { 850 netmap_load_map(na, fl->ifl_buf_tag, 851 map[nic_i], addr); 852 } else if (slot->flags & NS_BUF_CHANGED) { 853 /* buffer has changed, reload map */ 854 netmap_reload_map(na, fl->ifl_buf_tag, 855 map[nic_i], addr); 856 } 857 slot->flags &= ~NS_BUF_CHANGED; 858 859 nm_i = nm_next(nm_i, lim); 860 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 861 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 862 continue; 863 864 iru.iru_pidx = refill_pidx; 865 iru.iru_count = tmp_pidx+1; 866 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 867 refill_pidx = nic_i; 868 for (int n = 0; n < iru.iru_count; n++) { 869 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 870 BUS_DMASYNC_PREREAD); 871 /* XXX - change this to not use the netmap func*/ 872 nic_i_dma = nm_next(nic_i_dma, lim); 873 } 874 } 875 } 876 kring->nr_hwcur = head; 877 878 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 879 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 880 if (__predict_true(nic_i != UINT_MAX)) { 881 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 882 DBG_COUNTER_INC(rxd_flush); 883 } 884 return (0); 885 } 886 887 /* 888 * Reconcile kernel and user view of the transmit ring. 889 * 890 * All information is in the kring. 891 * Userspace wants to send packets up to the one before kring->rhead, 892 * kernel knows kring->nr_hwcur is the first unsent packet. 893 * 894 * Here we push packets out (as many as possible), and possibly 895 * reclaim buffers from previously completed transmission. 896 * 897 * The caller (netmap) guarantees that there is only one instance 898 * running at any time. Any interference with other driver 899 * methods should be handled by the individual drivers. 900 */ 901 static int 902 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 903 { 904 struct netmap_adapter *na = kring->na; 905 struct ifnet *ifp = na->ifp; 906 struct netmap_ring *ring = kring->ring; 907 u_int nm_i; /* index into the netmap kring */ 908 u_int nic_i; /* index into the NIC ring */ 909 u_int n; 910 u_int const lim = kring->nkr_num_slots - 1; 911 u_int const head = kring->rhead; 912 struct if_pkt_info pi; 913 914 /* 915 * interrupts on every tx packet are expensive so request 916 * them every half ring, or where NS_REPORT is set 917 */ 918 u_int report_frequency = kring->nkr_num_slots >> 1; 919 /* device-specific */ 920 if_ctx_t ctx = ifp->if_softc; 921 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 922 923 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 924 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 925 926 /* 927 * First part: process new packets to send. 928 * nm_i is the current index in the netmap kring, 929 * nic_i is the corresponding index in the NIC ring. 930 * 931 * If we have packets to send (nm_i != head) 932 * iterate over the netmap ring, fetch length and update 933 * the corresponding slot in the NIC ring. Some drivers also 934 * need to update the buffer's physical address in the NIC slot 935 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 936 * 937 * The netmap_reload_map() calls is especially expensive, 938 * even when (as in this case) the tag is 0, so do only 939 * when the buffer has actually changed. 940 * 941 * If possible do not set the report/intr bit on all slots, 942 * but only a few times per ring or when NS_REPORT is set. 943 * 944 * Finally, on 10G and faster drivers, it might be useful 945 * to prefetch the next slot and txr entry. 946 */ 947 948 nm_i = kring->nr_hwcur; 949 if (nm_i != head) { /* we have new packets to send */ 950 pkt_info_zero(&pi); 951 pi.ipi_segs = txq->ift_segs; 952 pi.ipi_qsidx = kring->ring_id; 953 nic_i = netmap_idx_k2n(kring, nm_i); 954 955 __builtin_prefetch(&ring->slot[nm_i]); 956 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 957 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 958 959 for (n = 0; nm_i != head; n++) { 960 struct netmap_slot *slot = &ring->slot[nm_i]; 961 u_int len = slot->len; 962 uint64_t paddr; 963 void *addr = PNMB(na, slot, &paddr); 964 int flags = (slot->flags & NS_REPORT || 965 nic_i == 0 || nic_i == report_frequency) ? 966 IPI_TX_INTR : 0; 967 968 /* device-specific */ 969 pi.ipi_len = len; 970 pi.ipi_segs[0].ds_addr = paddr; 971 pi.ipi_segs[0].ds_len = len; 972 pi.ipi_nsegs = 1; 973 pi.ipi_ndescs = 0; 974 pi.ipi_pidx = nic_i; 975 pi.ipi_flags = flags; 976 977 /* Fill the slot in the NIC ring. */ 978 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 979 DBG_COUNTER_INC(tx_encap); 980 981 /* prefetch for next round */ 982 __builtin_prefetch(&ring->slot[nm_i + 1]); 983 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 984 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 985 986 NM_CHECK_ADDR_LEN(na, addr, len); 987 988 if (slot->flags & NS_BUF_CHANGED) { 989 /* buffer has changed, reload map */ 990 netmap_reload_map(na, txq->ift_buf_tag, 991 txq->ift_sds.ifsd_map[nic_i], addr); 992 } 993 /* make sure changes to the buffer are synced */ 994 bus_dmamap_sync(txq->ift_buf_tag, 995 txq->ift_sds.ifsd_map[nic_i], 996 BUS_DMASYNC_PREWRITE); 997 998 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 999 nm_i = nm_next(nm_i, lim); 1000 nic_i = nm_next(nic_i, lim); 1001 } 1002 kring->nr_hwcur = nm_i; 1003 1004 /* synchronize the NIC ring */ 1005 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1006 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1007 1008 /* (re)start the tx unit up to slot nic_i (excluded) */ 1009 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1010 } 1011 1012 /* 1013 * Second part: reclaim buffers for completed transmissions. 1014 * 1015 * If there are unclaimed buffers, attempt to reclaim them. 1016 * If none are reclaimed, and TX IRQs are not in use, do an initial 1017 * minimal delay, then trigger the tx handler which will spin in the 1018 * group task queue. 1019 */ 1020 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1021 if (iflib_tx_credits_update(ctx, txq)) { 1022 /* some tx completed, increment avail */ 1023 nic_i = txq->ift_cidx_processed; 1024 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1025 } 1026 } 1027 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1028 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1029 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1030 iflib_timer, txq, txq->ift_timer.c_cpu); 1031 } 1032 return (0); 1033 } 1034 1035 /* 1036 * Reconcile kernel and user view of the receive ring. 1037 * Same as for the txsync, this routine must be efficient. 1038 * The caller guarantees a single invocations, but races against 1039 * the rest of the driver should be handled here. 1040 * 1041 * On call, kring->rhead is the first packet that userspace wants 1042 * to keep, and kring->rcur is the wakeup point. 1043 * The kernel has previously reported packets up to kring->rtail. 1044 * 1045 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1046 * of whether or not we received an interrupt. 1047 */ 1048 static int 1049 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1050 { 1051 struct netmap_adapter *na = kring->na; 1052 struct netmap_ring *ring = kring->ring; 1053 iflib_fl_t fl; 1054 uint32_t nm_i; /* index into the netmap ring */ 1055 uint32_t nic_i; /* index into the NIC ring */ 1056 u_int i, n; 1057 u_int const lim = kring->nkr_num_slots - 1; 1058 u_int const head = kring->rhead; 1059 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1060 struct if_rxd_info ri; 1061 1062 struct ifnet *ifp = na->ifp; 1063 if_ctx_t ctx = ifp->if_softc; 1064 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1065 if (head > lim) 1066 return netmap_ring_reinit(kring); 1067 1068 /* 1069 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1070 */ 1071 1072 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1073 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1074 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1075 } 1076 1077 /* 1078 * First part: import newly received packets. 1079 * 1080 * nm_i is the index of the next free slot in the netmap ring, 1081 * nic_i is the index of the next received packet in the NIC ring, 1082 * and they may differ in case if_init() has been called while 1083 * in netmap mode. For the receive ring we have 1084 * 1085 * nic_i = rxr->next_check; 1086 * nm_i = kring->nr_hwtail (previous) 1087 * and 1088 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1089 * 1090 * rxr->next_check is set to 0 on a ring reinit 1091 */ 1092 if (netmap_no_pendintr || force_update) { 1093 int crclen = iflib_crcstrip ? 0 : 4; 1094 int error, avail; 1095 1096 for (i = 0; i < rxq->ifr_nfl; i++) { 1097 fl = &rxq->ifr_fl[i]; 1098 nic_i = fl->ifl_cidx; 1099 nm_i = netmap_idx_n2k(kring, nic_i); 1100 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1101 rxq->ifr_id, nic_i, USHRT_MAX); 1102 for (n = 0; avail > 0; n++, avail--) { 1103 rxd_info_zero(&ri); 1104 ri.iri_frags = rxq->ifr_frags; 1105 ri.iri_qsidx = kring->ring_id; 1106 ri.iri_ifp = ctx->ifc_ifp; 1107 ri.iri_cidx = nic_i; 1108 1109 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1110 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1111 ring->slot[nm_i].flags = 0; 1112 bus_dmamap_sync(fl->ifl_buf_tag, 1113 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1114 nm_i = nm_next(nm_i, lim); 1115 nic_i = nm_next(nic_i, lim); 1116 } 1117 if (n) { /* update the state variables */ 1118 if (netmap_no_pendintr && !force_update) { 1119 /* diagnostics */ 1120 iflib_rx_miss ++; 1121 iflib_rx_miss_bufs += n; 1122 } 1123 fl->ifl_cidx = nic_i; 1124 kring->nr_hwtail = nm_i; 1125 } 1126 kring->nr_kflags &= ~NKR_PENDINTR; 1127 } 1128 } 1129 /* 1130 * Second part: skip past packets that userspace has released. 1131 * (kring->nr_hwcur to head excluded), 1132 * and make the buffers available for reception. 1133 * As usual nm_i is the index in the netmap ring, 1134 * nic_i is the index in the NIC ring, and 1135 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1136 */ 1137 /* XXX not sure how this will work with multiple free lists */ 1138 nm_i = kring->nr_hwcur; 1139 1140 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1141 } 1142 1143 static void 1144 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1145 { 1146 struct ifnet *ifp = na->ifp; 1147 if_ctx_t ctx = ifp->if_softc; 1148 1149 CTX_LOCK(ctx); 1150 if (onoff) { 1151 IFDI_INTR_ENABLE(ctx); 1152 } else { 1153 IFDI_INTR_DISABLE(ctx); 1154 } 1155 CTX_UNLOCK(ctx); 1156 } 1157 1158 1159 static int 1160 iflib_netmap_attach(if_ctx_t ctx) 1161 { 1162 struct netmap_adapter na; 1163 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1164 1165 bzero(&na, sizeof(na)); 1166 1167 na.ifp = ctx->ifc_ifp; 1168 na.na_flags = NAF_BDG_MAYSLEEP; 1169 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1170 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1171 1172 na.num_tx_desc = scctx->isc_ntxd[0]; 1173 na.num_rx_desc = scctx->isc_nrxd[0]; 1174 na.nm_txsync = iflib_netmap_txsync; 1175 na.nm_rxsync = iflib_netmap_rxsync; 1176 na.nm_register = iflib_netmap_register; 1177 na.nm_intr = iflib_netmap_intr; 1178 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1179 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1180 return (netmap_attach(&na)); 1181 } 1182 1183 static void 1184 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1185 { 1186 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1187 struct netmap_slot *slot; 1188 1189 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1190 if (slot == NULL) 1191 return; 1192 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1193 1194 /* 1195 * In netmap mode, set the map for the packet buffer. 1196 * NOTE: Some drivers (not this one) also need to set 1197 * the physical buffer address in the NIC ring. 1198 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1199 * netmap slot index, si 1200 */ 1201 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1202 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1203 NMB(na, slot + si)); 1204 } 1205 } 1206 1207 static void 1208 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1209 { 1210 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1211 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1212 struct netmap_slot *slot; 1213 uint32_t nm_i; 1214 1215 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1216 if (slot == NULL) 1217 return; 1218 nm_i = netmap_idx_n2k(kring, 0); 1219 netmap_fl_refill(rxq, kring, nm_i, true); 1220 } 1221 1222 static void 1223 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1224 { 1225 struct netmap_kring *kring; 1226 uint16_t txqid; 1227 1228 txqid = txq->ift_id; 1229 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1230 1231 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1232 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1233 BUS_DMASYNC_POSTREAD); 1234 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1235 netmap_tx_irq(ctx->ifc_ifp, txqid); 1236 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1237 if (hz < 2000) 1238 *reset_on = 1; 1239 else 1240 *reset_on = hz / 1000; 1241 } 1242 } 1243 } 1244 1245 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1246 1247 #else 1248 #define iflib_netmap_txq_init(ctx, txq) 1249 #define iflib_netmap_rxq_init(ctx, rxq) 1250 #define iflib_netmap_detach(ifp) 1251 1252 #define iflib_netmap_attach(ctx) (0) 1253 #define netmap_rx_irq(ifp, qid, budget) (0) 1254 #define netmap_tx_irq(ifp, qid) do {} while (0) 1255 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1256 1257 #endif 1258 1259 #if defined(__i386__) || defined(__amd64__) 1260 static __inline void 1261 prefetch(void *x) 1262 { 1263 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1264 } 1265 static __inline void 1266 prefetch2cachelines(void *x) 1267 { 1268 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1269 #if (CACHE_LINE_SIZE < 128) 1270 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1271 #endif 1272 } 1273 #else 1274 #define prefetch(x) 1275 #define prefetch2cachelines(x) 1276 #endif 1277 1278 static void 1279 iflib_gen_mac(if_ctx_t ctx) 1280 { 1281 struct thread *td; 1282 MD5_CTX mdctx; 1283 char uuid[HOSTUUIDLEN+1]; 1284 char buf[HOSTUUIDLEN+16]; 1285 uint8_t *mac; 1286 unsigned char digest[16]; 1287 1288 td = curthread; 1289 mac = ctx->ifc_mac; 1290 uuid[HOSTUUIDLEN] = 0; 1291 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN); 1292 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev)); 1293 /* 1294 * Generate a pseudo-random, deterministic MAC 1295 * address based on the UUID and unit number. 1296 * The FreeBSD Foundation OUI of 58-9C-FC is used. 1297 */ 1298 MD5Init(&mdctx); 1299 MD5Update(&mdctx, buf, strlen(buf)); 1300 MD5Final(digest, &mdctx); 1301 1302 mac[0] = 0x58; 1303 mac[1] = 0x9C; 1304 mac[2] = 0xFC; 1305 mac[3] = digest[0]; 1306 mac[4] = digest[1]; 1307 mac[5] = digest[2]; 1308 } 1309 1310 static void 1311 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1312 { 1313 iflib_fl_t fl; 1314 1315 fl = &rxq->ifr_fl[flid]; 1316 iru->iru_paddrs = fl->ifl_bus_addrs; 1317 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1318 iru->iru_idxs = fl->ifl_rxd_idxs; 1319 iru->iru_qsidx = rxq->ifr_id; 1320 iru->iru_buf_size = fl->ifl_buf_size; 1321 iru->iru_flidx = fl->ifl_id; 1322 } 1323 1324 static void 1325 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1326 { 1327 if (err) 1328 return; 1329 *(bus_addr_t *) arg = segs[0].ds_addr; 1330 } 1331 1332 int 1333 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1334 { 1335 int err; 1336 device_t dev = ctx->ifc_dev; 1337 1338 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1339 align, 0, /* alignment, bounds */ 1340 BUS_SPACE_MAXADDR, /* lowaddr */ 1341 BUS_SPACE_MAXADDR, /* highaddr */ 1342 NULL, NULL, /* filter, filterarg */ 1343 size, /* maxsize */ 1344 1, /* nsegments */ 1345 size, /* maxsegsize */ 1346 BUS_DMA_ALLOCNOW, /* flags */ 1347 NULL, /* lockfunc */ 1348 NULL, /* lockarg */ 1349 &dma->idi_tag); 1350 if (err) { 1351 device_printf(dev, 1352 "%s: bus_dma_tag_create failed: %d\n", 1353 __func__, err); 1354 goto fail_0; 1355 } 1356 1357 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1358 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1359 if (err) { 1360 device_printf(dev, 1361 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1362 __func__, (uintmax_t)size, err); 1363 goto fail_1; 1364 } 1365 1366 dma->idi_paddr = IF_BAD_DMA; 1367 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1368 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1369 if (err || dma->idi_paddr == IF_BAD_DMA) { 1370 device_printf(dev, 1371 "%s: bus_dmamap_load failed: %d\n", 1372 __func__, err); 1373 goto fail_2; 1374 } 1375 1376 dma->idi_size = size; 1377 return (0); 1378 1379 fail_2: 1380 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1381 fail_1: 1382 bus_dma_tag_destroy(dma->idi_tag); 1383 fail_0: 1384 dma->idi_tag = NULL; 1385 1386 return (err); 1387 } 1388 1389 int 1390 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1391 { 1392 if_shared_ctx_t sctx = ctx->ifc_sctx; 1393 1394 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1395 1396 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1397 } 1398 1399 int 1400 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1401 { 1402 int i, err; 1403 iflib_dma_info_t *dmaiter; 1404 1405 dmaiter = dmalist; 1406 for (i = 0; i < count; i++, dmaiter++) { 1407 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1408 break; 1409 } 1410 if (err) 1411 iflib_dma_free_multi(dmalist, i); 1412 return (err); 1413 } 1414 1415 void 1416 iflib_dma_free(iflib_dma_info_t dma) 1417 { 1418 if (dma->idi_tag == NULL) 1419 return; 1420 if (dma->idi_paddr != IF_BAD_DMA) { 1421 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1422 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1423 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1424 dma->idi_paddr = IF_BAD_DMA; 1425 } 1426 if (dma->idi_vaddr != NULL) { 1427 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1428 dma->idi_vaddr = NULL; 1429 } 1430 bus_dma_tag_destroy(dma->idi_tag); 1431 dma->idi_tag = NULL; 1432 } 1433 1434 void 1435 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1436 { 1437 int i; 1438 iflib_dma_info_t *dmaiter = dmalist; 1439 1440 for (i = 0; i < count; i++, dmaiter++) 1441 iflib_dma_free(*dmaiter); 1442 } 1443 1444 #ifdef EARLY_AP_STARTUP 1445 static const int iflib_started = 1; 1446 #else 1447 /* 1448 * We used to abuse the smp_started flag to decide if the queues have been 1449 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1450 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1451 * is set. Run a SYSINIT() strictly after that to just set a usable 1452 * completion flag. 1453 */ 1454 1455 static int iflib_started; 1456 1457 static void 1458 iflib_record_started(void *arg) 1459 { 1460 iflib_started = 1; 1461 } 1462 1463 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1464 iflib_record_started, NULL); 1465 #endif 1466 1467 static int 1468 iflib_fast_intr(void *arg) 1469 { 1470 iflib_filter_info_t info = arg; 1471 struct grouptask *gtask = info->ifi_task; 1472 int result; 1473 1474 if (!iflib_started) 1475 return (FILTER_STRAY); 1476 1477 DBG_COUNTER_INC(fast_intrs); 1478 if (info->ifi_filter != NULL) { 1479 result = info->ifi_filter(info->ifi_filter_arg); 1480 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1481 return (result); 1482 } 1483 1484 GROUPTASK_ENQUEUE(gtask); 1485 return (FILTER_HANDLED); 1486 } 1487 1488 static int 1489 iflib_fast_intr_rxtx(void *arg) 1490 { 1491 iflib_filter_info_t info = arg; 1492 struct grouptask *gtask = info->ifi_task; 1493 if_ctx_t ctx; 1494 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1495 iflib_txq_t txq; 1496 void *sc; 1497 int i, cidx, result; 1498 qidx_t txqid; 1499 1500 if (!iflib_started) 1501 return (FILTER_STRAY); 1502 1503 DBG_COUNTER_INC(fast_intrs); 1504 if (info->ifi_filter != NULL) { 1505 result = info->ifi_filter(info->ifi_filter_arg); 1506 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1507 return (result); 1508 } 1509 1510 ctx = rxq->ifr_ctx; 1511 sc = ctx->ifc_softc; 1512 MPASS(rxq->ifr_ntxqirq); 1513 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1514 txqid = rxq->ifr_txqid[i]; 1515 txq = &ctx->ifc_txqs[txqid]; 1516 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1517 BUS_DMASYNC_POSTREAD); 1518 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1519 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1520 continue; 1521 } 1522 GROUPTASK_ENQUEUE(&txq->ift_task); 1523 } 1524 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1525 cidx = rxq->ifr_cq_cidx; 1526 else 1527 cidx = rxq->ifr_fl[0].ifl_cidx; 1528 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1529 GROUPTASK_ENQUEUE(gtask); 1530 else { 1531 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1532 DBG_COUNTER_INC(rx_intr_enables); 1533 } 1534 return (FILTER_HANDLED); 1535 } 1536 1537 1538 static int 1539 iflib_fast_intr_ctx(void *arg) 1540 { 1541 iflib_filter_info_t info = arg; 1542 struct grouptask *gtask = info->ifi_task; 1543 int result; 1544 1545 if (!iflib_started) 1546 return (FILTER_STRAY); 1547 1548 DBG_COUNTER_INC(fast_intrs); 1549 if (info->ifi_filter != NULL) { 1550 result = info->ifi_filter(info->ifi_filter_arg); 1551 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1552 return (result); 1553 } 1554 1555 GROUPTASK_ENQUEUE(gtask); 1556 return (FILTER_HANDLED); 1557 } 1558 1559 static int 1560 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1561 driver_filter_t filter, driver_intr_t handler, void *arg, 1562 const char *name) 1563 { 1564 int rc, flags; 1565 struct resource *res; 1566 void *tag = NULL; 1567 device_t dev = ctx->ifc_dev; 1568 1569 flags = RF_ACTIVE; 1570 if (ctx->ifc_flags & IFC_LEGACY) 1571 flags |= RF_SHAREABLE; 1572 MPASS(rid < 512); 1573 irq->ii_rid = rid; 1574 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1575 if (res == NULL) { 1576 device_printf(dev, 1577 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1578 return (ENOMEM); 1579 } 1580 irq->ii_res = res; 1581 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1582 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1583 filter, handler, arg, &tag); 1584 if (rc != 0) { 1585 device_printf(dev, 1586 "failed to setup interrupt for rid %d, name %s: %d\n", 1587 rid, name ? name : "unknown", rc); 1588 return (rc); 1589 } else if (name) 1590 bus_describe_intr(dev, res, tag, "%s", name); 1591 1592 irq->ii_tag = tag; 1593 return (0); 1594 } 1595 1596 1597 /********************************************************************* 1598 * 1599 * Allocate DMA resources for TX buffers as well as memory for the TX 1600 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1601 * iflib_sw_tx_desc_array structure, storing all the information that 1602 * is needed to transmit a packet on the wire. This is called only 1603 * once at attach, setup is done every reset. 1604 * 1605 **********************************************************************/ 1606 static int 1607 iflib_txsd_alloc(iflib_txq_t txq) 1608 { 1609 if_ctx_t ctx = txq->ift_ctx; 1610 if_shared_ctx_t sctx = ctx->ifc_sctx; 1611 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1612 device_t dev = ctx->ifc_dev; 1613 bus_size_t tsomaxsize; 1614 int err, nsegments, ntsosegments; 1615 bool tso; 1616 1617 nsegments = scctx->isc_tx_nsegments; 1618 ntsosegments = scctx->isc_tx_tso_segments_max; 1619 tsomaxsize = scctx->isc_tx_tso_size_max; 1620 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1621 tsomaxsize += sizeof(struct ether_vlan_header); 1622 MPASS(scctx->isc_ntxd[0] > 0); 1623 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1624 MPASS(nsegments > 0); 1625 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1626 MPASS(ntsosegments > 0); 1627 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1628 } 1629 1630 /* 1631 * Set up DMA tags for TX buffers. 1632 */ 1633 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1634 1, 0, /* alignment, bounds */ 1635 BUS_SPACE_MAXADDR, /* lowaddr */ 1636 BUS_SPACE_MAXADDR, /* highaddr */ 1637 NULL, NULL, /* filter, filterarg */ 1638 sctx->isc_tx_maxsize, /* maxsize */ 1639 nsegments, /* nsegments */ 1640 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1641 0, /* flags */ 1642 NULL, /* lockfunc */ 1643 NULL, /* lockfuncarg */ 1644 &txq->ift_buf_tag))) { 1645 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1646 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1647 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1648 goto fail; 1649 } 1650 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1651 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1652 1, 0, /* alignment, bounds */ 1653 BUS_SPACE_MAXADDR, /* lowaddr */ 1654 BUS_SPACE_MAXADDR, /* highaddr */ 1655 NULL, NULL, /* filter, filterarg */ 1656 tsomaxsize, /* maxsize */ 1657 ntsosegments, /* nsegments */ 1658 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1659 0, /* flags */ 1660 NULL, /* lockfunc */ 1661 NULL, /* lockfuncarg */ 1662 &txq->ift_tso_buf_tag))) { 1663 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1664 err); 1665 goto fail; 1666 } 1667 1668 /* Allocate memory for the TX mbuf map. */ 1669 if (!(txq->ift_sds.ifsd_m = 1670 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1671 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1672 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1673 err = ENOMEM; 1674 goto fail; 1675 } 1676 1677 /* 1678 * Create the DMA maps for TX buffers. 1679 */ 1680 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1681 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1682 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1683 device_printf(dev, 1684 "Unable to allocate TX buffer DMA map memory\n"); 1685 err = ENOMEM; 1686 goto fail; 1687 } 1688 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1689 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1690 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1691 device_printf(dev, 1692 "Unable to allocate TSO TX buffer map memory\n"); 1693 err = ENOMEM; 1694 goto fail; 1695 } 1696 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1697 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1698 &txq->ift_sds.ifsd_map[i]); 1699 if (err != 0) { 1700 device_printf(dev, "Unable to create TX DMA map\n"); 1701 goto fail; 1702 } 1703 if (!tso) 1704 continue; 1705 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1706 &txq->ift_sds.ifsd_tso_map[i]); 1707 if (err != 0) { 1708 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1709 goto fail; 1710 } 1711 } 1712 return (0); 1713 fail: 1714 /* We free all, it handles case where we are in the middle */ 1715 iflib_tx_structures_free(ctx); 1716 return (err); 1717 } 1718 1719 static void 1720 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1721 { 1722 bus_dmamap_t map; 1723 1724 map = NULL; 1725 if (txq->ift_sds.ifsd_map != NULL) 1726 map = txq->ift_sds.ifsd_map[i]; 1727 if (map != NULL) { 1728 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1729 bus_dmamap_unload(txq->ift_buf_tag, map); 1730 bus_dmamap_destroy(txq->ift_buf_tag, map); 1731 txq->ift_sds.ifsd_map[i] = NULL; 1732 } 1733 1734 map = NULL; 1735 if (txq->ift_sds.ifsd_tso_map != NULL) 1736 map = txq->ift_sds.ifsd_tso_map[i]; 1737 if (map != NULL) { 1738 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1739 BUS_DMASYNC_POSTWRITE); 1740 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1741 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1742 txq->ift_sds.ifsd_tso_map[i] = NULL; 1743 } 1744 } 1745 1746 static void 1747 iflib_txq_destroy(iflib_txq_t txq) 1748 { 1749 if_ctx_t ctx = txq->ift_ctx; 1750 1751 for (int i = 0; i < txq->ift_size; i++) 1752 iflib_txsd_destroy(ctx, txq, i); 1753 if (txq->ift_sds.ifsd_map != NULL) { 1754 free(txq->ift_sds.ifsd_map, M_IFLIB); 1755 txq->ift_sds.ifsd_map = NULL; 1756 } 1757 if (txq->ift_sds.ifsd_tso_map != NULL) { 1758 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1759 txq->ift_sds.ifsd_tso_map = NULL; 1760 } 1761 if (txq->ift_sds.ifsd_m != NULL) { 1762 free(txq->ift_sds.ifsd_m, M_IFLIB); 1763 txq->ift_sds.ifsd_m = NULL; 1764 } 1765 if (txq->ift_buf_tag != NULL) { 1766 bus_dma_tag_destroy(txq->ift_buf_tag); 1767 txq->ift_buf_tag = NULL; 1768 } 1769 if (txq->ift_tso_buf_tag != NULL) { 1770 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1771 txq->ift_tso_buf_tag = NULL; 1772 } 1773 } 1774 1775 static void 1776 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1777 { 1778 struct mbuf **mp; 1779 1780 mp = &txq->ift_sds.ifsd_m[i]; 1781 if (*mp == NULL) 1782 return; 1783 1784 if (txq->ift_sds.ifsd_map != NULL) { 1785 bus_dmamap_sync(txq->ift_buf_tag, 1786 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1787 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1788 } 1789 if (txq->ift_sds.ifsd_tso_map != NULL) { 1790 bus_dmamap_sync(txq->ift_tso_buf_tag, 1791 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1792 bus_dmamap_unload(txq->ift_tso_buf_tag, 1793 txq->ift_sds.ifsd_tso_map[i]); 1794 } 1795 m_free(*mp); 1796 DBG_COUNTER_INC(tx_frees); 1797 *mp = NULL; 1798 } 1799 1800 static int 1801 iflib_txq_setup(iflib_txq_t txq) 1802 { 1803 if_ctx_t ctx = txq->ift_ctx; 1804 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1805 if_shared_ctx_t sctx = ctx->ifc_sctx; 1806 iflib_dma_info_t di; 1807 int i; 1808 1809 /* Set number of descriptors available */ 1810 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1811 /* XXX make configurable */ 1812 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1813 1814 /* Reset indices */ 1815 txq->ift_cidx_processed = 0; 1816 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1817 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1818 1819 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1820 bzero((void *)di->idi_vaddr, di->idi_size); 1821 1822 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1823 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1824 bus_dmamap_sync(di->idi_tag, di->idi_map, 1825 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1826 return (0); 1827 } 1828 1829 /********************************************************************* 1830 * 1831 * Allocate DMA resources for RX buffers as well as memory for the RX 1832 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1833 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1834 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1835 * Since we use use one entry in iflib_sw_rx_desc_array per received 1836 * packet, the maximum number of entries we'll need is equal to the 1837 * number of hardware receive descriptors that we've allocated. 1838 * 1839 **********************************************************************/ 1840 static int 1841 iflib_rxsd_alloc(iflib_rxq_t rxq) 1842 { 1843 if_ctx_t ctx = rxq->ifr_ctx; 1844 if_shared_ctx_t sctx = ctx->ifc_sctx; 1845 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1846 device_t dev = ctx->ifc_dev; 1847 iflib_fl_t fl; 1848 int err; 1849 1850 MPASS(scctx->isc_nrxd[0] > 0); 1851 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1852 1853 fl = rxq->ifr_fl; 1854 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1855 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1856 /* Set up DMA tag for RX buffers. */ 1857 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1858 1, 0, /* alignment, bounds */ 1859 BUS_SPACE_MAXADDR, /* lowaddr */ 1860 BUS_SPACE_MAXADDR, /* highaddr */ 1861 NULL, NULL, /* filter, filterarg */ 1862 sctx->isc_rx_maxsize, /* maxsize */ 1863 sctx->isc_rx_nsegments, /* nsegments */ 1864 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1865 0, /* flags */ 1866 NULL, /* lockfunc */ 1867 NULL, /* lockarg */ 1868 &fl->ifl_buf_tag); 1869 if (err) { 1870 device_printf(dev, 1871 "Unable to allocate RX DMA tag: %d\n", err); 1872 goto fail; 1873 } 1874 1875 /* Allocate memory for the RX mbuf map. */ 1876 if (!(fl->ifl_sds.ifsd_m = 1877 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1878 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1879 device_printf(dev, 1880 "Unable to allocate RX mbuf map memory\n"); 1881 err = ENOMEM; 1882 goto fail; 1883 } 1884 1885 /* Allocate memory for the direct RX cluster pointer map. */ 1886 if (!(fl->ifl_sds.ifsd_cl = 1887 (caddr_t *) malloc(sizeof(caddr_t) * 1888 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1889 device_printf(dev, 1890 "Unable to allocate RX cluster map memory\n"); 1891 err = ENOMEM; 1892 goto fail; 1893 } 1894 1895 /* Allocate memory for the RX cluster bus address map. */ 1896 if (!(fl->ifl_sds.ifsd_ba = 1897 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1898 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1899 device_printf(dev, 1900 "Unable to allocate RX bus address map memory\n"); 1901 err = ENOMEM; 1902 goto fail; 1903 } 1904 1905 /* 1906 * Create the DMA maps for RX buffers. 1907 */ 1908 if (!(fl->ifl_sds.ifsd_map = 1909 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1910 device_printf(dev, 1911 "Unable to allocate RX buffer DMA map memory\n"); 1912 err = ENOMEM; 1913 goto fail; 1914 } 1915 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1916 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1917 &fl->ifl_sds.ifsd_map[i]); 1918 if (err != 0) { 1919 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1920 goto fail; 1921 } 1922 } 1923 } 1924 return (0); 1925 1926 fail: 1927 iflib_rx_structures_free(ctx); 1928 return (err); 1929 } 1930 1931 1932 /* 1933 * Internal service routines 1934 */ 1935 1936 struct rxq_refill_cb_arg { 1937 int error; 1938 bus_dma_segment_t seg; 1939 int nseg; 1940 }; 1941 1942 static void 1943 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1944 { 1945 struct rxq_refill_cb_arg *cb_arg = arg; 1946 1947 cb_arg->error = error; 1948 cb_arg->seg = segs[0]; 1949 cb_arg->nseg = nseg; 1950 } 1951 1952 /** 1953 * rxq_refill - refill an rxq free-buffer list 1954 * @ctx: the iflib context 1955 * @rxq: the free-list to refill 1956 * @n: the number of new buffers to allocate 1957 * 1958 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1959 * The caller must assure that @n does not exceed the queue's capacity. 1960 */ 1961 static void 1962 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1963 { 1964 struct if_rxd_update iru; 1965 struct rxq_refill_cb_arg cb_arg; 1966 struct mbuf *m; 1967 caddr_t cl, *sd_cl; 1968 struct mbuf **sd_m; 1969 bus_dmamap_t *sd_map; 1970 bus_addr_t bus_addr, *sd_ba; 1971 int err, frag_idx, i, idx, n, pidx; 1972 qidx_t credits; 1973 1974 sd_m = fl->ifl_sds.ifsd_m; 1975 sd_map = fl->ifl_sds.ifsd_map; 1976 sd_cl = fl->ifl_sds.ifsd_cl; 1977 sd_ba = fl->ifl_sds.ifsd_ba; 1978 pidx = fl->ifl_pidx; 1979 idx = pidx; 1980 frag_idx = fl->ifl_fragidx; 1981 credits = fl->ifl_credits; 1982 1983 i = 0; 1984 n = count; 1985 MPASS(n > 0); 1986 MPASS(credits + n <= fl->ifl_size); 1987 1988 if (pidx < fl->ifl_cidx) 1989 MPASS(pidx + n <= fl->ifl_cidx); 1990 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1991 MPASS(fl->ifl_gen == 0); 1992 if (pidx > fl->ifl_cidx) 1993 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1994 1995 DBG_COUNTER_INC(fl_refills); 1996 if (n > 8) 1997 DBG_COUNTER_INC(fl_refills_large); 1998 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1999 while (n--) { 2000 /* 2001 * We allocate an uninitialized mbuf + cluster, mbuf is 2002 * initialized after rx. 2003 * 2004 * If the cluster is still set then we know a minimum sized packet was received 2005 */ 2006 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2007 &frag_idx); 2008 if (frag_idx < 0) 2009 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2010 MPASS(frag_idx >= 0); 2011 if ((cl = sd_cl[frag_idx]) == NULL) { 2012 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 2013 break; 2014 2015 cb_arg.error = 0; 2016 MPASS(sd_map != NULL); 2017 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2018 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2019 BUS_DMA_NOWAIT); 2020 if (err != 0 || cb_arg.error) { 2021 /* 2022 * !zone_pack ? 2023 */ 2024 if (fl->ifl_zone == zone_pack) 2025 uma_zfree(fl->ifl_zone, cl); 2026 break; 2027 } 2028 2029 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2030 sd_cl[frag_idx] = cl; 2031 #if MEMORY_LOGGING 2032 fl->ifl_cl_enqueued++; 2033 #endif 2034 } else { 2035 bus_addr = sd_ba[frag_idx]; 2036 } 2037 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2038 BUS_DMASYNC_PREREAD); 2039 2040 MPASS(sd_m[frag_idx] == NULL); 2041 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2042 break; 2043 } 2044 sd_m[frag_idx] = m; 2045 bit_set(fl->ifl_rx_bitmap, frag_idx); 2046 #if MEMORY_LOGGING 2047 fl->ifl_m_enqueued++; 2048 #endif 2049 2050 DBG_COUNTER_INC(rx_allocs); 2051 fl->ifl_rxd_idxs[i] = frag_idx; 2052 fl->ifl_bus_addrs[i] = bus_addr; 2053 fl->ifl_vm_addrs[i] = cl; 2054 credits++; 2055 i++; 2056 MPASS(credits <= fl->ifl_size); 2057 if (++idx == fl->ifl_size) { 2058 fl->ifl_gen = 1; 2059 idx = 0; 2060 } 2061 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2062 iru.iru_pidx = pidx; 2063 iru.iru_count = i; 2064 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2065 i = 0; 2066 pidx = idx; 2067 fl->ifl_pidx = idx; 2068 fl->ifl_credits = credits; 2069 } 2070 } 2071 2072 if (i) { 2073 iru.iru_pidx = pidx; 2074 iru.iru_count = i; 2075 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2076 fl->ifl_pidx = idx; 2077 fl->ifl_credits = credits; 2078 } 2079 DBG_COUNTER_INC(rxd_flush); 2080 if (fl->ifl_pidx == 0) 2081 pidx = fl->ifl_size - 1; 2082 else 2083 pidx = fl->ifl_pidx - 1; 2084 2085 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2086 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2087 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2088 fl->ifl_fragidx = frag_idx; 2089 } 2090 2091 static __inline void 2092 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2093 { 2094 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2095 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2096 #ifdef INVARIANTS 2097 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2098 #endif 2099 2100 MPASS(fl->ifl_credits <= fl->ifl_size); 2101 MPASS(reclaimable == delta); 2102 2103 if (reclaimable > 0) 2104 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2105 } 2106 2107 uint8_t 2108 iflib_in_detach(if_ctx_t ctx) 2109 { 2110 bool in_detach; 2111 STATE_LOCK(ctx); 2112 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2113 STATE_UNLOCK(ctx); 2114 return (in_detach); 2115 } 2116 2117 static void 2118 iflib_fl_bufs_free(iflib_fl_t fl) 2119 { 2120 iflib_dma_info_t idi = fl->ifl_ifdi; 2121 bus_dmamap_t sd_map; 2122 uint32_t i; 2123 2124 for (i = 0; i < fl->ifl_size; i++) { 2125 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2126 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2127 2128 if (*sd_cl != NULL) { 2129 sd_map = fl->ifl_sds.ifsd_map[i]; 2130 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2131 BUS_DMASYNC_POSTREAD); 2132 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2133 if (*sd_cl != NULL) 2134 uma_zfree(fl->ifl_zone, *sd_cl); 2135 // XXX: Should this get moved out? 2136 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2137 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map); 2138 if (*sd_m != NULL) { 2139 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2140 uma_zfree(zone_mbuf, *sd_m); 2141 } 2142 } else { 2143 MPASS(*sd_cl == NULL); 2144 MPASS(*sd_m == NULL); 2145 } 2146 #if MEMORY_LOGGING 2147 fl->ifl_m_dequeued++; 2148 fl->ifl_cl_dequeued++; 2149 #endif 2150 *sd_cl = NULL; 2151 *sd_m = NULL; 2152 } 2153 #ifdef INVARIANTS 2154 for (i = 0; i < fl->ifl_size; i++) { 2155 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2156 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2157 } 2158 #endif 2159 /* 2160 * Reset free list values 2161 */ 2162 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2163 bzero(idi->idi_vaddr, idi->idi_size); 2164 } 2165 2166 /********************************************************************* 2167 * 2168 * Initialize a receive ring and its buffers. 2169 * 2170 **********************************************************************/ 2171 static int 2172 iflib_fl_setup(iflib_fl_t fl) 2173 { 2174 iflib_rxq_t rxq = fl->ifl_rxq; 2175 if_ctx_t ctx = rxq->ifr_ctx; 2176 2177 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2178 /* 2179 ** Free current RX buffer structs and their mbufs 2180 */ 2181 iflib_fl_bufs_free(fl); 2182 /* Now replenish the mbufs */ 2183 MPASS(fl->ifl_credits == 0); 2184 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2185 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2186 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2187 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2188 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2189 2190 2191 /* avoid pre-allocating zillions of clusters to an idle card 2192 * potentially speeding up attach 2193 */ 2194 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2195 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2196 if (min(128, fl->ifl_size) != fl->ifl_credits) 2197 return (ENOBUFS); 2198 /* 2199 * handle failure 2200 */ 2201 MPASS(rxq != NULL); 2202 MPASS(fl->ifl_ifdi != NULL); 2203 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2204 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2205 return (0); 2206 } 2207 2208 /********************************************************************* 2209 * 2210 * Free receive ring data structures 2211 * 2212 **********************************************************************/ 2213 static void 2214 iflib_rx_sds_free(iflib_rxq_t rxq) 2215 { 2216 iflib_fl_t fl; 2217 int i, j; 2218 2219 if (rxq->ifr_fl != NULL) { 2220 for (i = 0; i < rxq->ifr_nfl; i++) { 2221 fl = &rxq->ifr_fl[i]; 2222 if (fl->ifl_buf_tag != NULL) { 2223 if (fl->ifl_sds.ifsd_map != NULL) { 2224 for (j = 0; j < fl->ifl_size; j++) { 2225 if (fl->ifl_sds.ifsd_map[j] == 2226 NULL) 2227 continue; 2228 bus_dmamap_sync( 2229 fl->ifl_buf_tag, 2230 fl->ifl_sds.ifsd_map[j], 2231 BUS_DMASYNC_POSTREAD); 2232 bus_dmamap_unload( 2233 fl->ifl_buf_tag, 2234 fl->ifl_sds.ifsd_map[j]); 2235 } 2236 } 2237 bus_dma_tag_destroy(fl->ifl_buf_tag); 2238 fl->ifl_buf_tag = NULL; 2239 } 2240 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2241 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2242 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2243 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2244 fl->ifl_sds.ifsd_m = NULL; 2245 fl->ifl_sds.ifsd_cl = NULL; 2246 fl->ifl_sds.ifsd_ba = NULL; 2247 fl->ifl_sds.ifsd_map = NULL; 2248 } 2249 free(rxq->ifr_fl, M_IFLIB); 2250 rxq->ifr_fl = NULL; 2251 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2252 } 2253 } 2254 2255 /* 2256 * MI independent logic 2257 * 2258 */ 2259 static void 2260 iflib_timer(void *arg) 2261 { 2262 iflib_txq_t txq = arg; 2263 if_ctx_t ctx = txq->ift_ctx; 2264 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2265 uint64_t this_tick = ticks; 2266 uint32_t reset_on = hz / 2; 2267 2268 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2269 return; 2270 /* 2271 ** Check on the state of the TX queue(s), this 2272 ** can be done without the lock because its RO 2273 ** and the HUNG state will be static if set. 2274 */ 2275 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2276 txq->ift_last_timer_tick = this_tick; 2277 IFDI_TIMER(ctx, txq->ift_id); 2278 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2279 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2280 (sctx->isc_pause_frames == 0))) 2281 goto hung; 2282 2283 if (ifmp_ring_is_stalled(txq->ift_br)) 2284 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2285 txq->ift_cleaned_prev = txq->ift_cleaned; 2286 } 2287 #ifdef DEV_NETMAP 2288 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2289 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2290 #endif 2291 /* handle any laggards */ 2292 if (txq->ift_db_pending) 2293 GROUPTASK_ENQUEUE(&txq->ift_task); 2294 2295 sctx->isc_pause_frames = 0; 2296 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2297 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2298 return; 2299 hung: 2300 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2301 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2302 STATE_LOCK(ctx); 2303 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2304 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2305 iflib_admin_intr_deferred(ctx); 2306 STATE_UNLOCK(ctx); 2307 } 2308 2309 static void 2310 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2311 { 2312 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2313 2314 /* 2315 * XXX don't set the max_frame_size to larger 2316 * than the hardware can handle 2317 */ 2318 if (sctx->isc_max_frame_size <= MCLBYTES) 2319 ctx->ifc_rx_mbuf_sz = MCLBYTES; 2320 else 2321 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE; 2322 } 2323 2324 uint32_t 2325 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2326 { 2327 return (ctx->ifc_rx_mbuf_sz); 2328 } 2329 2330 static void 2331 iflib_init_locked(if_ctx_t ctx) 2332 { 2333 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2334 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2335 if_t ifp = ctx->ifc_ifp; 2336 iflib_fl_t fl; 2337 iflib_txq_t txq; 2338 iflib_rxq_t rxq; 2339 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2340 2341 2342 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2343 IFDI_INTR_DISABLE(ctx); 2344 2345 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2346 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2347 /* Set hardware offload abilities */ 2348 if_clearhwassist(ifp); 2349 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2350 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2351 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2352 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2353 if (if_getcapenable(ifp) & IFCAP_TSO4) 2354 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2355 if (if_getcapenable(ifp) & IFCAP_TSO6) 2356 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2357 2358 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2359 CALLOUT_LOCK(txq); 2360 callout_stop(&txq->ift_timer); 2361 CALLOUT_UNLOCK(txq); 2362 iflib_netmap_txq_init(ctx, txq); 2363 } 2364 2365 /* 2366 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2367 * that drivers can use the value when setting up the hardware receive 2368 * buffers. 2369 */ 2370 iflib_calc_rx_mbuf_sz(ctx); 2371 2372 #ifdef INVARIANTS 2373 i = if_getdrvflags(ifp); 2374 #endif 2375 IFDI_INIT(ctx); 2376 MPASS(if_getdrvflags(ifp) == i); 2377 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2378 /* XXX this should really be done on a per-queue basis */ 2379 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2380 MPASS(rxq->ifr_id == i); 2381 iflib_netmap_rxq_init(ctx, rxq); 2382 continue; 2383 } 2384 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2385 if (iflib_fl_setup(fl)) { 2386 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2387 goto done; 2388 } 2389 } 2390 } 2391 done: 2392 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2393 IFDI_INTR_ENABLE(ctx); 2394 txq = ctx->ifc_txqs; 2395 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2396 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2397 txq->ift_timer.c_cpu); 2398 } 2399 2400 static int 2401 iflib_media_change(if_t ifp) 2402 { 2403 if_ctx_t ctx = if_getsoftc(ifp); 2404 int err; 2405 2406 CTX_LOCK(ctx); 2407 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2408 iflib_init_locked(ctx); 2409 CTX_UNLOCK(ctx); 2410 return (err); 2411 } 2412 2413 static void 2414 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2415 { 2416 if_ctx_t ctx = if_getsoftc(ifp); 2417 2418 CTX_LOCK(ctx); 2419 IFDI_UPDATE_ADMIN_STATUS(ctx); 2420 IFDI_MEDIA_STATUS(ctx, ifmr); 2421 CTX_UNLOCK(ctx); 2422 } 2423 2424 void 2425 iflib_stop(if_ctx_t ctx) 2426 { 2427 iflib_txq_t txq = ctx->ifc_txqs; 2428 iflib_rxq_t rxq = ctx->ifc_rxqs; 2429 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2430 if_shared_ctx_t sctx = ctx->ifc_sctx; 2431 iflib_dma_info_t di; 2432 iflib_fl_t fl; 2433 int i, j; 2434 2435 /* Tell the stack that the interface is no longer active */ 2436 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2437 2438 IFDI_INTR_DISABLE(ctx); 2439 DELAY(1000); 2440 IFDI_STOP(ctx); 2441 DELAY(1000); 2442 2443 iflib_debug_reset(); 2444 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2445 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2446 /* make sure all transmitters have completed before proceeding XXX */ 2447 2448 CALLOUT_LOCK(txq); 2449 callout_stop(&txq->ift_timer); 2450 CALLOUT_UNLOCK(txq); 2451 2452 /* clean any enqueued buffers */ 2453 iflib_ifmp_purge(txq); 2454 /* Free any existing tx buffers. */ 2455 for (j = 0; j < txq->ift_size; j++) { 2456 iflib_txsd_free(ctx, txq, j); 2457 } 2458 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2459 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2460 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2461 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2462 txq->ift_pullups = 0; 2463 ifmp_ring_reset_stats(txq->ift_br); 2464 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2465 bzero((void *)di->idi_vaddr, di->idi_size); 2466 } 2467 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2468 /* make sure all transmitters have completed before proceeding XXX */ 2469 2470 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2471 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2472 bzero((void *)di->idi_vaddr, di->idi_size); 2473 /* also resets the free lists pidx/cidx */ 2474 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2475 iflib_fl_bufs_free(fl); 2476 } 2477 } 2478 2479 static inline caddr_t 2480 calc_next_rxd(iflib_fl_t fl, int cidx) 2481 { 2482 qidx_t size; 2483 int nrxd; 2484 caddr_t start, end, cur, next; 2485 2486 nrxd = fl->ifl_size; 2487 size = fl->ifl_rxd_size; 2488 start = fl->ifl_ifdi->idi_vaddr; 2489 2490 if (__predict_false(size == 0)) 2491 return (start); 2492 cur = start + size*cidx; 2493 end = start + size*nrxd; 2494 next = CACHE_PTR_NEXT(cur); 2495 return (next < end ? next : start); 2496 } 2497 2498 static inline void 2499 prefetch_pkts(iflib_fl_t fl, int cidx) 2500 { 2501 int nextptr; 2502 int nrxd = fl->ifl_size; 2503 caddr_t next_rxd; 2504 2505 2506 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2507 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2508 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2509 next_rxd = calc_next_rxd(fl, cidx); 2510 prefetch(next_rxd); 2511 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2512 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2513 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2514 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2515 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2516 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2517 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2518 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2519 } 2520 2521 static void 2522 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2523 { 2524 int flid, cidx; 2525 bus_dmamap_t map; 2526 iflib_fl_t fl; 2527 int next; 2528 2529 map = NULL; 2530 flid = irf->irf_flid; 2531 cidx = irf->irf_idx; 2532 fl = &rxq->ifr_fl[flid]; 2533 sd->ifsd_fl = fl; 2534 sd->ifsd_cidx = cidx; 2535 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2536 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2537 fl->ifl_credits--; 2538 #if MEMORY_LOGGING 2539 fl->ifl_m_dequeued++; 2540 #endif 2541 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2542 prefetch_pkts(fl, cidx); 2543 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2544 prefetch(&fl->ifl_sds.ifsd_map[next]); 2545 map = fl->ifl_sds.ifsd_map[cidx]; 2546 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2547 2548 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2549 MPASS(fl->ifl_cidx == cidx); 2550 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2551 if (unload) 2552 bus_dmamap_unload(fl->ifl_buf_tag, map); 2553 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2554 if (__predict_false(fl->ifl_cidx == 0)) 2555 fl->ifl_gen = 0; 2556 bit_clear(fl->ifl_rx_bitmap, cidx); 2557 } 2558 2559 static struct mbuf * 2560 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2561 { 2562 int i, padlen , flags; 2563 struct mbuf *m, *mh, *mt; 2564 caddr_t cl; 2565 2566 i = 0; 2567 mh = NULL; 2568 do { 2569 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2570 2571 MPASS(*sd->ifsd_cl != NULL); 2572 MPASS(*sd->ifsd_m != NULL); 2573 2574 /* Don't include zero-length frags */ 2575 if (ri->iri_frags[i].irf_len == 0) { 2576 /* XXX we can save the cluster here, but not the mbuf */ 2577 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2578 m_free(*sd->ifsd_m); 2579 *sd->ifsd_m = NULL; 2580 continue; 2581 } 2582 m = *sd->ifsd_m; 2583 *sd->ifsd_m = NULL; 2584 if (mh == NULL) { 2585 flags = M_PKTHDR|M_EXT; 2586 mh = mt = m; 2587 padlen = ri->iri_pad; 2588 } else { 2589 flags = M_EXT; 2590 mt->m_next = m; 2591 mt = m; 2592 /* assuming padding is only on the first fragment */ 2593 padlen = 0; 2594 } 2595 cl = *sd->ifsd_cl; 2596 *sd->ifsd_cl = NULL; 2597 2598 /* Can these two be made one ? */ 2599 m_init(m, M_NOWAIT, MT_DATA, flags); 2600 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2601 /* 2602 * These must follow m_init and m_cljset 2603 */ 2604 m->m_data += padlen; 2605 ri->iri_len -= padlen; 2606 m->m_len = ri->iri_frags[i].irf_len; 2607 } while (++i < ri->iri_nfrags); 2608 2609 return (mh); 2610 } 2611 2612 /* 2613 * Process one software descriptor 2614 */ 2615 static struct mbuf * 2616 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2617 { 2618 struct if_rxsd sd; 2619 struct mbuf *m; 2620 2621 /* should I merge this back in now that the two paths are basically duplicated? */ 2622 if (ri->iri_nfrags == 1 && 2623 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2624 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2625 m = *sd.ifsd_m; 2626 *sd.ifsd_m = NULL; 2627 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2628 #ifndef __NO_STRICT_ALIGNMENT 2629 if (!IP_ALIGNED(m)) 2630 m->m_data += 2; 2631 #endif 2632 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2633 m->m_len = ri->iri_frags[0].irf_len; 2634 } else { 2635 m = assemble_segments(rxq, ri, &sd); 2636 } 2637 m->m_pkthdr.len = ri->iri_len; 2638 m->m_pkthdr.rcvif = ri->iri_ifp; 2639 m->m_flags |= ri->iri_flags; 2640 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2641 m->m_pkthdr.flowid = ri->iri_flowid; 2642 M_HASHTYPE_SET(m, ri->iri_rsstype); 2643 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2644 m->m_pkthdr.csum_data = ri->iri_csum_data; 2645 return (m); 2646 } 2647 2648 #if defined(INET6) || defined(INET) 2649 static void 2650 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2651 { 2652 CURVNET_SET(lc->ifp->if_vnet); 2653 #if defined(INET6) 2654 *v6 = VNET(ip6_forwarding); 2655 #endif 2656 #if defined(INET) 2657 *v4 = VNET(ipforwarding); 2658 #endif 2659 CURVNET_RESTORE(); 2660 } 2661 2662 /* 2663 * Returns true if it's possible this packet could be LROed. 2664 * if it returns false, it is guaranteed that tcp_lro_rx() 2665 * would not return zero. 2666 */ 2667 static bool 2668 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2669 { 2670 struct ether_header *eh; 2671 uint16_t eh_type; 2672 2673 eh = mtod(m, struct ether_header *); 2674 eh_type = ntohs(eh->ether_type); 2675 switch (eh_type) { 2676 #if defined(INET6) 2677 case ETHERTYPE_IPV6: 2678 return !v6_forwarding; 2679 #endif 2680 #if defined (INET) 2681 case ETHERTYPE_IP: 2682 return !v4_forwarding; 2683 #endif 2684 } 2685 2686 return false; 2687 } 2688 #else 2689 static void 2690 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2691 { 2692 } 2693 #endif 2694 2695 static bool 2696 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2697 { 2698 if_ctx_t ctx = rxq->ifr_ctx; 2699 if_shared_ctx_t sctx = ctx->ifc_sctx; 2700 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2701 int avail, i; 2702 qidx_t *cidxp; 2703 struct if_rxd_info ri; 2704 int err, budget_left, rx_bytes, rx_pkts; 2705 iflib_fl_t fl; 2706 struct ifnet *ifp; 2707 int lro_enabled; 2708 bool v4_forwarding, v6_forwarding, lro_possible; 2709 2710 /* 2711 * XXX early demux data packets so that if_input processing only handles 2712 * acks in interrupt context 2713 */ 2714 struct mbuf *m, *mh, *mt, *mf; 2715 2716 lro_possible = v4_forwarding = v6_forwarding = false; 2717 ifp = ctx->ifc_ifp; 2718 mh = mt = NULL; 2719 MPASS(budget > 0); 2720 rx_pkts = rx_bytes = 0; 2721 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2722 cidxp = &rxq->ifr_cq_cidx; 2723 else 2724 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2725 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2726 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2727 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2728 DBG_COUNTER_INC(rx_unavail); 2729 return (false); 2730 } 2731 2732 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2733 if (__predict_false(!CTX_ACTIVE(ctx))) { 2734 DBG_COUNTER_INC(rx_ctx_inactive); 2735 break; 2736 } 2737 /* 2738 * Reset client set fields to their default values 2739 */ 2740 rxd_info_zero(&ri); 2741 ri.iri_qsidx = rxq->ifr_id; 2742 ri.iri_cidx = *cidxp; 2743 ri.iri_ifp = ifp; 2744 ri.iri_frags = rxq->ifr_frags; 2745 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2746 2747 if (err) 2748 goto err; 2749 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2750 *cidxp = ri.iri_cidx; 2751 /* Update our consumer index */ 2752 /* XXX NB: shurd - check if this is still safe */ 2753 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2754 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2755 rxq->ifr_cq_gen = 0; 2756 } 2757 /* was this only a completion queue message? */ 2758 if (__predict_false(ri.iri_nfrags == 0)) 2759 continue; 2760 } 2761 MPASS(ri.iri_nfrags != 0); 2762 MPASS(ri.iri_len != 0); 2763 2764 /* will advance the cidx on the corresponding free lists */ 2765 m = iflib_rxd_pkt_get(rxq, &ri); 2766 avail--; 2767 budget_left--; 2768 if (avail == 0 && budget_left) 2769 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2770 2771 if (__predict_false(m == NULL)) { 2772 DBG_COUNTER_INC(rx_mbuf_null); 2773 continue; 2774 } 2775 /* imm_pkt: -- cxgb */ 2776 if (mh == NULL) 2777 mh = mt = m; 2778 else { 2779 mt->m_nextpkt = m; 2780 mt = m; 2781 } 2782 } 2783 /* make sure that we can refill faster than drain */ 2784 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2785 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2786 2787 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2788 if (lro_enabled) 2789 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2790 mt = mf = NULL; 2791 while (mh != NULL) { 2792 m = mh; 2793 mh = mh->m_nextpkt; 2794 m->m_nextpkt = NULL; 2795 #ifndef __NO_STRICT_ALIGNMENT 2796 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2797 continue; 2798 #endif 2799 rx_bytes += m->m_pkthdr.len; 2800 rx_pkts++; 2801 #if defined(INET6) || defined(INET) 2802 if (lro_enabled) { 2803 if (!lro_possible) { 2804 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2805 if (lro_possible && mf != NULL) { 2806 ifp->if_input(ifp, mf); 2807 DBG_COUNTER_INC(rx_if_input); 2808 mt = mf = NULL; 2809 } 2810 } 2811 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2812 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2813 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2814 continue; 2815 } 2816 } 2817 #endif 2818 if (lro_possible) { 2819 ifp->if_input(ifp, m); 2820 DBG_COUNTER_INC(rx_if_input); 2821 continue; 2822 } 2823 2824 if (mf == NULL) 2825 mf = m; 2826 if (mt != NULL) 2827 mt->m_nextpkt = m; 2828 mt = m; 2829 } 2830 if (mf != NULL) { 2831 ifp->if_input(ifp, mf); 2832 DBG_COUNTER_INC(rx_if_input); 2833 } 2834 2835 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2836 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2837 2838 /* 2839 * Flush any outstanding LRO work 2840 */ 2841 #if defined(INET6) || defined(INET) 2842 tcp_lro_flush_all(&rxq->ifr_lc); 2843 #endif 2844 if (avail) 2845 return true; 2846 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2847 err: 2848 STATE_LOCK(ctx); 2849 ctx->ifc_flags |= IFC_DO_RESET; 2850 iflib_admin_intr_deferred(ctx); 2851 STATE_UNLOCK(ctx); 2852 return (false); 2853 } 2854 2855 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2856 static inline qidx_t 2857 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2858 { 2859 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2860 qidx_t minthresh = txq->ift_size / 8; 2861 if (in_use > 4*minthresh) 2862 return (notify_count); 2863 if (in_use > 2*minthresh) 2864 return (notify_count >> 1); 2865 if (in_use > minthresh) 2866 return (notify_count >> 3); 2867 return (0); 2868 } 2869 2870 static inline qidx_t 2871 txq_max_rs_deferred(iflib_txq_t txq) 2872 { 2873 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2874 qidx_t minthresh = txq->ift_size / 8; 2875 if (txq->ift_in_use > 4*minthresh) 2876 return (notify_count); 2877 if (txq->ift_in_use > 2*minthresh) 2878 return (notify_count >> 1); 2879 if (txq->ift_in_use > minthresh) 2880 return (notify_count >> 2); 2881 return (2); 2882 } 2883 2884 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2885 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2886 2887 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2888 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2889 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2890 2891 /* forward compatibility for cxgb */ 2892 #define FIRST_QSET(ctx) 0 2893 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2894 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2895 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2896 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2897 2898 /* XXX we should be setting this to something other than zero */ 2899 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2900 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2901 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2902 2903 static inline bool 2904 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2905 { 2906 qidx_t dbval, max; 2907 bool rang; 2908 2909 rang = false; 2910 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2911 if (ring || txq->ift_db_pending >= max) { 2912 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2913 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2914 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2915 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2916 txq->ift_db_pending = txq->ift_npending = 0; 2917 rang = true; 2918 } 2919 return (rang); 2920 } 2921 2922 #ifdef PKT_DEBUG 2923 static void 2924 print_pkt(if_pkt_info_t pi) 2925 { 2926 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2927 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2928 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2929 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2930 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2931 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2932 } 2933 #endif 2934 2935 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2936 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2937 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2938 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2939 2940 static int 2941 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2942 { 2943 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2944 struct ether_vlan_header *eh; 2945 struct mbuf *m; 2946 2947 m = *mp; 2948 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2949 M_WRITABLE(m) == 0) { 2950 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2951 return (ENOMEM); 2952 } else { 2953 m_freem(*mp); 2954 DBG_COUNTER_INC(tx_frees); 2955 *mp = m; 2956 } 2957 } 2958 2959 /* 2960 * Determine where frame payload starts. 2961 * Jump over vlan headers if already present, 2962 * helpful for QinQ too. 2963 */ 2964 if (__predict_false(m->m_len < sizeof(*eh))) { 2965 txq->ift_pullups++; 2966 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2967 return (ENOMEM); 2968 } 2969 eh = mtod(m, struct ether_vlan_header *); 2970 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2971 pi->ipi_etype = ntohs(eh->evl_proto); 2972 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2973 } else { 2974 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2975 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2976 } 2977 2978 switch (pi->ipi_etype) { 2979 #ifdef INET 2980 case ETHERTYPE_IP: 2981 { 2982 struct mbuf *n; 2983 struct ip *ip = NULL; 2984 struct tcphdr *th = NULL; 2985 int minthlen; 2986 2987 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2988 if (__predict_false(m->m_len < minthlen)) { 2989 /* 2990 * if this code bloat is causing too much of a hit 2991 * move it to a separate function and mark it noinline 2992 */ 2993 if (m->m_len == pi->ipi_ehdrlen) { 2994 n = m->m_next; 2995 MPASS(n); 2996 if (n->m_len >= sizeof(*ip)) { 2997 ip = (struct ip *)n->m_data; 2998 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2999 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3000 } else { 3001 txq->ift_pullups++; 3002 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3003 return (ENOMEM); 3004 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3005 } 3006 } else { 3007 txq->ift_pullups++; 3008 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3009 return (ENOMEM); 3010 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3011 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3012 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3013 } 3014 } else { 3015 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3016 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3017 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3018 } 3019 pi->ipi_ip_hlen = ip->ip_hl << 2; 3020 pi->ipi_ipproto = ip->ip_p; 3021 pi->ipi_flags |= IPI_TX_IPV4; 3022 3023 /* TCP checksum offload may require TCP header length */ 3024 if (IS_TX_OFFLOAD4(pi)) { 3025 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3026 if (__predict_false(th == NULL)) { 3027 txq->ift_pullups++; 3028 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3029 return (ENOMEM); 3030 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3031 } 3032 pi->ipi_tcp_hflags = th->th_flags; 3033 pi->ipi_tcp_hlen = th->th_off << 2; 3034 pi->ipi_tcp_seq = th->th_seq; 3035 } 3036 if (IS_TSO4(pi)) { 3037 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3038 return (ENXIO); 3039 /* 3040 * TSO always requires hardware checksum offload. 3041 */ 3042 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3043 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3044 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3045 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3046 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3047 ip->ip_sum = 0; 3048 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3049 } 3050 } 3051 } 3052 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3053 ip->ip_sum = 0; 3054 3055 break; 3056 } 3057 #endif 3058 #ifdef INET6 3059 case ETHERTYPE_IPV6: 3060 { 3061 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3062 struct tcphdr *th; 3063 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3064 3065 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3066 txq->ift_pullups++; 3067 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3068 return (ENOMEM); 3069 } 3070 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3071 3072 /* XXX-BZ this will go badly in case of ext hdrs. */ 3073 pi->ipi_ipproto = ip6->ip6_nxt; 3074 pi->ipi_flags |= IPI_TX_IPV6; 3075 3076 /* TCP checksum offload may require TCP header length */ 3077 if (IS_TX_OFFLOAD6(pi)) { 3078 if (pi->ipi_ipproto == IPPROTO_TCP) { 3079 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3080 txq->ift_pullups++; 3081 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3082 return (ENOMEM); 3083 } 3084 pi->ipi_tcp_hflags = th->th_flags; 3085 pi->ipi_tcp_hlen = th->th_off << 2; 3086 pi->ipi_tcp_seq = th->th_seq; 3087 } 3088 if (IS_TSO6(pi)) { 3089 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3090 return (ENXIO); 3091 /* 3092 * TSO always requires hardware checksum offload. 3093 */ 3094 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3095 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3096 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3097 } 3098 } 3099 break; 3100 } 3101 #endif 3102 default: 3103 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3104 pi->ipi_ip_hlen = 0; 3105 break; 3106 } 3107 *mp = m; 3108 3109 return (0); 3110 } 3111 3112 /* 3113 * If dodgy hardware rejects the scatter gather chain we've handed it 3114 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3115 * m_defrag'd mbufs 3116 */ 3117 static __noinline struct mbuf * 3118 iflib_remove_mbuf(iflib_txq_t txq) 3119 { 3120 int ntxd, pidx; 3121 struct mbuf *m, **ifsd_m; 3122 3123 ifsd_m = txq->ift_sds.ifsd_m; 3124 ntxd = txq->ift_size; 3125 pidx = txq->ift_pidx & (ntxd - 1); 3126 ifsd_m = txq->ift_sds.ifsd_m; 3127 m = ifsd_m[pidx]; 3128 ifsd_m[pidx] = NULL; 3129 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3130 if (txq->ift_sds.ifsd_tso_map != NULL) 3131 bus_dmamap_unload(txq->ift_tso_buf_tag, 3132 txq->ift_sds.ifsd_tso_map[pidx]); 3133 #if MEMORY_LOGGING 3134 txq->ift_dequeued++; 3135 #endif 3136 return (m); 3137 } 3138 3139 static inline caddr_t 3140 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3141 { 3142 qidx_t size; 3143 int ntxd; 3144 caddr_t start, end, cur, next; 3145 3146 ntxd = txq->ift_size; 3147 size = txq->ift_txd_size[qid]; 3148 start = txq->ift_ifdi[qid].idi_vaddr; 3149 3150 if (__predict_false(size == 0)) 3151 return (start); 3152 cur = start + size*cidx; 3153 end = start + size*ntxd; 3154 next = CACHE_PTR_NEXT(cur); 3155 return (next < end ? next : start); 3156 } 3157 3158 /* 3159 * Pad an mbuf to ensure a minimum ethernet frame size. 3160 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3161 */ 3162 static __noinline int 3163 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3164 { 3165 /* 3166 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3167 * and ARP message is the smallest common payload I can think of 3168 */ 3169 static char pad[18]; /* just zeros */ 3170 int n; 3171 struct mbuf *new_head; 3172 3173 if (!M_WRITABLE(*m_head)) { 3174 new_head = m_dup(*m_head, M_NOWAIT); 3175 if (new_head == NULL) { 3176 m_freem(*m_head); 3177 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3178 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3179 DBG_COUNTER_INC(tx_frees); 3180 return ENOMEM; 3181 } 3182 m_freem(*m_head); 3183 *m_head = new_head; 3184 } 3185 3186 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3187 n > 0; n -= sizeof(pad)) 3188 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3189 break; 3190 3191 if (n > 0) { 3192 m_freem(*m_head); 3193 device_printf(dev, "cannot pad short frame\n"); 3194 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3195 DBG_COUNTER_INC(tx_frees); 3196 return (ENOBUFS); 3197 } 3198 3199 return 0; 3200 } 3201 3202 static int 3203 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3204 { 3205 if_ctx_t ctx; 3206 if_shared_ctx_t sctx; 3207 if_softc_ctx_t scctx; 3208 bus_dma_tag_t buf_tag; 3209 bus_dma_segment_t *segs; 3210 struct mbuf *m_head, **ifsd_m; 3211 void *next_txd; 3212 bus_dmamap_t map; 3213 struct if_pkt_info pi; 3214 int remap = 0; 3215 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3216 3217 ctx = txq->ift_ctx; 3218 sctx = ctx->ifc_sctx; 3219 scctx = &ctx->ifc_softc_ctx; 3220 segs = txq->ift_segs; 3221 ntxd = txq->ift_size; 3222 m_head = *m_headp; 3223 map = NULL; 3224 3225 /* 3226 * If we're doing TSO the next descriptor to clean may be quite far ahead 3227 */ 3228 cidx = txq->ift_cidx; 3229 pidx = txq->ift_pidx; 3230 if (ctx->ifc_flags & IFC_PREFETCH) { 3231 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3232 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3233 next_txd = calc_next_txd(txq, cidx, 0); 3234 prefetch(next_txd); 3235 } 3236 3237 /* prefetch the next cache line of mbuf pointers and flags */ 3238 prefetch(&txq->ift_sds.ifsd_m[next]); 3239 prefetch(&txq->ift_sds.ifsd_map[next]); 3240 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3241 } 3242 map = txq->ift_sds.ifsd_map[pidx]; 3243 ifsd_m = txq->ift_sds.ifsd_m; 3244 3245 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3246 buf_tag = txq->ift_tso_buf_tag; 3247 max_segs = scctx->isc_tx_tso_segments_max; 3248 map = txq->ift_sds.ifsd_tso_map[pidx]; 3249 MPASS(buf_tag != NULL); 3250 MPASS(max_segs > 0); 3251 } else { 3252 buf_tag = txq->ift_buf_tag; 3253 max_segs = scctx->isc_tx_nsegments; 3254 map = txq->ift_sds.ifsd_map[pidx]; 3255 } 3256 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3257 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3258 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3259 if (err) { 3260 DBG_COUNTER_INC(encap_txd_encap_fail); 3261 return err; 3262 } 3263 } 3264 m_head = *m_headp; 3265 3266 pkt_info_zero(&pi); 3267 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3268 pi.ipi_pidx = pidx; 3269 pi.ipi_qsidx = txq->ift_id; 3270 pi.ipi_len = m_head->m_pkthdr.len; 3271 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3272 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3273 3274 /* deliberate bitwise OR to make one condition */ 3275 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3276 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3277 DBG_COUNTER_INC(encap_txd_encap_fail); 3278 return (err); 3279 } 3280 m_head = *m_headp; 3281 } 3282 3283 retry: 3284 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3285 BUS_DMA_NOWAIT); 3286 defrag: 3287 if (__predict_false(err)) { 3288 switch (err) { 3289 case EFBIG: 3290 /* try collapse once and defrag once */ 3291 if (remap == 0) { 3292 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3293 /* try defrag if collapsing fails */ 3294 if (m_head == NULL) 3295 remap++; 3296 } 3297 if (remap == 1) { 3298 txq->ift_mbuf_defrag++; 3299 m_head = m_defrag(*m_headp, M_NOWAIT); 3300 } 3301 /* 3302 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3303 * failed to map an mbuf that was run through m_defrag 3304 */ 3305 MPASS(remap <= 1); 3306 if (__predict_false(m_head == NULL || remap > 1)) 3307 goto defrag_failed; 3308 remap++; 3309 *m_headp = m_head; 3310 goto retry; 3311 break; 3312 case ENOMEM: 3313 txq->ift_no_tx_dma_setup++; 3314 break; 3315 default: 3316 txq->ift_no_tx_dma_setup++; 3317 m_freem(*m_headp); 3318 DBG_COUNTER_INC(tx_frees); 3319 *m_headp = NULL; 3320 break; 3321 } 3322 txq->ift_map_failed++; 3323 DBG_COUNTER_INC(encap_load_mbuf_fail); 3324 DBG_COUNTER_INC(encap_txd_encap_fail); 3325 return (err); 3326 } 3327 ifsd_m[pidx] = m_head; 3328 /* 3329 * XXX assumes a 1 to 1 relationship between segments and 3330 * descriptors - this does not hold true on all drivers, e.g. 3331 * cxgb 3332 */ 3333 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3334 txq->ift_no_desc_avail++; 3335 bus_dmamap_unload(buf_tag, map); 3336 DBG_COUNTER_INC(encap_txq_avail_fail); 3337 DBG_COUNTER_INC(encap_txd_encap_fail); 3338 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3339 GROUPTASK_ENQUEUE(&txq->ift_task); 3340 return (ENOBUFS); 3341 } 3342 /* 3343 * On Intel cards we can greatly reduce the number of TX interrupts 3344 * we see by only setting report status on every Nth descriptor. 3345 * However, this also means that the driver will need to keep track 3346 * of the descriptors that RS was set on to check them for the DD bit. 3347 */ 3348 txq->ift_rs_pending += nsegs + 1; 3349 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3350 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3351 pi.ipi_flags |= IPI_TX_INTR; 3352 txq->ift_rs_pending = 0; 3353 } 3354 3355 pi.ipi_segs = segs; 3356 pi.ipi_nsegs = nsegs; 3357 3358 MPASS(pidx >= 0 && pidx < txq->ift_size); 3359 #ifdef PKT_DEBUG 3360 print_pkt(&pi); 3361 #endif 3362 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3363 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3364 DBG_COUNTER_INC(tx_encap); 3365 MPASS(pi.ipi_new_pidx < txq->ift_size); 3366 3367 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3368 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3369 ndesc += txq->ift_size; 3370 txq->ift_gen = 1; 3371 } 3372 /* 3373 * drivers can need as many as 3374 * two sentinels 3375 */ 3376 MPASS(ndesc <= pi.ipi_nsegs + 2); 3377 MPASS(pi.ipi_new_pidx != pidx); 3378 MPASS(ndesc > 0); 3379 txq->ift_in_use += ndesc; 3380 3381 /* 3382 * We update the last software descriptor again here because there may 3383 * be a sentinel and/or there may be more mbufs than segments 3384 */ 3385 txq->ift_pidx = pi.ipi_new_pidx; 3386 txq->ift_npending += pi.ipi_ndescs; 3387 } else { 3388 *m_headp = m_head = iflib_remove_mbuf(txq); 3389 if (err == EFBIG) { 3390 txq->ift_txd_encap_efbig++; 3391 if (remap < 2) { 3392 remap = 1; 3393 goto defrag; 3394 } 3395 } 3396 goto defrag_failed; 3397 } 3398 /* 3399 * err can't possibly be non-zero here, so we don't neet to test it 3400 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3401 */ 3402 return (err); 3403 3404 defrag_failed: 3405 txq->ift_mbuf_defrag_failed++; 3406 txq->ift_map_failed++; 3407 m_freem(*m_headp); 3408 DBG_COUNTER_INC(tx_frees); 3409 *m_headp = NULL; 3410 DBG_COUNTER_INC(encap_txd_encap_fail); 3411 return (ENOMEM); 3412 } 3413 3414 static void 3415 iflib_tx_desc_free(iflib_txq_t txq, int n) 3416 { 3417 uint32_t qsize, cidx, mask, gen; 3418 struct mbuf *m, **ifsd_m; 3419 bool do_prefetch; 3420 3421 cidx = txq->ift_cidx; 3422 gen = txq->ift_gen; 3423 qsize = txq->ift_size; 3424 mask = qsize-1; 3425 ifsd_m = txq->ift_sds.ifsd_m; 3426 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3427 3428 while (n-- > 0) { 3429 if (do_prefetch) { 3430 prefetch(ifsd_m[(cidx + 3) & mask]); 3431 prefetch(ifsd_m[(cidx + 4) & mask]); 3432 } 3433 if ((m = ifsd_m[cidx]) != NULL) { 3434 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3435 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3436 bus_dmamap_sync(txq->ift_tso_buf_tag, 3437 txq->ift_sds.ifsd_tso_map[cidx], 3438 BUS_DMASYNC_POSTWRITE); 3439 bus_dmamap_unload(txq->ift_tso_buf_tag, 3440 txq->ift_sds.ifsd_tso_map[cidx]); 3441 } else { 3442 bus_dmamap_sync(txq->ift_buf_tag, 3443 txq->ift_sds.ifsd_map[cidx], 3444 BUS_DMASYNC_POSTWRITE); 3445 bus_dmamap_unload(txq->ift_buf_tag, 3446 txq->ift_sds.ifsd_map[cidx]); 3447 } 3448 /* XXX we don't support any drivers that batch packets yet */ 3449 MPASS(m->m_nextpkt == NULL); 3450 m_freem(m); 3451 ifsd_m[cidx] = NULL; 3452 #if MEMORY_LOGGING 3453 txq->ift_dequeued++; 3454 #endif 3455 DBG_COUNTER_INC(tx_frees); 3456 } 3457 if (__predict_false(++cidx == qsize)) { 3458 cidx = 0; 3459 gen = 0; 3460 } 3461 } 3462 txq->ift_cidx = cidx; 3463 txq->ift_gen = gen; 3464 } 3465 3466 static __inline int 3467 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3468 { 3469 int reclaim; 3470 if_ctx_t ctx = txq->ift_ctx; 3471 3472 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3473 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3474 3475 /* 3476 * Need a rate-limiting check so that this isn't called every time 3477 */ 3478 iflib_tx_credits_update(ctx, txq); 3479 reclaim = DESC_RECLAIMABLE(txq); 3480 3481 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3482 #ifdef INVARIANTS 3483 if (iflib_verbose_debug) { 3484 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3485 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3486 reclaim, thresh); 3487 3488 } 3489 #endif 3490 return (0); 3491 } 3492 iflib_tx_desc_free(txq, reclaim); 3493 txq->ift_cleaned += reclaim; 3494 txq->ift_in_use -= reclaim; 3495 3496 return (reclaim); 3497 } 3498 3499 static struct mbuf ** 3500 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3501 { 3502 int next, size; 3503 struct mbuf **items; 3504 3505 size = r->size; 3506 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3507 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3508 3509 prefetch(items[(cidx + offset) & (size-1)]); 3510 if (remaining > 1) { 3511 prefetch2cachelines(&items[next]); 3512 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3513 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3514 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3515 } 3516 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3517 } 3518 3519 static void 3520 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3521 { 3522 3523 ifmp_ring_check_drainage(txq->ift_br, budget); 3524 } 3525 3526 static uint32_t 3527 iflib_txq_can_drain(struct ifmp_ring *r) 3528 { 3529 iflib_txq_t txq = r->cookie; 3530 if_ctx_t ctx = txq->ift_ctx; 3531 3532 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3533 return (1); 3534 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3535 BUS_DMASYNC_POSTREAD); 3536 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3537 false)); 3538 } 3539 3540 static uint32_t 3541 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3542 { 3543 iflib_txq_t txq = r->cookie; 3544 if_ctx_t ctx = txq->ift_ctx; 3545 struct ifnet *ifp = ctx->ifc_ifp; 3546 struct mbuf **mp, *m; 3547 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3548 int reclaimed, err, in_use_prev, desc_used; 3549 bool do_prefetch, ring, rang; 3550 3551 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3552 !LINK_ACTIVE(ctx))) { 3553 DBG_COUNTER_INC(txq_drain_notready); 3554 return (0); 3555 } 3556 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3557 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3558 avail = IDXDIFF(pidx, cidx, r->size); 3559 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3560 DBG_COUNTER_INC(txq_drain_flushing); 3561 for (i = 0; i < avail; i++) { 3562 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3563 m_free(r->items[(cidx + i) & (r->size-1)]); 3564 r->items[(cidx + i) & (r->size-1)] = NULL; 3565 } 3566 return (avail); 3567 } 3568 3569 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3570 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3571 CALLOUT_LOCK(txq); 3572 callout_stop(&txq->ift_timer); 3573 CALLOUT_UNLOCK(txq); 3574 DBG_COUNTER_INC(txq_drain_oactive); 3575 return (0); 3576 } 3577 if (reclaimed) 3578 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3579 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3580 count = MIN(avail, TX_BATCH_SIZE); 3581 #ifdef INVARIANTS 3582 if (iflib_verbose_debug) 3583 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3584 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3585 #endif 3586 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3587 avail = TXQ_AVAIL(txq); 3588 err = 0; 3589 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3590 int rem = do_prefetch ? count - i : 0; 3591 3592 mp = _ring_peek_one(r, cidx, i, rem); 3593 MPASS(mp != NULL && *mp != NULL); 3594 if (__predict_false(*mp == (struct mbuf *)txq)) { 3595 consumed++; 3596 reclaimed++; 3597 continue; 3598 } 3599 in_use_prev = txq->ift_in_use; 3600 err = iflib_encap(txq, mp); 3601 if (__predict_false(err)) { 3602 /* no room - bail out */ 3603 if (err == ENOBUFS) 3604 break; 3605 consumed++; 3606 /* we can't send this packet - skip it */ 3607 continue; 3608 } 3609 consumed++; 3610 pkt_sent++; 3611 m = *mp; 3612 DBG_COUNTER_INC(tx_sent); 3613 bytes_sent += m->m_pkthdr.len; 3614 mcast_sent += !!(m->m_flags & M_MCAST); 3615 avail = TXQ_AVAIL(txq); 3616 3617 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3618 desc_used += (txq->ift_in_use - in_use_prev); 3619 ETHER_BPF_MTAP(ifp, m); 3620 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3621 break; 3622 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3623 } 3624 3625 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3626 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3627 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3628 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3629 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3630 if (mcast_sent) 3631 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3632 #ifdef INVARIANTS 3633 if (iflib_verbose_debug) 3634 printf("consumed=%d\n", consumed); 3635 #endif 3636 return (consumed); 3637 } 3638 3639 static uint32_t 3640 iflib_txq_drain_always(struct ifmp_ring *r) 3641 { 3642 return (1); 3643 } 3644 3645 static uint32_t 3646 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3647 { 3648 int i, avail; 3649 struct mbuf **mp; 3650 iflib_txq_t txq; 3651 3652 txq = r->cookie; 3653 3654 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3655 CALLOUT_LOCK(txq); 3656 callout_stop(&txq->ift_timer); 3657 CALLOUT_UNLOCK(txq); 3658 3659 avail = IDXDIFF(pidx, cidx, r->size); 3660 for (i = 0; i < avail; i++) { 3661 mp = _ring_peek_one(r, cidx, i, avail - i); 3662 if (__predict_false(*mp == (struct mbuf *)txq)) 3663 continue; 3664 m_freem(*mp); 3665 DBG_COUNTER_INC(tx_frees); 3666 } 3667 MPASS(ifmp_ring_is_stalled(r) == 0); 3668 return (avail); 3669 } 3670 3671 static void 3672 iflib_ifmp_purge(iflib_txq_t txq) 3673 { 3674 struct ifmp_ring *r; 3675 3676 r = txq->ift_br; 3677 r->drain = iflib_txq_drain_free; 3678 r->can_drain = iflib_txq_drain_always; 3679 3680 ifmp_ring_check_drainage(r, r->size); 3681 3682 r->drain = iflib_txq_drain; 3683 r->can_drain = iflib_txq_can_drain; 3684 } 3685 3686 static void 3687 _task_fn_tx(void *context) 3688 { 3689 iflib_txq_t txq = context; 3690 if_ctx_t ctx = txq->ift_ctx; 3691 #if defined(ALTQ) || defined(DEV_NETMAP) 3692 if_t ifp = ctx->ifc_ifp; 3693 #endif 3694 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3695 3696 #ifdef IFLIB_DIAGNOSTICS 3697 txq->ift_cpu_exec_count[curcpu]++; 3698 #endif 3699 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3700 return; 3701 #ifdef DEV_NETMAP 3702 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3703 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3704 BUS_DMASYNC_POSTREAD); 3705 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3706 netmap_tx_irq(ifp, txq->ift_id); 3707 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3708 return; 3709 } 3710 #endif 3711 #ifdef ALTQ 3712 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3713 iflib_altq_if_start(ifp); 3714 #endif 3715 if (txq->ift_db_pending) 3716 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3717 else if (!abdicate) 3718 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3719 /* 3720 * When abdicating, we always need to check drainage, not just when we don't enqueue 3721 */ 3722 if (abdicate) 3723 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3724 if (ctx->ifc_flags & IFC_LEGACY) 3725 IFDI_INTR_ENABLE(ctx); 3726 else { 3727 #ifdef INVARIANTS 3728 int rc = 3729 #endif 3730 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3731 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3732 } 3733 } 3734 3735 static void 3736 _task_fn_rx(void *context) 3737 { 3738 iflib_rxq_t rxq = context; 3739 if_ctx_t ctx = rxq->ifr_ctx; 3740 bool more; 3741 uint16_t budget; 3742 3743 #ifdef IFLIB_DIAGNOSTICS 3744 rxq->ifr_cpu_exec_count[curcpu]++; 3745 #endif 3746 DBG_COUNTER_INC(task_fn_rxs); 3747 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3748 return; 3749 more = true; 3750 #ifdef DEV_NETMAP 3751 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3752 u_int work = 0; 3753 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3754 more = false; 3755 } 3756 } 3757 #endif 3758 budget = ctx->ifc_sysctl_rx_budget; 3759 if (budget == 0) 3760 budget = 16; /* XXX */ 3761 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3762 if (ctx->ifc_flags & IFC_LEGACY) 3763 IFDI_INTR_ENABLE(ctx); 3764 else { 3765 #ifdef INVARIANTS 3766 int rc = 3767 #endif 3768 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3769 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3770 DBG_COUNTER_INC(rx_intr_enables); 3771 } 3772 } 3773 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3774 return; 3775 if (more) 3776 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3777 } 3778 3779 static void 3780 _task_fn_admin(void *context) 3781 { 3782 if_ctx_t ctx = context; 3783 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3784 iflib_txq_t txq; 3785 int i; 3786 bool oactive, running, do_reset, do_watchdog, in_detach; 3787 uint32_t reset_on = hz / 2; 3788 3789 STATE_LOCK(ctx); 3790 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3791 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3792 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3793 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3794 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3795 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3796 STATE_UNLOCK(ctx); 3797 3798 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3799 return; 3800 if (in_detach) 3801 return; 3802 3803 CTX_LOCK(ctx); 3804 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3805 CALLOUT_LOCK(txq); 3806 callout_stop(&txq->ift_timer); 3807 CALLOUT_UNLOCK(txq); 3808 } 3809 if (do_watchdog) { 3810 ctx->ifc_watchdog_events++; 3811 IFDI_WATCHDOG_RESET(ctx); 3812 } 3813 IFDI_UPDATE_ADMIN_STATUS(ctx); 3814 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3815 #ifdef DEV_NETMAP 3816 reset_on = hz / 2; 3817 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3818 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3819 #endif 3820 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3821 } 3822 IFDI_LINK_INTR_ENABLE(ctx); 3823 if (do_reset) 3824 iflib_if_init_locked(ctx); 3825 CTX_UNLOCK(ctx); 3826 3827 if (LINK_ACTIVE(ctx) == 0) 3828 return; 3829 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3830 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3831 } 3832 3833 3834 static void 3835 _task_fn_iov(void *context) 3836 { 3837 if_ctx_t ctx = context; 3838 3839 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3840 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3841 return; 3842 3843 CTX_LOCK(ctx); 3844 IFDI_VFLR_HANDLE(ctx); 3845 CTX_UNLOCK(ctx); 3846 } 3847 3848 static int 3849 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3850 { 3851 int err; 3852 if_int_delay_info_t info; 3853 if_ctx_t ctx; 3854 3855 info = (if_int_delay_info_t)arg1; 3856 ctx = info->iidi_ctx; 3857 info->iidi_req = req; 3858 info->iidi_oidp = oidp; 3859 CTX_LOCK(ctx); 3860 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3861 CTX_UNLOCK(ctx); 3862 return (err); 3863 } 3864 3865 /********************************************************************* 3866 * 3867 * IFNET FUNCTIONS 3868 * 3869 **********************************************************************/ 3870 3871 static void 3872 iflib_if_init_locked(if_ctx_t ctx) 3873 { 3874 iflib_stop(ctx); 3875 iflib_init_locked(ctx); 3876 } 3877 3878 3879 static void 3880 iflib_if_init(void *arg) 3881 { 3882 if_ctx_t ctx = arg; 3883 3884 CTX_LOCK(ctx); 3885 iflib_if_init_locked(ctx); 3886 CTX_UNLOCK(ctx); 3887 } 3888 3889 static int 3890 iflib_if_transmit(if_t ifp, struct mbuf *m) 3891 { 3892 if_ctx_t ctx = if_getsoftc(ifp); 3893 3894 iflib_txq_t txq; 3895 int err, qidx; 3896 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3897 3898 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3899 DBG_COUNTER_INC(tx_frees); 3900 m_freem(m); 3901 return (ENOBUFS); 3902 } 3903 3904 MPASS(m->m_nextpkt == NULL); 3905 /* ALTQ-enabled interfaces always use queue 0. */ 3906 qidx = 0; 3907 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3908 qidx = QIDX(ctx, m); 3909 /* 3910 * XXX calculate buf_ring based on flowid (divvy up bits?) 3911 */ 3912 txq = &ctx->ifc_txqs[qidx]; 3913 3914 #ifdef DRIVER_BACKPRESSURE 3915 if (txq->ift_closed) { 3916 while (m != NULL) { 3917 next = m->m_nextpkt; 3918 m->m_nextpkt = NULL; 3919 m_freem(m); 3920 DBG_COUNTER_INC(tx_frees); 3921 m = next; 3922 } 3923 return (ENOBUFS); 3924 } 3925 #endif 3926 #ifdef notyet 3927 qidx = count = 0; 3928 mp = marr; 3929 next = m; 3930 do { 3931 count++; 3932 next = next->m_nextpkt; 3933 } while (next != NULL); 3934 3935 if (count > nitems(marr)) 3936 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3937 /* XXX check nextpkt */ 3938 m_freem(m); 3939 /* XXX simplify for now */ 3940 DBG_COUNTER_INC(tx_frees); 3941 return (ENOBUFS); 3942 } 3943 for (next = m, i = 0; next != NULL; i++) { 3944 mp[i] = next; 3945 next = next->m_nextpkt; 3946 mp[i]->m_nextpkt = NULL; 3947 } 3948 #endif 3949 DBG_COUNTER_INC(tx_seen); 3950 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3951 3952 if (abdicate) 3953 GROUPTASK_ENQUEUE(&txq->ift_task); 3954 if (err) { 3955 if (!abdicate) 3956 GROUPTASK_ENQUEUE(&txq->ift_task); 3957 /* support forthcoming later */ 3958 #ifdef DRIVER_BACKPRESSURE 3959 txq->ift_closed = TRUE; 3960 #endif 3961 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3962 m_freem(m); 3963 DBG_COUNTER_INC(tx_frees); 3964 } 3965 3966 return (err); 3967 } 3968 3969 #ifdef ALTQ 3970 /* 3971 * The overall approach to integrating iflib with ALTQ is to continue to use 3972 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 3973 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 3974 * is redundant/unnecessary, but doing so minimizes the amount of 3975 * ALTQ-specific code required in iflib. It is assumed that the overhead of 3976 * redundantly queueing to an intermediate mp_ring is swamped by the 3977 * performance limitations inherent in using ALTQ. 3978 * 3979 * When ALTQ support is compiled in, all iflib drivers will use a transmit 3980 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 3981 * given interface. If ALTQ is enabled for an interface, then all 3982 * transmitted packets for that interface will be submitted to the ALTQ 3983 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 3984 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 3985 * update stats that the iflib machinery handles, and which is sensitve to 3986 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 3987 * will be installed as the start routine for use by ALTQ facilities that 3988 * need to trigger queue drains on a scheduled basis. 3989 * 3990 */ 3991 static void 3992 iflib_altq_if_start(if_t ifp) 3993 { 3994 struct ifaltq *ifq = &ifp->if_snd; 3995 struct mbuf *m; 3996 3997 IFQ_LOCK(ifq); 3998 IFQ_DEQUEUE_NOLOCK(ifq, m); 3999 while (m != NULL) { 4000 iflib_if_transmit(ifp, m); 4001 IFQ_DEQUEUE_NOLOCK(ifq, m); 4002 } 4003 IFQ_UNLOCK(ifq); 4004 } 4005 4006 static int 4007 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4008 { 4009 int err; 4010 4011 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4012 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4013 if (err == 0) 4014 iflib_altq_if_start(ifp); 4015 } else 4016 err = iflib_if_transmit(ifp, m); 4017 4018 return (err); 4019 } 4020 #endif /* ALTQ */ 4021 4022 static void 4023 iflib_if_qflush(if_t ifp) 4024 { 4025 if_ctx_t ctx = if_getsoftc(ifp); 4026 iflib_txq_t txq = ctx->ifc_txqs; 4027 int i; 4028 4029 STATE_LOCK(ctx); 4030 ctx->ifc_flags |= IFC_QFLUSH; 4031 STATE_UNLOCK(ctx); 4032 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4033 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4034 iflib_txq_check_drain(txq, 0); 4035 STATE_LOCK(ctx); 4036 ctx->ifc_flags &= ~IFC_QFLUSH; 4037 STATE_UNLOCK(ctx); 4038 4039 /* 4040 * When ALTQ is enabled, this will also take care of purging the 4041 * ALTQ queue(s). 4042 */ 4043 if_qflush(ifp); 4044 } 4045 4046 4047 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4048 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4049 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4050 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM) 4051 4052 static int 4053 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4054 { 4055 if_ctx_t ctx = if_getsoftc(ifp); 4056 struct ifreq *ifr = (struct ifreq *)data; 4057 #if defined(INET) || defined(INET6) 4058 struct ifaddr *ifa = (struct ifaddr *)data; 4059 #endif 4060 bool avoid_reset = FALSE; 4061 int err = 0, reinit = 0, bits; 4062 4063 switch (command) { 4064 case SIOCSIFADDR: 4065 #ifdef INET 4066 if (ifa->ifa_addr->sa_family == AF_INET) 4067 avoid_reset = TRUE; 4068 #endif 4069 #ifdef INET6 4070 if (ifa->ifa_addr->sa_family == AF_INET6) 4071 avoid_reset = TRUE; 4072 #endif 4073 /* 4074 ** Calling init results in link renegotiation, 4075 ** so we avoid doing it when possible. 4076 */ 4077 if (avoid_reset) { 4078 if_setflagbits(ifp, IFF_UP,0); 4079 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4080 reinit = 1; 4081 #ifdef INET 4082 if (!(if_getflags(ifp) & IFF_NOARP)) 4083 arp_ifinit(ifp, ifa); 4084 #endif 4085 } else 4086 err = ether_ioctl(ifp, command, data); 4087 break; 4088 case SIOCSIFMTU: 4089 CTX_LOCK(ctx); 4090 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4091 CTX_UNLOCK(ctx); 4092 break; 4093 } 4094 bits = if_getdrvflags(ifp); 4095 /* stop the driver and free any clusters before proceeding */ 4096 iflib_stop(ctx); 4097 4098 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4099 STATE_LOCK(ctx); 4100 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4101 ctx->ifc_flags |= IFC_MULTISEG; 4102 else 4103 ctx->ifc_flags &= ~IFC_MULTISEG; 4104 STATE_UNLOCK(ctx); 4105 err = if_setmtu(ifp, ifr->ifr_mtu); 4106 } 4107 iflib_init_locked(ctx); 4108 STATE_LOCK(ctx); 4109 if_setdrvflags(ifp, bits); 4110 STATE_UNLOCK(ctx); 4111 CTX_UNLOCK(ctx); 4112 break; 4113 case SIOCSIFFLAGS: 4114 CTX_LOCK(ctx); 4115 if (if_getflags(ifp) & IFF_UP) { 4116 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4117 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4118 (IFF_PROMISC | IFF_ALLMULTI)) { 4119 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4120 } 4121 } else 4122 reinit = 1; 4123 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4124 iflib_stop(ctx); 4125 } 4126 ctx->ifc_if_flags = if_getflags(ifp); 4127 CTX_UNLOCK(ctx); 4128 break; 4129 case SIOCADDMULTI: 4130 case SIOCDELMULTI: 4131 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4132 CTX_LOCK(ctx); 4133 IFDI_INTR_DISABLE(ctx); 4134 IFDI_MULTI_SET(ctx); 4135 IFDI_INTR_ENABLE(ctx); 4136 CTX_UNLOCK(ctx); 4137 } 4138 break; 4139 case SIOCSIFMEDIA: 4140 CTX_LOCK(ctx); 4141 IFDI_MEDIA_SET(ctx); 4142 CTX_UNLOCK(ctx); 4143 /* falls thru */ 4144 case SIOCGIFMEDIA: 4145 case SIOCGIFXMEDIA: 4146 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4147 break; 4148 case SIOCGI2C: 4149 { 4150 struct ifi2creq i2c; 4151 4152 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4153 if (err != 0) 4154 break; 4155 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4156 err = EINVAL; 4157 break; 4158 } 4159 if (i2c.len > sizeof(i2c.data)) { 4160 err = EINVAL; 4161 break; 4162 } 4163 4164 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4165 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4166 sizeof(i2c)); 4167 break; 4168 } 4169 case SIOCSIFCAP: 4170 { 4171 int mask, setmask, oldmask; 4172 4173 oldmask = if_getcapenable(ifp); 4174 mask = ifr->ifr_reqcap ^ oldmask; 4175 mask &= ctx->ifc_softc_ctx.isc_capabilities; 4176 setmask = 0; 4177 #ifdef TCP_OFFLOAD 4178 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4179 #endif 4180 setmask |= (mask & IFCAP_FLAGS); 4181 setmask |= (mask & IFCAP_WOL); 4182 4183 /* 4184 * If any RX csum has changed, change all the ones that 4185 * are supported by the driver. 4186 */ 4187 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4188 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4189 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4190 } 4191 4192 /* 4193 * want to ensure that traffic has stopped before we change any of the flags 4194 */ 4195 if (setmask) { 4196 CTX_LOCK(ctx); 4197 bits = if_getdrvflags(ifp); 4198 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4199 iflib_stop(ctx); 4200 STATE_LOCK(ctx); 4201 if_togglecapenable(ifp, setmask); 4202 STATE_UNLOCK(ctx); 4203 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4204 iflib_init_locked(ctx); 4205 STATE_LOCK(ctx); 4206 if_setdrvflags(ifp, bits); 4207 STATE_UNLOCK(ctx); 4208 CTX_UNLOCK(ctx); 4209 } 4210 if_vlancap(ifp); 4211 break; 4212 } 4213 case SIOCGPRIVATE_0: 4214 case SIOCSDRVSPEC: 4215 case SIOCGDRVSPEC: 4216 CTX_LOCK(ctx); 4217 err = IFDI_PRIV_IOCTL(ctx, command, data); 4218 CTX_UNLOCK(ctx); 4219 break; 4220 default: 4221 err = ether_ioctl(ifp, command, data); 4222 break; 4223 } 4224 if (reinit) 4225 iflib_if_init(ctx); 4226 return (err); 4227 } 4228 4229 static uint64_t 4230 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4231 { 4232 if_ctx_t ctx = if_getsoftc(ifp); 4233 4234 return (IFDI_GET_COUNTER(ctx, cnt)); 4235 } 4236 4237 /********************************************************************* 4238 * 4239 * OTHER FUNCTIONS EXPORTED TO THE STACK 4240 * 4241 **********************************************************************/ 4242 4243 static void 4244 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4245 { 4246 if_ctx_t ctx = if_getsoftc(ifp); 4247 4248 if ((void *)ctx != arg) 4249 return; 4250 4251 if ((vtag == 0) || (vtag > 4095)) 4252 return; 4253 4254 CTX_LOCK(ctx); 4255 IFDI_VLAN_REGISTER(ctx, vtag); 4256 /* Re-init to load the changes */ 4257 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4258 iflib_if_init_locked(ctx); 4259 CTX_UNLOCK(ctx); 4260 } 4261 4262 static void 4263 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4264 { 4265 if_ctx_t ctx = if_getsoftc(ifp); 4266 4267 if ((void *)ctx != arg) 4268 return; 4269 4270 if ((vtag == 0) || (vtag > 4095)) 4271 return; 4272 4273 CTX_LOCK(ctx); 4274 IFDI_VLAN_UNREGISTER(ctx, vtag); 4275 /* Re-init to load the changes */ 4276 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4277 iflib_if_init_locked(ctx); 4278 CTX_UNLOCK(ctx); 4279 } 4280 4281 static void 4282 iflib_led_func(void *arg, int onoff) 4283 { 4284 if_ctx_t ctx = arg; 4285 4286 CTX_LOCK(ctx); 4287 IFDI_LED_FUNC(ctx, onoff); 4288 CTX_UNLOCK(ctx); 4289 } 4290 4291 /********************************************************************* 4292 * 4293 * BUS FUNCTION DEFINITIONS 4294 * 4295 **********************************************************************/ 4296 4297 int 4298 iflib_device_probe(device_t dev) 4299 { 4300 pci_vendor_info_t *ent; 4301 4302 uint16_t pci_vendor_id, pci_device_id; 4303 uint16_t pci_subvendor_id, pci_subdevice_id; 4304 uint16_t pci_rev_id; 4305 if_shared_ctx_t sctx; 4306 4307 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4308 return (ENOTSUP); 4309 4310 pci_vendor_id = pci_get_vendor(dev); 4311 pci_device_id = pci_get_device(dev); 4312 pci_subvendor_id = pci_get_subvendor(dev); 4313 pci_subdevice_id = pci_get_subdevice(dev); 4314 pci_rev_id = pci_get_revid(dev); 4315 if (sctx->isc_parse_devinfo != NULL) 4316 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4317 4318 ent = sctx->isc_vendor_info; 4319 while (ent->pvi_vendor_id != 0) { 4320 if (pci_vendor_id != ent->pvi_vendor_id) { 4321 ent++; 4322 continue; 4323 } 4324 if ((pci_device_id == ent->pvi_device_id) && 4325 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4326 (ent->pvi_subvendor_id == 0)) && 4327 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4328 (ent->pvi_subdevice_id == 0)) && 4329 ((pci_rev_id == ent->pvi_rev_id) || 4330 (ent->pvi_rev_id == 0))) { 4331 4332 device_set_desc_copy(dev, ent->pvi_name); 4333 /* this needs to be changed to zero if the bus probing code 4334 * ever stops re-probing on best match because the sctx 4335 * may have its values over written by register calls 4336 * in subsequent probes 4337 */ 4338 return (BUS_PROBE_DEFAULT); 4339 } 4340 ent++; 4341 } 4342 return (ENXIO); 4343 } 4344 4345 static void 4346 iflib_reset_qvalues(if_ctx_t ctx) 4347 { 4348 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4349 if_shared_ctx_t sctx = ctx->ifc_sctx; 4350 device_t dev = ctx->ifc_dev; 4351 int i; 4352 4353 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4354 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4355 /* 4356 * XXX sanity check that ntxd & nrxd are a power of 2 4357 */ 4358 if (ctx->ifc_sysctl_ntxqs != 0) 4359 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4360 if (ctx->ifc_sysctl_nrxqs != 0) 4361 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4362 4363 for (i = 0; i < sctx->isc_ntxqs; i++) { 4364 if (ctx->ifc_sysctl_ntxds[i] != 0) 4365 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4366 else 4367 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4368 } 4369 4370 for (i = 0; i < sctx->isc_nrxqs; i++) { 4371 if (ctx->ifc_sysctl_nrxds[i] != 0) 4372 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4373 else 4374 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4375 } 4376 4377 for (i = 0; i < sctx->isc_nrxqs; i++) { 4378 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4379 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4380 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4381 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4382 } 4383 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4384 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4385 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4386 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4387 } 4388 } 4389 4390 for (i = 0; i < sctx->isc_ntxqs; i++) { 4391 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4392 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4393 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4394 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4395 } 4396 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4397 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4398 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4399 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4400 } 4401 } 4402 } 4403 4404 int 4405 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4406 { 4407 int err, rid, msix; 4408 if_ctx_t ctx; 4409 if_t ifp; 4410 if_softc_ctx_t scctx; 4411 int i; 4412 uint16_t main_txq; 4413 uint16_t main_rxq; 4414 4415 4416 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4417 4418 if (sc == NULL) { 4419 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4420 device_set_softc(dev, ctx); 4421 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4422 } 4423 4424 ctx->ifc_sctx = sctx; 4425 ctx->ifc_dev = dev; 4426 ctx->ifc_softc = sc; 4427 4428 if ((err = iflib_register(ctx)) != 0) { 4429 device_printf(dev, "iflib_register failed %d\n", err); 4430 goto fail_ctx_free; 4431 } 4432 iflib_add_device_sysctl_pre(ctx); 4433 4434 scctx = &ctx->ifc_softc_ctx; 4435 ifp = ctx->ifc_ifp; 4436 4437 iflib_reset_qvalues(ctx); 4438 CTX_LOCK(ctx); 4439 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4440 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4441 goto fail_unlock; 4442 } 4443 _iflib_pre_assert(scctx); 4444 ctx->ifc_txrx = *scctx->isc_txrx; 4445 4446 #ifdef INVARIANTS 4447 MPASS(scctx->isc_capabilities); 4448 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4449 MPASS(scctx->isc_tx_csum_flags); 4450 #endif 4451 4452 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4453 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4454 4455 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4456 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4457 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4458 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4459 4460 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4461 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4462 4463 /* XXX change for per-queue sizes */ 4464 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n", 4465 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4466 for (i = 0; i < sctx->isc_nrxqs; i++) { 4467 if (!powerof2(scctx->isc_nrxd[i])) { 4468 /* round down instead? */ 4469 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4470 err = EINVAL; 4471 goto fail_iflib_detach; 4472 } 4473 } 4474 for (i = 0; i < sctx->isc_ntxqs; i++) { 4475 if (!powerof2(scctx->isc_ntxd[i])) { 4476 device_printf(dev, 4477 "# tx descriptors must be a power of 2"); 4478 err = EINVAL; 4479 goto fail_iflib_detach; 4480 } 4481 } 4482 4483 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4484 MAX_SINGLE_PACKET_FRACTION) 4485 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4486 MAX_SINGLE_PACKET_FRACTION); 4487 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4488 MAX_SINGLE_PACKET_FRACTION) 4489 scctx->isc_tx_tso_segments_max = max(1, 4490 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4491 4492 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4493 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4494 /* 4495 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4496 * but some MACs do. 4497 */ 4498 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4499 IP_MAXPACKET)); 4500 /* 4501 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4502 * into account. In the worst case, each of these calls will 4503 * add another mbuf and, thus, the requirement for another DMA 4504 * segment. So for best performance, it doesn't make sense to 4505 * advertize a maximum of TSO segments that typically will 4506 * require defragmentation in iflib_encap(). 4507 */ 4508 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4509 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4510 } 4511 if (scctx->isc_rss_table_size == 0) 4512 scctx->isc_rss_table_size = 64; 4513 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4514 4515 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4516 /* XXX format name */ 4517 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4518 NULL, NULL, "admin"); 4519 4520 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4521 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4522 device_printf(dev, "Unable to fetch CPU list\n"); 4523 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4524 } 4525 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4526 4527 /* 4528 ** Now set up MSI or MSI-X, should return us the number of supported 4529 ** vectors (will be 1 for a legacy interrupt and MSI). 4530 */ 4531 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4532 msix = scctx->isc_vectors; 4533 } else if (scctx->isc_msix_bar != 0) 4534 /* 4535 * The simple fact that isc_msix_bar is not 0 does not mean we 4536 * we have a good value there that is known to work. 4537 */ 4538 msix = iflib_msix_init(ctx); 4539 else { 4540 scctx->isc_vectors = 1; 4541 scctx->isc_ntxqsets = 1; 4542 scctx->isc_nrxqsets = 1; 4543 scctx->isc_intr = IFLIB_INTR_LEGACY; 4544 msix = 0; 4545 } 4546 /* Get memory for the station queues */ 4547 if ((err = iflib_queues_alloc(ctx))) { 4548 device_printf(dev, "Unable to allocate queue memory\n"); 4549 goto fail_intr_free; 4550 } 4551 4552 if ((err = iflib_qset_structures_setup(ctx))) 4553 goto fail_queues; 4554 4555 /* 4556 * Group taskqueues aren't properly set up until SMP is started, 4557 * so we disable interrupts until we can handle them post 4558 * SI_SUB_SMP. 4559 * 4560 * XXX: disabling interrupts doesn't actually work, at least for 4561 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4562 * we do null handling and depend on this not causing too large an 4563 * interrupt storm. 4564 */ 4565 IFDI_INTR_DISABLE(ctx); 4566 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4567 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4568 goto fail_queues; 4569 } 4570 if (msix <= 1) { 4571 rid = 0; 4572 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4573 MPASS(msix == 1); 4574 rid = 1; 4575 } 4576 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4577 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4578 goto fail_queues; 4579 } 4580 } 4581 4582 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4583 4584 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4585 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4586 goto fail_detach; 4587 } 4588 4589 /* 4590 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4591 * This must appear after the call to ether_ifattach() because 4592 * ether_ifattach() sets if_hdrlen to the default value. 4593 */ 4594 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4595 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4596 4597 if ((err = iflib_netmap_attach(ctx))) { 4598 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4599 goto fail_detach; 4600 } 4601 *ctxp = ctx; 4602 4603 NETDUMP_SET(ctx->ifc_ifp, iflib); 4604 4605 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4606 iflib_add_device_sysctl_post(ctx); 4607 ctx->ifc_flags |= IFC_INIT_DONE; 4608 CTX_UNLOCK(ctx); 4609 return (0); 4610 4611 fail_detach: 4612 ether_ifdetach(ctx->ifc_ifp); 4613 fail_intr_free: 4614 iflib_free_intr_mem(ctx); 4615 fail_queues: 4616 iflib_tx_structures_free(ctx); 4617 iflib_rx_structures_free(ctx); 4618 fail_iflib_detach: 4619 IFDI_DETACH(ctx); 4620 fail_unlock: 4621 CTX_UNLOCK(ctx); 4622 fail_ctx_free: 4623 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4624 free(ctx->ifc_softc, M_IFLIB); 4625 free(ctx, M_IFLIB); 4626 return (err); 4627 } 4628 4629 int 4630 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4631 struct iflib_cloneattach_ctx *clctx) 4632 { 4633 int err; 4634 if_ctx_t ctx; 4635 if_t ifp; 4636 if_softc_ctx_t scctx; 4637 int i; 4638 void *sc; 4639 uint16_t main_txq; 4640 uint16_t main_rxq; 4641 4642 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4643 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4644 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4645 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4646 ctx->ifc_flags |= IFC_PSEUDO; 4647 4648 ctx->ifc_sctx = sctx; 4649 ctx->ifc_softc = sc; 4650 ctx->ifc_dev = dev; 4651 4652 if ((err = iflib_register(ctx)) != 0) { 4653 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4654 goto fail_ctx_free; 4655 } 4656 iflib_add_device_sysctl_pre(ctx); 4657 4658 scctx = &ctx->ifc_softc_ctx; 4659 ifp = ctx->ifc_ifp; 4660 4661 /* 4662 * XXX sanity check that ntxd & nrxd are a power of 2 4663 */ 4664 iflib_reset_qvalues(ctx); 4665 4666 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4667 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4668 goto fail_ctx_free; 4669 } 4670 if (sctx->isc_flags & IFLIB_GEN_MAC) 4671 iflib_gen_mac(ctx); 4672 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4673 clctx->cc_params)) != 0) { 4674 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4675 goto fail_ctx_free; 4676 } 4677 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4678 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4679 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4680 4681 #ifdef INVARIANTS 4682 MPASS(scctx->isc_capabilities); 4683 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4684 MPASS(scctx->isc_tx_csum_flags); 4685 #endif 4686 4687 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4688 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4689 4690 ifp->if_flags |= IFF_NOGROUP; 4691 if (sctx->isc_flags & IFLIB_PSEUDO) { 4692 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4693 4694 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4695 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4696 goto fail_detach; 4697 } 4698 *ctxp = ctx; 4699 4700 /* 4701 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4702 * This must appear after the call to ether_ifattach() because 4703 * ether_ifattach() sets if_hdrlen to the default value. 4704 */ 4705 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4706 if_setifheaderlen(ifp, 4707 sizeof(struct ether_vlan_header)); 4708 4709 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4710 iflib_add_device_sysctl_post(ctx); 4711 ctx->ifc_flags |= IFC_INIT_DONE; 4712 return (0); 4713 } 4714 _iflib_pre_assert(scctx); 4715 ctx->ifc_txrx = *scctx->isc_txrx; 4716 4717 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4718 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4719 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4720 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4721 4722 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4723 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4724 4725 /* XXX change for per-queue sizes */ 4726 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n", 4727 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4728 for (i = 0; i < sctx->isc_nrxqs; i++) { 4729 if (!powerof2(scctx->isc_nrxd[i])) { 4730 /* round down instead? */ 4731 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4732 err = EINVAL; 4733 goto fail_iflib_detach; 4734 } 4735 } 4736 for (i = 0; i < sctx->isc_ntxqs; i++) { 4737 if (!powerof2(scctx->isc_ntxd[i])) { 4738 device_printf(dev, 4739 "# tx descriptors must be a power of 2"); 4740 err = EINVAL; 4741 goto fail_iflib_detach; 4742 } 4743 } 4744 4745 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4746 MAX_SINGLE_PACKET_FRACTION) 4747 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4748 MAX_SINGLE_PACKET_FRACTION); 4749 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4750 MAX_SINGLE_PACKET_FRACTION) 4751 scctx->isc_tx_tso_segments_max = max(1, 4752 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4753 4754 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4755 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4756 /* 4757 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4758 * but some MACs do. 4759 */ 4760 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4761 IP_MAXPACKET)); 4762 /* 4763 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4764 * into account. In the worst case, each of these calls will 4765 * add another mbuf and, thus, the requirement for another DMA 4766 * segment. So for best performance, it doesn't make sense to 4767 * advertize a maximum of TSO segments that typically will 4768 * require defragmentation in iflib_encap(). 4769 */ 4770 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4771 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4772 } 4773 if (scctx->isc_rss_table_size == 0) 4774 scctx->isc_rss_table_size = 64; 4775 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4776 4777 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4778 /* XXX format name */ 4779 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4780 NULL, NULL, "admin"); 4781 4782 /* XXX --- can support > 1 -- but keep it simple for now */ 4783 scctx->isc_intr = IFLIB_INTR_LEGACY; 4784 4785 /* Get memory for the station queues */ 4786 if ((err = iflib_queues_alloc(ctx))) { 4787 device_printf(dev, "Unable to allocate queue memory\n"); 4788 goto fail_iflib_detach; 4789 } 4790 4791 if ((err = iflib_qset_structures_setup(ctx))) { 4792 device_printf(dev, "qset structure setup failed %d\n", err); 4793 goto fail_queues; 4794 } 4795 4796 /* 4797 * XXX What if anything do we want to do about interrupts? 4798 */ 4799 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4800 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4801 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4802 goto fail_detach; 4803 } 4804 4805 /* 4806 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4807 * This must appear after the call to ether_ifattach() because 4808 * ether_ifattach() sets if_hdrlen to the default value. 4809 */ 4810 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4811 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4812 4813 /* XXX handle more than one queue */ 4814 for (i = 0; i < scctx->isc_nrxqsets; i++) 4815 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4816 4817 *ctxp = ctx; 4818 4819 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4820 iflib_add_device_sysctl_post(ctx); 4821 ctx->ifc_flags |= IFC_INIT_DONE; 4822 return (0); 4823 fail_detach: 4824 ether_ifdetach(ctx->ifc_ifp); 4825 fail_queues: 4826 iflib_tx_structures_free(ctx); 4827 iflib_rx_structures_free(ctx); 4828 fail_iflib_detach: 4829 IFDI_DETACH(ctx); 4830 fail_ctx_free: 4831 free(ctx->ifc_softc, M_IFLIB); 4832 free(ctx, M_IFLIB); 4833 return (err); 4834 } 4835 4836 int 4837 iflib_pseudo_deregister(if_ctx_t ctx) 4838 { 4839 if_t ifp = ctx->ifc_ifp; 4840 iflib_txq_t txq; 4841 iflib_rxq_t rxq; 4842 int i, j; 4843 struct taskqgroup *tqg; 4844 iflib_fl_t fl; 4845 4846 /* Unregister VLAN events */ 4847 if (ctx->ifc_vlan_attach_event != NULL) 4848 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4849 if (ctx->ifc_vlan_detach_event != NULL) 4850 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4851 4852 ether_ifdetach(ifp); 4853 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4854 CTX_LOCK_DESTROY(ctx); 4855 /* XXX drain any dependent tasks */ 4856 tqg = qgroup_if_io_tqg; 4857 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4858 callout_drain(&txq->ift_timer); 4859 if (txq->ift_task.gt_uniq != NULL) 4860 taskqgroup_detach(tqg, &txq->ift_task); 4861 } 4862 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4863 if (rxq->ifr_task.gt_uniq != NULL) 4864 taskqgroup_detach(tqg, &rxq->ifr_task); 4865 4866 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4867 free(fl->ifl_rx_bitmap, M_IFLIB); 4868 } 4869 tqg = qgroup_if_config_tqg; 4870 if (ctx->ifc_admin_task.gt_uniq != NULL) 4871 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4872 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4873 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4874 4875 if_free(ifp); 4876 4877 iflib_tx_structures_free(ctx); 4878 iflib_rx_structures_free(ctx); 4879 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4880 free(ctx->ifc_softc, M_IFLIB); 4881 free(ctx, M_IFLIB); 4882 return (0); 4883 } 4884 4885 int 4886 iflib_device_attach(device_t dev) 4887 { 4888 if_ctx_t ctx; 4889 if_shared_ctx_t sctx; 4890 4891 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4892 return (ENOTSUP); 4893 4894 pci_enable_busmaster(dev); 4895 4896 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4897 } 4898 4899 int 4900 iflib_device_deregister(if_ctx_t ctx) 4901 { 4902 if_t ifp = ctx->ifc_ifp; 4903 iflib_txq_t txq; 4904 iflib_rxq_t rxq; 4905 device_t dev = ctx->ifc_dev; 4906 int i, j; 4907 struct taskqgroup *tqg; 4908 iflib_fl_t fl; 4909 4910 /* Make sure VLANS are not using driver */ 4911 if (if_vlantrunkinuse(ifp)) { 4912 device_printf(dev, "Vlan in use, detach first\n"); 4913 return (EBUSY); 4914 } 4915 #ifdef PCI_IOV 4916 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 4917 device_printf(dev, "SR-IOV in use; detach first.\n"); 4918 return (EBUSY); 4919 } 4920 #endif 4921 4922 STATE_LOCK(ctx); 4923 ctx->ifc_flags |= IFC_IN_DETACH; 4924 STATE_UNLOCK(ctx); 4925 4926 CTX_LOCK(ctx); 4927 iflib_stop(ctx); 4928 CTX_UNLOCK(ctx); 4929 4930 /* Unregister VLAN events */ 4931 if (ctx->ifc_vlan_attach_event != NULL) 4932 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4933 if (ctx->ifc_vlan_detach_event != NULL) 4934 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4935 4936 iflib_netmap_detach(ifp); 4937 ether_ifdetach(ifp); 4938 if (ctx->ifc_led_dev != NULL) 4939 led_destroy(ctx->ifc_led_dev); 4940 /* XXX drain any dependent tasks */ 4941 tqg = qgroup_if_io_tqg; 4942 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4943 callout_drain(&txq->ift_timer); 4944 if (txq->ift_task.gt_uniq != NULL) 4945 taskqgroup_detach(tqg, &txq->ift_task); 4946 } 4947 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4948 if (rxq->ifr_task.gt_uniq != NULL) 4949 taskqgroup_detach(tqg, &rxq->ifr_task); 4950 4951 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4952 free(fl->ifl_rx_bitmap, M_IFLIB); 4953 } 4954 tqg = qgroup_if_config_tqg; 4955 if (ctx->ifc_admin_task.gt_uniq != NULL) 4956 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4957 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4958 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4959 CTX_LOCK(ctx); 4960 IFDI_DETACH(ctx); 4961 CTX_UNLOCK(ctx); 4962 4963 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4964 CTX_LOCK_DESTROY(ctx); 4965 device_set_softc(ctx->ifc_dev, NULL); 4966 iflib_free_intr_mem(ctx); 4967 4968 bus_generic_detach(dev); 4969 if_free(ifp); 4970 4971 iflib_tx_structures_free(ctx); 4972 iflib_rx_structures_free(ctx); 4973 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4974 free(ctx->ifc_softc, M_IFLIB); 4975 STATE_LOCK_DESTROY(ctx); 4976 free(ctx, M_IFLIB); 4977 return (0); 4978 } 4979 4980 static void 4981 iflib_free_intr_mem(if_ctx_t ctx) 4982 { 4983 4984 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4985 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4986 } 4987 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4988 pci_release_msi(ctx->ifc_dev); 4989 } 4990 if (ctx->ifc_msix_mem != NULL) { 4991 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4992 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 4993 ctx->ifc_msix_mem = NULL; 4994 } 4995 } 4996 4997 int 4998 iflib_device_detach(device_t dev) 4999 { 5000 if_ctx_t ctx = device_get_softc(dev); 5001 5002 return (iflib_device_deregister(ctx)); 5003 } 5004 5005 int 5006 iflib_device_suspend(device_t dev) 5007 { 5008 if_ctx_t ctx = device_get_softc(dev); 5009 5010 CTX_LOCK(ctx); 5011 IFDI_SUSPEND(ctx); 5012 CTX_UNLOCK(ctx); 5013 5014 return bus_generic_suspend(dev); 5015 } 5016 int 5017 iflib_device_shutdown(device_t dev) 5018 { 5019 if_ctx_t ctx = device_get_softc(dev); 5020 5021 CTX_LOCK(ctx); 5022 IFDI_SHUTDOWN(ctx); 5023 CTX_UNLOCK(ctx); 5024 5025 return bus_generic_suspend(dev); 5026 } 5027 5028 5029 int 5030 iflib_device_resume(device_t dev) 5031 { 5032 if_ctx_t ctx = device_get_softc(dev); 5033 iflib_txq_t txq = ctx->ifc_txqs; 5034 5035 CTX_LOCK(ctx); 5036 IFDI_RESUME(ctx); 5037 iflib_if_init_locked(ctx); 5038 CTX_UNLOCK(ctx); 5039 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5040 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5041 5042 return (bus_generic_resume(dev)); 5043 } 5044 5045 int 5046 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5047 { 5048 int error; 5049 if_ctx_t ctx = device_get_softc(dev); 5050 5051 CTX_LOCK(ctx); 5052 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5053 CTX_UNLOCK(ctx); 5054 5055 return (error); 5056 } 5057 5058 void 5059 iflib_device_iov_uninit(device_t dev) 5060 { 5061 if_ctx_t ctx = device_get_softc(dev); 5062 5063 CTX_LOCK(ctx); 5064 IFDI_IOV_UNINIT(ctx); 5065 CTX_UNLOCK(ctx); 5066 } 5067 5068 int 5069 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5070 { 5071 int error; 5072 if_ctx_t ctx = device_get_softc(dev); 5073 5074 CTX_LOCK(ctx); 5075 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5076 CTX_UNLOCK(ctx); 5077 5078 return (error); 5079 } 5080 5081 /********************************************************************* 5082 * 5083 * MODULE FUNCTION DEFINITIONS 5084 * 5085 **********************************************************************/ 5086 5087 /* 5088 * - Start a fast taskqueue thread for each core 5089 * - Start a taskqueue for control operations 5090 */ 5091 static int 5092 iflib_module_init(void) 5093 { 5094 return (0); 5095 } 5096 5097 static int 5098 iflib_module_event_handler(module_t mod, int what, void *arg) 5099 { 5100 int err; 5101 5102 switch (what) { 5103 case MOD_LOAD: 5104 if ((err = iflib_module_init()) != 0) 5105 return (err); 5106 break; 5107 case MOD_UNLOAD: 5108 return (EBUSY); 5109 default: 5110 return (EOPNOTSUPP); 5111 } 5112 5113 return (0); 5114 } 5115 5116 /********************************************************************* 5117 * 5118 * PUBLIC FUNCTION DEFINITIONS 5119 * ordered as in iflib.h 5120 * 5121 **********************************************************************/ 5122 5123 5124 static void 5125 _iflib_assert(if_shared_ctx_t sctx) 5126 { 5127 MPASS(sctx->isc_tx_maxsize); 5128 MPASS(sctx->isc_tx_maxsegsize); 5129 5130 MPASS(sctx->isc_rx_maxsize); 5131 MPASS(sctx->isc_rx_nsegments); 5132 MPASS(sctx->isc_rx_maxsegsize); 5133 5134 MPASS(sctx->isc_nrxd_min[0]); 5135 MPASS(sctx->isc_nrxd_max[0]); 5136 MPASS(sctx->isc_nrxd_default[0]); 5137 MPASS(sctx->isc_ntxd_min[0]); 5138 MPASS(sctx->isc_ntxd_max[0]); 5139 MPASS(sctx->isc_ntxd_default[0]); 5140 } 5141 5142 static void 5143 _iflib_pre_assert(if_softc_ctx_t scctx) 5144 { 5145 5146 MPASS(scctx->isc_txrx->ift_txd_encap); 5147 MPASS(scctx->isc_txrx->ift_txd_flush); 5148 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5149 MPASS(scctx->isc_txrx->ift_rxd_available); 5150 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5151 MPASS(scctx->isc_txrx->ift_rxd_refill); 5152 MPASS(scctx->isc_txrx->ift_rxd_flush); 5153 } 5154 5155 static int 5156 iflib_register(if_ctx_t ctx) 5157 { 5158 if_shared_ctx_t sctx = ctx->ifc_sctx; 5159 driver_t *driver = sctx->isc_driver; 5160 device_t dev = ctx->ifc_dev; 5161 if_t ifp; 5162 5163 _iflib_assert(sctx); 5164 5165 CTX_LOCK_INIT(ctx); 5166 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5167 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5168 if (ifp == NULL) { 5169 device_printf(dev, "can not allocate ifnet structure\n"); 5170 return (ENOMEM); 5171 } 5172 5173 /* 5174 * Initialize our context's device specific methods 5175 */ 5176 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5177 kobj_class_compile((kobj_class_t) driver); 5178 driver->refs++; 5179 5180 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5181 if_setsoftc(ifp, ctx); 5182 if_setdev(ifp, dev); 5183 if_setinitfn(ifp, iflib_if_init); 5184 if_setioctlfn(ifp, iflib_if_ioctl); 5185 #ifdef ALTQ 5186 if_setstartfn(ifp, iflib_altq_if_start); 5187 if_settransmitfn(ifp, iflib_altq_if_transmit); 5188 if_setsendqready(ifp); 5189 #else 5190 if_settransmitfn(ifp, iflib_if_transmit); 5191 #endif 5192 if_setqflushfn(ifp, iflib_if_qflush); 5193 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5194 5195 ctx->ifc_vlan_attach_event = 5196 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5197 EVENTHANDLER_PRI_FIRST); 5198 ctx->ifc_vlan_detach_event = 5199 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5200 EVENTHANDLER_PRI_FIRST); 5201 5202 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5203 iflib_media_change, iflib_media_status); 5204 5205 return (0); 5206 } 5207 5208 5209 static int 5210 iflib_queues_alloc(if_ctx_t ctx) 5211 { 5212 if_shared_ctx_t sctx = ctx->ifc_sctx; 5213 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5214 device_t dev = ctx->ifc_dev; 5215 int nrxqsets = scctx->isc_nrxqsets; 5216 int ntxqsets = scctx->isc_ntxqsets; 5217 iflib_txq_t txq; 5218 iflib_rxq_t rxq; 5219 iflib_fl_t fl = NULL; 5220 int i, j, cpu, err, txconf, rxconf; 5221 iflib_dma_info_t ifdip; 5222 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5223 uint32_t *txqsizes = scctx->isc_txqsizes; 5224 uint8_t nrxqs = sctx->isc_nrxqs; 5225 uint8_t ntxqs = sctx->isc_ntxqs; 5226 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5227 caddr_t *vaddrs; 5228 uint64_t *paddrs; 5229 5230 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5231 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5232 5233 /* Allocate the TX ring struct memory */ 5234 if (!(ctx->ifc_txqs = 5235 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5236 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5237 device_printf(dev, "Unable to allocate TX ring memory\n"); 5238 err = ENOMEM; 5239 goto fail; 5240 } 5241 5242 /* Now allocate the RX */ 5243 if (!(ctx->ifc_rxqs = 5244 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5245 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5246 device_printf(dev, "Unable to allocate RX ring memory\n"); 5247 err = ENOMEM; 5248 goto rx_fail; 5249 } 5250 5251 txq = ctx->ifc_txqs; 5252 rxq = ctx->ifc_rxqs; 5253 5254 /* 5255 * XXX handle allocation failure 5256 */ 5257 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5258 /* Set up some basics */ 5259 5260 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5261 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5262 device_printf(dev, 5263 "Unable to allocate TX DMA info memory\n"); 5264 err = ENOMEM; 5265 goto err_tx_desc; 5266 } 5267 txq->ift_ifdi = ifdip; 5268 for (j = 0; j < ntxqs; j++, ifdip++) { 5269 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5270 device_printf(dev, 5271 "Unable to allocate TX descriptors\n"); 5272 err = ENOMEM; 5273 goto err_tx_desc; 5274 } 5275 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5276 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5277 } 5278 txq->ift_ctx = ctx; 5279 txq->ift_id = i; 5280 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5281 txq->ift_br_offset = 1; 5282 } else { 5283 txq->ift_br_offset = 0; 5284 } 5285 /* XXX fix this */ 5286 txq->ift_timer.c_cpu = cpu; 5287 5288 if (iflib_txsd_alloc(txq)) { 5289 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5290 err = ENOMEM; 5291 goto err_tx_desc; 5292 } 5293 5294 /* Initialize the TX lock */ 5295 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5296 device_get_nameunit(dev), txq->ift_id); 5297 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5298 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5299 5300 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5301 device_get_nameunit(dev), txq->ift_id); 5302 5303 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5304 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5305 if (err) { 5306 /* XXX free any allocated rings */ 5307 device_printf(dev, "Unable to allocate buf_ring\n"); 5308 goto err_tx_desc; 5309 } 5310 } 5311 5312 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5313 /* Set up some basics */ 5314 5315 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5316 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5317 device_printf(dev, 5318 "Unable to allocate RX DMA info memory\n"); 5319 err = ENOMEM; 5320 goto err_tx_desc; 5321 } 5322 5323 rxq->ifr_ifdi = ifdip; 5324 /* XXX this needs to be changed if #rx queues != #tx queues */ 5325 rxq->ifr_ntxqirq = 1; 5326 rxq->ifr_txqid[0] = i; 5327 for (j = 0; j < nrxqs; j++, ifdip++) { 5328 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5329 device_printf(dev, 5330 "Unable to allocate RX descriptors\n"); 5331 err = ENOMEM; 5332 goto err_tx_desc; 5333 } 5334 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5335 } 5336 rxq->ifr_ctx = ctx; 5337 rxq->ifr_id = i; 5338 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5339 rxq->ifr_fl_offset = 1; 5340 } else { 5341 rxq->ifr_fl_offset = 0; 5342 } 5343 rxq->ifr_nfl = nfree_lists; 5344 if (!(fl = 5345 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5346 device_printf(dev, "Unable to allocate free list memory\n"); 5347 err = ENOMEM; 5348 goto err_tx_desc; 5349 } 5350 rxq->ifr_fl = fl; 5351 for (j = 0; j < nfree_lists; j++) { 5352 fl[j].ifl_rxq = rxq; 5353 fl[j].ifl_id = j; 5354 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5355 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5356 } 5357 /* Allocate receive buffers for the ring */ 5358 if (iflib_rxsd_alloc(rxq)) { 5359 device_printf(dev, 5360 "Critical Failure setting up receive buffers\n"); 5361 err = ENOMEM; 5362 goto err_rx_desc; 5363 } 5364 5365 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5366 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5367 M_WAITOK); 5368 } 5369 5370 /* TXQs */ 5371 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5372 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5373 for (i = 0; i < ntxqsets; i++) { 5374 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5375 5376 for (j = 0; j < ntxqs; j++, di++) { 5377 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5378 paddrs[i*ntxqs + j] = di->idi_paddr; 5379 } 5380 } 5381 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5382 device_printf(ctx->ifc_dev, 5383 "Unable to allocate device TX queue\n"); 5384 iflib_tx_structures_free(ctx); 5385 free(vaddrs, M_IFLIB); 5386 free(paddrs, M_IFLIB); 5387 goto err_rx_desc; 5388 } 5389 free(vaddrs, M_IFLIB); 5390 free(paddrs, M_IFLIB); 5391 5392 /* RXQs */ 5393 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5394 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5395 for (i = 0; i < nrxqsets; i++) { 5396 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5397 5398 for (j = 0; j < nrxqs; j++, di++) { 5399 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5400 paddrs[i*nrxqs + j] = di->idi_paddr; 5401 } 5402 } 5403 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5404 device_printf(ctx->ifc_dev, 5405 "Unable to allocate device RX queue\n"); 5406 iflib_tx_structures_free(ctx); 5407 free(vaddrs, M_IFLIB); 5408 free(paddrs, M_IFLIB); 5409 goto err_rx_desc; 5410 } 5411 free(vaddrs, M_IFLIB); 5412 free(paddrs, M_IFLIB); 5413 5414 return (0); 5415 5416 /* XXX handle allocation failure changes */ 5417 err_rx_desc: 5418 err_tx_desc: 5419 rx_fail: 5420 if (ctx->ifc_rxqs != NULL) 5421 free(ctx->ifc_rxqs, M_IFLIB); 5422 ctx->ifc_rxqs = NULL; 5423 if (ctx->ifc_txqs != NULL) 5424 free(ctx->ifc_txqs, M_IFLIB); 5425 ctx->ifc_txqs = NULL; 5426 fail: 5427 return (err); 5428 } 5429 5430 static int 5431 iflib_tx_structures_setup(if_ctx_t ctx) 5432 { 5433 iflib_txq_t txq = ctx->ifc_txqs; 5434 int i; 5435 5436 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5437 iflib_txq_setup(txq); 5438 5439 return (0); 5440 } 5441 5442 static void 5443 iflib_tx_structures_free(if_ctx_t ctx) 5444 { 5445 iflib_txq_t txq = ctx->ifc_txqs; 5446 if_shared_ctx_t sctx = ctx->ifc_sctx; 5447 int i, j; 5448 5449 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5450 iflib_txq_destroy(txq); 5451 for (j = 0; j < sctx->isc_ntxqs; j++) 5452 iflib_dma_free(&txq->ift_ifdi[j]); 5453 } 5454 free(ctx->ifc_txqs, M_IFLIB); 5455 ctx->ifc_txqs = NULL; 5456 IFDI_QUEUES_FREE(ctx); 5457 } 5458 5459 /********************************************************************* 5460 * 5461 * Initialize all receive rings. 5462 * 5463 **********************************************************************/ 5464 static int 5465 iflib_rx_structures_setup(if_ctx_t ctx) 5466 { 5467 iflib_rxq_t rxq = ctx->ifc_rxqs; 5468 int q; 5469 #if defined(INET6) || defined(INET) 5470 int i, err; 5471 #endif 5472 5473 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5474 #if defined(INET6) || defined(INET) 5475 tcp_lro_free(&rxq->ifr_lc); 5476 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5477 TCP_LRO_ENTRIES, min(1024, 5478 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5479 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5480 goto fail; 5481 } 5482 rxq->ifr_lro_enabled = TRUE; 5483 #endif 5484 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5485 } 5486 return (0); 5487 #if defined(INET6) || defined(INET) 5488 fail: 5489 /* 5490 * Free RX software descriptors allocated so far, we will only handle 5491 * the rings that completed, the failing case will have 5492 * cleaned up for itself. 'q' failed, so its the terminus. 5493 */ 5494 rxq = ctx->ifc_rxqs; 5495 for (i = 0; i < q; ++i, rxq++) { 5496 iflib_rx_sds_free(rxq); 5497 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5498 } 5499 return (err); 5500 #endif 5501 } 5502 5503 /********************************************************************* 5504 * 5505 * Free all receive rings. 5506 * 5507 **********************************************************************/ 5508 static void 5509 iflib_rx_structures_free(if_ctx_t ctx) 5510 { 5511 iflib_rxq_t rxq = ctx->ifc_rxqs; 5512 5513 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5514 iflib_rx_sds_free(rxq); 5515 } 5516 free(ctx->ifc_rxqs, M_IFLIB); 5517 ctx->ifc_rxqs = NULL; 5518 } 5519 5520 static int 5521 iflib_qset_structures_setup(if_ctx_t ctx) 5522 { 5523 int err; 5524 5525 /* 5526 * It is expected that the caller takes care of freeing queues if this 5527 * fails. 5528 */ 5529 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5530 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5531 return (err); 5532 } 5533 5534 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5535 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5536 5537 return (err); 5538 } 5539 5540 int 5541 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5542 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5543 { 5544 5545 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5546 } 5547 5548 #ifdef SMP 5549 static int 5550 find_nth(if_ctx_t ctx, int qid) 5551 { 5552 cpuset_t cpus; 5553 int i, cpuid, eqid, count; 5554 5555 CPU_COPY(&ctx->ifc_cpus, &cpus); 5556 count = CPU_COUNT(&cpus); 5557 eqid = qid % count; 5558 /* clear up to the qid'th bit */ 5559 for (i = 0; i < eqid; i++) { 5560 cpuid = CPU_FFS(&cpus); 5561 MPASS(cpuid != 0); 5562 CPU_CLR(cpuid-1, &cpus); 5563 } 5564 cpuid = CPU_FFS(&cpus); 5565 MPASS(cpuid != 0); 5566 return (cpuid-1); 5567 } 5568 5569 #ifdef SCHED_ULE 5570 extern struct cpu_group *cpu_top; /* CPU topology */ 5571 5572 static int 5573 find_child_with_core(int cpu, struct cpu_group *grp) 5574 { 5575 int i; 5576 5577 if (grp->cg_children == 0) 5578 return -1; 5579 5580 MPASS(grp->cg_child); 5581 for (i = 0; i < grp->cg_children; i++) { 5582 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5583 return i; 5584 } 5585 5586 return -1; 5587 } 5588 5589 /* 5590 * Find the nth "close" core to the specified core 5591 * "close" is defined as the deepest level that shares 5592 * at least an L2 cache. With threads, this will be 5593 * threads on the same core. If the sahred cache is L3 5594 * or higher, simply returns the same core. 5595 */ 5596 static int 5597 find_close_core(int cpu, int core_offset) 5598 { 5599 struct cpu_group *grp; 5600 int i; 5601 int fcpu; 5602 cpuset_t cs; 5603 5604 grp = cpu_top; 5605 if (grp == NULL) 5606 return cpu; 5607 i = 0; 5608 while ((i = find_child_with_core(cpu, grp)) != -1) { 5609 /* If the child only has one cpu, don't descend */ 5610 if (grp->cg_child[i].cg_count <= 1) 5611 break; 5612 grp = &grp->cg_child[i]; 5613 } 5614 5615 /* If they don't share at least an L2 cache, use the same CPU */ 5616 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5617 return cpu; 5618 5619 /* Now pick one */ 5620 CPU_COPY(&grp->cg_mask, &cs); 5621 5622 /* Add the selected CPU offset to core offset. */ 5623 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5624 if (fcpu - 1 == cpu) 5625 break; 5626 CPU_CLR(fcpu - 1, &cs); 5627 } 5628 MPASS(fcpu); 5629 5630 core_offset += i; 5631 5632 CPU_COPY(&grp->cg_mask, &cs); 5633 for (i = core_offset % grp->cg_count; i > 0; i--) { 5634 MPASS(CPU_FFS(&cs)); 5635 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5636 } 5637 MPASS(CPU_FFS(&cs)); 5638 return CPU_FFS(&cs) - 1; 5639 } 5640 #else 5641 static int 5642 find_close_core(int cpu, int core_offset __unused) 5643 { 5644 return cpu; 5645 } 5646 #endif 5647 5648 static int 5649 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5650 { 5651 switch (type) { 5652 case IFLIB_INTR_TX: 5653 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5654 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5655 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5656 case IFLIB_INTR_RX: 5657 case IFLIB_INTR_RXTX: 5658 /* RX queues get the specified core */ 5659 return qid / CPU_COUNT(&ctx->ifc_cpus); 5660 default: 5661 return -1; 5662 } 5663 } 5664 #else 5665 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5666 #define find_close_core(cpuid, tid) CPU_FIRST() 5667 #define find_nth(ctx, gid) CPU_FIRST() 5668 #endif 5669 5670 /* Just to avoid copy/paste */ 5671 static inline int 5672 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5673 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5674 const char *name) 5675 { 5676 device_t dev; 5677 int err, cpuid, tid; 5678 5679 dev = ctx->ifc_dev; 5680 cpuid = find_nth(ctx, qid); 5681 tid = get_core_offset(ctx, type, qid); 5682 MPASS(tid >= 0); 5683 cpuid = find_close_core(cpuid, tid); 5684 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5685 name); 5686 if (err) { 5687 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5688 return (err); 5689 } 5690 #ifdef notyet 5691 if (cpuid > ctx->ifc_cpuid_highest) 5692 ctx->ifc_cpuid_highest = cpuid; 5693 #endif 5694 return 0; 5695 } 5696 5697 int 5698 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5699 iflib_intr_type_t type, driver_filter_t *filter, 5700 void *filter_arg, int qid, const char *name) 5701 { 5702 device_t dev; 5703 struct grouptask *gtask; 5704 struct taskqgroup *tqg; 5705 iflib_filter_info_t info; 5706 gtask_fn_t *fn; 5707 int tqrid, err; 5708 driver_filter_t *intr_fast; 5709 void *q; 5710 5711 info = &ctx->ifc_filter_info; 5712 tqrid = rid; 5713 5714 switch (type) { 5715 /* XXX merge tx/rx for netmap? */ 5716 case IFLIB_INTR_TX: 5717 q = &ctx->ifc_txqs[qid]; 5718 info = &ctx->ifc_txqs[qid].ift_filter_info; 5719 gtask = &ctx->ifc_txqs[qid].ift_task; 5720 tqg = qgroup_if_io_tqg; 5721 fn = _task_fn_tx; 5722 intr_fast = iflib_fast_intr; 5723 GROUPTASK_INIT(gtask, 0, fn, q); 5724 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5725 break; 5726 case IFLIB_INTR_RX: 5727 q = &ctx->ifc_rxqs[qid]; 5728 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5729 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5730 tqg = qgroup_if_io_tqg; 5731 fn = _task_fn_rx; 5732 intr_fast = iflib_fast_intr; 5733 GROUPTASK_INIT(gtask, 0, fn, q); 5734 break; 5735 case IFLIB_INTR_RXTX: 5736 q = &ctx->ifc_rxqs[qid]; 5737 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5738 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5739 tqg = qgroup_if_io_tqg; 5740 fn = _task_fn_rx; 5741 intr_fast = iflib_fast_intr_rxtx; 5742 GROUPTASK_INIT(gtask, 0, fn, q); 5743 break; 5744 case IFLIB_INTR_ADMIN: 5745 q = ctx; 5746 tqrid = -1; 5747 info = &ctx->ifc_filter_info; 5748 gtask = &ctx->ifc_admin_task; 5749 tqg = qgroup_if_config_tqg; 5750 fn = _task_fn_admin; 5751 intr_fast = iflib_fast_intr_ctx; 5752 break; 5753 default: 5754 panic("unknown net intr type"); 5755 } 5756 5757 info->ifi_filter = filter; 5758 info->ifi_filter_arg = filter_arg; 5759 info->ifi_task = gtask; 5760 info->ifi_ctx = q; 5761 5762 dev = ctx->ifc_dev; 5763 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5764 if (err != 0) { 5765 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 5766 return (err); 5767 } 5768 if (type == IFLIB_INTR_ADMIN) 5769 return (0); 5770 5771 if (tqrid != -1) { 5772 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5773 q, name); 5774 if (err) 5775 return (err); 5776 } else { 5777 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 5778 } 5779 5780 return (0); 5781 } 5782 5783 void 5784 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5785 { 5786 struct grouptask *gtask; 5787 struct taskqgroup *tqg; 5788 gtask_fn_t *fn; 5789 void *q; 5790 int err; 5791 5792 switch (type) { 5793 case IFLIB_INTR_TX: 5794 q = &ctx->ifc_txqs[qid]; 5795 gtask = &ctx->ifc_txqs[qid].ift_task; 5796 tqg = qgroup_if_io_tqg; 5797 fn = _task_fn_tx; 5798 break; 5799 case IFLIB_INTR_RX: 5800 q = &ctx->ifc_rxqs[qid]; 5801 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5802 tqg = qgroup_if_io_tqg; 5803 fn = _task_fn_rx; 5804 break; 5805 case IFLIB_INTR_IOV: 5806 q = ctx; 5807 gtask = &ctx->ifc_vflr_task; 5808 tqg = qgroup_if_config_tqg; 5809 fn = _task_fn_iov; 5810 break; 5811 default: 5812 panic("unknown net intr type"); 5813 } 5814 GROUPTASK_INIT(gtask, 0, fn, q); 5815 if (irq != NULL) { 5816 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5817 q, name); 5818 if (err) 5819 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 5820 irq->ii_res, name); 5821 } else { 5822 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 5823 } 5824 } 5825 5826 void 5827 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5828 { 5829 5830 if (irq->ii_tag) 5831 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5832 5833 if (irq->ii_res) 5834 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 5835 rman_get_rid(irq->ii_res), irq->ii_res); 5836 } 5837 5838 static int 5839 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5840 { 5841 iflib_txq_t txq = ctx->ifc_txqs; 5842 iflib_rxq_t rxq = ctx->ifc_rxqs; 5843 if_irq_t irq = &ctx->ifc_legacy_irq; 5844 iflib_filter_info_t info; 5845 device_t dev; 5846 struct grouptask *gtask; 5847 struct resource *res; 5848 struct taskqgroup *tqg; 5849 gtask_fn_t *fn; 5850 int tqrid; 5851 void *q; 5852 int err; 5853 5854 q = &ctx->ifc_rxqs[0]; 5855 info = &rxq[0].ifr_filter_info; 5856 gtask = &rxq[0].ifr_task; 5857 tqg = qgroup_if_io_tqg; 5858 tqrid = irq->ii_rid = *rid; 5859 fn = _task_fn_rx; 5860 5861 ctx->ifc_flags |= IFC_LEGACY; 5862 info->ifi_filter = filter; 5863 info->ifi_filter_arg = filter_arg; 5864 info->ifi_task = gtask; 5865 info->ifi_ctx = ctx; 5866 5867 dev = ctx->ifc_dev; 5868 /* We allocate a single interrupt resource */ 5869 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5870 return (err); 5871 GROUPTASK_INIT(gtask, 0, fn, q); 5872 res = irq->ii_res; 5873 taskqgroup_attach(tqg, gtask, q, dev, res, name); 5874 5875 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5876 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 5877 "tx"); 5878 return (0); 5879 } 5880 5881 void 5882 iflib_led_create(if_ctx_t ctx) 5883 { 5884 5885 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5886 device_get_nameunit(ctx->ifc_dev)); 5887 } 5888 5889 void 5890 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5891 { 5892 5893 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5894 } 5895 5896 void 5897 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5898 { 5899 5900 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5901 } 5902 5903 void 5904 iflib_admin_intr_deferred(if_ctx_t ctx) 5905 { 5906 #ifdef INVARIANTS 5907 struct grouptask *gtask; 5908 5909 gtask = &ctx->ifc_admin_task; 5910 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5911 #endif 5912 5913 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5914 } 5915 5916 void 5917 iflib_iov_intr_deferred(if_ctx_t ctx) 5918 { 5919 5920 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5921 } 5922 5923 void 5924 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5925 { 5926 5927 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 5928 name); 5929 } 5930 5931 void 5932 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5933 const char *name) 5934 { 5935 5936 GROUPTASK_INIT(gtask, 0, fn, ctx); 5937 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 5938 name); 5939 } 5940 5941 void 5942 iflib_config_gtask_deinit(struct grouptask *gtask) 5943 { 5944 5945 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5946 } 5947 5948 void 5949 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5950 { 5951 if_t ifp = ctx->ifc_ifp; 5952 iflib_txq_t txq = ctx->ifc_txqs; 5953 5954 if_setbaudrate(ifp, baudrate); 5955 if (baudrate >= IF_Gbps(10)) { 5956 STATE_LOCK(ctx); 5957 ctx->ifc_flags |= IFC_PREFETCH; 5958 STATE_UNLOCK(ctx); 5959 } 5960 /* If link down, disable watchdog */ 5961 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5962 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5963 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5964 } 5965 ctx->ifc_link_state = link_state; 5966 if_link_state_change(ifp, link_state); 5967 } 5968 5969 static int 5970 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5971 { 5972 int credits; 5973 #ifdef INVARIANTS 5974 int credits_pre = txq->ift_cidx_processed; 5975 #endif 5976 5977 if (ctx->isc_txd_credits_update == NULL) 5978 return (0); 5979 5980 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 5981 BUS_DMASYNC_POSTREAD); 5982 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5983 return (0); 5984 5985 txq->ift_processed += credits; 5986 txq->ift_cidx_processed += credits; 5987 5988 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5989 if (txq->ift_cidx_processed >= txq->ift_size) 5990 txq->ift_cidx_processed -= txq->ift_size; 5991 return (credits); 5992 } 5993 5994 static int 5995 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5996 { 5997 iflib_fl_t fl; 5998 u_int i; 5999 6000 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6001 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6002 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6003 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6004 budget)); 6005 } 6006 6007 void 6008 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6009 const char *description, if_int_delay_info_t info, 6010 int offset, int value) 6011 { 6012 info->iidi_ctx = ctx; 6013 info->iidi_offset = offset; 6014 info->iidi_value = value; 6015 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6016 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6017 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 6018 info, 0, iflib_sysctl_int_delay, "I", description); 6019 } 6020 6021 struct sx * 6022 iflib_ctx_lock_get(if_ctx_t ctx) 6023 { 6024 6025 return (&ctx->ifc_ctx_sx); 6026 } 6027 6028 static int 6029 iflib_msix_init(if_ctx_t ctx) 6030 { 6031 device_t dev = ctx->ifc_dev; 6032 if_shared_ctx_t sctx = ctx->ifc_sctx; 6033 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6034 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 6035 int iflib_num_tx_queues, iflib_num_rx_queues; 6036 int err, admincnt, bar; 6037 6038 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6039 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6040 6041 if (bootverbose) 6042 device_printf(dev, "msix_init qsets capped at %d\n", 6043 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6044 6045 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6046 admincnt = sctx->isc_admin_intrcnt; 6047 /* Override by tuneable */ 6048 if (scctx->isc_disable_msix) 6049 goto msi; 6050 6051 /* First try MSI-X */ 6052 if ((msgs = pci_msix_count(dev)) == 0) { 6053 if (bootverbose) 6054 device_printf(dev, "MSI-X not supported or disabled\n"); 6055 goto msi; 6056 } 6057 /* 6058 * bar == -1 => "trust me I know what I'm doing" 6059 * Some drivers are for hardware that is so shoddily 6060 * documented that no one knows which bars are which 6061 * so the developer has to map all bars. This hack 6062 * allows shoddy garbage to use MSI-X in this framework. 6063 */ 6064 if (bar != -1) { 6065 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6066 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6067 if (ctx->ifc_msix_mem == NULL) { 6068 device_printf(dev, "Unable to map MSI-X table\n"); 6069 goto msi; 6070 } 6071 } 6072 #if IFLIB_DEBUG 6073 /* use only 1 qset in debug mode */ 6074 queuemsgs = min(msgs - admincnt, 1); 6075 #else 6076 queuemsgs = msgs - admincnt; 6077 #endif 6078 #ifdef RSS 6079 queues = imin(queuemsgs, rss_getnumbuckets()); 6080 #else 6081 queues = queuemsgs; 6082 #endif 6083 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6084 if (bootverbose) 6085 device_printf(dev, 6086 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6087 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6088 #ifdef RSS 6089 /* If we're doing RSS, clamp at the number of RSS buckets */ 6090 if (queues > rss_getnumbuckets()) 6091 queues = rss_getnumbuckets(); 6092 #endif 6093 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6094 rx_queues = iflib_num_rx_queues; 6095 else 6096 rx_queues = queues; 6097 6098 if (rx_queues > scctx->isc_nrxqsets) 6099 rx_queues = scctx->isc_nrxqsets; 6100 6101 /* 6102 * We want this to be all logical CPUs by default 6103 */ 6104 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6105 tx_queues = iflib_num_tx_queues; 6106 else 6107 tx_queues = mp_ncpus; 6108 6109 if (tx_queues > scctx->isc_ntxqsets) 6110 tx_queues = scctx->isc_ntxqsets; 6111 6112 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6113 #ifdef INVARIANTS 6114 if (tx_queues != rx_queues) 6115 device_printf(dev, 6116 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6117 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6118 #endif 6119 tx_queues = min(rx_queues, tx_queues); 6120 rx_queues = min(rx_queues, tx_queues); 6121 } 6122 6123 device_printf(dev, "Using %d rx queues %d tx queues\n", 6124 rx_queues, tx_queues); 6125 6126 vectors = rx_queues + admincnt; 6127 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6128 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6129 vectors); 6130 scctx->isc_vectors = vectors; 6131 scctx->isc_nrxqsets = rx_queues; 6132 scctx->isc_ntxqsets = tx_queues; 6133 scctx->isc_intr = IFLIB_INTR_MSIX; 6134 6135 return (vectors); 6136 } else { 6137 device_printf(dev, 6138 "failed to allocate %d MSI-X vectors, err: %d - using MSI\n", 6139 vectors, err); 6140 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6141 ctx->ifc_msix_mem); 6142 ctx->ifc_msix_mem = NULL; 6143 } 6144 msi: 6145 vectors = pci_msi_count(dev); 6146 scctx->isc_nrxqsets = 1; 6147 scctx->isc_ntxqsets = 1; 6148 scctx->isc_vectors = vectors; 6149 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6150 device_printf(dev,"Using an MSI interrupt\n"); 6151 scctx->isc_intr = IFLIB_INTR_MSI; 6152 } else { 6153 scctx->isc_vectors = 1; 6154 device_printf(dev,"Using a Legacy interrupt\n"); 6155 scctx->isc_intr = IFLIB_INTR_LEGACY; 6156 } 6157 6158 return (vectors); 6159 } 6160 6161 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6162 6163 static int 6164 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6165 { 6166 int rc; 6167 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6168 struct sbuf *sb; 6169 const char *ring_state = "UNKNOWN"; 6170 6171 /* XXX needed ? */ 6172 rc = sysctl_wire_old_buffer(req, 0); 6173 MPASS(rc == 0); 6174 if (rc != 0) 6175 return (rc); 6176 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6177 MPASS(sb != NULL); 6178 if (sb == NULL) 6179 return (ENOMEM); 6180 if (state[3] <= 3) 6181 ring_state = ring_states[state[3]]; 6182 6183 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6184 state[0], state[1], state[2], ring_state); 6185 rc = sbuf_finish(sb); 6186 sbuf_delete(sb); 6187 return(rc); 6188 } 6189 6190 enum iflib_ndesc_handler { 6191 IFLIB_NTXD_HANDLER, 6192 IFLIB_NRXD_HANDLER, 6193 }; 6194 6195 static int 6196 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6197 { 6198 if_ctx_t ctx = (void *)arg1; 6199 enum iflib_ndesc_handler type = arg2; 6200 char buf[256] = {0}; 6201 qidx_t *ndesc; 6202 char *p, *next; 6203 int nqs, rc, i; 6204 6205 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6206 6207 nqs = 8; 6208 switch(type) { 6209 case IFLIB_NTXD_HANDLER: 6210 ndesc = ctx->ifc_sysctl_ntxds; 6211 if (ctx->ifc_sctx) 6212 nqs = ctx->ifc_sctx->isc_ntxqs; 6213 break; 6214 case IFLIB_NRXD_HANDLER: 6215 ndesc = ctx->ifc_sysctl_nrxds; 6216 if (ctx->ifc_sctx) 6217 nqs = ctx->ifc_sctx->isc_nrxqs; 6218 break; 6219 default: 6220 panic("unhandled type"); 6221 } 6222 if (nqs == 0) 6223 nqs = 8; 6224 6225 for (i=0; i<8; i++) { 6226 if (i >= nqs) 6227 break; 6228 if (i) 6229 strcat(buf, ","); 6230 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6231 } 6232 6233 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6234 if (rc || req->newptr == NULL) 6235 return rc; 6236 6237 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6238 i++, p = strsep(&next, " ,")) { 6239 ndesc[i] = strtoul(p, NULL, 10); 6240 } 6241 6242 return(rc); 6243 } 6244 6245 #define NAME_BUFLEN 32 6246 static void 6247 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6248 { 6249 device_t dev = iflib_get_dev(ctx); 6250 struct sysctl_oid_list *child, *oid_list; 6251 struct sysctl_ctx_list *ctx_list; 6252 struct sysctl_oid *node; 6253 6254 ctx_list = device_get_sysctl_ctx(dev); 6255 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6256 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6257 CTLFLAG_RD, NULL, "IFLIB fields"); 6258 oid_list = SYSCTL_CHILDREN(node); 6259 6260 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6261 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6262 "driver version"); 6263 6264 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6265 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6266 "# of txqs to use, 0 => use default #"); 6267 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6268 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6269 "# of rxqs to use, 0 => use default #"); 6270 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6271 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6272 "permit #txq != #rxq"); 6273 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6274 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6275 "disable MSI-X (default 0)"); 6276 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6277 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6278 "set the rx budget"); 6279 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6280 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6281 "cause tx to abdicate instead of running to completion"); 6282 6283 /* XXX change for per-queue sizes */ 6284 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6285 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6286 mp_ndesc_handler, "A", 6287 "list of # of tx descriptors to use, 0 = use default #"); 6288 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6289 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6290 mp_ndesc_handler, "A", 6291 "list of # of rx descriptors to use, 0 = use default #"); 6292 } 6293 6294 static void 6295 iflib_add_device_sysctl_post(if_ctx_t ctx) 6296 { 6297 if_shared_ctx_t sctx = ctx->ifc_sctx; 6298 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6299 device_t dev = iflib_get_dev(ctx); 6300 struct sysctl_oid_list *child; 6301 struct sysctl_ctx_list *ctx_list; 6302 iflib_fl_t fl; 6303 iflib_txq_t txq; 6304 iflib_rxq_t rxq; 6305 int i, j; 6306 char namebuf[NAME_BUFLEN]; 6307 char *qfmt; 6308 struct sysctl_oid *queue_node, *fl_node, *node; 6309 struct sysctl_oid_list *queue_list, *fl_list; 6310 ctx_list = device_get_sysctl_ctx(dev); 6311 6312 node = ctx->ifc_sysctl_node; 6313 child = SYSCTL_CHILDREN(node); 6314 6315 if (scctx->isc_ntxqsets > 100) 6316 qfmt = "txq%03d"; 6317 else if (scctx->isc_ntxqsets > 10) 6318 qfmt = "txq%02d"; 6319 else 6320 qfmt = "txq%d"; 6321 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6322 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6323 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6324 CTLFLAG_RD, NULL, "Queue Name"); 6325 queue_list = SYSCTL_CHILDREN(queue_node); 6326 #if MEMORY_LOGGING 6327 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6328 CTLFLAG_RD, 6329 &txq->ift_dequeued, "total mbufs freed"); 6330 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6331 CTLFLAG_RD, 6332 &txq->ift_enqueued, "total mbufs enqueued"); 6333 #endif 6334 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6335 CTLFLAG_RD, 6336 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6337 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6338 CTLFLAG_RD, 6339 &txq->ift_pullups, "# of times m_pullup was called"); 6340 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6341 CTLFLAG_RD, 6342 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6343 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6344 CTLFLAG_RD, 6345 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6346 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6347 CTLFLAG_RD, 6348 &txq->ift_map_failed, "# of times dma map failed"); 6349 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6350 CTLFLAG_RD, 6351 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6352 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6353 CTLFLAG_RD, 6354 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6355 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6356 CTLFLAG_RD, 6357 &txq->ift_pidx, 1, "Producer Index"); 6358 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6359 CTLFLAG_RD, 6360 &txq->ift_cidx, 1, "Consumer Index"); 6361 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6362 CTLFLAG_RD, 6363 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6364 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6365 CTLFLAG_RD, 6366 &txq->ift_in_use, 1, "descriptors in use"); 6367 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6368 CTLFLAG_RD, 6369 &txq->ift_processed, "descriptors procesed for clean"); 6370 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6371 CTLFLAG_RD, 6372 &txq->ift_cleaned, "total cleaned"); 6373 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6374 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6375 0, mp_ring_state_handler, "A", "soft ring state"); 6376 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6377 CTLFLAG_RD, &txq->ift_br->enqueues, 6378 "# of enqueues to the mp_ring for this queue"); 6379 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6380 CTLFLAG_RD, &txq->ift_br->drops, 6381 "# of drops in the mp_ring for this queue"); 6382 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6383 CTLFLAG_RD, &txq->ift_br->starts, 6384 "# of normal consumer starts in the mp_ring for this queue"); 6385 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6386 CTLFLAG_RD, &txq->ift_br->stalls, 6387 "# of consumer stalls in the mp_ring for this queue"); 6388 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6389 CTLFLAG_RD, &txq->ift_br->restarts, 6390 "# of consumer restarts in the mp_ring for this queue"); 6391 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6392 CTLFLAG_RD, &txq->ift_br->abdications, 6393 "# of consumer abdications in the mp_ring for this queue"); 6394 } 6395 6396 if (scctx->isc_nrxqsets > 100) 6397 qfmt = "rxq%03d"; 6398 else if (scctx->isc_nrxqsets > 10) 6399 qfmt = "rxq%02d"; 6400 else 6401 qfmt = "rxq%d"; 6402 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6403 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6404 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6405 CTLFLAG_RD, NULL, "Queue Name"); 6406 queue_list = SYSCTL_CHILDREN(queue_node); 6407 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6408 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6409 CTLFLAG_RD, 6410 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6411 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6412 CTLFLAG_RD, 6413 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6414 } 6415 6416 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6417 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6418 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6419 CTLFLAG_RD, NULL, "freelist Name"); 6420 fl_list = SYSCTL_CHILDREN(fl_node); 6421 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6422 CTLFLAG_RD, 6423 &fl->ifl_pidx, 1, "Producer Index"); 6424 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6425 CTLFLAG_RD, 6426 &fl->ifl_cidx, 1, "Consumer Index"); 6427 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6428 CTLFLAG_RD, 6429 &fl->ifl_credits, 1, "credits available"); 6430 #if MEMORY_LOGGING 6431 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6432 CTLFLAG_RD, 6433 &fl->ifl_m_enqueued, "mbufs allocated"); 6434 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6435 CTLFLAG_RD, 6436 &fl->ifl_m_dequeued, "mbufs freed"); 6437 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6438 CTLFLAG_RD, 6439 &fl->ifl_cl_enqueued, "clusters allocated"); 6440 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6441 CTLFLAG_RD, 6442 &fl->ifl_cl_dequeued, "clusters freed"); 6443 #endif 6444 6445 } 6446 } 6447 6448 } 6449 6450 void 6451 iflib_request_reset(if_ctx_t ctx) 6452 { 6453 6454 STATE_LOCK(ctx); 6455 ctx->ifc_flags |= IFC_DO_RESET; 6456 STATE_UNLOCK(ctx); 6457 } 6458 6459 #ifndef __NO_STRICT_ALIGNMENT 6460 static struct mbuf * 6461 iflib_fixup_rx(struct mbuf *m) 6462 { 6463 struct mbuf *n; 6464 6465 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6466 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6467 m->m_data += ETHER_HDR_LEN; 6468 n = m; 6469 } else { 6470 MGETHDR(n, M_NOWAIT, MT_DATA); 6471 if (n == NULL) { 6472 m_freem(m); 6473 return (NULL); 6474 } 6475 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6476 m->m_data += ETHER_HDR_LEN; 6477 m->m_len -= ETHER_HDR_LEN; 6478 n->m_len = ETHER_HDR_LEN; 6479 M_MOVE_PKTHDR(n, m); 6480 n->m_next = m; 6481 } 6482 return (n); 6483 } 6484 #endif 6485 6486 #ifdef NETDUMP 6487 static void 6488 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6489 { 6490 if_ctx_t ctx; 6491 6492 ctx = if_getsoftc(ifp); 6493 CTX_LOCK(ctx); 6494 *nrxr = NRXQSETS(ctx); 6495 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6496 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6497 CTX_UNLOCK(ctx); 6498 } 6499 6500 static void 6501 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6502 { 6503 if_ctx_t ctx; 6504 if_softc_ctx_t scctx; 6505 iflib_fl_t fl; 6506 iflib_rxq_t rxq; 6507 int i, j; 6508 6509 ctx = if_getsoftc(ifp); 6510 scctx = &ctx->ifc_softc_ctx; 6511 6512 switch (event) { 6513 case NETDUMP_START: 6514 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6515 rxq = &ctx->ifc_rxqs[i]; 6516 for (j = 0; j < rxq->ifr_nfl; j++) { 6517 fl = rxq->ifr_fl; 6518 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6519 } 6520 } 6521 iflib_no_tx_batch = 1; 6522 break; 6523 default: 6524 break; 6525 } 6526 } 6527 6528 static int 6529 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6530 { 6531 if_ctx_t ctx; 6532 iflib_txq_t txq; 6533 int error; 6534 6535 ctx = if_getsoftc(ifp); 6536 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6537 IFF_DRV_RUNNING) 6538 return (EBUSY); 6539 6540 txq = &ctx->ifc_txqs[0]; 6541 error = iflib_encap(txq, &m); 6542 if (error == 0) 6543 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6544 return (error); 6545 } 6546 6547 static int 6548 iflib_netdump_poll(struct ifnet *ifp, int count) 6549 { 6550 if_ctx_t ctx; 6551 if_softc_ctx_t scctx; 6552 iflib_txq_t txq; 6553 int i; 6554 6555 ctx = if_getsoftc(ifp); 6556 scctx = &ctx->ifc_softc_ctx; 6557 6558 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6559 IFF_DRV_RUNNING) 6560 return (EBUSY); 6561 6562 txq = &ctx->ifc_txqs[0]; 6563 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6564 6565 for (i = 0; i < scctx->isc_nrxqsets; i++) 6566 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6567 return (0); 6568 } 6569 #endif /* NETDUMP */ 6570