1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 static void iflib_tqg_detach(if_ctx_t ctx); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 199 qidx_t ifc_sysctl_ntxds[8]; 200 qidx_t ifc_sysctl_nrxds[8]; 201 struct if_txrx ifc_txrx; 202 #define isc_txd_encap ifc_txrx.ift_txd_encap 203 #define isc_txd_flush ifc_txrx.ift_txd_flush 204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 205 #define isc_rxd_available ifc_txrx.ift_rxd_available 206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 210 eventhandler_tag ifc_vlan_attach_event; 211 eventhandler_tag ifc_vlan_detach_event; 212 struct ether_addr ifc_mac; 213 }; 214 215 void * 216 iflib_get_softc(if_ctx_t ctx) 217 { 218 219 return (ctx->ifc_softc); 220 } 221 222 device_t 223 iflib_get_dev(if_ctx_t ctx) 224 { 225 226 return (ctx->ifc_dev); 227 } 228 229 if_t 230 iflib_get_ifp(if_ctx_t ctx) 231 { 232 233 return (ctx->ifc_ifp); 234 } 235 236 struct ifmedia * 237 iflib_get_media(if_ctx_t ctx) 238 { 239 240 return (ctx->ifc_mediap); 241 } 242 243 uint32_t 244 iflib_get_flags(if_ctx_t ctx) 245 { 246 return (ctx->ifc_flags); 247 } 248 249 void 250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 251 { 252 253 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 254 } 255 256 if_softc_ctx_t 257 iflib_get_softc_ctx(if_ctx_t ctx) 258 { 259 260 return (&ctx->ifc_softc_ctx); 261 } 262 263 if_shared_ctx_t 264 iflib_get_sctx(if_ctx_t ctx) 265 { 266 267 return (ctx->ifc_sctx); 268 } 269 270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 273 274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 276 277 typedef struct iflib_sw_rx_desc_array { 278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 279 struct mbuf **ifsd_m; /* pkthdr mbufs */ 280 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 281 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 282 } iflib_rxsd_array_t; 283 284 typedef struct iflib_sw_tx_desc_array { 285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 286 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 287 struct mbuf **ifsd_m; /* pkthdr mbufs */ 288 } if_txsd_vec_t; 289 290 /* magic number that should be high enough for any hardware */ 291 #define IFLIB_MAX_TX_SEGS 128 292 #define IFLIB_RX_COPY_THRESH 128 293 #define IFLIB_MAX_RX_REFRESH 32 294 /* The minimum descriptors per second before we start coalescing */ 295 #define IFLIB_MIN_DESC_SEC 16384 296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 297 #define IFLIB_QUEUE_IDLE 0 298 #define IFLIB_QUEUE_HUNG 1 299 #define IFLIB_QUEUE_WORKING 2 300 /* maximum number of txqs that can share an rx interrupt */ 301 #define IFLIB_MAX_TX_SHARED_INTR 4 302 303 /* this should really scale with ring size - this is a fairly arbitrary value */ 304 #define TX_BATCH_SIZE 32 305 306 #define IFLIB_RESTART_BUDGET 8 307 308 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 309 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 310 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 311 312 struct iflib_txq { 313 qidx_t ift_in_use; 314 qidx_t ift_cidx; 315 qidx_t ift_cidx_processed; 316 qidx_t ift_pidx; 317 uint8_t ift_gen; 318 uint8_t ift_br_offset; 319 uint16_t ift_npending; 320 uint16_t ift_db_pending; 321 uint16_t ift_rs_pending; 322 /* implicit pad */ 323 uint8_t ift_txd_size[8]; 324 uint64_t ift_processed; 325 uint64_t ift_cleaned; 326 uint64_t ift_cleaned_prev; 327 #if MEMORY_LOGGING 328 uint64_t ift_enqueued; 329 uint64_t ift_dequeued; 330 #endif 331 uint64_t ift_no_tx_dma_setup; 332 uint64_t ift_no_desc_avail; 333 uint64_t ift_mbuf_defrag_failed; 334 uint64_t ift_mbuf_defrag; 335 uint64_t ift_map_failed; 336 uint64_t ift_txd_encap_efbig; 337 uint64_t ift_pullups; 338 uint64_t ift_last_timer_tick; 339 340 struct mtx ift_mtx; 341 struct mtx ift_db_mtx; 342 343 /* constant values */ 344 if_ctx_t ift_ctx; 345 struct ifmp_ring *ift_br; 346 struct grouptask ift_task; 347 qidx_t ift_size; 348 uint16_t ift_id; 349 struct callout ift_timer; 350 #ifdef DEV_NETMAP 351 struct callout ift_netmap_timer; 352 #endif /* DEV_NETMAP */ 353 354 if_txsd_vec_t ift_sds; 355 uint8_t ift_qstatus; 356 uint8_t ift_closed; 357 uint8_t ift_update_freq; 358 struct iflib_filter_info ift_filter_info; 359 bus_dma_tag_t ift_buf_tag; 360 bus_dma_tag_t ift_tso_buf_tag; 361 iflib_dma_info_t ift_ifdi; 362 #define MTX_NAME_LEN 32 363 char ift_mtx_name[MTX_NAME_LEN]; 364 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 365 #ifdef IFLIB_DIAGNOSTICS 366 uint64_t ift_cpu_exec_count[256]; 367 #endif 368 } __aligned(CACHE_LINE_SIZE); 369 370 struct iflib_fl { 371 qidx_t ifl_cidx; 372 qidx_t ifl_pidx; 373 qidx_t ifl_credits; 374 uint8_t ifl_gen; 375 uint8_t ifl_rxd_size; 376 #if MEMORY_LOGGING 377 uint64_t ifl_m_enqueued; 378 uint64_t ifl_m_dequeued; 379 uint64_t ifl_cl_enqueued; 380 uint64_t ifl_cl_dequeued; 381 #endif 382 /* implicit pad */ 383 bitstr_t *ifl_rx_bitmap; 384 qidx_t ifl_fragidx; 385 /* constant */ 386 qidx_t ifl_size; 387 uint16_t ifl_buf_size; 388 uint16_t ifl_cltype; 389 uma_zone_t ifl_zone; 390 iflib_rxsd_array_t ifl_sds; 391 iflib_rxq_t ifl_rxq; 392 uint8_t ifl_id; 393 bus_dma_tag_t ifl_buf_tag; 394 iflib_dma_info_t ifl_ifdi; 395 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 397 } __aligned(CACHE_LINE_SIZE); 398 399 static inline qidx_t 400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 401 { 402 qidx_t used; 403 404 if (pidx > cidx) 405 used = pidx - cidx; 406 else if (pidx < cidx) 407 used = size - cidx + pidx; 408 else if (gen == 0 && pidx == cidx) 409 used = 0; 410 else if (gen == 1 && pidx == cidx) 411 used = size; 412 else 413 panic("bad state"); 414 415 return (used); 416 } 417 418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 419 420 #define IDXDIFF(head, tail, wrap) \ 421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 422 423 struct iflib_rxq { 424 if_ctx_t ifr_ctx; 425 iflib_fl_t ifr_fl; 426 uint64_t ifr_rx_irq; 427 struct pfil_head *pfil; 428 /* 429 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 430 * the completion queue consumer index. Otherwise it's unused. 431 */ 432 qidx_t ifr_cq_cidx; 433 uint16_t ifr_id; 434 uint8_t ifr_nfl; 435 uint8_t ifr_ntxqirq; 436 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 437 uint8_t ifr_fl_offset; 438 struct lro_ctrl ifr_lc; 439 struct grouptask ifr_task; 440 struct callout ifr_watchdog; 441 struct iflib_filter_info ifr_filter_info; 442 iflib_dma_info_t ifr_ifdi; 443 444 /* dynamically allocate if any drivers need a value substantially larger than this */ 445 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 446 #ifdef IFLIB_DIAGNOSTICS 447 uint64_t ifr_cpu_exec_count[256]; 448 #endif 449 } __aligned(CACHE_LINE_SIZE); 450 451 typedef struct if_rxsd { 452 caddr_t *ifsd_cl; 453 iflib_fl_t ifsd_fl; 454 } *if_rxsd_t; 455 456 /* multiple of word size */ 457 #ifdef __LP64__ 458 #define PKT_INFO_SIZE 6 459 #define RXD_INFO_SIZE 5 460 #define PKT_TYPE uint64_t 461 #else 462 #define PKT_INFO_SIZE 11 463 #define RXD_INFO_SIZE 8 464 #define PKT_TYPE uint32_t 465 #endif 466 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 467 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 468 469 typedef struct if_pkt_info_pad { 470 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 471 } *if_pkt_info_pad_t; 472 typedef struct if_rxd_info_pad { 473 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 474 } *if_rxd_info_pad_t; 475 476 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 477 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 478 479 static inline void 480 pkt_info_zero(if_pkt_info_t pi) 481 { 482 if_pkt_info_pad_t pi_pad; 483 484 pi_pad = (if_pkt_info_pad_t)pi; 485 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 486 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 487 #ifndef __LP64__ 488 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 489 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 490 #endif 491 } 492 493 static device_method_t iflib_pseudo_methods[] = { 494 DEVMETHOD(device_attach, noop_attach), 495 DEVMETHOD(device_detach, iflib_pseudo_detach), 496 DEVMETHOD_END 497 }; 498 499 driver_t iflib_pseudodriver = { 500 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 501 }; 502 503 static inline void 504 rxd_info_zero(if_rxd_info_t ri) 505 { 506 if_rxd_info_pad_t ri_pad; 507 int i; 508 509 ri_pad = (if_rxd_info_pad_t)ri; 510 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 511 ri_pad->rxd_val[i] = 0; 512 ri_pad->rxd_val[i+1] = 0; 513 ri_pad->rxd_val[i+2] = 0; 514 ri_pad->rxd_val[i+3] = 0; 515 } 516 #ifdef __LP64__ 517 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 518 #endif 519 } 520 521 /* 522 * Only allow a single packet to take up most 1/nth of the tx ring 523 */ 524 #define MAX_SINGLE_PACKET_FRACTION 12 525 #define IF_BAD_DMA (bus_addr_t)-1 526 527 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 528 529 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 530 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 531 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 532 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 533 534 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 535 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 536 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 537 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 538 539 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 540 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 541 542 void 543 iflib_set_detach(if_ctx_t ctx) 544 { 545 STATE_LOCK(ctx); 546 ctx->ifc_flags |= IFC_IN_DETACH; 547 STATE_UNLOCK(ctx); 548 } 549 550 /* Our boot-time initialization hook */ 551 static int iflib_module_event_handler(module_t, int, void *); 552 553 static moduledata_t iflib_moduledata = { 554 "iflib", 555 iflib_module_event_handler, 556 NULL 557 }; 558 559 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 560 MODULE_VERSION(iflib, 1); 561 562 MODULE_DEPEND(iflib, pci, 1, 1, 1); 563 MODULE_DEPEND(iflib, ether, 1, 1, 1); 564 565 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 566 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 567 568 #ifndef IFLIB_DEBUG_COUNTERS 569 #ifdef INVARIANTS 570 #define IFLIB_DEBUG_COUNTERS 1 571 #else 572 #define IFLIB_DEBUG_COUNTERS 0 573 #endif /* !INVARIANTS */ 574 #endif 575 576 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 577 "iflib driver parameters"); 578 579 /* 580 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 581 */ 582 static int iflib_min_tx_latency = 0; 583 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 584 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 585 static int iflib_no_tx_batch = 0; 586 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 587 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 588 static int iflib_timer_default = 1000; 589 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 590 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 591 592 593 #if IFLIB_DEBUG_COUNTERS 594 595 static int iflib_tx_seen; 596 static int iflib_tx_sent; 597 static int iflib_tx_encap; 598 static int iflib_rx_allocs; 599 static int iflib_fl_refills; 600 static int iflib_fl_refills_large; 601 static int iflib_tx_frees; 602 603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 604 &iflib_tx_seen, 0, "# TX mbufs seen"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 606 &iflib_tx_sent, 0, "# TX mbufs sent"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 608 &iflib_tx_encap, 0, "# TX mbufs encapped"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 610 &iflib_tx_frees, 0, "# TX frees"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 612 &iflib_rx_allocs, 0, "# RX allocations"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 614 &iflib_fl_refills, 0, "# refills"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 616 &iflib_fl_refills_large, 0, "# large refills"); 617 618 static int iflib_txq_drain_flushing; 619 static int iflib_txq_drain_oactive; 620 static int iflib_txq_drain_notready; 621 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 623 &iflib_txq_drain_flushing, 0, "# drain flushes"); 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 625 &iflib_txq_drain_oactive, 0, "# drain oactives"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 627 &iflib_txq_drain_notready, 0, "# drain notready"); 628 629 static int iflib_encap_load_mbuf_fail; 630 static int iflib_encap_pad_mbuf_fail; 631 static int iflib_encap_txq_avail_fail; 632 static int iflib_encap_txd_encap_fail; 633 634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 635 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 637 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 639 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 641 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 642 643 static int iflib_task_fn_rxs; 644 static int iflib_rx_intr_enables; 645 static int iflib_fast_intrs; 646 static int iflib_rx_unavail; 647 static int iflib_rx_ctx_inactive; 648 static int iflib_rx_if_input; 649 static int iflib_rxd_flush; 650 651 static int iflib_verbose_debug; 652 653 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 654 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 656 &iflib_rx_intr_enables, 0, "# RX intr enables"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 658 &iflib_fast_intrs, 0, "# fast_intr calls"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 660 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 662 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 664 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 666 &iflib_rxd_flush, 0, "# times rxd_flush called"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 668 &iflib_verbose_debug, 0, "enable verbose debugging"); 669 670 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 671 static void 672 iflib_debug_reset(void) 673 { 674 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 675 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 676 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 677 iflib_txq_drain_notready = 678 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 679 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 680 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 681 iflib_rx_unavail = 682 iflib_rx_ctx_inactive = iflib_rx_if_input = 683 iflib_rxd_flush = 0; 684 } 685 686 #else 687 #define DBG_COUNTER_INC(name) 688 static void iflib_debug_reset(void) {} 689 #endif 690 691 #define IFLIB_DEBUG 0 692 693 static void iflib_tx_structures_free(if_ctx_t ctx); 694 static void iflib_rx_structures_free(if_ctx_t ctx); 695 static int iflib_queues_alloc(if_ctx_t ctx); 696 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 697 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 698 static int iflib_qset_structures_setup(if_ctx_t ctx); 699 static int iflib_msix_init(if_ctx_t ctx); 700 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 701 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 702 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 703 #ifdef ALTQ 704 static void iflib_altq_if_start(if_t ifp); 705 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 706 #endif 707 static int iflib_register(if_ctx_t); 708 static void iflib_deregister(if_ctx_t); 709 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 710 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 711 static void iflib_init_locked(if_ctx_t ctx); 712 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 713 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 714 static void iflib_ifmp_purge(iflib_txq_t txq); 715 static void _iflib_pre_assert(if_softc_ctx_t scctx); 716 static void iflib_if_init_locked(if_ctx_t ctx); 717 static void iflib_free_intr_mem(if_ctx_t ctx); 718 #ifndef __NO_STRICT_ALIGNMENT 719 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 720 #endif 721 722 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 723 SLIST_HEAD_INITIALIZER(cpu_offsets); 724 struct cpu_offset { 725 SLIST_ENTRY(cpu_offset) entries; 726 cpuset_t set; 727 unsigned int refcount; 728 uint16_t offset; 729 }; 730 static struct mtx cpu_offset_mtx; 731 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 732 MTX_DEF); 733 734 DEBUGNET_DEFINE(iflib); 735 736 static int 737 iflib_num_rx_descs(if_ctx_t ctx) 738 { 739 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 740 if_shared_ctx_t sctx = ctx->ifc_sctx; 741 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 742 743 return scctx->isc_nrxd[first_rxq]; 744 } 745 746 static int 747 iflib_num_tx_descs(if_ctx_t ctx) 748 { 749 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 750 if_shared_ctx_t sctx = ctx->ifc_sctx; 751 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 752 753 return scctx->isc_ntxd[first_txq]; 754 } 755 756 #ifdef DEV_NETMAP 757 #include <sys/selinfo.h> 758 #include <net/netmap.h> 759 #include <dev/netmap/netmap_kern.h> 760 761 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 762 763 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 764 static void iflib_netmap_timer(void *arg); 765 766 /* 767 * device-specific sysctl variables: 768 * 769 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 770 * During regular operations the CRC is stripped, but on some 771 * hardware reception of frames not multiple of 64 is slower, 772 * so using crcstrip=0 helps in benchmarks. 773 * 774 * iflib_rx_miss, iflib_rx_miss_bufs: 775 * count packets that might be missed due to lost interrupts. 776 */ 777 SYSCTL_DECL(_dev_netmap); 778 /* 779 * The xl driver by default strips CRCs and we do not override it. 780 */ 781 782 int iflib_crcstrip = 1; 783 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 784 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 785 786 int iflib_rx_miss, iflib_rx_miss_bufs; 787 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 788 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 789 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 790 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 791 792 /* 793 * Register/unregister. We are already under netmap lock. 794 * Only called on the first register or the last unregister. 795 */ 796 static int 797 iflib_netmap_register(struct netmap_adapter *na, int onoff) 798 { 799 if_t ifp = na->ifp; 800 if_ctx_t ctx = ifp->if_softc; 801 int status; 802 803 CTX_LOCK(ctx); 804 if (!CTX_IS_VF(ctx)) 805 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 806 807 iflib_stop(ctx); 808 809 /* 810 * Enable (or disable) netmap flags, and intercept (or restore) 811 * ifp->if_transmit. This is done once the device has been stopped 812 * to prevent race conditions. Also, this must be done after 813 * calling netmap_disable_all_rings() and before calling 814 * netmap_enable_all_rings(), so that these two functions see the 815 * updated state of the NAF_NETMAP_ON bit. 816 */ 817 if (onoff) { 818 nm_set_native_flags(na); 819 } else { 820 nm_clear_native_flags(na); 821 } 822 823 iflib_init_locked(ctx); 824 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 825 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 826 if (status) 827 nm_clear_native_flags(na); 828 CTX_UNLOCK(ctx); 829 return (status); 830 } 831 832 static int 833 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 834 { 835 struct netmap_adapter *na = kring->na; 836 u_int const lim = kring->nkr_num_slots - 1; 837 struct netmap_ring *ring = kring->ring; 838 bus_dmamap_t *map; 839 struct if_rxd_update iru; 840 if_ctx_t ctx = rxq->ifr_ctx; 841 iflib_fl_t fl = &rxq->ifr_fl[0]; 842 u_int nic_i_first, nic_i; 843 u_int nm_i; 844 int i, n; 845 #if IFLIB_DEBUG_COUNTERS 846 int rf_count = 0; 847 #endif 848 849 /* 850 * This function is used both at initialization and in rxsync. 851 * At initialization we need to prepare (with isc_rxd_refill()) 852 * all the netmap buffers currently owned by the kernel, in 853 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 854 * (except for kring->nkr_hwofs). These may be less than 855 * kring->nkr_num_slots if netmap_reset() was called while 856 * an application using the kring that still owned some 857 * buffers. 858 * At rxsync time, both indexes point to the next buffer to be 859 * refilled. 860 * In any case we publish (with isc_rxd_flush()) up to 861 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 862 * pointer to overrun the head/cons pointer, although this is 863 * not necessary for some NICs (e.g. vmx). 864 */ 865 if (__predict_false(init)) { 866 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 867 } else { 868 n = kring->rhead - kring->nr_hwcur; 869 if (n == 0) 870 return (0); /* Nothing to do. */ 871 if (n < 0) 872 n += kring->nkr_num_slots; 873 } 874 875 iru_init(&iru, rxq, 0 /* flid */); 876 map = fl->ifl_sds.ifsd_map; 877 nic_i = fl->ifl_pidx; 878 nm_i = netmap_idx_n2k(kring, nic_i); 879 if (__predict_false(init)) { 880 /* 881 * On init/reset, nic_i must be 0, and we must 882 * start to refill from hwtail (see netmap_reset()). 883 */ 884 MPASS(nic_i == 0); 885 MPASS(nm_i == kring->nr_hwtail); 886 } else 887 MPASS(nm_i == kring->nr_hwcur); 888 DBG_COUNTER_INC(fl_refills); 889 while (n > 0) { 890 #if IFLIB_DEBUG_COUNTERS 891 if (++rf_count == 9) 892 DBG_COUNTER_INC(fl_refills_large); 893 #endif 894 nic_i_first = nic_i; 895 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 896 struct netmap_slot *slot = &ring->slot[nm_i]; 897 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 898 899 MPASS(i < IFLIB_MAX_RX_REFRESH); 900 901 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 902 return netmap_ring_reinit(kring); 903 904 fl->ifl_rxd_idxs[i] = nic_i; 905 906 if (__predict_false(init)) { 907 netmap_load_map(na, fl->ifl_buf_tag, 908 map[nic_i], addr); 909 } else if (slot->flags & NS_BUF_CHANGED) { 910 /* buffer has changed, reload map */ 911 netmap_reload_map(na, fl->ifl_buf_tag, 912 map[nic_i], addr); 913 } 914 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 915 BUS_DMASYNC_PREREAD); 916 slot->flags &= ~NS_BUF_CHANGED; 917 918 nm_i = nm_next(nm_i, lim); 919 nic_i = nm_next(nic_i, lim); 920 } 921 922 iru.iru_pidx = nic_i_first; 923 iru.iru_count = i; 924 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 925 } 926 fl->ifl_pidx = nic_i; 927 /* 928 * At the end of the loop we must have refilled everything 929 * we could possibly refill. 930 */ 931 MPASS(nm_i == kring->rhead); 932 kring->nr_hwcur = nm_i; 933 934 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 935 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 936 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 937 nm_prev(nic_i, lim)); 938 DBG_COUNTER_INC(rxd_flush); 939 940 return (0); 941 } 942 943 #define NETMAP_TX_TIMER_US 90 944 945 /* 946 * Reconcile kernel and user view of the transmit ring. 947 * 948 * All information is in the kring. 949 * Userspace wants to send packets up to the one before kring->rhead, 950 * kernel knows kring->nr_hwcur is the first unsent packet. 951 * 952 * Here we push packets out (as many as possible), and possibly 953 * reclaim buffers from previously completed transmission. 954 * 955 * The caller (netmap) guarantees that there is only one instance 956 * running at any time. Any interference with other driver 957 * methods should be handled by the individual drivers. 958 */ 959 static int 960 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 961 { 962 struct netmap_adapter *na = kring->na; 963 if_t ifp = na->ifp; 964 struct netmap_ring *ring = kring->ring; 965 u_int nm_i; /* index into the netmap kring */ 966 u_int nic_i; /* index into the NIC ring */ 967 u_int n; 968 u_int const lim = kring->nkr_num_slots - 1; 969 u_int const head = kring->rhead; 970 struct if_pkt_info pi; 971 972 /* 973 * interrupts on every tx packet are expensive so request 974 * them every half ring, or where NS_REPORT is set 975 */ 976 u_int report_frequency = kring->nkr_num_slots >> 1; 977 /* device-specific */ 978 if_ctx_t ctx = ifp->if_softc; 979 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 980 981 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 982 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 983 984 /* 985 * First part: process new packets to send. 986 * nm_i is the current index in the netmap kring, 987 * nic_i is the corresponding index in the NIC ring. 988 * 989 * If we have packets to send (nm_i != head) 990 * iterate over the netmap ring, fetch length and update 991 * the corresponding slot in the NIC ring. Some drivers also 992 * need to update the buffer's physical address in the NIC slot 993 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 994 * 995 * The netmap_reload_map() calls is especially expensive, 996 * even when (as in this case) the tag is 0, so do only 997 * when the buffer has actually changed. 998 * 999 * If possible do not set the report/intr bit on all slots, 1000 * but only a few times per ring or when NS_REPORT is set. 1001 * 1002 * Finally, on 10G and faster drivers, it might be useful 1003 * to prefetch the next slot and txr entry. 1004 */ 1005 1006 nm_i = kring->nr_hwcur; 1007 if (nm_i != head) { /* we have new packets to send */ 1008 uint32_t pkt_len = 0, seg_idx = 0; 1009 int nic_i_start = -1, flags = 0; 1010 pkt_info_zero(&pi); 1011 pi.ipi_segs = txq->ift_segs; 1012 pi.ipi_qsidx = kring->ring_id; 1013 nic_i = netmap_idx_k2n(kring, nm_i); 1014 1015 __builtin_prefetch(&ring->slot[nm_i]); 1016 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1017 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1018 1019 for (n = 0; nm_i != head; n++) { 1020 struct netmap_slot *slot = &ring->slot[nm_i]; 1021 u_int len = slot->len; 1022 uint64_t paddr; 1023 void *addr = PNMB(na, slot, &paddr); 1024 1025 flags |= (slot->flags & NS_REPORT || 1026 nic_i == 0 || nic_i == report_frequency) ? 1027 IPI_TX_INTR : 0; 1028 1029 /* 1030 * If this is the first packet fragment, save the 1031 * index of the first NIC slot for later. 1032 */ 1033 if (nic_i_start < 0) 1034 nic_i_start = nic_i; 1035 1036 pi.ipi_segs[seg_idx].ds_addr = paddr; 1037 pi.ipi_segs[seg_idx].ds_len = len; 1038 if (len) { 1039 pkt_len += len; 1040 seg_idx++; 1041 } 1042 1043 if (!(slot->flags & NS_MOREFRAG)) { 1044 pi.ipi_len = pkt_len; 1045 pi.ipi_nsegs = seg_idx; 1046 pi.ipi_pidx = nic_i_start; 1047 pi.ipi_ndescs = 0; 1048 pi.ipi_flags = flags; 1049 1050 /* Prepare the NIC TX ring. */ 1051 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1052 DBG_COUNTER_INC(tx_encap); 1053 1054 /* Reinit per-packet info for the next one. */ 1055 flags = seg_idx = pkt_len = 0; 1056 nic_i_start = -1; 1057 } 1058 1059 /* prefetch for next round */ 1060 __builtin_prefetch(&ring->slot[nm_i + 1]); 1061 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1062 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1063 1064 NM_CHECK_ADDR_LEN(na, addr, len); 1065 1066 if (slot->flags & NS_BUF_CHANGED) { 1067 /* buffer has changed, reload map */ 1068 netmap_reload_map(na, txq->ift_buf_tag, 1069 txq->ift_sds.ifsd_map[nic_i], addr); 1070 } 1071 /* make sure changes to the buffer are synced */ 1072 bus_dmamap_sync(txq->ift_buf_tag, 1073 txq->ift_sds.ifsd_map[nic_i], 1074 BUS_DMASYNC_PREWRITE); 1075 1076 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1077 nm_i = nm_next(nm_i, lim); 1078 nic_i = nm_next(nic_i, lim); 1079 } 1080 kring->nr_hwcur = nm_i; 1081 1082 /* synchronize the NIC ring */ 1083 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1084 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1085 1086 /* (re)start the tx unit up to slot nic_i (excluded) */ 1087 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1088 } 1089 1090 /* 1091 * Second part: reclaim buffers for completed transmissions. 1092 * 1093 * If there are unclaimed buffers, attempt to reclaim them. 1094 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1095 * trigger a per-tx-queue timer to try again later. 1096 */ 1097 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1098 if (iflib_tx_credits_update(ctx, txq)) { 1099 /* some tx completed, increment avail */ 1100 nic_i = txq->ift_cidx_processed; 1101 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1102 } 1103 } 1104 1105 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1106 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1107 callout_reset_sbt_on(&txq->ift_netmap_timer, 1108 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1109 iflib_netmap_timer, txq, 1110 txq->ift_netmap_timer.c_cpu, 0); 1111 } 1112 return (0); 1113 } 1114 1115 /* 1116 * Reconcile kernel and user view of the receive ring. 1117 * Same as for the txsync, this routine must be efficient. 1118 * The caller guarantees a single invocations, but races against 1119 * the rest of the driver should be handled here. 1120 * 1121 * On call, kring->rhead is the first packet that userspace wants 1122 * to keep, and kring->rcur is the wakeup point. 1123 * The kernel has previously reported packets up to kring->rtail. 1124 * 1125 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1126 * of whether or not we received an interrupt. 1127 */ 1128 static int 1129 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1130 { 1131 struct netmap_adapter *na = kring->na; 1132 struct netmap_ring *ring = kring->ring; 1133 if_t ifp = na->ifp; 1134 uint32_t nm_i; /* index into the netmap ring */ 1135 uint32_t nic_i; /* index into the NIC ring */ 1136 u_int n; 1137 u_int const lim = kring->nkr_num_slots - 1; 1138 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1139 int i = 0; 1140 1141 if_ctx_t ctx = ifp->if_softc; 1142 if_shared_ctx_t sctx = ctx->ifc_sctx; 1143 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1144 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1145 iflib_fl_t fl = &rxq->ifr_fl[0]; 1146 struct if_rxd_info ri; 1147 qidx_t *cidxp; 1148 1149 /* 1150 * netmap only uses free list 0, to avoid out of order consumption 1151 * of receive buffers 1152 */ 1153 1154 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1155 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1156 1157 /* 1158 * First part: import newly received packets. 1159 * 1160 * nm_i is the index of the next free slot in the netmap ring, 1161 * nic_i is the index of the next received packet in the NIC ring 1162 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1163 * differ in case if_init() has been called while 1164 * in netmap mode. For the receive ring we have 1165 * 1166 * nic_i = fl->ifl_cidx; 1167 * nm_i = kring->nr_hwtail (previous) 1168 * and 1169 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1170 * 1171 * fl->ifl_cidx is set to 0 on a ring reinit 1172 */ 1173 if (netmap_no_pendintr || force_update) { 1174 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1175 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1176 int crclen = iflib_crcstrip ? 0 : 4; 1177 int error, avail; 1178 1179 /* 1180 * For the free list consumer index, we use the same 1181 * logic as in iflib_rxeof(). 1182 */ 1183 if (have_rxcq) 1184 cidxp = &rxq->ifr_cq_cidx; 1185 else 1186 cidxp = &fl->ifl_cidx; 1187 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1188 rxq->ifr_id, *cidxp, USHRT_MAX); 1189 1190 nic_i = fl->ifl_cidx; 1191 nm_i = netmap_idx_n2k(kring, nic_i); 1192 MPASS(nm_i == kring->nr_hwtail); 1193 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1194 rxd_info_zero(&ri); 1195 ri.iri_frags = rxq->ifr_frags; 1196 ri.iri_qsidx = kring->ring_id; 1197 ri.iri_ifp = ctx->ifc_ifp; 1198 ri.iri_cidx = *cidxp; 1199 1200 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1201 for (i = 0; i < ri.iri_nfrags; i++) { 1202 if (error) { 1203 ring->slot[nm_i].len = 0; 1204 ring->slot[nm_i].flags = 0; 1205 } else { 1206 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1207 if (i == (ri.iri_nfrags - 1)) { 1208 ring->slot[nm_i].len -= crclen; 1209 ring->slot[nm_i].flags = 0; 1210 } else 1211 ring->slot[nm_i].flags = NS_MOREFRAG; 1212 } 1213 1214 bus_dmamap_sync(fl->ifl_buf_tag, 1215 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1216 nm_i = nm_next(nm_i, lim); 1217 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1218 } 1219 1220 if (have_rxcq) { 1221 *cidxp = ri.iri_cidx; 1222 while (*cidxp >= scctx->isc_nrxd[0]) 1223 *cidxp -= scctx->isc_nrxd[0]; 1224 } 1225 1226 } 1227 if (n) { /* update the state variables */ 1228 if (netmap_no_pendintr && !force_update) { 1229 /* diagnostics */ 1230 iflib_rx_miss ++; 1231 iflib_rx_miss_bufs += n; 1232 } 1233 kring->nr_hwtail = nm_i; 1234 } 1235 kring->nr_kflags &= ~NKR_PENDINTR; 1236 } 1237 /* 1238 * Second part: skip past packets that userspace has released. 1239 * (kring->nr_hwcur to head excluded), 1240 * and make the buffers available for reception. 1241 * As usual nm_i is the index in the netmap ring, 1242 * nic_i is the index in the NIC ring, and 1243 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1244 */ 1245 netmap_fl_refill(rxq, kring, false); 1246 1247 return (0); 1248 } 1249 1250 static void 1251 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1252 { 1253 if_ctx_t ctx = na->ifp->if_softc; 1254 1255 CTX_LOCK(ctx); 1256 if (onoff) { 1257 IFDI_INTR_ENABLE(ctx); 1258 } else { 1259 IFDI_INTR_DISABLE(ctx); 1260 } 1261 CTX_UNLOCK(ctx); 1262 } 1263 1264 static int 1265 iflib_netmap_attach(if_ctx_t ctx) 1266 { 1267 struct netmap_adapter na; 1268 1269 bzero(&na, sizeof(na)); 1270 1271 na.ifp = ctx->ifc_ifp; 1272 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG; 1273 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1274 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1275 1276 na.num_tx_desc = iflib_num_tx_descs(ctx); 1277 na.num_rx_desc = iflib_num_rx_descs(ctx); 1278 na.nm_txsync = iflib_netmap_txsync; 1279 na.nm_rxsync = iflib_netmap_rxsync; 1280 na.nm_register = iflib_netmap_register; 1281 na.nm_intr = iflib_netmap_intr; 1282 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1283 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1284 return (netmap_attach(&na)); 1285 } 1286 1287 static int 1288 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1289 { 1290 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1291 struct netmap_slot *slot; 1292 1293 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1294 if (slot == NULL) 1295 return (0); 1296 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1297 /* 1298 * In netmap mode, set the map for the packet buffer. 1299 * NOTE: Some drivers (not this one) also need to set 1300 * the physical buffer address in the NIC ring. 1301 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1302 * netmap slot index, si 1303 */ 1304 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1305 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1306 NMB(na, slot + si)); 1307 } 1308 return (1); 1309 } 1310 1311 static int 1312 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1313 { 1314 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1315 struct netmap_kring *kring; 1316 struct netmap_slot *slot; 1317 1318 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1319 if (slot == NULL) 1320 return (0); 1321 kring = na->rx_rings[rxq->ifr_id]; 1322 netmap_fl_refill(rxq, kring, true); 1323 return (1); 1324 } 1325 1326 static void 1327 iflib_netmap_timer(void *arg) 1328 { 1329 iflib_txq_t txq = arg; 1330 if_ctx_t ctx = txq->ift_ctx; 1331 1332 /* 1333 * Wake up the netmap application, to give it a chance to 1334 * call txsync and reclaim more completed TX buffers. 1335 */ 1336 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1337 } 1338 1339 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1340 1341 #else 1342 #define iflib_netmap_txq_init(ctx, txq) (0) 1343 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1344 #define iflib_netmap_detach(ifp) 1345 #define netmap_enable_all_rings(ifp) 1346 #define netmap_disable_all_rings(ifp) 1347 1348 #define iflib_netmap_attach(ctx) (0) 1349 #define netmap_rx_irq(ifp, qid, budget) (0) 1350 #endif 1351 1352 #if defined(__i386__) || defined(__amd64__) 1353 static __inline void 1354 prefetch(void *x) 1355 { 1356 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1357 } 1358 static __inline void 1359 prefetch2cachelines(void *x) 1360 { 1361 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1362 #if (CACHE_LINE_SIZE < 128) 1363 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1364 #endif 1365 } 1366 #else 1367 #define prefetch(x) 1368 #define prefetch2cachelines(x) 1369 #endif 1370 1371 static void 1372 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1373 { 1374 iflib_fl_t fl; 1375 1376 fl = &rxq->ifr_fl[flid]; 1377 iru->iru_paddrs = fl->ifl_bus_addrs; 1378 iru->iru_idxs = fl->ifl_rxd_idxs; 1379 iru->iru_qsidx = rxq->ifr_id; 1380 iru->iru_buf_size = fl->ifl_buf_size; 1381 iru->iru_flidx = fl->ifl_id; 1382 } 1383 1384 static void 1385 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1386 { 1387 if (err) 1388 return; 1389 *(bus_addr_t *) arg = segs[0].ds_addr; 1390 } 1391 1392 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1393 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1394 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1395 1396 int 1397 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1398 { 1399 int err; 1400 device_t dev = ctx->ifc_dev; 1401 bus_addr_t lowaddr; 1402 1403 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1404 1405 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1406 align, 0, /* alignment, bounds */ 1407 lowaddr, /* lowaddr */ 1408 BUS_SPACE_MAXADDR, /* highaddr */ 1409 NULL, NULL, /* filter, filterarg */ 1410 size, /* maxsize */ 1411 1, /* nsegments */ 1412 size, /* maxsegsize */ 1413 BUS_DMA_ALLOCNOW, /* flags */ 1414 NULL, /* lockfunc */ 1415 NULL, /* lockarg */ 1416 &dma->idi_tag); 1417 if (err) { 1418 device_printf(dev, 1419 "%s: bus_dma_tag_create failed: %d\n", 1420 __func__, err); 1421 goto fail_0; 1422 } 1423 1424 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1425 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1426 if (err) { 1427 device_printf(dev, 1428 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1429 __func__, (uintmax_t)size, err); 1430 goto fail_1; 1431 } 1432 1433 dma->idi_paddr = IF_BAD_DMA; 1434 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1435 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1436 if (err || dma->idi_paddr == IF_BAD_DMA) { 1437 device_printf(dev, 1438 "%s: bus_dmamap_load failed: %d\n", 1439 __func__, err); 1440 goto fail_2; 1441 } 1442 1443 dma->idi_size = size; 1444 return (0); 1445 1446 fail_2: 1447 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1448 fail_1: 1449 bus_dma_tag_destroy(dma->idi_tag); 1450 fail_0: 1451 dma->idi_tag = NULL; 1452 1453 return (err); 1454 } 1455 1456 int 1457 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1458 { 1459 if_shared_ctx_t sctx = ctx->ifc_sctx; 1460 1461 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1462 1463 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1464 } 1465 1466 int 1467 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1468 { 1469 int i, err; 1470 iflib_dma_info_t *dmaiter; 1471 1472 dmaiter = dmalist; 1473 for (i = 0; i < count; i++, dmaiter++) { 1474 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1475 break; 1476 } 1477 if (err) 1478 iflib_dma_free_multi(dmalist, i); 1479 return (err); 1480 } 1481 1482 void 1483 iflib_dma_free(iflib_dma_info_t dma) 1484 { 1485 if (dma->idi_tag == NULL) 1486 return; 1487 if (dma->idi_paddr != IF_BAD_DMA) { 1488 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1489 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1490 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1491 dma->idi_paddr = IF_BAD_DMA; 1492 } 1493 if (dma->idi_vaddr != NULL) { 1494 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1495 dma->idi_vaddr = NULL; 1496 } 1497 bus_dma_tag_destroy(dma->idi_tag); 1498 dma->idi_tag = NULL; 1499 } 1500 1501 void 1502 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1503 { 1504 int i; 1505 iflib_dma_info_t *dmaiter = dmalist; 1506 1507 for (i = 0; i < count; i++, dmaiter++) 1508 iflib_dma_free(*dmaiter); 1509 } 1510 1511 static int 1512 iflib_fast_intr(void *arg) 1513 { 1514 iflib_filter_info_t info = arg; 1515 struct grouptask *gtask = info->ifi_task; 1516 int result; 1517 1518 DBG_COUNTER_INC(fast_intrs); 1519 if (info->ifi_filter != NULL) { 1520 result = info->ifi_filter(info->ifi_filter_arg); 1521 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1522 return (result); 1523 } 1524 1525 GROUPTASK_ENQUEUE(gtask); 1526 return (FILTER_HANDLED); 1527 } 1528 1529 static int 1530 iflib_fast_intr_rxtx(void *arg) 1531 { 1532 iflib_filter_info_t info = arg; 1533 struct grouptask *gtask = info->ifi_task; 1534 if_ctx_t ctx; 1535 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1536 iflib_txq_t txq; 1537 void *sc; 1538 int i, cidx, result; 1539 qidx_t txqid; 1540 bool intr_enable, intr_legacy; 1541 1542 DBG_COUNTER_INC(fast_intrs); 1543 if (info->ifi_filter != NULL) { 1544 result = info->ifi_filter(info->ifi_filter_arg); 1545 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1546 return (result); 1547 } 1548 1549 ctx = rxq->ifr_ctx; 1550 sc = ctx->ifc_softc; 1551 intr_enable = false; 1552 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1553 MPASS(rxq->ifr_ntxqirq); 1554 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1555 txqid = rxq->ifr_txqid[i]; 1556 txq = &ctx->ifc_txqs[txqid]; 1557 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1558 BUS_DMASYNC_POSTREAD); 1559 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1560 if (intr_legacy) 1561 intr_enable = true; 1562 else 1563 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1564 continue; 1565 } 1566 GROUPTASK_ENQUEUE(&txq->ift_task); 1567 } 1568 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1569 cidx = rxq->ifr_cq_cidx; 1570 else 1571 cidx = rxq->ifr_fl[0].ifl_cidx; 1572 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1573 GROUPTASK_ENQUEUE(gtask); 1574 else { 1575 if (intr_legacy) 1576 intr_enable = true; 1577 else 1578 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1579 DBG_COUNTER_INC(rx_intr_enables); 1580 } 1581 if (intr_enable) 1582 IFDI_INTR_ENABLE(ctx); 1583 return (FILTER_HANDLED); 1584 } 1585 1586 static int 1587 iflib_fast_intr_ctx(void *arg) 1588 { 1589 iflib_filter_info_t info = arg; 1590 struct grouptask *gtask = info->ifi_task; 1591 int result; 1592 1593 DBG_COUNTER_INC(fast_intrs); 1594 if (info->ifi_filter != NULL) { 1595 result = info->ifi_filter(info->ifi_filter_arg); 1596 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1597 return (result); 1598 } 1599 1600 GROUPTASK_ENQUEUE(gtask); 1601 return (FILTER_HANDLED); 1602 } 1603 1604 static int 1605 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1606 driver_filter_t filter, driver_intr_t handler, void *arg, 1607 const char *name) 1608 { 1609 struct resource *res; 1610 void *tag = NULL; 1611 device_t dev = ctx->ifc_dev; 1612 int flags, i, rc; 1613 1614 flags = RF_ACTIVE; 1615 if (ctx->ifc_flags & IFC_LEGACY) 1616 flags |= RF_SHAREABLE; 1617 MPASS(rid < 512); 1618 i = rid; 1619 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1620 if (res == NULL) { 1621 device_printf(dev, 1622 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1623 return (ENOMEM); 1624 } 1625 irq->ii_res = res; 1626 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1627 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1628 filter, handler, arg, &tag); 1629 if (rc != 0) { 1630 device_printf(dev, 1631 "failed to setup interrupt for rid %d, name %s: %d\n", 1632 rid, name ? name : "unknown", rc); 1633 return (rc); 1634 } else if (name) 1635 bus_describe_intr(dev, res, tag, "%s", name); 1636 1637 irq->ii_tag = tag; 1638 return (0); 1639 } 1640 1641 /********************************************************************* 1642 * 1643 * Allocate DMA resources for TX buffers as well as memory for the TX 1644 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1645 * iflib_sw_tx_desc_array structure, storing all the information that 1646 * is needed to transmit a packet on the wire. This is called only 1647 * once at attach, setup is done every reset. 1648 * 1649 **********************************************************************/ 1650 static int 1651 iflib_txsd_alloc(iflib_txq_t txq) 1652 { 1653 if_ctx_t ctx = txq->ift_ctx; 1654 if_shared_ctx_t sctx = ctx->ifc_sctx; 1655 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1656 device_t dev = ctx->ifc_dev; 1657 bus_size_t tsomaxsize; 1658 bus_addr_t lowaddr; 1659 int err, nsegments, ntsosegments; 1660 bool tso; 1661 1662 nsegments = scctx->isc_tx_nsegments; 1663 ntsosegments = scctx->isc_tx_tso_segments_max; 1664 tsomaxsize = scctx->isc_tx_tso_size_max; 1665 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1666 tsomaxsize += sizeof(struct ether_vlan_header); 1667 MPASS(scctx->isc_ntxd[0] > 0); 1668 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1669 MPASS(nsegments > 0); 1670 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1671 MPASS(ntsosegments > 0); 1672 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1673 } 1674 1675 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1676 1677 /* 1678 * Set up DMA tags for TX buffers. 1679 */ 1680 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1681 1, 0, /* alignment, bounds */ 1682 lowaddr, /* lowaddr */ 1683 BUS_SPACE_MAXADDR, /* highaddr */ 1684 NULL, NULL, /* filter, filterarg */ 1685 sctx->isc_tx_maxsize, /* maxsize */ 1686 nsegments, /* nsegments */ 1687 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1688 0, /* flags */ 1689 NULL, /* lockfunc */ 1690 NULL, /* lockfuncarg */ 1691 &txq->ift_buf_tag))) { 1692 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1693 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1694 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1695 goto fail; 1696 } 1697 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1698 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1699 1, 0, /* alignment, bounds */ 1700 lowaddr, /* lowaddr */ 1701 BUS_SPACE_MAXADDR, /* highaddr */ 1702 NULL, NULL, /* filter, filterarg */ 1703 tsomaxsize, /* maxsize */ 1704 ntsosegments, /* nsegments */ 1705 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1706 0, /* flags */ 1707 NULL, /* lockfunc */ 1708 NULL, /* lockfuncarg */ 1709 &txq->ift_tso_buf_tag))) { 1710 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1711 err); 1712 goto fail; 1713 } 1714 1715 /* Allocate memory for the TX mbuf map. */ 1716 if (!(txq->ift_sds.ifsd_m = 1717 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1718 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1719 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1720 err = ENOMEM; 1721 goto fail; 1722 } 1723 1724 /* 1725 * Create the DMA maps for TX buffers. 1726 */ 1727 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1728 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1729 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1730 device_printf(dev, 1731 "Unable to allocate TX buffer DMA map memory\n"); 1732 err = ENOMEM; 1733 goto fail; 1734 } 1735 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1736 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1737 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1738 device_printf(dev, 1739 "Unable to allocate TSO TX buffer map memory\n"); 1740 err = ENOMEM; 1741 goto fail; 1742 } 1743 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1744 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1745 &txq->ift_sds.ifsd_map[i]); 1746 if (err != 0) { 1747 device_printf(dev, "Unable to create TX DMA map\n"); 1748 goto fail; 1749 } 1750 if (!tso) 1751 continue; 1752 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1753 &txq->ift_sds.ifsd_tso_map[i]); 1754 if (err != 0) { 1755 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1756 goto fail; 1757 } 1758 } 1759 return (0); 1760 fail: 1761 /* We free all, it handles case where we are in the middle */ 1762 iflib_tx_structures_free(ctx); 1763 return (err); 1764 } 1765 1766 static void 1767 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1768 { 1769 bus_dmamap_t map; 1770 1771 if (txq->ift_sds.ifsd_map != NULL) { 1772 map = txq->ift_sds.ifsd_map[i]; 1773 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1774 bus_dmamap_unload(txq->ift_buf_tag, map); 1775 bus_dmamap_destroy(txq->ift_buf_tag, map); 1776 txq->ift_sds.ifsd_map[i] = NULL; 1777 } 1778 1779 if (txq->ift_sds.ifsd_tso_map != NULL) { 1780 map = txq->ift_sds.ifsd_tso_map[i]; 1781 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1782 BUS_DMASYNC_POSTWRITE); 1783 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1784 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1785 txq->ift_sds.ifsd_tso_map[i] = NULL; 1786 } 1787 } 1788 1789 static void 1790 iflib_txq_destroy(iflib_txq_t txq) 1791 { 1792 if_ctx_t ctx = txq->ift_ctx; 1793 1794 for (int i = 0; i < txq->ift_size; i++) 1795 iflib_txsd_destroy(ctx, txq, i); 1796 1797 if (txq->ift_br != NULL) { 1798 ifmp_ring_free(txq->ift_br); 1799 txq->ift_br = NULL; 1800 } 1801 1802 mtx_destroy(&txq->ift_mtx); 1803 1804 if (txq->ift_sds.ifsd_map != NULL) { 1805 free(txq->ift_sds.ifsd_map, M_IFLIB); 1806 txq->ift_sds.ifsd_map = NULL; 1807 } 1808 if (txq->ift_sds.ifsd_tso_map != NULL) { 1809 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1810 txq->ift_sds.ifsd_tso_map = NULL; 1811 } 1812 if (txq->ift_sds.ifsd_m != NULL) { 1813 free(txq->ift_sds.ifsd_m, M_IFLIB); 1814 txq->ift_sds.ifsd_m = NULL; 1815 } 1816 if (txq->ift_buf_tag != NULL) { 1817 bus_dma_tag_destroy(txq->ift_buf_tag); 1818 txq->ift_buf_tag = NULL; 1819 } 1820 if (txq->ift_tso_buf_tag != NULL) { 1821 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1822 txq->ift_tso_buf_tag = NULL; 1823 } 1824 if (txq->ift_ifdi != NULL) { 1825 free(txq->ift_ifdi, M_IFLIB); 1826 } 1827 } 1828 1829 static void 1830 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1831 { 1832 struct mbuf **mp; 1833 1834 mp = &txq->ift_sds.ifsd_m[i]; 1835 if (*mp == NULL) 1836 return; 1837 1838 if (txq->ift_sds.ifsd_map != NULL) { 1839 bus_dmamap_sync(txq->ift_buf_tag, 1840 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1841 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1842 } 1843 if (txq->ift_sds.ifsd_tso_map != NULL) { 1844 bus_dmamap_sync(txq->ift_tso_buf_tag, 1845 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1846 bus_dmamap_unload(txq->ift_tso_buf_tag, 1847 txq->ift_sds.ifsd_tso_map[i]); 1848 } 1849 m_freem(*mp); 1850 DBG_COUNTER_INC(tx_frees); 1851 *mp = NULL; 1852 } 1853 1854 static int 1855 iflib_txq_setup(iflib_txq_t txq) 1856 { 1857 if_ctx_t ctx = txq->ift_ctx; 1858 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1859 if_shared_ctx_t sctx = ctx->ifc_sctx; 1860 iflib_dma_info_t di; 1861 int i; 1862 1863 /* Set number of descriptors available */ 1864 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1865 /* XXX make configurable */ 1866 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1867 1868 /* Reset indices */ 1869 txq->ift_cidx_processed = 0; 1870 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1871 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1872 1873 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1874 bzero((void *)di->idi_vaddr, di->idi_size); 1875 1876 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1877 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1878 bus_dmamap_sync(di->idi_tag, di->idi_map, 1879 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1880 return (0); 1881 } 1882 1883 /********************************************************************* 1884 * 1885 * Allocate DMA resources for RX buffers as well as memory for the RX 1886 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1887 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1888 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1889 * Since we use use one entry in iflib_sw_rx_desc_array per received 1890 * packet, the maximum number of entries we'll need is equal to the 1891 * number of hardware receive descriptors that we've allocated. 1892 * 1893 **********************************************************************/ 1894 static int 1895 iflib_rxsd_alloc(iflib_rxq_t rxq) 1896 { 1897 if_ctx_t ctx = rxq->ifr_ctx; 1898 if_shared_ctx_t sctx = ctx->ifc_sctx; 1899 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1900 device_t dev = ctx->ifc_dev; 1901 iflib_fl_t fl; 1902 bus_addr_t lowaddr; 1903 int err; 1904 1905 MPASS(scctx->isc_nrxd[0] > 0); 1906 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1907 1908 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1909 1910 fl = rxq->ifr_fl; 1911 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1912 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1913 /* Set up DMA tag for RX buffers. */ 1914 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1915 1, 0, /* alignment, bounds */ 1916 lowaddr, /* lowaddr */ 1917 BUS_SPACE_MAXADDR, /* highaddr */ 1918 NULL, NULL, /* filter, filterarg */ 1919 sctx->isc_rx_maxsize, /* maxsize */ 1920 sctx->isc_rx_nsegments, /* nsegments */ 1921 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1922 0, /* flags */ 1923 NULL, /* lockfunc */ 1924 NULL, /* lockarg */ 1925 &fl->ifl_buf_tag); 1926 if (err) { 1927 device_printf(dev, 1928 "Unable to allocate RX DMA tag: %d\n", err); 1929 goto fail; 1930 } 1931 1932 /* Allocate memory for the RX mbuf map. */ 1933 if (!(fl->ifl_sds.ifsd_m = 1934 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1935 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1936 device_printf(dev, 1937 "Unable to allocate RX mbuf map memory\n"); 1938 err = ENOMEM; 1939 goto fail; 1940 } 1941 1942 /* Allocate memory for the direct RX cluster pointer map. */ 1943 if (!(fl->ifl_sds.ifsd_cl = 1944 (caddr_t *) malloc(sizeof(caddr_t) * 1945 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1946 device_printf(dev, 1947 "Unable to allocate RX cluster map memory\n"); 1948 err = ENOMEM; 1949 goto fail; 1950 } 1951 1952 /* Allocate memory for the RX cluster bus address map. */ 1953 if (!(fl->ifl_sds.ifsd_ba = 1954 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1955 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1956 device_printf(dev, 1957 "Unable to allocate RX bus address map memory\n"); 1958 err = ENOMEM; 1959 goto fail; 1960 } 1961 1962 /* 1963 * Create the DMA maps for RX buffers. 1964 */ 1965 if (!(fl->ifl_sds.ifsd_map = 1966 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1967 device_printf(dev, 1968 "Unable to allocate RX buffer DMA map memory\n"); 1969 err = ENOMEM; 1970 goto fail; 1971 } 1972 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1973 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1974 &fl->ifl_sds.ifsd_map[i]); 1975 if (err != 0) { 1976 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1977 goto fail; 1978 } 1979 } 1980 } 1981 return (0); 1982 1983 fail: 1984 iflib_rx_structures_free(ctx); 1985 return (err); 1986 } 1987 1988 /* 1989 * Internal service routines 1990 */ 1991 1992 struct rxq_refill_cb_arg { 1993 int error; 1994 bus_dma_segment_t seg; 1995 int nseg; 1996 }; 1997 1998 static void 1999 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2000 { 2001 struct rxq_refill_cb_arg *cb_arg = arg; 2002 2003 cb_arg->error = error; 2004 cb_arg->seg = segs[0]; 2005 cb_arg->nseg = nseg; 2006 } 2007 2008 /** 2009 * iflib_fl_refill - refill an rxq free-buffer list 2010 * @ctx: the iflib context 2011 * @fl: the free list to refill 2012 * @count: the number of new buffers to allocate 2013 * 2014 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2015 * The caller must assure that @count does not exceed the queue's capacity 2016 * minus one (since we always leave a descriptor unavailable). 2017 */ 2018 static uint8_t 2019 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2020 { 2021 struct if_rxd_update iru; 2022 struct rxq_refill_cb_arg cb_arg; 2023 struct mbuf *m; 2024 caddr_t cl, *sd_cl; 2025 struct mbuf **sd_m; 2026 bus_dmamap_t *sd_map; 2027 bus_addr_t bus_addr, *sd_ba; 2028 int err, frag_idx, i, idx, n, pidx; 2029 qidx_t credits; 2030 2031 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2032 2033 sd_m = fl->ifl_sds.ifsd_m; 2034 sd_map = fl->ifl_sds.ifsd_map; 2035 sd_cl = fl->ifl_sds.ifsd_cl; 2036 sd_ba = fl->ifl_sds.ifsd_ba; 2037 pidx = fl->ifl_pidx; 2038 idx = pidx; 2039 frag_idx = fl->ifl_fragidx; 2040 credits = fl->ifl_credits; 2041 2042 i = 0; 2043 n = count; 2044 MPASS(n > 0); 2045 MPASS(credits + n <= fl->ifl_size); 2046 2047 if (pidx < fl->ifl_cidx) 2048 MPASS(pidx + n <= fl->ifl_cidx); 2049 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2050 MPASS(fl->ifl_gen == 0); 2051 if (pidx > fl->ifl_cidx) 2052 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2053 2054 DBG_COUNTER_INC(fl_refills); 2055 if (n > 8) 2056 DBG_COUNTER_INC(fl_refills_large); 2057 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2058 while (n-- > 0) { 2059 /* 2060 * We allocate an uninitialized mbuf + cluster, mbuf is 2061 * initialized after rx. 2062 * 2063 * If the cluster is still set then we know a minimum sized 2064 * packet was received 2065 */ 2066 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2067 &frag_idx); 2068 if (frag_idx < 0) 2069 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2070 MPASS(frag_idx >= 0); 2071 if ((cl = sd_cl[frag_idx]) == NULL) { 2072 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2073 if (__predict_false(cl == NULL)) 2074 break; 2075 2076 cb_arg.error = 0; 2077 MPASS(sd_map != NULL); 2078 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2079 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2080 BUS_DMA_NOWAIT); 2081 if (__predict_false(err != 0 || cb_arg.error)) { 2082 uma_zfree(fl->ifl_zone, cl); 2083 break; 2084 } 2085 2086 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2087 sd_cl[frag_idx] = cl; 2088 #if MEMORY_LOGGING 2089 fl->ifl_cl_enqueued++; 2090 #endif 2091 } else { 2092 bus_addr = sd_ba[frag_idx]; 2093 } 2094 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2095 BUS_DMASYNC_PREREAD); 2096 2097 if (sd_m[frag_idx] == NULL) { 2098 m = m_gethdr(M_NOWAIT, MT_NOINIT); 2099 if (__predict_false(m == NULL)) 2100 break; 2101 sd_m[frag_idx] = m; 2102 } 2103 bit_set(fl->ifl_rx_bitmap, frag_idx); 2104 #if MEMORY_LOGGING 2105 fl->ifl_m_enqueued++; 2106 #endif 2107 2108 DBG_COUNTER_INC(rx_allocs); 2109 fl->ifl_rxd_idxs[i] = frag_idx; 2110 fl->ifl_bus_addrs[i] = bus_addr; 2111 credits++; 2112 i++; 2113 MPASS(credits <= fl->ifl_size); 2114 if (++idx == fl->ifl_size) { 2115 #ifdef INVARIANTS 2116 fl->ifl_gen = 1; 2117 #endif 2118 idx = 0; 2119 } 2120 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2121 iru.iru_pidx = pidx; 2122 iru.iru_count = i; 2123 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2124 fl->ifl_pidx = idx; 2125 fl->ifl_credits = credits; 2126 pidx = idx; 2127 i = 0; 2128 } 2129 } 2130 2131 if (n < count - 1) { 2132 if (i != 0) { 2133 iru.iru_pidx = pidx; 2134 iru.iru_count = i; 2135 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2136 fl->ifl_pidx = idx; 2137 fl->ifl_credits = credits; 2138 } 2139 DBG_COUNTER_INC(rxd_flush); 2140 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2141 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2142 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2143 fl->ifl_id, fl->ifl_pidx); 2144 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2145 fl->ifl_fragidx = frag_idx + 1; 2146 if (fl->ifl_fragidx == fl->ifl_size) 2147 fl->ifl_fragidx = 0; 2148 } else { 2149 fl->ifl_fragidx = frag_idx; 2150 } 2151 } 2152 2153 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2154 } 2155 2156 static inline uint8_t 2157 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2158 { 2159 /* 2160 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2161 * This is important as it confuses most NICs. For instance, 2162 * Intel NICs have (per receive ring) RDH and RDT registers, where 2163 * RDH points to the next receive descriptor to be used by the NIC, 2164 * and RDT for the next receive descriptor to be published by the 2165 * driver to the NIC (RDT - 1 is thus the last valid one). 2166 * The condition RDH == RDT means no descriptors are available to 2167 * the NIC, and thus it would be ambiguous if it also meant that 2168 * all the descriptors are available to the NIC. 2169 */ 2170 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2171 #ifdef INVARIANTS 2172 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2173 #endif 2174 2175 MPASS(fl->ifl_credits <= fl->ifl_size); 2176 MPASS(reclaimable == delta); 2177 2178 if (reclaimable > 0) 2179 return (iflib_fl_refill(ctx, fl, reclaimable)); 2180 return (0); 2181 } 2182 2183 uint8_t 2184 iflib_in_detach(if_ctx_t ctx) 2185 { 2186 bool in_detach; 2187 2188 STATE_LOCK(ctx); 2189 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2190 STATE_UNLOCK(ctx); 2191 return (in_detach); 2192 } 2193 2194 static void 2195 iflib_fl_bufs_free(iflib_fl_t fl) 2196 { 2197 iflib_dma_info_t idi = fl->ifl_ifdi; 2198 bus_dmamap_t sd_map; 2199 uint32_t i; 2200 2201 for (i = 0; i < fl->ifl_size; i++) { 2202 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2203 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2204 2205 if (*sd_cl != NULL) { 2206 sd_map = fl->ifl_sds.ifsd_map[i]; 2207 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2208 BUS_DMASYNC_POSTREAD); 2209 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2210 uma_zfree(fl->ifl_zone, *sd_cl); 2211 *sd_cl = NULL; 2212 if (*sd_m != NULL) { 2213 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2214 uma_zfree(zone_mbuf, *sd_m); 2215 *sd_m = NULL; 2216 } 2217 } else { 2218 MPASS(*sd_m == NULL); 2219 } 2220 #if MEMORY_LOGGING 2221 fl->ifl_m_dequeued++; 2222 fl->ifl_cl_dequeued++; 2223 #endif 2224 } 2225 #ifdef INVARIANTS 2226 for (i = 0; i < fl->ifl_size; i++) { 2227 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2228 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2229 } 2230 #endif 2231 /* 2232 * Reset free list values 2233 */ 2234 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2235 bzero(idi->idi_vaddr, idi->idi_size); 2236 } 2237 2238 /********************************************************************* 2239 * 2240 * Initialize a free list and its buffers. 2241 * 2242 **********************************************************************/ 2243 static int 2244 iflib_fl_setup(iflib_fl_t fl) 2245 { 2246 iflib_rxq_t rxq = fl->ifl_rxq; 2247 if_ctx_t ctx = rxq->ifr_ctx; 2248 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2249 int qidx; 2250 2251 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2252 /* 2253 ** Free current RX buffer structs and their mbufs 2254 */ 2255 iflib_fl_bufs_free(fl); 2256 /* Now replenish the mbufs */ 2257 MPASS(fl->ifl_credits == 0); 2258 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2259 if (scctx->isc_rxd_buf_size[qidx] != 0) 2260 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2261 else 2262 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2263 /* 2264 * ifl_buf_size may be a driver-supplied value, so pull it up 2265 * to the selected mbuf size. 2266 */ 2267 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2268 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2269 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2270 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2271 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2272 2273 /* 2274 * Avoid pre-allocating zillions of clusters to an idle card 2275 * potentially speeding up attach. In any case make sure 2276 * to leave a descriptor unavailable. See the comment in 2277 * iflib_fl_refill_all(). 2278 */ 2279 MPASS(fl->ifl_size > 0); 2280 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2281 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2282 return (ENOBUFS); 2283 /* 2284 * handle failure 2285 */ 2286 MPASS(rxq != NULL); 2287 MPASS(fl->ifl_ifdi != NULL); 2288 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2289 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2290 return (0); 2291 } 2292 2293 /********************************************************************* 2294 * 2295 * Free receive ring data structures 2296 * 2297 **********************************************************************/ 2298 static void 2299 iflib_rx_sds_free(iflib_rxq_t rxq) 2300 { 2301 iflib_fl_t fl; 2302 int i, j; 2303 2304 if (rxq->ifr_fl != NULL) { 2305 for (i = 0; i < rxq->ifr_nfl; i++) { 2306 fl = &rxq->ifr_fl[i]; 2307 if (fl->ifl_buf_tag != NULL) { 2308 if (fl->ifl_sds.ifsd_map != NULL) { 2309 for (j = 0; j < fl->ifl_size; j++) { 2310 bus_dmamap_sync( 2311 fl->ifl_buf_tag, 2312 fl->ifl_sds.ifsd_map[j], 2313 BUS_DMASYNC_POSTREAD); 2314 bus_dmamap_unload( 2315 fl->ifl_buf_tag, 2316 fl->ifl_sds.ifsd_map[j]); 2317 bus_dmamap_destroy( 2318 fl->ifl_buf_tag, 2319 fl->ifl_sds.ifsd_map[j]); 2320 } 2321 } 2322 bus_dma_tag_destroy(fl->ifl_buf_tag); 2323 fl->ifl_buf_tag = NULL; 2324 } 2325 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2326 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2327 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2328 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2329 free(fl->ifl_rx_bitmap, M_IFLIB); 2330 fl->ifl_sds.ifsd_m = NULL; 2331 fl->ifl_sds.ifsd_cl = NULL; 2332 fl->ifl_sds.ifsd_ba = NULL; 2333 fl->ifl_sds.ifsd_map = NULL; 2334 fl->ifl_rx_bitmap = NULL; 2335 } 2336 free(rxq->ifr_fl, M_IFLIB); 2337 rxq->ifr_fl = NULL; 2338 free(rxq->ifr_ifdi, M_IFLIB); 2339 rxq->ifr_ifdi = NULL; 2340 rxq->ifr_cq_cidx = 0; 2341 } 2342 } 2343 2344 /* 2345 * Timer routine 2346 */ 2347 static void 2348 iflib_timer(void *arg) 2349 { 2350 iflib_txq_t txq = arg; 2351 if_ctx_t ctx = txq->ift_ctx; 2352 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2353 uint64_t this_tick = ticks; 2354 2355 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2356 return; 2357 2358 /* 2359 ** Check on the state of the TX queue(s), this 2360 ** can be done without the lock because its RO 2361 ** and the HUNG state will be static if set. 2362 */ 2363 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2364 txq->ift_last_timer_tick = this_tick; 2365 IFDI_TIMER(ctx, txq->ift_id); 2366 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2367 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2368 (sctx->isc_pause_frames == 0))) 2369 goto hung; 2370 2371 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2372 ifmp_ring_is_stalled(txq->ift_br)) { 2373 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2374 ("queue can't be marked as hung if interface is down")); 2375 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2376 } 2377 txq->ift_cleaned_prev = txq->ift_cleaned; 2378 } 2379 /* handle any laggards */ 2380 if (txq->ift_db_pending) 2381 GROUPTASK_ENQUEUE(&txq->ift_task); 2382 2383 sctx->isc_pause_frames = 0; 2384 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2385 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2386 txq, txq->ift_timer.c_cpu); 2387 return; 2388 2389 hung: 2390 device_printf(ctx->ifc_dev, 2391 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2392 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2393 STATE_LOCK(ctx); 2394 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2395 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2396 iflib_admin_intr_deferred(ctx); 2397 STATE_UNLOCK(ctx); 2398 } 2399 2400 static uint16_t 2401 iflib_get_mbuf_size_for(unsigned int size) 2402 { 2403 2404 if (size <= MCLBYTES) 2405 return (MCLBYTES); 2406 else 2407 return (MJUMPAGESIZE); 2408 } 2409 2410 static void 2411 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2412 { 2413 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2414 2415 /* 2416 * XXX don't set the max_frame_size to larger 2417 * than the hardware can handle 2418 */ 2419 ctx->ifc_rx_mbuf_sz = 2420 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2421 } 2422 2423 uint32_t 2424 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2425 { 2426 2427 return (ctx->ifc_rx_mbuf_sz); 2428 } 2429 2430 static void 2431 iflib_init_locked(if_ctx_t ctx) 2432 { 2433 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2434 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2435 if_t ifp = ctx->ifc_ifp; 2436 iflib_fl_t fl; 2437 iflib_txq_t txq; 2438 iflib_rxq_t rxq; 2439 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2440 2441 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2442 IFDI_INTR_DISABLE(ctx); 2443 2444 /* 2445 * See iflib_stop(). Useful in case iflib_init_locked() is 2446 * called without first calling iflib_stop(). 2447 */ 2448 netmap_disable_all_rings(ifp); 2449 2450 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2451 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2452 /* Set hardware offload abilities */ 2453 if_clearhwassist(ifp); 2454 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2455 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2456 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2457 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2458 if (if_getcapenable(ifp) & IFCAP_TSO4) 2459 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2460 if (if_getcapenable(ifp) & IFCAP_TSO6) 2461 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2462 2463 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2464 CALLOUT_LOCK(txq); 2465 callout_stop(&txq->ift_timer); 2466 #ifdef DEV_NETMAP 2467 callout_stop(&txq->ift_netmap_timer); 2468 #endif /* DEV_NETMAP */ 2469 CALLOUT_UNLOCK(txq); 2470 (void)iflib_netmap_txq_init(ctx, txq); 2471 } 2472 2473 /* 2474 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2475 * that drivers can use the value when setting up the hardware receive 2476 * buffers. 2477 */ 2478 iflib_calc_rx_mbuf_sz(ctx); 2479 2480 #ifdef INVARIANTS 2481 i = if_getdrvflags(ifp); 2482 #endif 2483 IFDI_INIT(ctx); 2484 MPASS(if_getdrvflags(ifp) == i); 2485 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2486 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2487 /* This rxq is in netmap mode. Skip normal init. */ 2488 continue; 2489 } 2490 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2491 if (iflib_fl_setup(fl)) { 2492 device_printf(ctx->ifc_dev, 2493 "setting up free list %d failed - " 2494 "check cluster settings\n", j); 2495 goto done; 2496 } 2497 } 2498 } 2499 done: 2500 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2501 IFDI_INTR_ENABLE(ctx); 2502 txq = ctx->ifc_txqs; 2503 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2504 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2505 txq->ift_timer.c_cpu); 2506 2507 /* Re-enable txsync/rxsync. */ 2508 netmap_enable_all_rings(ifp); 2509 } 2510 2511 static int 2512 iflib_media_change(if_t ifp) 2513 { 2514 if_ctx_t ctx = if_getsoftc(ifp); 2515 int err; 2516 2517 CTX_LOCK(ctx); 2518 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2519 iflib_if_init_locked(ctx); 2520 CTX_UNLOCK(ctx); 2521 return (err); 2522 } 2523 2524 static void 2525 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2526 { 2527 if_ctx_t ctx = if_getsoftc(ifp); 2528 2529 CTX_LOCK(ctx); 2530 IFDI_UPDATE_ADMIN_STATUS(ctx); 2531 IFDI_MEDIA_STATUS(ctx, ifmr); 2532 CTX_UNLOCK(ctx); 2533 } 2534 2535 void 2536 iflib_stop(if_ctx_t ctx) 2537 { 2538 iflib_txq_t txq = ctx->ifc_txqs; 2539 iflib_rxq_t rxq = ctx->ifc_rxqs; 2540 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2541 if_shared_ctx_t sctx = ctx->ifc_sctx; 2542 iflib_dma_info_t di; 2543 iflib_fl_t fl; 2544 int i, j; 2545 2546 /* Tell the stack that the interface is no longer active */ 2547 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2548 2549 IFDI_INTR_DISABLE(ctx); 2550 DELAY(1000); 2551 IFDI_STOP(ctx); 2552 DELAY(1000); 2553 2554 /* 2555 * Stop any pending txsync/rxsync and prevent new ones 2556 * form starting. Processes blocked in poll() will get 2557 * POLLERR. 2558 */ 2559 netmap_disable_all_rings(ctx->ifc_ifp); 2560 2561 iflib_debug_reset(); 2562 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2563 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2564 /* make sure all transmitters have completed before proceeding XXX */ 2565 2566 CALLOUT_LOCK(txq); 2567 callout_stop(&txq->ift_timer); 2568 #ifdef DEV_NETMAP 2569 callout_stop(&txq->ift_netmap_timer); 2570 #endif /* DEV_NETMAP */ 2571 CALLOUT_UNLOCK(txq); 2572 2573 /* clean any enqueued buffers */ 2574 iflib_ifmp_purge(txq); 2575 /* Free any existing tx buffers. */ 2576 for (j = 0; j < txq->ift_size; j++) { 2577 iflib_txsd_free(ctx, txq, j); 2578 } 2579 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2580 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2581 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2582 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2583 txq->ift_pullups = 0; 2584 ifmp_ring_reset_stats(txq->ift_br); 2585 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2586 bzero((void *)di->idi_vaddr, di->idi_size); 2587 } 2588 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2589 /* make sure all transmitters have completed before proceeding XXX */ 2590 2591 rxq->ifr_cq_cidx = 0; 2592 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2593 bzero((void *)di->idi_vaddr, di->idi_size); 2594 /* also resets the free lists pidx/cidx */ 2595 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2596 iflib_fl_bufs_free(fl); 2597 } 2598 } 2599 2600 static inline caddr_t 2601 calc_next_rxd(iflib_fl_t fl, int cidx) 2602 { 2603 qidx_t size; 2604 int nrxd; 2605 caddr_t start, end, cur, next; 2606 2607 nrxd = fl->ifl_size; 2608 size = fl->ifl_rxd_size; 2609 start = fl->ifl_ifdi->idi_vaddr; 2610 2611 if (__predict_false(size == 0)) 2612 return (start); 2613 cur = start + size*cidx; 2614 end = start + size*nrxd; 2615 next = CACHE_PTR_NEXT(cur); 2616 return (next < end ? next : start); 2617 } 2618 2619 static inline void 2620 prefetch_pkts(iflib_fl_t fl, int cidx) 2621 { 2622 int nextptr; 2623 int nrxd = fl->ifl_size; 2624 caddr_t next_rxd; 2625 2626 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2627 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2628 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2629 next_rxd = calc_next_rxd(fl, cidx); 2630 prefetch(next_rxd); 2631 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2632 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2633 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2634 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2635 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2636 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2637 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2638 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2639 } 2640 2641 static struct mbuf * 2642 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2643 int *pf_rv, if_rxd_info_t ri) 2644 { 2645 bus_dmamap_t map; 2646 iflib_fl_t fl; 2647 caddr_t payload; 2648 struct mbuf *m; 2649 int flid, cidx, len, next; 2650 2651 map = NULL; 2652 flid = irf->irf_flid; 2653 cidx = irf->irf_idx; 2654 fl = &rxq->ifr_fl[flid]; 2655 sd->ifsd_fl = fl; 2656 m = fl->ifl_sds.ifsd_m[cidx]; 2657 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2658 fl->ifl_credits--; 2659 #if MEMORY_LOGGING 2660 fl->ifl_m_dequeued++; 2661 #endif 2662 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2663 prefetch_pkts(fl, cidx); 2664 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2665 prefetch(&fl->ifl_sds.ifsd_map[next]); 2666 map = fl->ifl_sds.ifsd_map[cidx]; 2667 2668 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2669 2670 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2671 irf->irf_len != 0) { 2672 payload = *sd->ifsd_cl; 2673 payload += ri->iri_pad; 2674 len = ri->iri_len - ri->iri_pad; 2675 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2676 len | PFIL_MEMPTR | PFIL_IN, NULL); 2677 switch (*pf_rv) { 2678 case PFIL_DROPPED: 2679 case PFIL_CONSUMED: 2680 /* 2681 * The filter ate it. Everything is recycled. 2682 */ 2683 m = NULL; 2684 unload = 0; 2685 break; 2686 case PFIL_REALLOCED: 2687 /* 2688 * The filter copied it. Everything is recycled. 2689 */ 2690 m = pfil_mem2mbuf(payload); 2691 unload = 0; 2692 break; 2693 case PFIL_PASS: 2694 /* 2695 * Filter said it was OK, so receive like 2696 * normal 2697 */ 2698 fl->ifl_sds.ifsd_m[cidx] = NULL; 2699 break; 2700 default: 2701 MPASS(0); 2702 } 2703 } else { 2704 fl->ifl_sds.ifsd_m[cidx] = NULL; 2705 if (pf_rv != NULL) 2706 *pf_rv = PFIL_PASS; 2707 } 2708 2709 if (unload && irf->irf_len != 0) 2710 bus_dmamap_unload(fl->ifl_buf_tag, map); 2711 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2712 if (__predict_false(fl->ifl_cidx == 0)) 2713 fl->ifl_gen = 0; 2714 bit_clear(fl->ifl_rx_bitmap, cidx); 2715 return (m); 2716 } 2717 2718 static struct mbuf * 2719 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2720 { 2721 struct mbuf *m, *mh, *mt; 2722 caddr_t cl; 2723 int *pf_rv_ptr, flags, i, padlen; 2724 bool consumed; 2725 2726 i = 0; 2727 mh = NULL; 2728 consumed = false; 2729 *pf_rv = PFIL_PASS; 2730 pf_rv_ptr = pf_rv; 2731 do { 2732 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2733 pf_rv_ptr, ri); 2734 2735 MPASS(*sd->ifsd_cl != NULL); 2736 2737 /* 2738 * Exclude zero-length frags & frags from 2739 * packets the filter has consumed or dropped 2740 */ 2741 if (ri->iri_frags[i].irf_len == 0 || consumed || 2742 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2743 if (mh == NULL) { 2744 /* everything saved here */ 2745 consumed = true; 2746 pf_rv_ptr = NULL; 2747 continue; 2748 } 2749 /* XXX we can save the cluster here, but not the mbuf */ 2750 m_init(m, M_NOWAIT, MT_DATA, 0); 2751 m_free(m); 2752 continue; 2753 } 2754 if (mh == NULL) { 2755 flags = M_PKTHDR|M_EXT; 2756 mh = mt = m; 2757 padlen = ri->iri_pad; 2758 } else { 2759 flags = M_EXT; 2760 mt->m_next = m; 2761 mt = m; 2762 /* assuming padding is only on the first fragment */ 2763 padlen = 0; 2764 } 2765 cl = *sd->ifsd_cl; 2766 *sd->ifsd_cl = NULL; 2767 2768 /* Can these two be made one ? */ 2769 m_init(m, M_NOWAIT, MT_DATA, flags); 2770 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2771 /* 2772 * These must follow m_init and m_cljset 2773 */ 2774 m->m_data += padlen; 2775 ri->iri_len -= padlen; 2776 m->m_len = ri->iri_frags[i].irf_len; 2777 } while (++i < ri->iri_nfrags); 2778 2779 return (mh); 2780 } 2781 2782 /* 2783 * Process one software descriptor 2784 */ 2785 static struct mbuf * 2786 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2787 { 2788 struct if_rxsd sd; 2789 struct mbuf *m; 2790 int pf_rv; 2791 2792 /* should I merge this back in now that the two paths are basically duplicated? */ 2793 if (ri->iri_nfrags == 1 && 2794 ri->iri_frags[0].irf_len != 0 && 2795 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2796 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2797 &pf_rv, ri); 2798 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2799 return (m); 2800 if (pf_rv == PFIL_PASS) { 2801 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2802 #ifndef __NO_STRICT_ALIGNMENT 2803 if (!IP_ALIGNED(m)) 2804 m->m_data += 2; 2805 #endif 2806 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2807 m->m_len = ri->iri_frags[0].irf_len; 2808 } 2809 } else { 2810 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2811 if (m == NULL) 2812 return (NULL); 2813 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2814 return (m); 2815 } 2816 m->m_pkthdr.len = ri->iri_len; 2817 m->m_pkthdr.rcvif = ri->iri_ifp; 2818 m->m_flags |= ri->iri_flags; 2819 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2820 m->m_pkthdr.flowid = ri->iri_flowid; 2821 M_HASHTYPE_SET(m, ri->iri_rsstype); 2822 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2823 m->m_pkthdr.csum_data = ri->iri_csum_data; 2824 return (m); 2825 } 2826 2827 #if defined(INET6) || defined(INET) 2828 static void 2829 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2830 { 2831 CURVNET_SET(lc->ifp->if_vnet); 2832 #if defined(INET6) 2833 *v6 = V_ip6_forwarding; 2834 #endif 2835 #if defined(INET) 2836 *v4 = V_ipforwarding; 2837 #endif 2838 CURVNET_RESTORE(); 2839 } 2840 2841 /* 2842 * Returns true if it's possible this packet could be LROed. 2843 * if it returns false, it is guaranteed that tcp_lro_rx() 2844 * would not return zero. 2845 */ 2846 static bool 2847 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2848 { 2849 struct ether_header *eh; 2850 2851 eh = mtod(m, struct ether_header *); 2852 switch (eh->ether_type) { 2853 #if defined(INET6) 2854 case htons(ETHERTYPE_IPV6): 2855 return (!v6_forwarding); 2856 #endif 2857 #if defined (INET) 2858 case htons(ETHERTYPE_IP): 2859 return (!v4_forwarding); 2860 #endif 2861 } 2862 2863 return false; 2864 } 2865 #else 2866 static void 2867 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2868 { 2869 } 2870 #endif 2871 2872 static void 2873 _task_fn_rx_watchdog(void *context) 2874 { 2875 iflib_rxq_t rxq = context; 2876 2877 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2878 } 2879 2880 static uint8_t 2881 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2882 { 2883 if_t ifp; 2884 if_ctx_t ctx = rxq->ifr_ctx; 2885 if_shared_ctx_t sctx = ctx->ifc_sctx; 2886 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2887 int avail, i; 2888 qidx_t *cidxp; 2889 struct if_rxd_info ri; 2890 int err, budget_left, rx_bytes, rx_pkts; 2891 iflib_fl_t fl; 2892 int lro_enabled; 2893 bool v4_forwarding, v6_forwarding, lro_possible; 2894 uint8_t retval = 0; 2895 2896 /* 2897 * XXX early demux data packets so that if_input processing only handles 2898 * acks in interrupt context 2899 */ 2900 struct mbuf *m, *mh, *mt, *mf; 2901 2902 NET_EPOCH_ASSERT(); 2903 2904 lro_possible = v4_forwarding = v6_forwarding = false; 2905 ifp = ctx->ifc_ifp; 2906 mh = mt = NULL; 2907 MPASS(budget > 0); 2908 rx_pkts = rx_bytes = 0; 2909 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2910 cidxp = &rxq->ifr_cq_cidx; 2911 else 2912 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2913 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2914 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2915 retval |= iflib_fl_refill_all(ctx, fl); 2916 DBG_COUNTER_INC(rx_unavail); 2917 return (retval); 2918 } 2919 2920 /* pfil needs the vnet to be set */ 2921 CURVNET_SET_QUIET(ifp->if_vnet); 2922 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2923 if (__predict_false(!CTX_ACTIVE(ctx))) { 2924 DBG_COUNTER_INC(rx_ctx_inactive); 2925 break; 2926 } 2927 /* 2928 * Reset client set fields to their default values 2929 */ 2930 rxd_info_zero(&ri); 2931 ri.iri_qsidx = rxq->ifr_id; 2932 ri.iri_cidx = *cidxp; 2933 ri.iri_ifp = ifp; 2934 ri.iri_frags = rxq->ifr_frags; 2935 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2936 2937 if (err) 2938 goto err; 2939 rx_pkts += 1; 2940 rx_bytes += ri.iri_len; 2941 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2942 *cidxp = ri.iri_cidx; 2943 /* Update our consumer index */ 2944 /* XXX NB: shurd - check if this is still safe */ 2945 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2946 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2947 /* was this only a completion queue message? */ 2948 if (__predict_false(ri.iri_nfrags == 0)) 2949 continue; 2950 } 2951 MPASS(ri.iri_nfrags != 0); 2952 MPASS(ri.iri_len != 0); 2953 2954 /* will advance the cidx on the corresponding free lists */ 2955 m = iflib_rxd_pkt_get(rxq, &ri); 2956 avail--; 2957 budget_left--; 2958 if (avail == 0 && budget_left) 2959 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2960 2961 if (__predict_false(m == NULL)) 2962 continue; 2963 2964 /* imm_pkt: -- cxgb */ 2965 if (mh == NULL) 2966 mh = mt = m; 2967 else { 2968 mt->m_nextpkt = m; 2969 mt = m; 2970 } 2971 } 2972 CURVNET_RESTORE(); 2973 /* make sure that we can refill faster than drain */ 2974 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2975 retval |= iflib_fl_refill_all(ctx, fl); 2976 2977 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2978 if (lro_enabled) 2979 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2980 mt = mf = NULL; 2981 while (mh != NULL) { 2982 m = mh; 2983 mh = mh->m_nextpkt; 2984 m->m_nextpkt = NULL; 2985 #ifndef __NO_STRICT_ALIGNMENT 2986 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2987 continue; 2988 #endif 2989 #if defined(INET6) || defined(INET) 2990 if (lro_enabled) { 2991 if (!lro_possible) { 2992 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2993 if (lro_possible && mf != NULL) { 2994 ifp->if_input(ifp, mf); 2995 DBG_COUNTER_INC(rx_if_input); 2996 mt = mf = NULL; 2997 } 2998 } 2999 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 3000 (CSUM_L4_CALC|CSUM_L4_VALID)) { 3001 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 3002 continue; 3003 } 3004 } 3005 #endif 3006 if (lro_possible) { 3007 ifp->if_input(ifp, m); 3008 DBG_COUNTER_INC(rx_if_input); 3009 continue; 3010 } 3011 3012 if (mf == NULL) 3013 mf = m; 3014 if (mt != NULL) 3015 mt->m_nextpkt = m; 3016 mt = m; 3017 } 3018 if (mf != NULL) { 3019 ifp->if_input(ifp, mf); 3020 DBG_COUNTER_INC(rx_if_input); 3021 } 3022 3023 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3024 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3025 3026 /* 3027 * Flush any outstanding LRO work 3028 */ 3029 #if defined(INET6) || defined(INET) 3030 tcp_lro_flush_all(&rxq->ifr_lc); 3031 #endif 3032 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3033 retval |= IFLIB_RXEOF_MORE; 3034 return (retval); 3035 err: 3036 STATE_LOCK(ctx); 3037 ctx->ifc_flags |= IFC_DO_RESET; 3038 iflib_admin_intr_deferred(ctx); 3039 STATE_UNLOCK(ctx); 3040 return (0); 3041 } 3042 3043 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 3044 static inline qidx_t 3045 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3046 { 3047 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3048 qidx_t minthresh = txq->ift_size / 8; 3049 if (in_use > 4*minthresh) 3050 return (notify_count); 3051 if (in_use > 2*minthresh) 3052 return (notify_count >> 1); 3053 if (in_use > minthresh) 3054 return (notify_count >> 3); 3055 return (0); 3056 } 3057 3058 static inline qidx_t 3059 txq_max_rs_deferred(iflib_txq_t txq) 3060 { 3061 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3062 qidx_t minthresh = txq->ift_size / 8; 3063 if (txq->ift_in_use > 4*minthresh) 3064 return (notify_count); 3065 if (txq->ift_in_use > 2*minthresh) 3066 return (notify_count >> 1); 3067 if (txq->ift_in_use > minthresh) 3068 return (notify_count >> 2); 3069 return (2); 3070 } 3071 3072 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3073 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3074 3075 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3076 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3077 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3078 3079 /* forward compatibility for cxgb */ 3080 #define FIRST_QSET(ctx) 0 3081 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3082 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3083 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3084 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3085 3086 /* XXX we should be setting this to something other than zero */ 3087 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3088 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3089 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3090 3091 static inline bool 3092 iflib_txd_db_check(iflib_txq_t txq, int ring) 3093 { 3094 if_ctx_t ctx = txq->ift_ctx; 3095 qidx_t dbval, max; 3096 3097 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3098 3099 /* force || threshold exceeded || at the edge of the ring */ 3100 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3101 3102 /* 3103 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3104 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3105 * producer index explicitly (INTC). 3106 */ 3107 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3108 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3109 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3110 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3111 3112 /* 3113 * Absent bugs there are zero packets pending so reset pending counts to zero. 3114 */ 3115 txq->ift_db_pending = txq->ift_npending = 0; 3116 return (true); 3117 } 3118 return (false); 3119 } 3120 3121 #ifdef PKT_DEBUG 3122 static void 3123 print_pkt(if_pkt_info_t pi) 3124 { 3125 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3126 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3127 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3128 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3129 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3130 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3131 } 3132 #endif 3133 3134 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3135 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3136 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3137 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3138 3139 static int 3140 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3141 { 3142 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3143 struct ether_vlan_header *eh; 3144 struct mbuf *m; 3145 3146 m = *mp; 3147 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3148 M_WRITABLE(m) == 0) { 3149 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3150 return (ENOMEM); 3151 } else { 3152 m_freem(*mp); 3153 DBG_COUNTER_INC(tx_frees); 3154 *mp = m; 3155 } 3156 } 3157 3158 /* 3159 * Determine where frame payload starts. 3160 * Jump over vlan headers if already present, 3161 * helpful for QinQ too. 3162 */ 3163 if (__predict_false(m->m_len < sizeof(*eh))) { 3164 txq->ift_pullups++; 3165 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3166 return (ENOMEM); 3167 } 3168 eh = mtod(m, struct ether_vlan_header *); 3169 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3170 pi->ipi_etype = ntohs(eh->evl_proto); 3171 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3172 } else { 3173 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3174 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3175 } 3176 3177 switch (pi->ipi_etype) { 3178 #ifdef INET 3179 case ETHERTYPE_IP: 3180 { 3181 struct mbuf *n; 3182 struct ip *ip = NULL; 3183 struct tcphdr *th = NULL; 3184 int minthlen; 3185 3186 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3187 if (__predict_false(m->m_len < minthlen)) { 3188 /* 3189 * if this code bloat is causing too much of a hit 3190 * move it to a separate function and mark it noinline 3191 */ 3192 if (m->m_len == pi->ipi_ehdrlen) { 3193 n = m->m_next; 3194 MPASS(n); 3195 if (n->m_len >= sizeof(*ip)) { 3196 ip = (struct ip *)n->m_data; 3197 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3198 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3199 } else { 3200 txq->ift_pullups++; 3201 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3202 return (ENOMEM); 3203 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3204 } 3205 } else { 3206 txq->ift_pullups++; 3207 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3208 return (ENOMEM); 3209 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3210 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3211 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3212 } 3213 } else { 3214 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3215 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3216 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3217 } 3218 pi->ipi_ip_hlen = ip->ip_hl << 2; 3219 pi->ipi_ipproto = ip->ip_p; 3220 pi->ipi_flags |= IPI_TX_IPV4; 3221 3222 /* TCP checksum offload may require TCP header length */ 3223 if (IS_TX_OFFLOAD4(pi)) { 3224 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3225 if (__predict_false(th == NULL)) { 3226 txq->ift_pullups++; 3227 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3228 return (ENOMEM); 3229 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3230 } 3231 pi->ipi_tcp_hflags = th->th_flags; 3232 pi->ipi_tcp_hlen = th->th_off << 2; 3233 pi->ipi_tcp_seq = th->th_seq; 3234 } 3235 if (IS_TSO4(pi)) { 3236 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3237 return (ENXIO); 3238 /* 3239 * TSO always requires hardware checksum offload. 3240 */ 3241 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3242 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3243 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3244 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3245 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3246 ip->ip_sum = 0; 3247 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3248 } 3249 } 3250 } 3251 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3252 ip->ip_sum = 0; 3253 3254 break; 3255 } 3256 #endif 3257 #ifdef INET6 3258 case ETHERTYPE_IPV6: 3259 { 3260 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3261 struct tcphdr *th; 3262 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3263 3264 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3265 txq->ift_pullups++; 3266 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3267 return (ENOMEM); 3268 } 3269 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3270 3271 /* XXX-BZ this will go badly in case of ext hdrs. */ 3272 pi->ipi_ipproto = ip6->ip6_nxt; 3273 pi->ipi_flags |= IPI_TX_IPV6; 3274 3275 /* TCP checksum offload may require TCP header length */ 3276 if (IS_TX_OFFLOAD6(pi)) { 3277 if (pi->ipi_ipproto == IPPROTO_TCP) { 3278 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3279 txq->ift_pullups++; 3280 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3281 return (ENOMEM); 3282 } 3283 pi->ipi_tcp_hflags = th->th_flags; 3284 pi->ipi_tcp_hlen = th->th_off << 2; 3285 pi->ipi_tcp_seq = th->th_seq; 3286 } 3287 if (IS_TSO6(pi)) { 3288 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3289 return (ENXIO); 3290 /* 3291 * TSO always requires hardware checksum offload. 3292 */ 3293 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3294 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3295 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3296 } 3297 } 3298 break; 3299 } 3300 #endif 3301 default: 3302 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3303 pi->ipi_ip_hlen = 0; 3304 break; 3305 } 3306 *mp = m; 3307 3308 return (0); 3309 } 3310 3311 /* 3312 * If dodgy hardware rejects the scatter gather chain we've handed it 3313 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3314 * m_defrag'd mbufs 3315 */ 3316 static __noinline struct mbuf * 3317 iflib_remove_mbuf(iflib_txq_t txq) 3318 { 3319 int ntxd, pidx; 3320 struct mbuf *m, **ifsd_m; 3321 3322 ifsd_m = txq->ift_sds.ifsd_m; 3323 ntxd = txq->ift_size; 3324 pidx = txq->ift_pidx & (ntxd - 1); 3325 ifsd_m = txq->ift_sds.ifsd_m; 3326 m = ifsd_m[pidx]; 3327 ifsd_m[pidx] = NULL; 3328 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3329 if (txq->ift_sds.ifsd_tso_map != NULL) 3330 bus_dmamap_unload(txq->ift_tso_buf_tag, 3331 txq->ift_sds.ifsd_tso_map[pidx]); 3332 #if MEMORY_LOGGING 3333 txq->ift_dequeued++; 3334 #endif 3335 return (m); 3336 } 3337 3338 static inline caddr_t 3339 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3340 { 3341 qidx_t size; 3342 int ntxd; 3343 caddr_t start, end, cur, next; 3344 3345 ntxd = txq->ift_size; 3346 size = txq->ift_txd_size[qid]; 3347 start = txq->ift_ifdi[qid].idi_vaddr; 3348 3349 if (__predict_false(size == 0)) 3350 return (start); 3351 cur = start + size*cidx; 3352 end = start + size*ntxd; 3353 next = CACHE_PTR_NEXT(cur); 3354 return (next < end ? next : start); 3355 } 3356 3357 /* 3358 * Pad an mbuf to ensure a minimum ethernet frame size. 3359 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3360 */ 3361 static __noinline int 3362 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3363 { 3364 /* 3365 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3366 * and ARP message is the smallest common payload I can think of 3367 */ 3368 static char pad[18]; /* just zeros */ 3369 int n; 3370 struct mbuf *new_head; 3371 3372 if (!M_WRITABLE(*m_head)) { 3373 new_head = m_dup(*m_head, M_NOWAIT); 3374 if (new_head == NULL) { 3375 m_freem(*m_head); 3376 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3377 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3378 DBG_COUNTER_INC(tx_frees); 3379 return ENOMEM; 3380 } 3381 m_freem(*m_head); 3382 *m_head = new_head; 3383 } 3384 3385 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3386 n > 0; n -= sizeof(pad)) 3387 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3388 break; 3389 3390 if (n > 0) { 3391 m_freem(*m_head); 3392 device_printf(dev, "cannot pad short frame\n"); 3393 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3394 DBG_COUNTER_INC(tx_frees); 3395 return (ENOBUFS); 3396 } 3397 3398 return 0; 3399 } 3400 3401 static int 3402 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3403 { 3404 if_ctx_t ctx; 3405 if_shared_ctx_t sctx; 3406 if_softc_ctx_t scctx; 3407 bus_dma_tag_t buf_tag; 3408 bus_dma_segment_t *segs; 3409 struct mbuf *m_head, **ifsd_m; 3410 void *next_txd; 3411 bus_dmamap_t map; 3412 struct if_pkt_info pi; 3413 int remap = 0; 3414 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3415 3416 ctx = txq->ift_ctx; 3417 sctx = ctx->ifc_sctx; 3418 scctx = &ctx->ifc_softc_ctx; 3419 segs = txq->ift_segs; 3420 ntxd = txq->ift_size; 3421 m_head = *m_headp; 3422 map = NULL; 3423 3424 /* 3425 * If we're doing TSO the next descriptor to clean may be quite far ahead 3426 */ 3427 cidx = txq->ift_cidx; 3428 pidx = txq->ift_pidx; 3429 if (ctx->ifc_flags & IFC_PREFETCH) { 3430 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3431 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3432 next_txd = calc_next_txd(txq, cidx, 0); 3433 prefetch(next_txd); 3434 } 3435 3436 /* prefetch the next cache line of mbuf pointers and flags */ 3437 prefetch(&txq->ift_sds.ifsd_m[next]); 3438 prefetch(&txq->ift_sds.ifsd_map[next]); 3439 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3440 } 3441 map = txq->ift_sds.ifsd_map[pidx]; 3442 ifsd_m = txq->ift_sds.ifsd_m; 3443 3444 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3445 buf_tag = txq->ift_tso_buf_tag; 3446 max_segs = scctx->isc_tx_tso_segments_max; 3447 map = txq->ift_sds.ifsd_tso_map[pidx]; 3448 MPASS(buf_tag != NULL); 3449 MPASS(max_segs > 0); 3450 } else { 3451 buf_tag = txq->ift_buf_tag; 3452 max_segs = scctx->isc_tx_nsegments; 3453 map = txq->ift_sds.ifsd_map[pidx]; 3454 } 3455 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3456 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3457 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3458 if (err) { 3459 DBG_COUNTER_INC(encap_txd_encap_fail); 3460 return err; 3461 } 3462 } 3463 m_head = *m_headp; 3464 3465 pkt_info_zero(&pi); 3466 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3467 pi.ipi_pidx = pidx; 3468 pi.ipi_qsidx = txq->ift_id; 3469 pi.ipi_len = m_head->m_pkthdr.len; 3470 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3471 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3472 3473 /* deliberate bitwise OR to make one condition */ 3474 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3475 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3476 DBG_COUNTER_INC(encap_txd_encap_fail); 3477 return (err); 3478 } 3479 m_head = *m_headp; 3480 } 3481 3482 retry: 3483 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3484 BUS_DMA_NOWAIT); 3485 defrag: 3486 if (__predict_false(err)) { 3487 switch (err) { 3488 case EFBIG: 3489 /* try collapse once and defrag once */ 3490 if (remap == 0) { 3491 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3492 /* try defrag if collapsing fails */ 3493 if (m_head == NULL) 3494 remap++; 3495 } 3496 if (remap == 1) { 3497 txq->ift_mbuf_defrag++; 3498 m_head = m_defrag(*m_headp, M_NOWAIT); 3499 } 3500 /* 3501 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3502 * failed to map an mbuf that was run through m_defrag 3503 */ 3504 MPASS(remap <= 1); 3505 if (__predict_false(m_head == NULL || remap > 1)) 3506 goto defrag_failed; 3507 remap++; 3508 *m_headp = m_head; 3509 goto retry; 3510 break; 3511 case ENOMEM: 3512 txq->ift_no_tx_dma_setup++; 3513 break; 3514 default: 3515 txq->ift_no_tx_dma_setup++; 3516 m_freem(*m_headp); 3517 DBG_COUNTER_INC(tx_frees); 3518 *m_headp = NULL; 3519 break; 3520 } 3521 txq->ift_map_failed++; 3522 DBG_COUNTER_INC(encap_load_mbuf_fail); 3523 DBG_COUNTER_INC(encap_txd_encap_fail); 3524 return (err); 3525 } 3526 ifsd_m[pidx] = m_head; 3527 /* 3528 * XXX assumes a 1 to 1 relationship between segments and 3529 * descriptors - this does not hold true on all drivers, e.g. 3530 * cxgb 3531 */ 3532 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3533 txq->ift_no_desc_avail++; 3534 bus_dmamap_unload(buf_tag, map); 3535 DBG_COUNTER_INC(encap_txq_avail_fail); 3536 DBG_COUNTER_INC(encap_txd_encap_fail); 3537 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3538 GROUPTASK_ENQUEUE(&txq->ift_task); 3539 return (ENOBUFS); 3540 } 3541 /* 3542 * On Intel cards we can greatly reduce the number of TX interrupts 3543 * we see by only setting report status on every Nth descriptor. 3544 * However, this also means that the driver will need to keep track 3545 * of the descriptors that RS was set on to check them for the DD bit. 3546 */ 3547 txq->ift_rs_pending += nsegs + 1; 3548 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3549 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3550 pi.ipi_flags |= IPI_TX_INTR; 3551 txq->ift_rs_pending = 0; 3552 } 3553 3554 pi.ipi_segs = segs; 3555 pi.ipi_nsegs = nsegs; 3556 3557 MPASS(pidx >= 0 && pidx < txq->ift_size); 3558 #ifdef PKT_DEBUG 3559 print_pkt(&pi); 3560 #endif 3561 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3562 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3563 DBG_COUNTER_INC(tx_encap); 3564 MPASS(pi.ipi_new_pidx < txq->ift_size); 3565 3566 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3567 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3568 ndesc += txq->ift_size; 3569 txq->ift_gen = 1; 3570 } 3571 /* 3572 * drivers can need as many as 3573 * two sentinels 3574 */ 3575 MPASS(ndesc <= pi.ipi_nsegs + 2); 3576 MPASS(pi.ipi_new_pidx != pidx); 3577 MPASS(ndesc > 0); 3578 txq->ift_in_use += ndesc; 3579 txq->ift_db_pending += ndesc; 3580 3581 /* 3582 * We update the last software descriptor again here because there may 3583 * be a sentinel and/or there may be more mbufs than segments 3584 */ 3585 txq->ift_pidx = pi.ipi_new_pidx; 3586 txq->ift_npending += pi.ipi_ndescs; 3587 } else { 3588 *m_headp = m_head = iflib_remove_mbuf(txq); 3589 if (err == EFBIG) { 3590 txq->ift_txd_encap_efbig++; 3591 if (remap < 2) { 3592 remap = 1; 3593 goto defrag; 3594 } 3595 } 3596 goto defrag_failed; 3597 } 3598 /* 3599 * err can't possibly be non-zero here, so we don't neet to test it 3600 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3601 */ 3602 return (err); 3603 3604 defrag_failed: 3605 txq->ift_mbuf_defrag_failed++; 3606 txq->ift_map_failed++; 3607 m_freem(*m_headp); 3608 DBG_COUNTER_INC(tx_frees); 3609 *m_headp = NULL; 3610 DBG_COUNTER_INC(encap_txd_encap_fail); 3611 return (ENOMEM); 3612 } 3613 3614 static void 3615 iflib_tx_desc_free(iflib_txq_t txq, int n) 3616 { 3617 uint32_t qsize, cidx, mask, gen; 3618 struct mbuf *m, **ifsd_m; 3619 bool do_prefetch; 3620 3621 cidx = txq->ift_cidx; 3622 gen = txq->ift_gen; 3623 qsize = txq->ift_size; 3624 mask = qsize-1; 3625 ifsd_m = txq->ift_sds.ifsd_m; 3626 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3627 3628 while (n-- > 0) { 3629 if (do_prefetch) { 3630 prefetch(ifsd_m[(cidx + 3) & mask]); 3631 prefetch(ifsd_m[(cidx + 4) & mask]); 3632 } 3633 if ((m = ifsd_m[cidx]) != NULL) { 3634 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3635 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3636 bus_dmamap_sync(txq->ift_tso_buf_tag, 3637 txq->ift_sds.ifsd_tso_map[cidx], 3638 BUS_DMASYNC_POSTWRITE); 3639 bus_dmamap_unload(txq->ift_tso_buf_tag, 3640 txq->ift_sds.ifsd_tso_map[cidx]); 3641 } else { 3642 bus_dmamap_sync(txq->ift_buf_tag, 3643 txq->ift_sds.ifsd_map[cidx], 3644 BUS_DMASYNC_POSTWRITE); 3645 bus_dmamap_unload(txq->ift_buf_tag, 3646 txq->ift_sds.ifsd_map[cidx]); 3647 } 3648 /* XXX we don't support any drivers that batch packets yet */ 3649 MPASS(m->m_nextpkt == NULL); 3650 m_freem(m); 3651 ifsd_m[cidx] = NULL; 3652 #if MEMORY_LOGGING 3653 txq->ift_dequeued++; 3654 #endif 3655 DBG_COUNTER_INC(tx_frees); 3656 } 3657 if (__predict_false(++cidx == qsize)) { 3658 cidx = 0; 3659 gen = 0; 3660 } 3661 } 3662 txq->ift_cidx = cidx; 3663 txq->ift_gen = gen; 3664 } 3665 3666 static __inline int 3667 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3668 { 3669 int reclaim; 3670 if_ctx_t ctx = txq->ift_ctx; 3671 3672 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3673 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3674 3675 /* 3676 * Need a rate-limiting check so that this isn't called every time 3677 */ 3678 iflib_tx_credits_update(ctx, txq); 3679 reclaim = DESC_RECLAIMABLE(txq); 3680 3681 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3682 #ifdef INVARIANTS 3683 if (iflib_verbose_debug) { 3684 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3685 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3686 reclaim, thresh); 3687 } 3688 #endif 3689 return (0); 3690 } 3691 iflib_tx_desc_free(txq, reclaim); 3692 txq->ift_cleaned += reclaim; 3693 txq->ift_in_use -= reclaim; 3694 3695 return (reclaim); 3696 } 3697 3698 static struct mbuf ** 3699 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3700 { 3701 int next, size; 3702 struct mbuf **items; 3703 3704 size = r->size; 3705 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3706 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3707 3708 prefetch(items[(cidx + offset) & (size-1)]); 3709 if (remaining > 1) { 3710 prefetch2cachelines(&items[next]); 3711 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3712 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3713 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3714 } 3715 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3716 } 3717 3718 static void 3719 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3720 { 3721 3722 ifmp_ring_check_drainage(txq->ift_br, budget); 3723 } 3724 3725 static uint32_t 3726 iflib_txq_can_drain(struct ifmp_ring *r) 3727 { 3728 iflib_txq_t txq = r->cookie; 3729 if_ctx_t ctx = txq->ift_ctx; 3730 3731 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3732 return (1); 3733 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3734 BUS_DMASYNC_POSTREAD); 3735 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3736 false)); 3737 } 3738 3739 static uint32_t 3740 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3741 { 3742 iflib_txq_t txq = r->cookie; 3743 if_ctx_t ctx = txq->ift_ctx; 3744 if_t ifp = ctx->ifc_ifp; 3745 struct mbuf *m, **mp; 3746 int avail, bytes_sent, skipped, count, err, i; 3747 int mcast_sent, pkt_sent, reclaimed; 3748 bool do_prefetch, rang, ring; 3749 3750 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3751 !LINK_ACTIVE(ctx))) { 3752 DBG_COUNTER_INC(txq_drain_notready); 3753 return (0); 3754 } 3755 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3756 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3757 avail = IDXDIFF(pidx, cidx, r->size); 3758 3759 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3760 /* 3761 * The driver is unloading so we need to free all pending packets. 3762 */ 3763 DBG_COUNTER_INC(txq_drain_flushing); 3764 for (i = 0; i < avail; i++) { 3765 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3766 m_freem(r->items[(cidx + i) & (r->size-1)]); 3767 r->items[(cidx + i) & (r->size-1)] = NULL; 3768 } 3769 return (avail); 3770 } 3771 3772 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3773 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3774 CALLOUT_LOCK(txq); 3775 callout_stop(&txq->ift_timer); 3776 CALLOUT_UNLOCK(txq); 3777 DBG_COUNTER_INC(txq_drain_oactive); 3778 return (0); 3779 } 3780 3781 /* 3782 * If we've reclaimed any packets this queue cannot be hung. 3783 */ 3784 if (reclaimed) 3785 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3786 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3787 count = MIN(avail, TX_BATCH_SIZE); 3788 #ifdef INVARIANTS 3789 if (iflib_verbose_debug) 3790 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3791 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3792 #endif 3793 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3794 err = 0; 3795 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3796 int rem = do_prefetch ? count - i : 0; 3797 3798 mp = _ring_peek_one(r, cidx, i, rem); 3799 MPASS(mp != NULL && *mp != NULL); 3800 3801 /* 3802 * Completion interrupts will use the address of the txq 3803 * as a sentinel to enqueue _something_ in order to acquire 3804 * the lock on the mp_ring (there's no direct lock call). 3805 * We obviously whave to check for these sentinel cases 3806 * and skip them. 3807 */ 3808 if (__predict_false(*mp == (struct mbuf *)txq)) { 3809 skipped++; 3810 continue; 3811 } 3812 err = iflib_encap(txq, mp); 3813 if (__predict_false(err)) { 3814 /* no room - bail out */ 3815 if (err == ENOBUFS) 3816 break; 3817 skipped++; 3818 /* we can't send this packet - skip it */ 3819 continue; 3820 } 3821 pkt_sent++; 3822 m = *mp; 3823 DBG_COUNTER_INC(tx_sent); 3824 bytes_sent += m->m_pkthdr.len; 3825 mcast_sent += !!(m->m_flags & M_MCAST); 3826 3827 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3828 break; 3829 ETHER_BPF_MTAP(ifp, m); 3830 rang = iflib_txd_db_check(txq, false); 3831 } 3832 3833 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3834 ring = rang ? false : (iflib_min_tx_latency | err); 3835 iflib_txd_db_check(txq, ring); 3836 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3837 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3838 if (mcast_sent) 3839 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3840 #ifdef INVARIANTS 3841 if (iflib_verbose_debug) 3842 printf("consumed=%d\n", skipped + pkt_sent); 3843 #endif 3844 return (skipped + pkt_sent); 3845 } 3846 3847 static uint32_t 3848 iflib_txq_drain_always(struct ifmp_ring *r) 3849 { 3850 return (1); 3851 } 3852 3853 static uint32_t 3854 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3855 { 3856 int i, avail; 3857 struct mbuf **mp; 3858 iflib_txq_t txq; 3859 3860 txq = r->cookie; 3861 3862 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3863 CALLOUT_LOCK(txq); 3864 callout_stop(&txq->ift_timer); 3865 CALLOUT_UNLOCK(txq); 3866 3867 avail = IDXDIFF(pidx, cidx, r->size); 3868 for (i = 0; i < avail; i++) { 3869 mp = _ring_peek_one(r, cidx, i, avail - i); 3870 if (__predict_false(*mp == (struct mbuf *)txq)) 3871 continue; 3872 m_freem(*mp); 3873 DBG_COUNTER_INC(tx_frees); 3874 } 3875 MPASS(ifmp_ring_is_stalled(r) == 0); 3876 return (avail); 3877 } 3878 3879 static void 3880 iflib_ifmp_purge(iflib_txq_t txq) 3881 { 3882 struct ifmp_ring *r; 3883 3884 r = txq->ift_br; 3885 r->drain = iflib_txq_drain_free; 3886 r->can_drain = iflib_txq_drain_always; 3887 3888 ifmp_ring_check_drainage(r, r->size); 3889 3890 r->drain = iflib_txq_drain; 3891 r->can_drain = iflib_txq_can_drain; 3892 } 3893 3894 static void 3895 _task_fn_tx(void *context) 3896 { 3897 iflib_txq_t txq = context; 3898 if_ctx_t ctx = txq->ift_ctx; 3899 if_t ifp = ctx->ifc_ifp; 3900 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3901 3902 #ifdef IFLIB_DIAGNOSTICS 3903 txq->ift_cpu_exec_count[curcpu]++; 3904 #endif 3905 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3906 return; 3907 #ifdef DEV_NETMAP 3908 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3909 netmap_tx_irq(ifp, txq->ift_id)) 3910 goto skip_ifmp; 3911 #endif 3912 #ifdef ALTQ 3913 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3914 iflib_altq_if_start(ifp); 3915 #endif 3916 if (txq->ift_db_pending) 3917 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3918 else if (!abdicate) 3919 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3920 /* 3921 * When abdicating, we always need to check drainage, not just when we don't enqueue 3922 */ 3923 if (abdicate) 3924 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3925 #ifdef DEV_NETMAP 3926 skip_ifmp: 3927 #endif 3928 if (ctx->ifc_flags & IFC_LEGACY) 3929 IFDI_INTR_ENABLE(ctx); 3930 else 3931 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3932 } 3933 3934 static void 3935 _task_fn_rx(void *context) 3936 { 3937 iflib_rxq_t rxq = context; 3938 if_ctx_t ctx = rxq->ifr_ctx; 3939 uint8_t more; 3940 uint16_t budget; 3941 #ifdef DEV_NETMAP 3942 u_int work = 0; 3943 int nmirq; 3944 #endif 3945 3946 #ifdef IFLIB_DIAGNOSTICS 3947 rxq->ifr_cpu_exec_count[curcpu]++; 3948 #endif 3949 DBG_COUNTER_INC(task_fn_rxs); 3950 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3951 return; 3952 #ifdef DEV_NETMAP 3953 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 3954 if (nmirq != NM_IRQ_PASS) { 3955 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 3956 goto skip_rxeof; 3957 } 3958 #endif 3959 budget = ctx->ifc_sysctl_rx_budget; 3960 if (budget == 0) 3961 budget = 16; /* XXX */ 3962 more = iflib_rxeof(rxq, budget); 3963 #ifdef DEV_NETMAP 3964 skip_rxeof: 3965 #endif 3966 if ((more & IFLIB_RXEOF_MORE) == 0) { 3967 if (ctx->ifc_flags & IFC_LEGACY) 3968 IFDI_INTR_ENABLE(ctx); 3969 else 3970 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3971 DBG_COUNTER_INC(rx_intr_enables); 3972 } 3973 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3974 return; 3975 3976 if (more & IFLIB_RXEOF_MORE) 3977 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3978 else if (more & IFLIB_RXEOF_EMPTY) 3979 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 3980 } 3981 3982 static void 3983 _task_fn_admin(void *context) 3984 { 3985 if_ctx_t ctx = context; 3986 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3987 iflib_txq_t txq; 3988 int i; 3989 bool oactive, running, do_reset, do_watchdog, in_detach; 3990 3991 STATE_LOCK(ctx); 3992 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3993 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3994 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3995 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3996 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3997 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3998 STATE_UNLOCK(ctx); 3999 4000 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4001 return; 4002 if (in_detach) 4003 return; 4004 4005 CTX_LOCK(ctx); 4006 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4007 CALLOUT_LOCK(txq); 4008 callout_stop(&txq->ift_timer); 4009 CALLOUT_UNLOCK(txq); 4010 } 4011 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4012 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4013 if (do_watchdog) { 4014 ctx->ifc_watchdog_events++; 4015 IFDI_WATCHDOG_RESET(ctx); 4016 } 4017 IFDI_UPDATE_ADMIN_STATUS(ctx); 4018 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4019 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4020 txq->ift_timer.c_cpu); 4021 } 4022 IFDI_LINK_INTR_ENABLE(ctx); 4023 if (do_reset) 4024 iflib_if_init_locked(ctx); 4025 CTX_UNLOCK(ctx); 4026 4027 if (LINK_ACTIVE(ctx) == 0) 4028 return; 4029 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4030 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4031 } 4032 4033 static void 4034 _task_fn_iov(void *context) 4035 { 4036 if_ctx_t ctx = context; 4037 4038 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4039 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4040 return; 4041 4042 CTX_LOCK(ctx); 4043 IFDI_VFLR_HANDLE(ctx); 4044 CTX_UNLOCK(ctx); 4045 } 4046 4047 static int 4048 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4049 { 4050 int err; 4051 if_int_delay_info_t info; 4052 if_ctx_t ctx; 4053 4054 info = (if_int_delay_info_t)arg1; 4055 ctx = info->iidi_ctx; 4056 info->iidi_req = req; 4057 info->iidi_oidp = oidp; 4058 CTX_LOCK(ctx); 4059 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4060 CTX_UNLOCK(ctx); 4061 return (err); 4062 } 4063 4064 /********************************************************************* 4065 * 4066 * IFNET FUNCTIONS 4067 * 4068 **********************************************************************/ 4069 4070 static void 4071 iflib_if_init_locked(if_ctx_t ctx) 4072 { 4073 iflib_stop(ctx); 4074 iflib_init_locked(ctx); 4075 } 4076 4077 static void 4078 iflib_if_init(void *arg) 4079 { 4080 if_ctx_t ctx = arg; 4081 4082 CTX_LOCK(ctx); 4083 iflib_if_init_locked(ctx); 4084 CTX_UNLOCK(ctx); 4085 } 4086 4087 static int 4088 iflib_if_transmit(if_t ifp, struct mbuf *m) 4089 { 4090 if_ctx_t ctx = if_getsoftc(ifp); 4091 4092 iflib_txq_t txq; 4093 int err, qidx; 4094 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4095 4096 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4097 DBG_COUNTER_INC(tx_frees); 4098 m_freem(m); 4099 return (ENETDOWN); 4100 } 4101 4102 MPASS(m->m_nextpkt == NULL); 4103 /* ALTQ-enabled interfaces always use queue 0. */ 4104 qidx = 0; 4105 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 4106 qidx = QIDX(ctx, m); 4107 /* 4108 * XXX calculate buf_ring based on flowid (divvy up bits?) 4109 */ 4110 txq = &ctx->ifc_txqs[qidx]; 4111 4112 #ifdef DRIVER_BACKPRESSURE 4113 if (txq->ift_closed) { 4114 while (m != NULL) { 4115 next = m->m_nextpkt; 4116 m->m_nextpkt = NULL; 4117 m_freem(m); 4118 DBG_COUNTER_INC(tx_frees); 4119 m = next; 4120 } 4121 return (ENOBUFS); 4122 } 4123 #endif 4124 #ifdef notyet 4125 qidx = count = 0; 4126 mp = marr; 4127 next = m; 4128 do { 4129 count++; 4130 next = next->m_nextpkt; 4131 } while (next != NULL); 4132 4133 if (count > nitems(marr)) 4134 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4135 /* XXX check nextpkt */ 4136 m_freem(m); 4137 /* XXX simplify for now */ 4138 DBG_COUNTER_INC(tx_frees); 4139 return (ENOBUFS); 4140 } 4141 for (next = m, i = 0; next != NULL; i++) { 4142 mp[i] = next; 4143 next = next->m_nextpkt; 4144 mp[i]->m_nextpkt = NULL; 4145 } 4146 #endif 4147 DBG_COUNTER_INC(tx_seen); 4148 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4149 4150 if (abdicate) 4151 GROUPTASK_ENQUEUE(&txq->ift_task); 4152 if (err) { 4153 if (!abdicate) 4154 GROUPTASK_ENQUEUE(&txq->ift_task); 4155 /* support forthcoming later */ 4156 #ifdef DRIVER_BACKPRESSURE 4157 txq->ift_closed = TRUE; 4158 #endif 4159 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4160 m_freem(m); 4161 DBG_COUNTER_INC(tx_frees); 4162 } 4163 4164 return (err); 4165 } 4166 4167 #ifdef ALTQ 4168 /* 4169 * The overall approach to integrating iflib with ALTQ is to continue to use 4170 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4171 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4172 * is redundant/unnecessary, but doing so minimizes the amount of 4173 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4174 * redundantly queueing to an intermediate mp_ring is swamped by the 4175 * performance limitations inherent in using ALTQ. 4176 * 4177 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4178 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4179 * given interface. If ALTQ is enabled for an interface, then all 4180 * transmitted packets for that interface will be submitted to the ALTQ 4181 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4182 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4183 * update stats that the iflib machinery handles, and which is sensitve to 4184 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4185 * will be installed as the start routine for use by ALTQ facilities that 4186 * need to trigger queue drains on a scheduled basis. 4187 * 4188 */ 4189 static void 4190 iflib_altq_if_start(if_t ifp) 4191 { 4192 struct ifaltq *ifq = &ifp->if_snd; 4193 struct mbuf *m; 4194 4195 IFQ_LOCK(ifq); 4196 IFQ_DEQUEUE_NOLOCK(ifq, m); 4197 while (m != NULL) { 4198 iflib_if_transmit(ifp, m); 4199 IFQ_DEQUEUE_NOLOCK(ifq, m); 4200 } 4201 IFQ_UNLOCK(ifq); 4202 } 4203 4204 static int 4205 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4206 { 4207 int err; 4208 4209 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4210 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4211 if (err == 0) 4212 iflib_altq_if_start(ifp); 4213 } else 4214 err = iflib_if_transmit(ifp, m); 4215 4216 return (err); 4217 } 4218 #endif /* ALTQ */ 4219 4220 static void 4221 iflib_if_qflush(if_t ifp) 4222 { 4223 if_ctx_t ctx = if_getsoftc(ifp); 4224 iflib_txq_t txq = ctx->ifc_txqs; 4225 int i; 4226 4227 STATE_LOCK(ctx); 4228 ctx->ifc_flags |= IFC_QFLUSH; 4229 STATE_UNLOCK(ctx); 4230 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4231 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4232 iflib_txq_check_drain(txq, 0); 4233 STATE_LOCK(ctx); 4234 ctx->ifc_flags &= ~IFC_QFLUSH; 4235 STATE_UNLOCK(ctx); 4236 4237 /* 4238 * When ALTQ is enabled, this will also take care of purging the 4239 * ALTQ queue(s). 4240 */ 4241 if_qflush(ifp); 4242 } 4243 4244 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4245 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4246 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4247 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4248 4249 static int 4250 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4251 { 4252 if_ctx_t ctx = if_getsoftc(ifp); 4253 struct ifreq *ifr = (struct ifreq *)data; 4254 #if defined(INET) || defined(INET6) 4255 struct ifaddr *ifa = (struct ifaddr *)data; 4256 #endif 4257 bool avoid_reset = false; 4258 int err = 0, reinit = 0, bits; 4259 4260 switch (command) { 4261 case SIOCSIFADDR: 4262 #ifdef INET 4263 if (ifa->ifa_addr->sa_family == AF_INET) 4264 avoid_reset = true; 4265 #endif 4266 #ifdef INET6 4267 if (ifa->ifa_addr->sa_family == AF_INET6) 4268 avoid_reset = true; 4269 #endif 4270 /* 4271 ** Calling init results in link renegotiation, 4272 ** so we avoid doing it when possible. 4273 */ 4274 if (avoid_reset) { 4275 if_setflagbits(ifp, IFF_UP,0); 4276 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4277 reinit = 1; 4278 #ifdef INET 4279 if (!(if_getflags(ifp) & IFF_NOARP)) 4280 arp_ifinit(ifp, ifa); 4281 #endif 4282 } else 4283 err = ether_ioctl(ifp, command, data); 4284 break; 4285 case SIOCSIFMTU: 4286 CTX_LOCK(ctx); 4287 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4288 CTX_UNLOCK(ctx); 4289 break; 4290 } 4291 bits = if_getdrvflags(ifp); 4292 /* stop the driver and free any clusters before proceeding */ 4293 iflib_stop(ctx); 4294 4295 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4296 STATE_LOCK(ctx); 4297 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4298 ctx->ifc_flags |= IFC_MULTISEG; 4299 else 4300 ctx->ifc_flags &= ~IFC_MULTISEG; 4301 STATE_UNLOCK(ctx); 4302 err = if_setmtu(ifp, ifr->ifr_mtu); 4303 } 4304 iflib_init_locked(ctx); 4305 STATE_LOCK(ctx); 4306 if_setdrvflags(ifp, bits); 4307 STATE_UNLOCK(ctx); 4308 CTX_UNLOCK(ctx); 4309 break; 4310 case SIOCSIFFLAGS: 4311 CTX_LOCK(ctx); 4312 if (if_getflags(ifp) & IFF_UP) { 4313 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4314 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4315 (IFF_PROMISC | IFF_ALLMULTI)) { 4316 CTX_UNLOCK(ctx); 4317 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4318 CTX_LOCK(ctx); 4319 } 4320 } else 4321 reinit = 1; 4322 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4323 iflib_stop(ctx); 4324 } 4325 ctx->ifc_if_flags = if_getflags(ifp); 4326 CTX_UNLOCK(ctx); 4327 break; 4328 case SIOCADDMULTI: 4329 case SIOCDELMULTI: 4330 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4331 CTX_LOCK(ctx); 4332 IFDI_INTR_DISABLE(ctx); 4333 IFDI_MULTI_SET(ctx); 4334 IFDI_INTR_ENABLE(ctx); 4335 CTX_UNLOCK(ctx); 4336 } 4337 break; 4338 case SIOCSIFMEDIA: 4339 CTX_LOCK(ctx); 4340 IFDI_MEDIA_SET(ctx); 4341 CTX_UNLOCK(ctx); 4342 /* FALLTHROUGH */ 4343 case SIOCGIFMEDIA: 4344 case SIOCGIFXMEDIA: 4345 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4346 break; 4347 case SIOCGI2C: 4348 { 4349 struct ifi2creq i2c; 4350 4351 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4352 if (err != 0) 4353 break; 4354 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4355 err = EINVAL; 4356 break; 4357 } 4358 if (i2c.len > sizeof(i2c.data)) { 4359 err = EINVAL; 4360 break; 4361 } 4362 4363 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4364 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4365 sizeof(i2c)); 4366 break; 4367 } 4368 case SIOCSIFCAP: 4369 { 4370 int mask, setmask, oldmask; 4371 4372 oldmask = if_getcapenable(ifp); 4373 mask = ifr->ifr_reqcap ^ oldmask; 4374 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4375 setmask = 0; 4376 #ifdef TCP_OFFLOAD 4377 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4378 #endif 4379 setmask |= (mask & IFCAP_FLAGS); 4380 setmask |= (mask & IFCAP_WOL); 4381 4382 /* 4383 * If any RX csum has changed, change all the ones that 4384 * are supported by the driver. 4385 */ 4386 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4387 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4388 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4389 } 4390 4391 /* 4392 * want to ensure that traffic has stopped before we change any of the flags 4393 */ 4394 if (setmask) { 4395 CTX_LOCK(ctx); 4396 bits = if_getdrvflags(ifp); 4397 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4398 iflib_stop(ctx); 4399 STATE_LOCK(ctx); 4400 if_togglecapenable(ifp, setmask); 4401 STATE_UNLOCK(ctx); 4402 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4403 iflib_init_locked(ctx); 4404 STATE_LOCK(ctx); 4405 if_setdrvflags(ifp, bits); 4406 STATE_UNLOCK(ctx); 4407 CTX_UNLOCK(ctx); 4408 } 4409 if_vlancap(ifp); 4410 break; 4411 } 4412 case SIOCGPRIVATE_0: 4413 case SIOCSDRVSPEC: 4414 case SIOCGDRVSPEC: 4415 CTX_LOCK(ctx); 4416 err = IFDI_PRIV_IOCTL(ctx, command, data); 4417 CTX_UNLOCK(ctx); 4418 break; 4419 default: 4420 err = ether_ioctl(ifp, command, data); 4421 break; 4422 } 4423 if (reinit) 4424 iflib_if_init(ctx); 4425 return (err); 4426 } 4427 4428 static uint64_t 4429 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4430 { 4431 if_ctx_t ctx = if_getsoftc(ifp); 4432 4433 return (IFDI_GET_COUNTER(ctx, cnt)); 4434 } 4435 4436 /********************************************************************* 4437 * 4438 * OTHER FUNCTIONS EXPORTED TO THE STACK 4439 * 4440 **********************************************************************/ 4441 4442 static void 4443 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4444 { 4445 if_ctx_t ctx = if_getsoftc(ifp); 4446 4447 if ((void *)ctx != arg) 4448 return; 4449 4450 if ((vtag == 0) || (vtag > 4095)) 4451 return; 4452 4453 if (iflib_in_detach(ctx)) 4454 return; 4455 4456 CTX_LOCK(ctx); 4457 /* Driver may need all untagged packets to be flushed */ 4458 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4459 iflib_stop(ctx); 4460 IFDI_VLAN_REGISTER(ctx, vtag); 4461 /* Re-init to load the changes, if required */ 4462 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4463 iflib_init_locked(ctx); 4464 CTX_UNLOCK(ctx); 4465 } 4466 4467 static void 4468 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4469 { 4470 if_ctx_t ctx = if_getsoftc(ifp); 4471 4472 if ((void *)ctx != arg) 4473 return; 4474 4475 if ((vtag == 0) || (vtag > 4095)) 4476 return; 4477 4478 CTX_LOCK(ctx); 4479 /* Driver may need all tagged packets to be flushed */ 4480 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4481 iflib_stop(ctx); 4482 IFDI_VLAN_UNREGISTER(ctx, vtag); 4483 /* Re-init to load the changes, if required */ 4484 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4485 iflib_init_locked(ctx); 4486 CTX_UNLOCK(ctx); 4487 } 4488 4489 static void 4490 iflib_led_func(void *arg, int onoff) 4491 { 4492 if_ctx_t ctx = arg; 4493 4494 CTX_LOCK(ctx); 4495 IFDI_LED_FUNC(ctx, onoff); 4496 CTX_UNLOCK(ctx); 4497 } 4498 4499 /********************************************************************* 4500 * 4501 * BUS FUNCTION DEFINITIONS 4502 * 4503 **********************************************************************/ 4504 4505 int 4506 iflib_device_probe(device_t dev) 4507 { 4508 const pci_vendor_info_t *ent; 4509 if_shared_ctx_t sctx; 4510 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4511 uint16_t pci_vendor_id; 4512 4513 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4514 return (ENOTSUP); 4515 4516 pci_vendor_id = pci_get_vendor(dev); 4517 pci_device_id = pci_get_device(dev); 4518 pci_subvendor_id = pci_get_subvendor(dev); 4519 pci_subdevice_id = pci_get_subdevice(dev); 4520 pci_rev_id = pci_get_revid(dev); 4521 if (sctx->isc_parse_devinfo != NULL) 4522 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4523 4524 ent = sctx->isc_vendor_info; 4525 while (ent->pvi_vendor_id != 0) { 4526 if (pci_vendor_id != ent->pvi_vendor_id) { 4527 ent++; 4528 continue; 4529 } 4530 if ((pci_device_id == ent->pvi_device_id) && 4531 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4532 (ent->pvi_subvendor_id == 0)) && 4533 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4534 (ent->pvi_subdevice_id == 0)) && 4535 ((pci_rev_id == ent->pvi_rev_id) || 4536 (ent->pvi_rev_id == 0))) { 4537 device_set_desc_copy(dev, ent->pvi_name); 4538 /* this needs to be changed to zero if the bus probing code 4539 * ever stops re-probing on best match because the sctx 4540 * may have its values over written by register calls 4541 * in subsequent probes 4542 */ 4543 return (BUS_PROBE_DEFAULT); 4544 } 4545 ent++; 4546 } 4547 return (ENXIO); 4548 } 4549 4550 int 4551 iflib_device_probe_vendor(device_t dev) 4552 { 4553 int probe; 4554 4555 probe = iflib_device_probe(dev); 4556 if (probe == BUS_PROBE_DEFAULT) 4557 return (BUS_PROBE_VENDOR); 4558 else 4559 return (probe); 4560 } 4561 4562 static void 4563 iflib_reset_qvalues(if_ctx_t ctx) 4564 { 4565 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4566 if_shared_ctx_t sctx = ctx->ifc_sctx; 4567 device_t dev = ctx->ifc_dev; 4568 int i; 4569 4570 if (ctx->ifc_sysctl_ntxqs != 0) 4571 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4572 if (ctx->ifc_sysctl_nrxqs != 0) 4573 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4574 4575 for (i = 0; i < sctx->isc_ntxqs; i++) { 4576 if (ctx->ifc_sysctl_ntxds[i] != 0) 4577 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4578 else 4579 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4580 } 4581 4582 for (i = 0; i < sctx->isc_nrxqs; i++) { 4583 if (ctx->ifc_sysctl_nrxds[i] != 0) 4584 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4585 else 4586 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4587 } 4588 4589 for (i = 0; i < sctx->isc_nrxqs; i++) { 4590 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4591 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4592 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4593 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4594 } 4595 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4596 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4597 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4598 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4599 } 4600 if (!powerof2(scctx->isc_nrxd[i])) { 4601 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4602 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4603 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4604 } 4605 } 4606 4607 for (i = 0; i < sctx->isc_ntxqs; i++) { 4608 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4609 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4610 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4611 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4612 } 4613 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4614 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4615 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4616 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4617 } 4618 if (!powerof2(scctx->isc_ntxd[i])) { 4619 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4620 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4621 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4622 } 4623 } 4624 } 4625 4626 static void 4627 iflib_add_pfil(if_ctx_t ctx) 4628 { 4629 struct pfil_head *pfil; 4630 struct pfil_head_args pa; 4631 iflib_rxq_t rxq; 4632 int i; 4633 4634 pa.pa_version = PFIL_VERSION; 4635 pa.pa_flags = PFIL_IN; 4636 pa.pa_type = PFIL_TYPE_ETHERNET; 4637 pa.pa_headname = ctx->ifc_ifp->if_xname; 4638 pfil = pfil_head_register(&pa); 4639 4640 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4641 rxq->pfil = pfil; 4642 } 4643 } 4644 4645 static void 4646 iflib_rem_pfil(if_ctx_t ctx) 4647 { 4648 struct pfil_head *pfil; 4649 iflib_rxq_t rxq; 4650 int i; 4651 4652 rxq = ctx->ifc_rxqs; 4653 pfil = rxq->pfil; 4654 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4655 rxq->pfil = NULL; 4656 } 4657 pfil_head_unregister(pfil); 4658 } 4659 4660 static uint16_t 4661 get_ctx_core_offset(if_ctx_t ctx) 4662 { 4663 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4664 struct cpu_offset *op; 4665 uint16_t qc; 4666 uint16_t ret = ctx->ifc_sysctl_core_offset; 4667 4668 if (ret != CORE_OFFSET_UNSPECIFIED) 4669 return (ret); 4670 4671 if (ctx->ifc_sysctl_separate_txrx) 4672 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4673 else 4674 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4675 4676 mtx_lock(&cpu_offset_mtx); 4677 SLIST_FOREACH(op, &cpu_offsets, entries) { 4678 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4679 ret = op->offset; 4680 op->offset += qc; 4681 MPASS(op->refcount < UINT_MAX); 4682 op->refcount++; 4683 break; 4684 } 4685 } 4686 if (ret == CORE_OFFSET_UNSPECIFIED) { 4687 ret = 0; 4688 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4689 M_NOWAIT | M_ZERO); 4690 if (op == NULL) { 4691 device_printf(ctx->ifc_dev, 4692 "allocation for cpu offset failed.\n"); 4693 } else { 4694 op->offset = qc; 4695 op->refcount = 1; 4696 CPU_COPY(&ctx->ifc_cpus, &op->set); 4697 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4698 } 4699 } 4700 mtx_unlock(&cpu_offset_mtx); 4701 4702 return (ret); 4703 } 4704 4705 static void 4706 unref_ctx_core_offset(if_ctx_t ctx) 4707 { 4708 struct cpu_offset *op, *top; 4709 4710 mtx_lock(&cpu_offset_mtx); 4711 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4712 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4713 MPASS(op->refcount > 0); 4714 op->refcount--; 4715 if (op->refcount == 0) { 4716 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4717 free(op, M_IFLIB); 4718 } 4719 break; 4720 } 4721 } 4722 mtx_unlock(&cpu_offset_mtx); 4723 } 4724 4725 int 4726 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4727 { 4728 if_ctx_t ctx; 4729 if_t ifp; 4730 if_softc_ctx_t scctx; 4731 kobjop_desc_t kobj_desc; 4732 kobj_method_t *kobj_method; 4733 int err, msix, rid; 4734 int num_txd, num_rxd; 4735 4736 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4737 4738 if (sc == NULL) { 4739 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4740 device_set_softc(dev, ctx); 4741 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4742 } 4743 4744 ctx->ifc_sctx = sctx; 4745 ctx->ifc_dev = dev; 4746 ctx->ifc_softc = sc; 4747 4748 if ((err = iflib_register(ctx)) != 0) { 4749 device_printf(dev, "iflib_register failed %d\n", err); 4750 goto fail_ctx_free; 4751 } 4752 iflib_add_device_sysctl_pre(ctx); 4753 4754 scctx = &ctx->ifc_softc_ctx; 4755 ifp = ctx->ifc_ifp; 4756 4757 iflib_reset_qvalues(ctx); 4758 CTX_LOCK(ctx); 4759 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4760 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4761 goto fail_unlock; 4762 } 4763 _iflib_pre_assert(scctx); 4764 ctx->ifc_txrx = *scctx->isc_txrx; 4765 4766 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 4767 4768 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4769 ctx->ifc_mediap = scctx->isc_media; 4770 4771 #ifdef INVARIANTS 4772 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4773 MPASS(scctx->isc_tx_csum_flags); 4774 #endif 4775 4776 if_setcapabilities(ifp, 4777 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 4778 if_setcapenable(ifp, 4779 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 4780 4781 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4782 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4783 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4784 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4785 4786 num_txd = iflib_num_tx_descs(ctx); 4787 num_rxd = iflib_num_rx_descs(ctx); 4788 4789 /* XXX change for per-queue sizes */ 4790 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4791 num_txd, num_rxd); 4792 4793 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 4794 scctx->isc_tx_nsegments = max(1, num_txd / 4795 MAX_SINGLE_PACKET_FRACTION); 4796 if (scctx->isc_tx_tso_segments_max > num_txd / 4797 MAX_SINGLE_PACKET_FRACTION) 4798 scctx->isc_tx_tso_segments_max = max(1, 4799 num_txd / MAX_SINGLE_PACKET_FRACTION); 4800 4801 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4802 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4803 /* 4804 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4805 * but some MACs do. 4806 */ 4807 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4808 IP_MAXPACKET)); 4809 /* 4810 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4811 * into account. In the worst case, each of these calls will 4812 * add another mbuf and, thus, the requirement for another DMA 4813 * segment. So for best performance, it doesn't make sense to 4814 * advertize a maximum of TSO segments that typically will 4815 * require defragmentation in iflib_encap(). 4816 */ 4817 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4818 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4819 } 4820 if (scctx->isc_rss_table_size == 0) 4821 scctx->isc_rss_table_size = 64; 4822 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4823 4824 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4825 /* XXX format name */ 4826 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4827 NULL, NULL, "admin"); 4828 4829 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4830 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4831 device_printf(dev, "Unable to fetch CPU list\n"); 4832 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4833 } 4834 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4835 4836 /* 4837 ** Now set up MSI or MSI-X, should return us the number of supported 4838 ** vectors (will be 1 for a legacy interrupt and MSI). 4839 */ 4840 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4841 msix = scctx->isc_vectors; 4842 } else if (scctx->isc_msix_bar != 0) 4843 /* 4844 * The simple fact that isc_msix_bar is not 0 does not mean we 4845 * we have a good value there that is known to work. 4846 */ 4847 msix = iflib_msix_init(ctx); 4848 else { 4849 scctx->isc_vectors = 1; 4850 scctx->isc_ntxqsets = 1; 4851 scctx->isc_nrxqsets = 1; 4852 scctx->isc_intr = IFLIB_INTR_LEGACY; 4853 msix = 0; 4854 } 4855 /* Get memory for the station queues */ 4856 if ((err = iflib_queues_alloc(ctx))) { 4857 device_printf(dev, "Unable to allocate queue memory\n"); 4858 goto fail_intr_free; 4859 } 4860 4861 if ((err = iflib_qset_structures_setup(ctx))) 4862 goto fail_queues; 4863 4864 /* 4865 * Now that we know how many queues there are, get the core offset. 4866 */ 4867 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4868 4869 if (msix > 1) { 4870 /* 4871 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4872 * aren't the default NULL implementation. 4873 */ 4874 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4875 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4876 kobj_desc); 4877 if (kobj_method == &kobj_desc->deflt) { 4878 device_printf(dev, 4879 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4880 err = EOPNOTSUPP; 4881 goto fail_queues; 4882 } 4883 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4884 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4885 kobj_desc); 4886 if (kobj_method == &kobj_desc->deflt) { 4887 device_printf(dev, 4888 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4889 err = EOPNOTSUPP; 4890 goto fail_queues; 4891 } 4892 4893 /* 4894 * Assign the MSI-X vectors. 4895 * Note that the default NULL ifdi_msix_intr_assign method will 4896 * fail here, too. 4897 */ 4898 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4899 if (err != 0) { 4900 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4901 err); 4902 goto fail_queues; 4903 } 4904 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4905 rid = 0; 4906 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4907 MPASS(msix == 1); 4908 rid = 1; 4909 } 4910 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4911 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4912 goto fail_queues; 4913 } 4914 } else { 4915 device_printf(dev, 4916 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4917 err = ENODEV; 4918 goto fail_queues; 4919 } 4920 4921 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4922 4923 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4924 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4925 goto fail_detach; 4926 } 4927 4928 /* 4929 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4930 * This must appear after the call to ether_ifattach() because 4931 * ether_ifattach() sets if_hdrlen to the default value. 4932 */ 4933 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4934 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4935 4936 if ((err = iflib_netmap_attach(ctx))) { 4937 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4938 goto fail_detach; 4939 } 4940 *ctxp = ctx; 4941 4942 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4943 4944 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4945 iflib_add_device_sysctl_post(ctx); 4946 iflib_add_pfil(ctx); 4947 ctx->ifc_flags |= IFC_INIT_DONE; 4948 CTX_UNLOCK(ctx); 4949 4950 return (0); 4951 4952 fail_detach: 4953 ether_ifdetach(ctx->ifc_ifp); 4954 fail_queues: 4955 iflib_tqg_detach(ctx); 4956 iflib_tx_structures_free(ctx); 4957 iflib_rx_structures_free(ctx); 4958 IFDI_DETACH(ctx); 4959 IFDI_QUEUES_FREE(ctx); 4960 fail_intr_free: 4961 iflib_free_intr_mem(ctx); 4962 fail_unlock: 4963 CTX_UNLOCK(ctx); 4964 iflib_deregister(ctx); 4965 fail_ctx_free: 4966 device_set_softc(ctx->ifc_dev, NULL); 4967 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4968 free(ctx->ifc_softc, M_IFLIB); 4969 free(ctx, M_IFLIB); 4970 return (err); 4971 } 4972 4973 int 4974 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4975 struct iflib_cloneattach_ctx *clctx) 4976 { 4977 int num_txd, num_rxd; 4978 int err; 4979 if_ctx_t ctx; 4980 if_t ifp; 4981 if_softc_ctx_t scctx; 4982 int i; 4983 void *sc; 4984 4985 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4986 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4987 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4988 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4989 ctx->ifc_flags |= IFC_PSEUDO; 4990 4991 ctx->ifc_sctx = sctx; 4992 ctx->ifc_softc = sc; 4993 ctx->ifc_dev = dev; 4994 4995 if ((err = iflib_register(ctx)) != 0) { 4996 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4997 goto fail_ctx_free; 4998 } 4999 iflib_add_device_sysctl_pre(ctx); 5000 5001 scctx = &ctx->ifc_softc_ctx; 5002 ifp = ctx->ifc_ifp; 5003 5004 iflib_reset_qvalues(ctx); 5005 CTX_LOCK(ctx); 5006 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5007 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5008 goto fail_unlock; 5009 } 5010 if (sctx->isc_flags & IFLIB_GEN_MAC) 5011 ether_gen_addr(ifp, &ctx->ifc_mac); 5012 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 5013 clctx->cc_params)) != 0) { 5014 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 5015 goto fail_unlock; 5016 } 5017 #ifdef INVARIANTS 5018 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5019 MPASS(scctx->isc_tx_csum_flags); 5020 #endif 5021 5022 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5023 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5024 5025 ifp->if_flags |= IFF_NOGROUP; 5026 if (sctx->isc_flags & IFLIB_PSEUDO) { 5027 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5028 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5029 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 5030 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5031 } else { 5032 if_attach(ctx->ifc_ifp); 5033 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 5034 } 5035 5036 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5037 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5038 goto fail_detach; 5039 } 5040 *ctxp = ctx; 5041 5042 /* 5043 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5044 * This must appear after the call to ether_ifattach() because 5045 * ether_ifattach() sets if_hdrlen to the default value. 5046 */ 5047 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5048 if_setifheaderlen(ifp, 5049 sizeof(struct ether_vlan_header)); 5050 5051 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5052 iflib_add_device_sysctl_post(ctx); 5053 ctx->ifc_flags |= IFC_INIT_DONE; 5054 CTX_UNLOCK(ctx); 5055 return (0); 5056 } 5057 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 5058 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5059 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5060 5061 _iflib_pre_assert(scctx); 5062 ctx->ifc_txrx = *scctx->isc_txrx; 5063 5064 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5065 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5066 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5067 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5068 5069 num_txd = iflib_num_tx_descs(ctx); 5070 num_rxd = iflib_num_rx_descs(ctx); 5071 5072 /* XXX change for per-queue sizes */ 5073 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5074 num_txd, num_rxd); 5075 5076 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5077 scctx->isc_tx_nsegments = max(1, num_txd / 5078 MAX_SINGLE_PACKET_FRACTION); 5079 if (scctx->isc_tx_tso_segments_max > num_txd / 5080 MAX_SINGLE_PACKET_FRACTION) 5081 scctx->isc_tx_tso_segments_max = max(1, 5082 num_txd / MAX_SINGLE_PACKET_FRACTION); 5083 5084 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5085 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5086 /* 5087 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5088 * but some MACs do. 5089 */ 5090 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5091 IP_MAXPACKET)); 5092 /* 5093 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5094 * into account. In the worst case, each of these calls will 5095 * add another mbuf and, thus, the requirement for another DMA 5096 * segment. So for best performance, it doesn't make sense to 5097 * advertize a maximum of TSO segments that typically will 5098 * require defragmentation in iflib_encap(). 5099 */ 5100 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5101 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5102 } 5103 if (scctx->isc_rss_table_size == 0) 5104 scctx->isc_rss_table_size = 64; 5105 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5106 5107 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5108 /* XXX format name */ 5109 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5110 NULL, NULL, "admin"); 5111 5112 /* XXX --- can support > 1 -- but keep it simple for now */ 5113 scctx->isc_intr = IFLIB_INTR_LEGACY; 5114 5115 /* Get memory for the station queues */ 5116 if ((err = iflib_queues_alloc(ctx))) { 5117 device_printf(dev, "Unable to allocate queue memory\n"); 5118 goto fail_iflib_detach; 5119 } 5120 5121 if ((err = iflib_qset_structures_setup(ctx))) { 5122 device_printf(dev, "qset structure setup failed %d\n", err); 5123 goto fail_queues; 5124 } 5125 5126 /* 5127 * XXX What if anything do we want to do about interrupts? 5128 */ 5129 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5130 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5131 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5132 goto fail_detach; 5133 } 5134 5135 /* 5136 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5137 * This must appear after the call to ether_ifattach() because 5138 * ether_ifattach() sets if_hdrlen to the default value. 5139 */ 5140 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5141 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5142 5143 /* XXX handle more than one queue */ 5144 for (i = 0; i < scctx->isc_nrxqsets; i++) 5145 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5146 5147 *ctxp = ctx; 5148 5149 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5150 iflib_add_device_sysctl_post(ctx); 5151 ctx->ifc_flags |= IFC_INIT_DONE; 5152 CTX_UNLOCK(ctx); 5153 5154 return (0); 5155 fail_detach: 5156 ether_ifdetach(ctx->ifc_ifp); 5157 fail_queues: 5158 iflib_tqg_detach(ctx); 5159 iflib_tx_structures_free(ctx); 5160 iflib_rx_structures_free(ctx); 5161 fail_iflib_detach: 5162 IFDI_DETACH(ctx); 5163 IFDI_QUEUES_FREE(ctx); 5164 fail_unlock: 5165 CTX_UNLOCK(ctx); 5166 iflib_deregister(ctx); 5167 fail_ctx_free: 5168 free(ctx->ifc_softc, M_IFLIB); 5169 free(ctx, M_IFLIB); 5170 return (err); 5171 } 5172 5173 int 5174 iflib_pseudo_deregister(if_ctx_t ctx) 5175 { 5176 if_t ifp = ctx->ifc_ifp; 5177 if_shared_ctx_t sctx = ctx->ifc_sctx; 5178 5179 /* Unregister VLAN event handlers early */ 5180 iflib_unregister_vlan_handlers(ctx); 5181 5182 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5183 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5184 bpfdetach(ifp); 5185 if_detach(ifp); 5186 } else { 5187 ether_ifdetach(ifp); 5188 } 5189 5190 iflib_tqg_detach(ctx); 5191 iflib_tx_structures_free(ctx); 5192 iflib_rx_structures_free(ctx); 5193 IFDI_DETACH(ctx); 5194 IFDI_QUEUES_FREE(ctx); 5195 5196 iflib_deregister(ctx); 5197 5198 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5199 free(ctx->ifc_softc, M_IFLIB); 5200 free(ctx, M_IFLIB); 5201 return (0); 5202 } 5203 5204 int 5205 iflib_device_attach(device_t dev) 5206 { 5207 if_ctx_t ctx; 5208 if_shared_ctx_t sctx; 5209 5210 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5211 return (ENOTSUP); 5212 5213 pci_enable_busmaster(dev); 5214 5215 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5216 } 5217 5218 int 5219 iflib_device_deregister(if_ctx_t ctx) 5220 { 5221 if_t ifp = ctx->ifc_ifp; 5222 device_t dev = ctx->ifc_dev; 5223 5224 /* Make sure VLANS are not using driver */ 5225 if (if_vlantrunkinuse(ifp)) { 5226 device_printf(dev, "Vlan in use, detach first\n"); 5227 return (EBUSY); 5228 } 5229 #ifdef PCI_IOV 5230 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5231 device_printf(dev, "SR-IOV in use; detach first.\n"); 5232 return (EBUSY); 5233 } 5234 #endif 5235 5236 STATE_LOCK(ctx); 5237 ctx->ifc_flags |= IFC_IN_DETACH; 5238 STATE_UNLOCK(ctx); 5239 5240 /* Unregister VLAN handlers before calling iflib_stop() */ 5241 iflib_unregister_vlan_handlers(ctx); 5242 5243 iflib_netmap_detach(ifp); 5244 ether_ifdetach(ifp); 5245 5246 CTX_LOCK(ctx); 5247 iflib_stop(ctx); 5248 CTX_UNLOCK(ctx); 5249 5250 iflib_rem_pfil(ctx); 5251 if (ctx->ifc_led_dev != NULL) 5252 led_destroy(ctx->ifc_led_dev); 5253 5254 iflib_tqg_detach(ctx); 5255 iflib_tx_structures_free(ctx); 5256 iflib_rx_structures_free(ctx); 5257 5258 CTX_LOCK(ctx); 5259 IFDI_DETACH(ctx); 5260 IFDI_QUEUES_FREE(ctx); 5261 CTX_UNLOCK(ctx); 5262 5263 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5264 iflib_free_intr_mem(ctx); 5265 5266 bus_generic_detach(dev); 5267 5268 iflib_deregister(ctx); 5269 5270 device_set_softc(ctx->ifc_dev, NULL); 5271 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5272 free(ctx->ifc_softc, M_IFLIB); 5273 unref_ctx_core_offset(ctx); 5274 free(ctx, M_IFLIB); 5275 return (0); 5276 } 5277 5278 static void 5279 iflib_tqg_detach(if_ctx_t ctx) 5280 { 5281 iflib_txq_t txq; 5282 iflib_rxq_t rxq; 5283 int i; 5284 struct taskqgroup *tqg; 5285 5286 /* XXX drain any dependent tasks */ 5287 tqg = qgroup_if_io_tqg; 5288 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5289 callout_drain(&txq->ift_timer); 5290 #ifdef DEV_NETMAP 5291 callout_drain(&txq->ift_netmap_timer); 5292 #endif /* DEV_NETMAP */ 5293 if (txq->ift_task.gt_uniq != NULL) 5294 taskqgroup_detach(tqg, &txq->ift_task); 5295 } 5296 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5297 if (rxq->ifr_task.gt_uniq != NULL) 5298 taskqgroup_detach(tqg, &rxq->ifr_task); 5299 } 5300 tqg = qgroup_if_config_tqg; 5301 if (ctx->ifc_admin_task.gt_uniq != NULL) 5302 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5303 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5304 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5305 } 5306 5307 static void 5308 iflib_free_intr_mem(if_ctx_t ctx) 5309 { 5310 5311 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5312 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5313 } 5314 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5315 pci_release_msi(ctx->ifc_dev); 5316 } 5317 if (ctx->ifc_msix_mem != NULL) { 5318 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5319 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5320 ctx->ifc_msix_mem = NULL; 5321 } 5322 } 5323 5324 int 5325 iflib_device_detach(device_t dev) 5326 { 5327 if_ctx_t ctx = device_get_softc(dev); 5328 5329 return (iflib_device_deregister(ctx)); 5330 } 5331 5332 int 5333 iflib_device_suspend(device_t dev) 5334 { 5335 if_ctx_t ctx = device_get_softc(dev); 5336 5337 CTX_LOCK(ctx); 5338 IFDI_SUSPEND(ctx); 5339 CTX_UNLOCK(ctx); 5340 5341 return bus_generic_suspend(dev); 5342 } 5343 int 5344 iflib_device_shutdown(device_t dev) 5345 { 5346 if_ctx_t ctx = device_get_softc(dev); 5347 5348 CTX_LOCK(ctx); 5349 IFDI_SHUTDOWN(ctx); 5350 CTX_UNLOCK(ctx); 5351 5352 return bus_generic_suspend(dev); 5353 } 5354 5355 int 5356 iflib_device_resume(device_t dev) 5357 { 5358 if_ctx_t ctx = device_get_softc(dev); 5359 iflib_txq_t txq = ctx->ifc_txqs; 5360 5361 CTX_LOCK(ctx); 5362 IFDI_RESUME(ctx); 5363 iflib_if_init_locked(ctx); 5364 CTX_UNLOCK(ctx); 5365 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5366 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5367 5368 return (bus_generic_resume(dev)); 5369 } 5370 5371 int 5372 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5373 { 5374 int error; 5375 if_ctx_t ctx = device_get_softc(dev); 5376 5377 CTX_LOCK(ctx); 5378 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5379 CTX_UNLOCK(ctx); 5380 5381 return (error); 5382 } 5383 5384 void 5385 iflib_device_iov_uninit(device_t dev) 5386 { 5387 if_ctx_t ctx = device_get_softc(dev); 5388 5389 CTX_LOCK(ctx); 5390 IFDI_IOV_UNINIT(ctx); 5391 CTX_UNLOCK(ctx); 5392 } 5393 5394 int 5395 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5396 { 5397 int error; 5398 if_ctx_t ctx = device_get_softc(dev); 5399 5400 CTX_LOCK(ctx); 5401 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5402 CTX_UNLOCK(ctx); 5403 5404 return (error); 5405 } 5406 5407 /********************************************************************* 5408 * 5409 * MODULE FUNCTION DEFINITIONS 5410 * 5411 **********************************************************************/ 5412 5413 /* 5414 * - Start a fast taskqueue thread for each core 5415 * - Start a taskqueue for control operations 5416 */ 5417 static int 5418 iflib_module_init(void) 5419 { 5420 iflib_timer_default = hz / 2; 5421 return (0); 5422 } 5423 5424 static int 5425 iflib_module_event_handler(module_t mod, int what, void *arg) 5426 { 5427 int err; 5428 5429 switch (what) { 5430 case MOD_LOAD: 5431 if ((err = iflib_module_init()) != 0) 5432 return (err); 5433 break; 5434 case MOD_UNLOAD: 5435 return (EBUSY); 5436 default: 5437 return (EOPNOTSUPP); 5438 } 5439 5440 return (0); 5441 } 5442 5443 /********************************************************************* 5444 * 5445 * PUBLIC FUNCTION DEFINITIONS 5446 * ordered as in iflib.h 5447 * 5448 **********************************************************************/ 5449 5450 static void 5451 _iflib_assert(if_shared_ctx_t sctx) 5452 { 5453 int i; 5454 5455 MPASS(sctx->isc_tx_maxsize); 5456 MPASS(sctx->isc_tx_maxsegsize); 5457 5458 MPASS(sctx->isc_rx_maxsize); 5459 MPASS(sctx->isc_rx_nsegments); 5460 MPASS(sctx->isc_rx_maxsegsize); 5461 5462 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5463 for (i = 0; i < sctx->isc_nrxqs; i++) { 5464 MPASS(sctx->isc_nrxd_min[i]); 5465 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5466 MPASS(sctx->isc_nrxd_max[i]); 5467 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5468 MPASS(sctx->isc_nrxd_default[i]); 5469 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5470 } 5471 5472 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5473 for (i = 0; i < sctx->isc_ntxqs; i++) { 5474 MPASS(sctx->isc_ntxd_min[i]); 5475 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5476 MPASS(sctx->isc_ntxd_max[i]); 5477 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5478 MPASS(sctx->isc_ntxd_default[i]); 5479 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5480 } 5481 } 5482 5483 static void 5484 _iflib_pre_assert(if_softc_ctx_t scctx) 5485 { 5486 5487 MPASS(scctx->isc_txrx->ift_txd_encap); 5488 MPASS(scctx->isc_txrx->ift_txd_flush); 5489 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5490 MPASS(scctx->isc_txrx->ift_rxd_available); 5491 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5492 MPASS(scctx->isc_txrx->ift_rxd_refill); 5493 MPASS(scctx->isc_txrx->ift_rxd_flush); 5494 } 5495 5496 static int 5497 iflib_register(if_ctx_t ctx) 5498 { 5499 if_shared_ctx_t sctx = ctx->ifc_sctx; 5500 driver_t *driver = sctx->isc_driver; 5501 device_t dev = ctx->ifc_dev; 5502 if_t ifp; 5503 u_char type; 5504 int iflags; 5505 5506 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5507 _iflib_assert(sctx); 5508 5509 CTX_LOCK_INIT(ctx); 5510 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5511 if (sctx->isc_flags & IFLIB_PSEUDO) { 5512 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5513 type = IFT_ETHER; 5514 else 5515 type = IFT_PPP; 5516 } else 5517 type = IFT_ETHER; 5518 ifp = ctx->ifc_ifp = if_alloc(type); 5519 if (ifp == NULL) { 5520 device_printf(dev, "can not allocate ifnet structure\n"); 5521 return (ENOMEM); 5522 } 5523 5524 /* 5525 * Initialize our context's device specific methods 5526 */ 5527 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5528 kobj_class_compile((kobj_class_t) driver); 5529 5530 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5531 if_setsoftc(ifp, ctx); 5532 if_setdev(ifp, dev); 5533 if_setinitfn(ifp, iflib_if_init); 5534 if_setioctlfn(ifp, iflib_if_ioctl); 5535 #ifdef ALTQ 5536 if_setstartfn(ifp, iflib_altq_if_start); 5537 if_settransmitfn(ifp, iflib_altq_if_transmit); 5538 if_setsendqready(ifp); 5539 #else 5540 if_settransmitfn(ifp, iflib_if_transmit); 5541 #endif 5542 if_setqflushfn(ifp, iflib_if_qflush); 5543 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5544 5545 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5546 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5547 iflags |= IFF_POINTOPOINT; 5548 else 5549 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5550 if_setflags(ifp, iflags); 5551 ctx->ifc_vlan_attach_event = 5552 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5553 EVENTHANDLER_PRI_FIRST); 5554 ctx->ifc_vlan_detach_event = 5555 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5556 EVENTHANDLER_PRI_FIRST); 5557 5558 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5559 ctx->ifc_mediap = &ctx->ifc_media; 5560 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5561 iflib_media_change, iflib_media_status); 5562 } 5563 return (0); 5564 } 5565 5566 static void 5567 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5568 { 5569 /* Unregister VLAN events */ 5570 if (ctx->ifc_vlan_attach_event != NULL) { 5571 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5572 ctx->ifc_vlan_attach_event = NULL; 5573 } 5574 if (ctx->ifc_vlan_detach_event != NULL) { 5575 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5576 ctx->ifc_vlan_detach_event = NULL; 5577 } 5578 5579 } 5580 5581 static void 5582 iflib_deregister(if_ctx_t ctx) 5583 { 5584 if_t ifp = ctx->ifc_ifp; 5585 5586 /* Remove all media */ 5587 ifmedia_removeall(&ctx->ifc_media); 5588 5589 /* Ensure that VLAN event handlers are unregistered */ 5590 iflib_unregister_vlan_handlers(ctx); 5591 5592 /* Release kobject reference */ 5593 kobj_delete((kobj_t) ctx, NULL); 5594 5595 /* Free the ifnet structure */ 5596 if_free(ifp); 5597 5598 STATE_LOCK_DESTROY(ctx); 5599 5600 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5601 CTX_LOCK_DESTROY(ctx); 5602 } 5603 5604 static int 5605 iflib_queues_alloc(if_ctx_t ctx) 5606 { 5607 if_shared_ctx_t sctx = ctx->ifc_sctx; 5608 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5609 device_t dev = ctx->ifc_dev; 5610 int nrxqsets = scctx->isc_nrxqsets; 5611 int ntxqsets = scctx->isc_ntxqsets; 5612 iflib_txq_t txq; 5613 iflib_rxq_t rxq; 5614 iflib_fl_t fl = NULL; 5615 int i, j, cpu, err, txconf, rxconf; 5616 iflib_dma_info_t ifdip; 5617 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5618 uint32_t *txqsizes = scctx->isc_txqsizes; 5619 uint8_t nrxqs = sctx->isc_nrxqs; 5620 uint8_t ntxqs = sctx->isc_ntxqs; 5621 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5622 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5623 caddr_t *vaddrs; 5624 uint64_t *paddrs; 5625 5626 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5627 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5628 KASSERT(nrxqs >= fl_offset + nfree_lists, 5629 ("there must be at least a rxq for each free list")); 5630 5631 /* Allocate the TX ring struct memory */ 5632 if (!(ctx->ifc_txqs = 5633 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5634 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5635 device_printf(dev, "Unable to allocate TX ring memory\n"); 5636 err = ENOMEM; 5637 goto fail; 5638 } 5639 5640 /* Now allocate the RX */ 5641 if (!(ctx->ifc_rxqs = 5642 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5643 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5644 device_printf(dev, "Unable to allocate RX ring memory\n"); 5645 err = ENOMEM; 5646 goto rx_fail; 5647 } 5648 5649 txq = ctx->ifc_txqs; 5650 rxq = ctx->ifc_rxqs; 5651 5652 /* 5653 * XXX handle allocation failure 5654 */ 5655 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5656 /* Set up some basics */ 5657 5658 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5659 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5660 device_printf(dev, 5661 "Unable to allocate TX DMA info memory\n"); 5662 err = ENOMEM; 5663 goto err_tx_desc; 5664 } 5665 txq->ift_ifdi = ifdip; 5666 for (j = 0; j < ntxqs; j++, ifdip++) { 5667 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5668 device_printf(dev, 5669 "Unable to allocate TX descriptors\n"); 5670 err = ENOMEM; 5671 goto err_tx_desc; 5672 } 5673 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5674 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5675 } 5676 txq->ift_ctx = ctx; 5677 txq->ift_id = i; 5678 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5679 txq->ift_br_offset = 1; 5680 } else { 5681 txq->ift_br_offset = 0; 5682 } 5683 5684 if (iflib_txsd_alloc(txq)) { 5685 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5686 err = ENOMEM; 5687 goto err_tx_desc; 5688 } 5689 5690 /* Initialize the TX lock */ 5691 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5692 device_get_nameunit(dev), txq->ift_id); 5693 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5694 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5695 txq->ift_timer.c_cpu = cpu; 5696 #ifdef DEV_NETMAP 5697 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5698 txq->ift_netmap_timer.c_cpu = cpu; 5699 #endif /* DEV_NETMAP */ 5700 5701 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5702 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5703 if (err) { 5704 /* XXX free any allocated rings */ 5705 device_printf(dev, "Unable to allocate buf_ring\n"); 5706 goto err_tx_desc; 5707 } 5708 } 5709 5710 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5711 /* Set up some basics */ 5712 callout_init(&rxq->ifr_watchdog, 1); 5713 5714 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5715 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5716 device_printf(dev, 5717 "Unable to allocate RX DMA info memory\n"); 5718 err = ENOMEM; 5719 goto err_tx_desc; 5720 } 5721 5722 rxq->ifr_ifdi = ifdip; 5723 /* XXX this needs to be changed if #rx queues != #tx queues */ 5724 rxq->ifr_ntxqirq = 1; 5725 rxq->ifr_txqid[0] = i; 5726 for (j = 0; j < nrxqs; j++, ifdip++) { 5727 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5728 device_printf(dev, 5729 "Unable to allocate RX descriptors\n"); 5730 err = ENOMEM; 5731 goto err_tx_desc; 5732 } 5733 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5734 } 5735 rxq->ifr_ctx = ctx; 5736 rxq->ifr_id = i; 5737 rxq->ifr_fl_offset = fl_offset; 5738 rxq->ifr_nfl = nfree_lists; 5739 if (!(fl = 5740 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5741 device_printf(dev, "Unable to allocate free list memory\n"); 5742 err = ENOMEM; 5743 goto err_tx_desc; 5744 } 5745 rxq->ifr_fl = fl; 5746 for (j = 0; j < nfree_lists; j++) { 5747 fl[j].ifl_rxq = rxq; 5748 fl[j].ifl_id = j; 5749 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5750 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5751 } 5752 /* Allocate receive buffers for the ring */ 5753 if (iflib_rxsd_alloc(rxq)) { 5754 device_printf(dev, 5755 "Critical Failure setting up receive buffers\n"); 5756 err = ENOMEM; 5757 goto err_rx_desc; 5758 } 5759 5760 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5761 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5762 M_WAITOK); 5763 } 5764 5765 /* TXQs */ 5766 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5767 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5768 for (i = 0; i < ntxqsets; i++) { 5769 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5770 5771 for (j = 0; j < ntxqs; j++, di++) { 5772 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5773 paddrs[i*ntxqs + j] = di->idi_paddr; 5774 } 5775 } 5776 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5777 device_printf(ctx->ifc_dev, 5778 "Unable to allocate device TX queue\n"); 5779 iflib_tx_structures_free(ctx); 5780 free(vaddrs, M_IFLIB); 5781 free(paddrs, M_IFLIB); 5782 goto err_rx_desc; 5783 } 5784 free(vaddrs, M_IFLIB); 5785 free(paddrs, M_IFLIB); 5786 5787 /* RXQs */ 5788 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5789 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5790 for (i = 0; i < nrxqsets; i++) { 5791 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5792 5793 for (j = 0; j < nrxqs; j++, di++) { 5794 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5795 paddrs[i*nrxqs + j] = di->idi_paddr; 5796 } 5797 } 5798 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5799 device_printf(ctx->ifc_dev, 5800 "Unable to allocate device RX queue\n"); 5801 iflib_tx_structures_free(ctx); 5802 free(vaddrs, M_IFLIB); 5803 free(paddrs, M_IFLIB); 5804 goto err_rx_desc; 5805 } 5806 free(vaddrs, M_IFLIB); 5807 free(paddrs, M_IFLIB); 5808 5809 return (0); 5810 5811 /* XXX handle allocation failure changes */ 5812 err_rx_desc: 5813 err_tx_desc: 5814 rx_fail: 5815 if (ctx->ifc_rxqs != NULL) 5816 free(ctx->ifc_rxqs, M_IFLIB); 5817 ctx->ifc_rxqs = NULL; 5818 if (ctx->ifc_txqs != NULL) 5819 free(ctx->ifc_txqs, M_IFLIB); 5820 ctx->ifc_txqs = NULL; 5821 fail: 5822 return (err); 5823 } 5824 5825 static int 5826 iflib_tx_structures_setup(if_ctx_t ctx) 5827 { 5828 iflib_txq_t txq = ctx->ifc_txqs; 5829 int i; 5830 5831 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5832 iflib_txq_setup(txq); 5833 5834 return (0); 5835 } 5836 5837 static void 5838 iflib_tx_structures_free(if_ctx_t ctx) 5839 { 5840 iflib_txq_t txq = ctx->ifc_txqs; 5841 if_shared_ctx_t sctx = ctx->ifc_sctx; 5842 int i, j; 5843 5844 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5845 for (j = 0; j < sctx->isc_ntxqs; j++) 5846 iflib_dma_free(&txq->ift_ifdi[j]); 5847 iflib_txq_destroy(txq); 5848 } 5849 free(ctx->ifc_txqs, M_IFLIB); 5850 ctx->ifc_txqs = NULL; 5851 } 5852 5853 /********************************************************************* 5854 * 5855 * Initialize all receive rings. 5856 * 5857 **********************************************************************/ 5858 static int 5859 iflib_rx_structures_setup(if_ctx_t ctx) 5860 { 5861 iflib_rxq_t rxq = ctx->ifc_rxqs; 5862 int q; 5863 #if defined(INET6) || defined(INET) 5864 int err, i; 5865 #endif 5866 5867 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5868 #if defined(INET6) || defined(INET) 5869 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5870 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5871 TCP_LRO_ENTRIES, min(1024, 5872 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5873 if (err != 0) { 5874 device_printf(ctx->ifc_dev, 5875 "LRO Initialization failed!\n"); 5876 goto fail; 5877 } 5878 } 5879 #endif 5880 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5881 } 5882 return (0); 5883 #if defined(INET6) || defined(INET) 5884 fail: 5885 /* 5886 * Free LRO resources allocated so far, we will only handle 5887 * the rings that completed, the failing case will have 5888 * cleaned up for itself. 'q' failed, so its the terminus. 5889 */ 5890 rxq = ctx->ifc_rxqs; 5891 for (i = 0; i < q; ++i, rxq++) { 5892 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5893 tcp_lro_free(&rxq->ifr_lc); 5894 } 5895 return (err); 5896 #endif 5897 } 5898 5899 /********************************************************************* 5900 * 5901 * Free all receive rings. 5902 * 5903 **********************************************************************/ 5904 static void 5905 iflib_rx_structures_free(if_ctx_t ctx) 5906 { 5907 iflib_rxq_t rxq = ctx->ifc_rxqs; 5908 if_shared_ctx_t sctx = ctx->ifc_sctx; 5909 int i, j; 5910 5911 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5912 for (j = 0; j < sctx->isc_nrxqs; j++) 5913 iflib_dma_free(&rxq->ifr_ifdi[j]); 5914 iflib_rx_sds_free(rxq); 5915 #if defined(INET6) || defined(INET) 5916 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5917 tcp_lro_free(&rxq->ifr_lc); 5918 #endif 5919 } 5920 free(ctx->ifc_rxqs, M_IFLIB); 5921 ctx->ifc_rxqs = NULL; 5922 } 5923 5924 static int 5925 iflib_qset_structures_setup(if_ctx_t ctx) 5926 { 5927 int err; 5928 5929 /* 5930 * It is expected that the caller takes care of freeing queues if this 5931 * fails. 5932 */ 5933 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5934 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5935 return (err); 5936 } 5937 5938 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5939 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5940 5941 return (err); 5942 } 5943 5944 int 5945 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5946 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5947 { 5948 5949 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5950 } 5951 5952 #ifdef SMP 5953 static int 5954 find_nth(if_ctx_t ctx, int qid) 5955 { 5956 cpuset_t cpus; 5957 int i, cpuid, eqid, count; 5958 5959 CPU_COPY(&ctx->ifc_cpus, &cpus); 5960 count = CPU_COUNT(&cpus); 5961 eqid = qid % count; 5962 /* clear up to the qid'th bit */ 5963 for (i = 0; i < eqid; i++) { 5964 cpuid = CPU_FFS(&cpus); 5965 MPASS(cpuid != 0); 5966 CPU_CLR(cpuid-1, &cpus); 5967 } 5968 cpuid = CPU_FFS(&cpus); 5969 MPASS(cpuid != 0); 5970 return (cpuid-1); 5971 } 5972 5973 #ifdef SCHED_ULE 5974 extern struct cpu_group *cpu_top; /* CPU topology */ 5975 5976 static int 5977 find_child_with_core(int cpu, struct cpu_group *grp) 5978 { 5979 int i; 5980 5981 if (grp->cg_children == 0) 5982 return -1; 5983 5984 MPASS(grp->cg_child); 5985 for (i = 0; i < grp->cg_children; i++) { 5986 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5987 return i; 5988 } 5989 5990 return -1; 5991 } 5992 5993 /* 5994 * Find the nth "close" core to the specified core 5995 * "close" is defined as the deepest level that shares 5996 * at least an L2 cache. With threads, this will be 5997 * threads on the same core. If the shared cache is L3 5998 * or higher, simply returns the same core. 5999 */ 6000 static int 6001 find_close_core(int cpu, int core_offset) 6002 { 6003 struct cpu_group *grp; 6004 int i; 6005 int fcpu; 6006 cpuset_t cs; 6007 6008 grp = cpu_top; 6009 if (grp == NULL) 6010 return cpu; 6011 i = 0; 6012 while ((i = find_child_with_core(cpu, grp)) != -1) { 6013 /* If the child only has one cpu, don't descend */ 6014 if (grp->cg_child[i].cg_count <= 1) 6015 break; 6016 grp = &grp->cg_child[i]; 6017 } 6018 6019 /* If they don't share at least an L2 cache, use the same CPU */ 6020 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 6021 return cpu; 6022 6023 /* Now pick one */ 6024 CPU_COPY(&grp->cg_mask, &cs); 6025 6026 /* Add the selected CPU offset to core offset. */ 6027 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 6028 if (fcpu - 1 == cpu) 6029 break; 6030 CPU_CLR(fcpu - 1, &cs); 6031 } 6032 MPASS(fcpu); 6033 6034 core_offset += i; 6035 6036 CPU_COPY(&grp->cg_mask, &cs); 6037 for (i = core_offset % grp->cg_count; i > 0; i--) { 6038 MPASS(CPU_FFS(&cs)); 6039 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 6040 } 6041 MPASS(CPU_FFS(&cs)); 6042 return CPU_FFS(&cs) - 1; 6043 } 6044 #else 6045 static int 6046 find_close_core(int cpu, int core_offset __unused) 6047 { 6048 return cpu; 6049 } 6050 #endif 6051 6052 static int 6053 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 6054 { 6055 switch (type) { 6056 case IFLIB_INTR_TX: 6057 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 6058 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 6059 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 6060 case IFLIB_INTR_RX: 6061 case IFLIB_INTR_RXTX: 6062 /* RX queues get the specified core */ 6063 return qid / CPU_COUNT(&ctx->ifc_cpus); 6064 default: 6065 return -1; 6066 } 6067 } 6068 #else 6069 #define get_core_offset(ctx, type, qid) CPU_FIRST() 6070 #define find_close_core(cpuid, tid) CPU_FIRST() 6071 #define find_nth(ctx, gid) CPU_FIRST() 6072 #endif 6073 6074 /* Just to avoid copy/paste */ 6075 static inline int 6076 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6077 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6078 const char *name) 6079 { 6080 device_t dev; 6081 int co, cpuid, err, tid; 6082 6083 dev = ctx->ifc_dev; 6084 co = ctx->ifc_sysctl_core_offset; 6085 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 6086 co += ctx->ifc_softc_ctx.isc_nrxqsets; 6087 cpuid = find_nth(ctx, qid + co); 6088 tid = get_core_offset(ctx, type, qid); 6089 if (tid < 0) { 6090 device_printf(dev, "get_core_offset failed\n"); 6091 return (EOPNOTSUPP); 6092 } 6093 cpuid = find_close_core(cpuid, tid); 6094 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 6095 name); 6096 if (err) { 6097 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6098 return (err); 6099 } 6100 #ifdef notyet 6101 if (cpuid > ctx->ifc_cpuid_highest) 6102 ctx->ifc_cpuid_highest = cpuid; 6103 #endif 6104 return (0); 6105 } 6106 6107 int 6108 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6109 iflib_intr_type_t type, driver_filter_t *filter, 6110 void *filter_arg, int qid, const char *name) 6111 { 6112 device_t dev; 6113 struct grouptask *gtask; 6114 struct taskqgroup *tqg; 6115 iflib_filter_info_t info; 6116 gtask_fn_t *fn; 6117 int tqrid, err; 6118 driver_filter_t *intr_fast; 6119 void *q; 6120 6121 info = &ctx->ifc_filter_info; 6122 tqrid = rid; 6123 6124 switch (type) { 6125 /* XXX merge tx/rx for netmap? */ 6126 case IFLIB_INTR_TX: 6127 q = &ctx->ifc_txqs[qid]; 6128 info = &ctx->ifc_txqs[qid].ift_filter_info; 6129 gtask = &ctx->ifc_txqs[qid].ift_task; 6130 tqg = qgroup_if_io_tqg; 6131 fn = _task_fn_tx; 6132 intr_fast = iflib_fast_intr; 6133 GROUPTASK_INIT(gtask, 0, fn, q); 6134 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6135 break; 6136 case IFLIB_INTR_RX: 6137 q = &ctx->ifc_rxqs[qid]; 6138 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6139 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6140 tqg = qgroup_if_io_tqg; 6141 fn = _task_fn_rx; 6142 intr_fast = iflib_fast_intr; 6143 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6144 break; 6145 case IFLIB_INTR_RXTX: 6146 q = &ctx->ifc_rxqs[qid]; 6147 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6148 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6149 tqg = qgroup_if_io_tqg; 6150 fn = _task_fn_rx; 6151 intr_fast = iflib_fast_intr_rxtx; 6152 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6153 break; 6154 case IFLIB_INTR_ADMIN: 6155 q = ctx; 6156 tqrid = -1; 6157 info = &ctx->ifc_filter_info; 6158 gtask = &ctx->ifc_admin_task; 6159 tqg = qgroup_if_config_tqg; 6160 fn = _task_fn_admin; 6161 intr_fast = iflib_fast_intr_ctx; 6162 break; 6163 default: 6164 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6165 __func__); 6166 return (EINVAL); 6167 } 6168 6169 info->ifi_filter = filter; 6170 info->ifi_filter_arg = filter_arg; 6171 info->ifi_task = gtask; 6172 info->ifi_ctx = q; 6173 6174 dev = ctx->ifc_dev; 6175 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6176 if (err != 0) { 6177 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6178 return (err); 6179 } 6180 if (type == IFLIB_INTR_ADMIN) 6181 return (0); 6182 6183 if (tqrid != -1) { 6184 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6185 q, name); 6186 if (err) 6187 return (err); 6188 } else { 6189 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6190 } 6191 6192 return (0); 6193 } 6194 6195 void 6196 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6197 { 6198 struct grouptask *gtask; 6199 struct taskqgroup *tqg; 6200 gtask_fn_t *fn; 6201 void *q; 6202 int err; 6203 6204 switch (type) { 6205 case IFLIB_INTR_TX: 6206 q = &ctx->ifc_txqs[qid]; 6207 gtask = &ctx->ifc_txqs[qid].ift_task; 6208 tqg = qgroup_if_io_tqg; 6209 fn = _task_fn_tx; 6210 GROUPTASK_INIT(gtask, 0, fn, q); 6211 break; 6212 case IFLIB_INTR_RX: 6213 q = &ctx->ifc_rxqs[qid]; 6214 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6215 tqg = qgroup_if_io_tqg; 6216 fn = _task_fn_rx; 6217 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6218 break; 6219 case IFLIB_INTR_IOV: 6220 q = ctx; 6221 gtask = &ctx->ifc_vflr_task; 6222 tqg = qgroup_if_config_tqg; 6223 fn = _task_fn_iov; 6224 GROUPTASK_INIT(gtask, 0, fn, q); 6225 break; 6226 default: 6227 panic("unknown net intr type"); 6228 } 6229 if (irq != NULL) { 6230 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6231 q, name); 6232 if (err) 6233 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6234 irq->ii_res, name); 6235 } else { 6236 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6237 } 6238 } 6239 6240 void 6241 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6242 { 6243 6244 if (irq->ii_tag) 6245 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6246 6247 if (irq->ii_res) 6248 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6249 rman_get_rid(irq->ii_res), irq->ii_res); 6250 } 6251 6252 static int 6253 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6254 { 6255 iflib_txq_t txq = ctx->ifc_txqs; 6256 iflib_rxq_t rxq = ctx->ifc_rxqs; 6257 if_irq_t irq = &ctx->ifc_legacy_irq; 6258 iflib_filter_info_t info; 6259 device_t dev; 6260 struct grouptask *gtask; 6261 struct resource *res; 6262 struct taskqgroup *tqg; 6263 void *q; 6264 int err, tqrid; 6265 bool rx_only; 6266 6267 q = &ctx->ifc_rxqs[0]; 6268 info = &rxq[0].ifr_filter_info; 6269 gtask = &rxq[0].ifr_task; 6270 tqg = qgroup_if_io_tqg; 6271 tqrid = *rid; 6272 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6273 6274 ctx->ifc_flags |= IFC_LEGACY; 6275 info->ifi_filter = filter; 6276 info->ifi_filter_arg = filter_arg; 6277 info->ifi_task = gtask; 6278 info->ifi_ctx = rx_only ? ctx : q; 6279 6280 dev = ctx->ifc_dev; 6281 /* We allocate a single interrupt resource */ 6282 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6283 iflib_fast_intr_rxtx, NULL, info, name); 6284 if (err != 0) 6285 return (err); 6286 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6287 res = irq->ii_res; 6288 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6289 6290 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6291 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6292 "tx"); 6293 return (0); 6294 } 6295 6296 void 6297 iflib_led_create(if_ctx_t ctx) 6298 { 6299 6300 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6301 device_get_nameunit(ctx->ifc_dev)); 6302 } 6303 6304 void 6305 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6306 { 6307 6308 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6309 } 6310 6311 void 6312 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6313 { 6314 6315 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6316 } 6317 6318 void 6319 iflib_admin_intr_deferred(if_ctx_t ctx) 6320 { 6321 6322 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6323 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6324 } 6325 6326 void 6327 iflib_iov_intr_deferred(if_ctx_t ctx) 6328 { 6329 6330 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6331 } 6332 6333 void 6334 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6335 { 6336 6337 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6338 name); 6339 } 6340 6341 void 6342 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6343 const char *name) 6344 { 6345 6346 GROUPTASK_INIT(gtask, 0, fn, ctx); 6347 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6348 name); 6349 } 6350 6351 void 6352 iflib_config_gtask_deinit(struct grouptask *gtask) 6353 { 6354 6355 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6356 } 6357 6358 void 6359 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6360 { 6361 if_t ifp = ctx->ifc_ifp; 6362 iflib_txq_t txq = ctx->ifc_txqs; 6363 6364 if_setbaudrate(ifp, baudrate); 6365 if (baudrate >= IF_Gbps(10)) { 6366 STATE_LOCK(ctx); 6367 ctx->ifc_flags |= IFC_PREFETCH; 6368 STATE_UNLOCK(ctx); 6369 } 6370 /* If link down, disable watchdog */ 6371 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6372 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6373 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6374 } 6375 ctx->ifc_link_state = link_state; 6376 if_link_state_change(ifp, link_state); 6377 } 6378 6379 static int 6380 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6381 { 6382 int credits; 6383 #ifdef INVARIANTS 6384 int credits_pre = txq->ift_cidx_processed; 6385 #endif 6386 6387 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6388 BUS_DMASYNC_POSTREAD); 6389 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6390 return (0); 6391 6392 txq->ift_processed += credits; 6393 txq->ift_cidx_processed += credits; 6394 6395 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6396 if (txq->ift_cidx_processed >= txq->ift_size) 6397 txq->ift_cidx_processed -= txq->ift_size; 6398 return (credits); 6399 } 6400 6401 static int 6402 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6403 { 6404 iflib_fl_t fl; 6405 u_int i; 6406 6407 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6408 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6409 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6410 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6411 budget)); 6412 } 6413 6414 void 6415 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6416 const char *description, if_int_delay_info_t info, 6417 int offset, int value) 6418 { 6419 info->iidi_ctx = ctx; 6420 info->iidi_offset = offset; 6421 info->iidi_value = value; 6422 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6423 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6424 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6425 info, 0, iflib_sysctl_int_delay, "I", description); 6426 } 6427 6428 struct sx * 6429 iflib_ctx_lock_get(if_ctx_t ctx) 6430 { 6431 6432 return (&ctx->ifc_ctx_sx); 6433 } 6434 6435 static int 6436 iflib_msix_init(if_ctx_t ctx) 6437 { 6438 device_t dev = ctx->ifc_dev; 6439 if_shared_ctx_t sctx = ctx->ifc_sctx; 6440 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6441 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6442 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6443 6444 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6445 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6446 6447 if (bootverbose) 6448 device_printf(dev, "msix_init qsets capped at %d\n", 6449 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6450 6451 /* Override by tuneable */ 6452 if (scctx->isc_disable_msix) 6453 goto msi; 6454 6455 /* First try MSI-X */ 6456 if ((msgs = pci_msix_count(dev)) == 0) { 6457 if (bootverbose) 6458 device_printf(dev, "MSI-X not supported or disabled\n"); 6459 goto msi; 6460 } 6461 6462 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6463 /* 6464 * bar == -1 => "trust me I know what I'm doing" 6465 * Some drivers are for hardware that is so shoddily 6466 * documented that no one knows which bars are which 6467 * so the developer has to map all bars. This hack 6468 * allows shoddy garbage to use MSI-X in this framework. 6469 */ 6470 if (bar != -1) { 6471 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6472 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6473 if (ctx->ifc_msix_mem == NULL) { 6474 device_printf(dev, "Unable to map MSI-X table\n"); 6475 goto msi; 6476 } 6477 } 6478 6479 admincnt = sctx->isc_admin_intrcnt; 6480 #if IFLIB_DEBUG 6481 /* use only 1 qset in debug mode */ 6482 queuemsgs = min(msgs - admincnt, 1); 6483 #else 6484 queuemsgs = msgs - admincnt; 6485 #endif 6486 #ifdef RSS 6487 queues = imin(queuemsgs, rss_getnumbuckets()); 6488 #else 6489 queues = queuemsgs; 6490 #endif 6491 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6492 if (bootverbose) 6493 device_printf(dev, 6494 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6495 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6496 #ifdef RSS 6497 /* If we're doing RSS, clamp at the number of RSS buckets */ 6498 if (queues > rss_getnumbuckets()) 6499 queues = rss_getnumbuckets(); 6500 #endif 6501 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6502 rx_queues = iflib_num_rx_queues; 6503 else 6504 rx_queues = queues; 6505 6506 if (rx_queues > scctx->isc_nrxqsets) 6507 rx_queues = scctx->isc_nrxqsets; 6508 6509 /* 6510 * We want this to be all logical CPUs by default 6511 */ 6512 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6513 tx_queues = iflib_num_tx_queues; 6514 else 6515 tx_queues = mp_ncpus; 6516 6517 if (tx_queues > scctx->isc_ntxqsets) 6518 tx_queues = scctx->isc_ntxqsets; 6519 6520 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6521 #ifdef INVARIANTS 6522 if (tx_queues != rx_queues) 6523 device_printf(dev, 6524 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6525 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6526 #endif 6527 tx_queues = min(rx_queues, tx_queues); 6528 rx_queues = min(rx_queues, tx_queues); 6529 } 6530 6531 vectors = rx_queues + admincnt; 6532 if (msgs < vectors) { 6533 device_printf(dev, 6534 "insufficient number of MSI-X vectors " 6535 "(supported %d, need %d)\n", msgs, vectors); 6536 goto msi; 6537 } 6538 6539 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6540 tx_queues); 6541 msgs = vectors; 6542 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6543 if (vectors != msgs) { 6544 device_printf(dev, 6545 "Unable to allocate sufficient MSI-X vectors " 6546 "(got %d, need %d)\n", vectors, msgs); 6547 pci_release_msi(dev); 6548 if (bar != -1) { 6549 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6550 ctx->ifc_msix_mem); 6551 ctx->ifc_msix_mem = NULL; 6552 } 6553 goto msi; 6554 } 6555 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6556 vectors); 6557 scctx->isc_vectors = vectors; 6558 scctx->isc_nrxqsets = rx_queues; 6559 scctx->isc_ntxqsets = tx_queues; 6560 scctx->isc_intr = IFLIB_INTR_MSIX; 6561 6562 return (vectors); 6563 } else { 6564 device_printf(dev, 6565 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6566 err); 6567 if (bar != -1) { 6568 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6569 ctx->ifc_msix_mem); 6570 ctx->ifc_msix_mem = NULL; 6571 } 6572 } 6573 6574 msi: 6575 vectors = pci_msi_count(dev); 6576 scctx->isc_nrxqsets = 1; 6577 scctx->isc_ntxqsets = 1; 6578 scctx->isc_vectors = vectors; 6579 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6580 device_printf(dev,"Using an MSI interrupt\n"); 6581 scctx->isc_intr = IFLIB_INTR_MSI; 6582 } else { 6583 scctx->isc_vectors = 1; 6584 device_printf(dev,"Using a Legacy interrupt\n"); 6585 scctx->isc_intr = IFLIB_INTR_LEGACY; 6586 } 6587 6588 return (vectors); 6589 } 6590 6591 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6592 6593 static int 6594 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6595 { 6596 int rc; 6597 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6598 struct sbuf *sb; 6599 const char *ring_state = "UNKNOWN"; 6600 6601 /* XXX needed ? */ 6602 rc = sysctl_wire_old_buffer(req, 0); 6603 MPASS(rc == 0); 6604 if (rc != 0) 6605 return (rc); 6606 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6607 MPASS(sb != NULL); 6608 if (sb == NULL) 6609 return (ENOMEM); 6610 if (state[3] <= 3) 6611 ring_state = ring_states[state[3]]; 6612 6613 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6614 state[0], state[1], state[2], ring_state); 6615 rc = sbuf_finish(sb); 6616 sbuf_delete(sb); 6617 return(rc); 6618 } 6619 6620 enum iflib_ndesc_handler { 6621 IFLIB_NTXD_HANDLER, 6622 IFLIB_NRXD_HANDLER, 6623 }; 6624 6625 static int 6626 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6627 { 6628 if_ctx_t ctx = (void *)arg1; 6629 enum iflib_ndesc_handler type = arg2; 6630 char buf[256] = {0}; 6631 qidx_t *ndesc; 6632 char *p, *next; 6633 int nqs, rc, i; 6634 6635 nqs = 8; 6636 switch(type) { 6637 case IFLIB_NTXD_HANDLER: 6638 ndesc = ctx->ifc_sysctl_ntxds; 6639 if (ctx->ifc_sctx) 6640 nqs = ctx->ifc_sctx->isc_ntxqs; 6641 break; 6642 case IFLIB_NRXD_HANDLER: 6643 ndesc = ctx->ifc_sysctl_nrxds; 6644 if (ctx->ifc_sctx) 6645 nqs = ctx->ifc_sctx->isc_nrxqs; 6646 break; 6647 default: 6648 printf("%s: unhandled type\n", __func__); 6649 return (EINVAL); 6650 } 6651 if (nqs == 0) 6652 nqs = 8; 6653 6654 for (i=0; i<8; i++) { 6655 if (i >= nqs) 6656 break; 6657 if (i) 6658 strcat(buf, ","); 6659 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6660 } 6661 6662 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6663 if (rc || req->newptr == NULL) 6664 return rc; 6665 6666 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6667 i++, p = strsep(&next, " ,")) { 6668 ndesc[i] = strtoul(p, NULL, 10); 6669 } 6670 6671 return(rc); 6672 } 6673 6674 #define NAME_BUFLEN 32 6675 static void 6676 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6677 { 6678 device_t dev = iflib_get_dev(ctx); 6679 struct sysctl_oid_list *child, *oid_list; 6680 struct sysctl_ctx_list *ctx_list; 6681 struct sysctl_oid *node; 6682 6683 ctx_list = device_get_sysctl_ctx(dev); 6684 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6685 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6686 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6687 oid_list = SYSCTL_CHILDREN(node); 6688 6689 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6690 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6691 "driver version"); 6692 6693 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6694 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6695 "# of txqs to use, 0 => use default #"); 6696 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6697 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6698 "# of rxqs to use, 0 => use default #"); 6699 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6700 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6701 "permit #txq != #rxq"); 6702 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6703 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6704 "disable MSI-X (default 0)"); 6705 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6706 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6707 "set the RX budget"); 6708 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6709 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6710 "cause TX to abdicate instead of running to completion"); 6711 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6712 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6713 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6714 "offset to start using cores at"); 6715 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6716 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6717 "use separate cores for TX and RX"); 6718 6719 /* XXX change for per-queue sizes */ 6720 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6721 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6722 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6723 "list of # of TX descriptors to use, 0 = use default #"); 6724 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6725 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6726 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6727 "list of # of RX descriptors to use, 0 = use default #"); 6728 } 6729 6730 static void 6731 iflib_add_device_sysctl_post(if_ctx_t ctx) 6732 { 6733 if_shared_ctx_t sctx = ctx->ifc_sctx; 6734 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6735 device_t dev = iflib_get_dev(ctx); 6736 struct sysctl_oid_list *child; 6737 struct sysctl_ctx_list *ctx_list; 6738 iflib_fl_t fl; 6739 iflib_txq_t txq; 6740 iflib_rxq_t rxq; 6741 int i, j; 6742 char namebuf[NAME_BUFLEN]; 6743 char *qfmt; 6744 struct sysctl_oid *queue_node, *fl_node, *node; 6745 struct sysctl_oid_list *queue_list, *fl_list; 6746 ctx_list = device_get_sysctl_ctx(dev); 6747 6748 node = ctx->ifc_sysctl_node; 6749 child = SYSCTL_CHILDREN(node); 6750 6751 if (scctx->isc_ntxqsets > 100) 6752 qfmt = "txq%03d"; 6753 else if (scctx->isc_ntxqsets > 10) 6754 qfmt = "txq%02d"; 6755 else 6756 qfmt = "txq%d"; 6757 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6758 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6759 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6760 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6761 queue_list = SYSCTL_CHILDREN(queue_node); 6762 #if MEMORY_LOGGING 6763 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6764 CTLFLAG_RD, 6765 &txq->ift_dequeued, "total mbufs freed"); 6766 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6767 CTLFLAG_RD, 6768 &txq->ift_enqueued, "total mbufs enqueued"); 6769 #endif 6770 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6771 CTLFLAG_RD, 6772 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6773 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6774 CTLFLAG_RD, 6775 &txq->ift_pullups, "# of times m_pullup was called"); 6776 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6777 CTLFLAG_RD, 6778 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6779 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6780 CTLFLAG_RD, 6781 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6782 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6783 CTLFLAG_RD, 6784 &txq->ift_map_failed, "# of times DMA map failed"); 6785 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6786 CTLFLAG_RD, 6787 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6788 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6789 CTLFLAG_RD, 6790 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6791 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6792 CTLFLAG_RD, 6793 &txq->ift_pidx, 1, "Producer Index"); 6794 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6795 CTLFLAG_RD, 6796 &txq->ift_cidx, 1, "Consumer Index"); 6797 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6798 CTLFLAG_RD, 6799 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6800 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6801 CTLFLAG_RD, 6802 &txq->ift_in_use, 1, "descriptors in use"); 6803 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6804 CTLFLAG_RD, 6805 &txq->ift_processed, "descriptors procesed for clean"); 6806 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6807 CTLFLAG_RD, 6808 &txq->ift_cleaned, "total cleaned"); 6809 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6810 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6811 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6812 mp_ring_state_handler, "A", "soft ring state"); 6813 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6814 CTLFLAG_RD, &txq->ift_br->enqueues, 6815 "# of enqueues to the mp_ring for this queue"); 6816 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6817 CTLFLAG_RD, &txq->ift_br->drops, 6818 "# of drops in the mp_ring for this queue"); 6819 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6820 CTLFLAG_RD, &txq->ift_br->starts, 6821 "# of normal consumer starts in the mp_ring for this queue"); 6822 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6823 CTLFLAG_RD, &txq->ift_br->stalls, 6824 "# of consumer stalls in the mp_ring for this queue"); 6825 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6826 CTLFLAG_RD, &txq->ift_br->restarts, 6827 "# of consumer restarts in the mp_ring for this queue"); 6828 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6829 CTLFLAG_RD, &txq->ift_br->abdications, 6830 "# of consumer abdications in the mp_ring for this queue"); 6831 } 6832 6833 if (scctx->isc_nrxqsets > 100) 6834 qfmt = "rxq%03d"; 6835 else if (scctx->isc_nrxqsets > 10) 6836 qfmt = "rxq%02d"; 6837 else 6838 qfmt = "rxq%d"; 6839 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6840 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6841 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6842 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6843 queue_list = SYSCTL_CHILDREN(queue_node); 6844 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6845 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6846 CTLFLAG_RD, 6847 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6848 } 6849 6850 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6851 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6852 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6853 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 6854 fl_list = SYSCTL_CHILDREN(fl_node); 6855 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6856 CTLFLAG_RD, 6857 &fl->ifl_pidx, 1, "Producer Index"); 6858 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6859 CTLFLAG_RD, 6860 &fl->ifl_cidx, 1, "Consumer Index"); 6861 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6862 CTLFLAG_RD, 6863 &fl->ifl_credits, 1, "credits available"); 6864 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 6865 CTLFLAG_RD, 6866 &fl->ifl_buf_size, 1, "buffer size"); 6867 #if MEMORY_LOGGING 6868 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6869 CTLFLAG_RD, 6870 &fl->ifl_m_enqueued, "mbufs allocated"); 6871 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6872 CTLFLAG_RD, 6873 &fl->ifl_m_dequeued, "mbufs freed"); 6874 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6875 CTLFLAG_RD, 6876 &fl->ifl_cl_enqueued, "clusters allocated"); 6877 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6878 CTLFLAG_RD, 6879 &fl->ifl_cl_dequeued, "clusters freed"); 6880 #endif 6881 } 6882 } 6883 6884 } 6885 6886 void 6887 iflib_request_reset(if_ctx_t ctx) 6888 { 6889 6890 STATE_LOCK(ctx); 6891 ctx->ifc_flags |= IFC_DO_RESET; 6892 STATE_UNLOCK(ctx); 6893 } 6894 6895 #ifndef __NO_STRICT_ALIGNMENT 6896 static struct mbuf * 6897 iflib_fixup_rx(struct mbuf *m) 6898 { 6899 struct mbuf *n; 6900 6901 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6902 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6903 m->m_data += ETHER_HDR_LEN; 6904 n = m; 6905 } else { 6906 MGETHDR(n, M_NOWAIT, MT_DATA); 6907 if (n == NULL) { 6908 m_freem(m); 6909 return (NULL); 6910 } 6911 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6912 m->m_data += ETHER_HDR_LEN; 6913 m->m_len -= ETHER_HDR_LEN; 6914 n->m_len = ETHER_HDR_LEN; 6915 M_MOVE_PKTHDR(n, m); 6916 n->m_next = m; 6917 } 6918 return (n); 6919 } 6920 #endif 6921 6922 #ifdef DEBUGNET 6923 static void 6924 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6925 { 6926 if_ctx_t ctx; 6927 6928 ctx = if_getsoftc(ifp); 6929 CTX_LOCK(ctx); 6930 *nrxr = NRXQSETS(ctx); 6931 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6932 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6933 CTX_UNLOCK(ctx); 6934 } 6935 6936 static void 6937 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6938 { 6939 if_ctx_t ctx; 6940 if_softc_ctx_t scctx; 6941 iflib_fl_t fl; 6942 iflib_rxq_t rxq; 6943 int i, j; 6944 6945 ctx = if_getsoftc(ifp); 6946 scctx = &ctx->ifc_softc_ctx; 6947 6948 switch (event) { 6949 case DEBUGNET_START: 6950 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6951 rxq = &ctx->ifc_rxqs[i]; 6952 for (j = 0; j < rxq->ifr_nfl; j++) { 6953 fl = rxq->ifr_fl; 6954 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6955 } 6956 } 6957 iflib_no_tx_batch = 1; 6958 break; 6959 default: 6960 break; 6961 } 6962 } 6963 6964 static int 6965 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6966 { 6967 if_ctx_t ctx; 6968 iflib_txq_t txq; 6969 int error; 6970 6971 ctx = if_getsoftc(ifp); 6972 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6973 IFF_DRV_RUNNING) 6974 return (EBUSY); 6975 6976 txq = &ctx->ifc_txqs[0]; 6977 error = iflib_encap(txq, &m); 6978 if (error == 0) 6979 (void)iflib_txd_db_check(txq, true); 6980 return (error); 6981 } 6982 6983 static int 6984 iflib_debugnet_poll(if_t ifp, int count) 6985 { 6986 struct epoch_tracker et; 6987 if_ctx_t ctx; 6988 if_softc_ctx_t scctx; 6989 iflib_txq_t txq; 6990 int i; 6991 6992 ctx = if_getsoftc(ifp); 6993 scctx = &ctx->ifc_softc_ctx; 6994 6995 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6996 IFF_DRV_RUNNING) 6997 return (EBUSY); 6998 6999 txq = &ctx->ifc_txqs[0]; 7000 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 7001 7002 NET_EPOCH_ENTER(et); 7003 for (i = 0; i < scctx->isc_nrxqsets; i++) 7004 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7005 NET_EPOCH_EXIT(et); 7006 return (0); 7007 } 7008 #endif /* DEBUGNET */ 7009