1 /* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.44 1997/08/24 20:33:32 fsmp Exp $ 26 */ 27 28 #include "opt_smp.h" 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <vm/vm.h> /* for KERNBASE */ 34 #include <vm/vm_param.h> /* for KERNBASE */ 35 #include <vm/pmap.h> /* for KERNBASE */ 36 #include <vm/vm_kern.h> 37 #include <vm/vm_extern.h> 38 39 #include <machine/smp.h> 40 #include <machine/apic.h> 41 #include <machine/mpapic.h> 42 #include <machine/segments.h> 43 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 44 #include <machine/tss.h> 45 #include <machine/specialreg.h> 46 47 #include <i386/i386/cons.h> /* cngetc() */ 48 49 #if defined(APIC_IO) 50 #include <machine/md_var.h> /* setidt() */ 51 #include <i386/isa/icu.h> /* IPIs */ 52 #include <i386/isa/intr_machdep.h> /* IPIs */ 53 #endif /* APIC_IO */ 54 55 #if defined(TEST_DEFAULT_CONFIG) 56 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 57 #else 58 #define MPFPS_MPFB1 mpfps->mpfb1 59 #endif /* TEST_DEFAULT_CONFIG */ 60 61 #define WARMBOOT_TARGET 0 62 #define WARMBOOT_OFF (KERNBASE + 0x0467) 63 #define WARMBOOT_SEG (KERNBASE + 0x0469) 64 65 #define BIOS_BASE (0xf0000) 66 #define BIOS_SIZE (0x10000) 67 #define BIOS_COUNT (BIOS_SIZE/4) 68 69 #define CMOS_REG (0x70) 70 #define CMOS_DATA (0x71) 71 #define BIOS_RESET (0x0f) 72 #define BIOS_WARM (0x0a) 73 74 #define PROCENTRY_FLAG_EN 0x01 75 #define PROCENTRY_FLAG_BP 0x02 76 #define IOAPICENTRY_FLAG_EN 0x01 77 78 79 /* MP Floating Pointer Structure */ 80 typedef struct MPFPS { 81 char signature[4]; 82 void *pap; 83 u_char length; 84 u_char spec_rev; 85 u_char checksum; 86 u_char mpfb1; 87 u_char mpfb2; 88 u_char mpfb3; 89 u_char mpfb4; 90 u_char mpfb5; 91 } *mpfps_t; 92 93 /* MP Configuration Table Header */ 94 typedef struct MPCTH { 95 char signature[4]; 96 u_short base_table_length; 97 u_char spec_rev; 98 u_char checksum; 99 u_char oem_id[8]; 100 u_char product_id[12]; 101 void *oem_table_pointer; 102 u_short oem_table_size; 103 u_short entry_count; 104 void *apic_address; 105 u_short extended_table_length; 106 u_char extended_table_checksum; 107 u_char reserved; 108 } *mpcth_t; 109 110 111 typedef struct PROCENTRY { 112 u_char type; 113 u_char apic_id; 114 u_char apic_version; 115 u_char cpu_flags; 116 u_long cpu_signature; 117 u_long feature_flags; 118 u_long reserved1; 119 u_long reserved2; 120 } *proc_entry_ptr; 121 122 typedef struct BUSENTRY { 123 u_char type; 124 u_char bus_id; 125 char bus_type[6]; 126 } *bus_entry_ptr; 127 128 typedef struct IOAPICENTRY { 129 u_char type; 130 u_char apic_id; 131 u_char apic_version; 132 u_char apic_flags; 133 void *apic_address; 134 } *io_apic_entry_ptr; 135 136 typedef struct INTENTRY { 137 u_char type; 138 u_char int_type; 139 u_short int_flags; 140 u_char src_bus_id; 141 u_char src_bus_irq; 142 u_char dst_apic_id; 143 u_char dst_apic_int; 144 } *int_entry_ptr; 145 146 /* descriptions of MP basetable entries */ 147 typedef struct BASETABLE_ENTRY { 148 u_char type; 149 u_char length; 150 char name[16]; 151 } basetable_entry; 152 153 /* 154 * this code MUST be enabled here and in mpboot.s. 155 * it follows the very early stages of AP boot by placing values in CMOS ram. 156 * it NORMALLY will never be needed and thus the primitive method for enabling. 157 * 158 #define CHECK_POINTS 159 */ 160 161 #if defined(CHECK_POINTS) 162 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 163 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 164 165 #define CHECK_INIT(D); \ 166 CHECK_WRITE(0x34, (D)); \ 167 CHECK_WRITE(0x35, (D)); \ 168 CHECK_WRITE(0x36, (D)); \ 169 CHECK_WRITE(0x37, (D)); \ 170 CHECK_WRITE(0x38, (D)); \ 171 CHECK_WRITE(0x39, (D)); 172 173 #define CHECK_PRINT(S); \ 174 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 175 (S), \ 176 CHECK_READ(0x34), \ 177 CHECK_READ(0x35), \ 178 CHECK_READ(0x36), \ 179 CHECK_READ(0x37), \ 180 CHECK_READ(0x38), \ 181 CHECK_READ(0x39)); 182 183 #else /* CHECK_POINTS */ 184 185 #define CHECK_INIT(D) 186 #define CHECK_PRINT(S) 187 188 #endif /* CHECK_POINTS */ 189 190 /* 191 * Values to send to the POST hardware. 192 */ 193 #define MP_BOOTADDRESS_POST 0x10 194 #define MP_PROBE_POST 0x11 195 #define MP_START_POST 0x12 196 #define MP_ANNOUNCE_POST 0x13 197 #define MPTABLE_PASS1_POST 0x14 198 #define MPTABLE_PASS2_POST 0x15 199 #define MP_ENABLE_POST 0x16 200 #define START_ALL_APS_POST 0x17 201 #define INSTALL_AP_TRAMP_POST 0x18 202 #define START_AP_POST 0x19 203 204 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 205 int current_postcode; 206 207 /** XXX FIXME: what system files declare these??? */ 208 extern struct region_descriptor r_gdt, r_idt; 209 210 int bsp_apic_ready = 0; /* flags useability of BSP apic */ 211 int mp_ncpus; /* # of CPUs, including BSP */ 212 int mp_naps; /* # of Applications processors */ 213 int mp_nbusses; /* # of busses */ 214 int mp_napics; /* # of IO APICs */ 215 int boot_cpu_id; /* designated BSP */ 216 vm_offset_t cpu_apic_address; 217 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 218 219 u_int32_t cpu_apic_versions[NCPU]; 220 u_int32_t io_apic_versions[NAPIC]; 221 222 /* 223 * APIC ID logical/physical mapping structures. 224 * We oversize these to simplify boot-time config. 225 */ 226 int cpu_num_to_apic_id[NAPICID]; 227 int io_num_to_apic_id[NAPICID]; 228 int apic_id_to_logical[NAPICID]; 229 230 /* Bitmap of all available CPUs */ 231 u_int all_cpus; 232 233 /* Boot of AP uses this PTD */ 234 u_int *bootPTD; 235 236 /* Hotwire a 0->4MB V==P mapping */ 237 extern pt_entry_t KPTphys; 238 239 /* Virtual address of per-cpu common_tss */ 240 extern struct i386tss common_tss; 241 242 /* 243 * Local data and functions. 244 */ 245 246 static int mp_capable; 247 static u_int boot_address; 248 static u_int base_memory; 249 250 static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 251 static mpfps_t mpfps; 252 static int search_for_sig(u_int32_t target, int count); 253 static void mp_enable(u_int boot_addr); 254 255 static int mptable_pass1(void); 256 static int mptable_pass2(void); 257 static void default_mp_table(int type); 258 static void fix_mp_table(void); 259 static void init_locks(void); 260 static int start_all_aps(u_int boot_addr); 261 static void install_ap_tramp(u_int boot_addr); 262 static int start_ap(int logicalCpu, u_int boot_addr); 263 264 265 /* 266 * Calculate usable address in base memory for AP trampoline code. 267 */ 268 u_int 269 mp_bootaddress(u_int basemem) 270 { 271 POSTCODE(MP_BOOTADDRESS_POST); 272 273 base_memory = basemem * 1024; /* convert to bytes */ 274 275 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 276 if ((base_memory - boot_address) < bootMP_size) 277 boot_address -= 4096; /* not enough, lower by 4k */ 278 279 return boot_address; 280 } 281 282 283 /* 284 * Look for an Intel MP spec table (ie, SMP capable hardware). 285 */ 286 int 287 mp_probe(void) 288 { 289 int x; 290 u_long segment; 291 u_int32_t target; 292 293 POSTCODE(MP_PROBE_POST); 294 295 /* see if EBDA exists */ 296 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 297 /* search first 1K of EBDA */ 298 target = (u_int32_t) (segment << 4); 299 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 300 goto found; 301 } else { 302 /* last 1K of base memory, effective 'top of base' passed in */ 303 target = (u_int32_t) (base_memory - 0x400); 304 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 305 goto found; 306 } 307 308 /* search the BIOS */ 309 target = (u_int32_t) BIOS_BASE; 310 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 311 goto found; 312 313 /* nothing found */ 314 mpfps = (mpfps_t)0; 315 mp_capable = 0; 316 return 0; 317 318 found: 319 /* calculate needed resources */ 320 mpfps = (mpfps_t)x; 321 if (mptable_pass1()) 322 panic("you must reconfigure your kernel"); 323 324 /* flag fact that we are running multiple processors */ 325 mp_capable = 1; 326 return 1; 327 } 328 329 330 /* 331 * Startup the SMP processors. 332 */ 333 void 334 mp_start(void) 335 { 336 POSTCODE(MP_START_POST); 337 338 /* look for MP capable motherboard */ 339 if (mp_capable) 340 mp_enable(boot_address); 341 else 342 panic("MP hardware not found!"); 343 } 344 345 346 /* 347 * Print various information about the SMP system hardware and setup. 348 */ 349 void 350 mp_announce(void) 351 { 352 int x; 353 354 POSTCODE(MP_ANNOUNCE_POST); 355 356 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 357 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 358 printf(", version: 0x%08x", cpu_apic_versions[0]); 359 printf(", at 0x%08x\n", cpu_apic_address); 360 for (x = 1; x <= mp_naps; ++x) { 361 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 362 printf(", version: 0x%08x", cpu_apic_versions[x]); 363 printf(", at 0x%08x\n", cpu_apic_address); 364 } 365 366 #if defined(APIC_IO) 367 for (x = 0; x < mp_napics; ++x) { 368 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 369 printf(", version: 0x%08x", io_apic_versions[x]); 370 printf(", at 0x%08x\n", io_apic_address[x]); 371 } 372 #else 373 printf(" Warning: APIC I/O disabled\n"); 374 #endif /* APIC_IO */ 375 } 376 377 /* 378 * AP cpu's call this to sync up protected mode. 379 */ 380 void 381 init_secondary(void) 382 { 383 int gsel_tss, slot; 384 385 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 386 r_gdt.rd_base = (int) gdt; 387 lgdt(&r_gdt); /* does magic intra-segment return */ 388 lidt(&r_idt); 389 lldt(_default_ldt); 390 391 slot = NGDT + cpuid; 392 gsel_tss = GSEL(slot, SEL_KPL); 393 gdt[slot].sd.sd_type = SDT_SYS386TSS; 394 common_tss.tss_esp0 = 0; /* not used until after switch */ 395 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 396 common_tss.tss_ioopt = (sizeof common_tss) << 16; 397 ltr(gsel_tss); 398 399 load_cr0(0x8005003b); /* XXX! */ 400 401 PTD[0] = 0; 402 pmap_set_opt((unsigned *)PTD); 403 404 invltlb(); 405 } 406 407 408 #if defined(APIC_IO) 409 /* 410 * Final configuration of the BSP's local APIC: 411 * - disable 'pic mode'. 412 * - disable 'virtual wire mode'. 413 * - enable NMI. 414 */ 415 void 416 bsp_apic_configure(void) 417 { 418 u_char byte; 419 u_int32_t temp; 420 421 /* leave 'pic mode' if necessary */ 422 if (picmode) { 423 outb(0x22, 0x70); /* select IMCR */ 424 byte = inb(0x23); /* current contents */ 425 byte |= 0x01; /* mask external INTR */ 426 outb(0x23, byte); /* disconnect 8259s/NMI */ 427 } 428 429 /* mask lint0 (the 8259 'virtual wire' connection) */ 430 temp = lapic.lvt_lint0; 431 temp |= APIC_LVT_M; /* set the mask */ 432 lapic.lvt_lint0 = temp; 433 434 /* setup lint1 to handle NMI */ 435 temp = lapic.lvt_lint1; 436 temp &= ~APIC_LVT_M; /* clear the mask */ 437 lapic.lvt_lint1 = temp; 438 439 if (bootverbose) 440 apic_dump("bsp_apic_configure()"); 441 } 442 #endif /* APIC_IO */ 443 444 445 /******************************************************************* 446 * local functions and data 447 */ 448 449 /* 450 * start the SMP system 451 */ 452 static void 453 mp_enable(u_int boot_addr) 454 { 455 int x; 456 #if defined(APIC_IO) 457 int apic; 458 u_int ux; 459 #endif /* APIC_IO */ 460 461 POSTCODE(MP_ENABLE_POST); 462 463 /* turn on 4MB of V == P addressing so we can get to MP table */ 464 *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 465 invltlb(); 466 467 /* examine the MP table for needed info, uses physical addresses */ 468 x = mptable_pass2(); 469 470 *(int *)PTD = 0; 471 invltlb(); 472 473 /* can't process default configs till the CPU APIC is pmapped */ 474 if (x) 475 default_mp_table(x); 476 477 /* post scan cleanup */ 478 fix_mp_table(); 479 480 #if defined(APIC_IO) 481 482 /* fill the LOGICAL io_apic_versions table */ 483 for (apic = 0; apic < mp_napics; ++apic) { 484 ux = io_apic_read(apic, IOAPIC_VER); 485 io_apic_versions[apic] = ux; 486 } 487 488 /* program each IO APIC in the system */ 489 for (apic = 0; apic < mp_napics; ++apic) 490 if (io_apic_setup(apic) < 0) 491 panic("IO APIC setup failure"); 492 493 /* install a 'Spurious INTerrupt' vector */ 494 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 495 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 496 497 /* install an inter-CPU IPI for TLB invalidation */ 498 setidt(XINVLTLB_OFFSET, Xinvltlb, 499 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 500 501 /* install an inter-CPU IPI for CPU stop/restart */ 502 setidt(XCPUSTOP_OFFSET, Xcpustop, 503 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 504 505 #if defined(TEST_TEST1) 506 /* install a "fake hardware INTerrupt" vector */ 507 setidt(XTEST1_OFFSET, Xtest1, 508 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 509 #endif /** TEST_TEST1 */ 510 511 #endif /* APIC_IO */ 512 513 /* initialize all SMP locks */ 514 init_locks(); 515 516 /* start each Application Processor */ 517 start_all_aps(boot_addr); 518 519 /* 520 * The init process might be started on a different CPU now, 521 * and the boot CPU might not call prepare_usermode to get 522 * cr0 correctly configured. Thus we initialize cr0 here. 523 */ 524 load_cr0(rcr0() | CR0_WP | CR0_AM); 525 } 526 527 528 /* 529 * look for the MP spec signature 530 */ 531 532 /* string defined by the Intel MP Spec as identifying the MP table */ 533 #define MP_SIG 0x5f504d5f /* _MP_ */ 534 #define NEXT(X) ((X) += 4) 535 static int 536 search_for_sig(u_int32_t target, int count) 537 { 538 int x; 539 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 540 541 for (x = 0; x < count; NEXT(x)) 542 if (addr[x] == MP_SIG) 543 /* make array index a byte index */ 544 return (target + (x * sizeof(u_int32_t))); 545 546 return -1; 547 } 548 549 550 static basetable_entry basetable_entry_types[] = 551 { 552 {0, 20, "Processor"}, 553 {1, 8, "Bus"}, 554 {2, 8, "I/O APIC"}, 555 {3, 8, "I/O INT"}, 556 {4, 8, "Local INT"} 557 }; 558 559 typedef struct BUSDATA { 560 u_char bus_id; 561 enum busTypes bus_type; 562 } bus_datum; 563 564 typedef struct INTDATA { 565 u_char int_type; 566 u_short int_flags; 567 u_char src_bus_id; 568 u_char src_bus_irq; 569 u_char dst_apic_id; 570 u_char dst_apic_int; 571 } io_int, local_int; 572 573 typedef struct BUSTYPENAME { 574 u_char type; 575 char name[7]; 576 } bus_type_name; 577 578 static bus_type_name bus_type_table[] = 579 { 580 {CBUS, "CBUS"}, 581 {CBUSII, "CBUSII"}, 582 {EISA, "EISA"}, 583 {UNKNOWN_BUSTYPE, "---"}, 584 {UNKNOWN_BUSTYPE, "---"}, 585 {ISA, "ISA"}, 586 {UNKNOWN_BUSTYPE, "---"}, 587 {UNKNOWN_BUSTYPE, "---"}, 588 {UNKNOWN_BUSTYPE, "---"}, 589 {UNKNOWN_BUSTYPE, "---"}, 590 {UNKNOWN_BUSTYPE, "---"}, 591 {UNKNOWN_BUSTYPE, "---"}, 592 {PCI, "PCI"}, 593 {UNKNOWN_BUSTYPE, "---"}, 594 {UNKNOWN_BUSTYPE, "---"}, 595 {UNKNOWN_BUSTYPE, "---"}, 596 {UNKNOWN_BUSTYPE, "---"}, 597 {XPRESS, "XPRESS"}, 598 {UNKNOWN_BUSTYPE, "---"} 599 }; 600 /* from MP spec v1.4, table 5-1 */ 601 static int default_data[7][5] = 602 { 603 /* nbus, id0, type0, id1, type1 */ 604 {1, 0, ISA, 255, 255}, 605 {1, 0, EISA, 255, 255}, 606 {1, 0, EISA, 255, 255}, 607 {0, 255, 255, 255, 255},/* MCA not supported */ 608 {2, 0, ISA, 1, PCI}, 609 {2, 0, EISA, 1, PCI}, 610 {0, 255, 255, 255, 255} /* MCA not supported */ 611 }; 612 613 614 /* the bus data */ 615 bus_datum bus_data[NBUS]; 616 617 /* the IO INT data, one entry per possible APIC INTerrupt */ 618 io_int io_apic_ints[NINTR]; 619 620 static int nintrs; 621 622 static int processor_entry __P((proc_entry_ptr entry, int cpu)); 623 static int bus_entry __P((bus_entry_ptr entry, int bus)); 624 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 625 static int int_entry __P((int_entry_ptr entry, int intr)); 626 static int lookup_bus_type __P((char *name)); 627 628 629 /* 630 * 1st pass on motherboard's Intel MP specification table. 631 * 632 * initializes: 633 * mp_ncpus = 1 634 * 635 * determines: 636 * cpu_apic_address (common to all CPUs) 637 * io_apic_address[N] 638 * mp_naps 639 * mp_nbusses 640 * mp_napics 641 * nintrs 642 */ 643 static int 644 mptable_pass1(void) 645 { 646 int x; 647 mpcth_t cth; 648 int totalSize; 649 void* position; 650 int count; 651 int type; 652 int mustpanic; 653 654 POSTCODE(MPTABLE_PASS1_POST); 655 656 mustpanic = 0; 657 658 /* clear various tables */ 659 for (x = 0; x < NAPICID; ++x) { 660 io_apic_address[x] = ~0; /* IO APIC address table */ 661 } 662 663 /* init everything to empty */ 664 mp_naps = 0; 665 mp_nbusses = 0; 666 mp_napics = 0; 667 nintrs = 0; 668 669 /* check for use of 'default' configuration */ 670 if (MPFPS_MPFB1 != 0) { 671 /* use default addresses */ 672 cpu_apic_address = DEFAULT_APIC_BASE; 673 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 674 675 /* fill in with defaults */ 676 mp_naps = 2; /* includes BSP */ 677 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 678 #if defined(APIC_IO) 679 mp_napics = 1; 680 nintrs = 16; 681 #endif /* APIC_IO */ 682 } 683 else { 684 if ((cth = mpfps->pap) == 0) 685 panic("MP Configuration Table Header MISSING!"); 686 687 cpu_apic_address = (vm_offset_t) cth->apic_address; 688 689 /* walk the table, recording info of interest */ 690 totalSize = cth->base_table_length - sizeof(struct MPCTH); 691 position = (u_char *) cth + sizeof(struct MPCTH); 692 count = cth->entry_count; 693 694 while (count--) { 695 switch (type = *(u_char *) position) { 696 case 0: /* processor_entry */ 697 if (((proc_entry_ptr)position)->cpu_flags 698 & PROCENTRY_FLAG_EN) 699 ++mp_naps; 700 break; 701 case 1: /* bus_entry */ 702 ++mp_nbusses; 703 break; 704 case 2: /* io_apic_entry */ 705 if (((io_apic_entry_ptr)position)->apic_flags 706 & IOAPICENTRY_FLAG_EN) 707 io_apic_address[mp_napics++] = 708 (vm_offset_t)((io_apic_entry_ptr) 709 position)->apic_address; 710 break; 711 case 3: /* int_entry */ 712 ++nintrs; 713 break; 714 case 4: /* int_entry */ 715 break; 716 default: 717 panic("mpfps Base Table HOSED!"); 718 /* NOTREACHED */ 719 } 720 721 totalSize -= basetable_entry_types[type].length; 722 (u_char*)position += basetable_entry_types[type].length; 723 } 724 } 725 726 /* qualify the numbers */ 727 if (mp_naps > NCPU) 728 #if 0 /* XXX FIXME: kern/4255 */ 729 printf("Warning: only using %d of %d available CPUs!\n", 730 NCPU, mp_naps); 731 #else 732 { 733 printf("NCPU cannot be different than actual CPU count.\n"); 734 printf(" add 'options NCPU=%d' to your kernel config file,\n", 735 mp_naps); 736 printf(" then rerun config & rebuild your SMP kernel\n"); 737 mustpanic = 1; 738 } 739 #endif /* XXX FIXME: kern/4255 */ 740 if (mp_nbusses > NBUS) { 741 printf("found %d busses, increase NBUS\n", mp_nbusses); 742 mustpanic = 1; 743 } 744 if (mp_napics > NAPIC) { 745 printf("found %d apics, increase NAPIC\n", mp_napics); 746 mustpanic = 1; 747 } 748 if (nintrs > NINTR) { 749 printf("found %d intrs, increase NINTR\n", nintrs); 750 mustpanic = 1; 751 } 752 753 /* 754 * Count the BSP. 755 * This is also used as a counter while starting the APs. 756 */ 757 mp_ncpus = 1; 758 759 --mp_naps; /* subtract the BSP */ 760 761 return mustpanic; 762 } 763 764 765 /* 766 * 2nd pass on motherboard's Intel MP specification table. 767 * 768 * sets: 769 * boot_cpu_id 770 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 771 * CPU_TO_ID(N), logical CPU to APIC ID table 772 * IO_TO_ID(N), logical IO to APIC ID table 773 * bus_data[N] 774 * io_apic_ints[N] 775 */ 776 static int 777 mptable_pass2(void) 778 { 779 int x; 780 mpcth_t cth; 781 int totalSize; 782 void* position; 783 int count; 784 int type; 785 int apic, bus, cpu, intr; 786 787 POSTCODE(MPTABLE_PASS2_POST); 788 789 /* clear various tables */ 790 for (x = 0; x < NAPICID; ++x) { 791 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 792 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 793 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 794 } 795 796 /* clear bus data table */ 797 for (x = 0; x < NBUS; ++x) 798 bus_data[x].bus_id = 0xff; 799 800 /* clear IO APIC INT table */ 801 for (x = 0; x < NINTR; ++x) 802 io_apic_ints[x].int_type = 0xff; 803 804 /* setup the cpu/apic mapping arrays */ 805 boot_cpu_id = -1; 806 807 /* record whether PIC or virtual-wire mode */ 808 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 809 810 /* check for use of 'default' configuration */ 811 if (MPFPS_MPFB1 != 0) 812 return MPFPS_MPFB1; /* return default configuration type */ 813 814 if ((cth = mpfps->pap) == 0) 815 panic("MP Configuration Table Header MISSING!"); 816 817 /* walk the table, recording info of interest */ 818 totalSize = cth->base_table_length - sizeof(struct MPCTH); 819 position = (u_char *) cth + sizeof(struct MPCTH); 820 count = cth->entry_count; 821 apic = bus = intr = 0; 822 cpu = 1; /* pre-count the BSP */ 823 824 while (count--) { 825 switch (type = *(u_char *) position) { 826 case 0: 827 if (processor_entry(position, cpu)) 828 ++cpu; 829 break; 830 case 1: 831 if (bus_entry(position, bus)) 832 ++bus; 833 break; 834 case 2: 835 if (io_apic_entry(position, apic)) 836 ++apic; 837 break; 838 case 3: 839 if (int_entry(position, intr)) 840 ++intr; 841 break; 842 case 4: 843 /* int_entry(position); */ 844 break; 845 default: 846 panic("mpfps Base Table HOSED!"); 847 /* NOTREACHED */ 848 } 849 850 totalSize -= basetable_entry_types[type].length; 851 (u_char *) position += basetable_entry_types[type].length; 852 } 853 854 if (boot_cpu_id == -1) 855 panic("NO BSP found!"); 856 857 /* report fact that its NOT a default configuration */ 858 return 0; 859 } 860 861 862 /* 863 * parse an Intel MP specification table 864 */ 865 static void 866 fix_mp_table(void) 867 { 868 int x; 869 int id; 870 int bus_0; 871 int bus_pci; 872 int num_pci_bus; 873 874 /* 875 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 876 * did it wrong. The MP spec says that when more than 1 PCI bus 877 * exists the BIOS must begin with bus entries for the PCI bus and use 878 * actual PCI bus numbering. This implies that when only 1 PCI bus 879 * exists the BIOS can choose to ignore this ordering, and indeed many 880 * MP motherboards do ignore it. This causes a problem when the PCI 881 * sub-system makes requests of the MP sub-system based on PCI bus 882 * numbers. So here we look for the situation and renumber the 883 * busses and associated INTs in an effort to "make it right". 884 */ 885 886 /* find bus 0, PCI bus, count the number of PCI busses */ 887 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 888 if (bus_data[x].bus_id == 0) { 889 bus_0 = x; 890 } 891 if (bus_data[x].bus_type == PCI) { 892 ++num_pci_bus; 893 bus_pci = x; 894 } 895 } 896 /* 897 * bus_0 == slot of bus with ID of 0 898 * bus_pci == slot of last PCI bus encountered 899 */ 900 901 /* check the 1 PCI bus case for sanity */ 902 if (num_pci_bus == 1) { 903 904 /* if it is number 0 all is well */ 905 if (bus_data[bus_pci].bus_id == 0) 906 return; 907 908 /* mis-numbered, swap with whichever bus uses slot 0 */ 909 910 /* swap the bus entry types */ 911 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 912 bus_data[bus_0].bus_type = PCI; 913 914 /* swap each relavant INTerrupt entry */ 915 id = bus_data[bus_pci].bus_id; 916 for (x = 0; x < nintrs; ++x) { 917 if (io_apic_ints[x].src_bus_id == id) { 918 io_apic_ints[x].src_bus_id = 0; 919 } 920 else if (io_apic_ints[x].src_bus_id == 0) { 921 io_apic_ints[x].src_bus_id = id; 922 } 923 } 924 } 925 /* sanity check if more than 1 PCI bus */ 926 else if (num_pci_bus > 1) { 927 for (x = 0; x < mp_nbusses; ++x) { 928 if (bus_data[x].bus_type != PCI) 929 continue; 930 if (bus_data[x].bus_id >= num_pci_bus) 931 panic("bad PCI bus numbering"); 932 } 933 } 934 } 935 936 937 static int 938 processor_entry(proc_entry_ptr entry, int cpu) 939 { 940 /* check for usability */ 941 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 942 return 0; 943 944 /* check for BSP flag */ 945 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 946 boot_cpu_id = entry->apic_id; 947 CPU_TO_ID(0) = entry->apic_id; 948 ID_TO_CPU(entry->apic_id) = 0; 949 return 0; /* its already been counted */ 950 } 951 952 /* add another AP to list, if less than max number of CPUs */ 953 else { 954 CPU_TO_ID(cpu) = entry->apic_id; 955 ID_TO_CPU(entry->apic_id) = cpu; 956 return 1; 957 } 958 } 959 960 961 static int 962 bus_entry(bus_entry_ptr entry, int bus) 963 { 964 int x; 965 char c, name[8]; 966 967 /* encode the name into an index */ 968 for (x = 0; x < 6; ++x) { 969 if ((c = entry->bus_type[x]) == ' ') 970 break; 971 name[x] = c; 972 } 973 name[x] = '\0'; 974 975 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 976 panic("unknown bus type: '%s'", name); 977 978 bus_data[bus].bus_id = entry->bus_id; 979 bus_data[bus].bus_type = x; 980 981 return 1; 982 } 983 984 985 static int 986 io_apic_entry(io_apic_entry_ptr entry, int apic) 987 { 988 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 989 return 0; 990 991 IO_TO_ID(apic) = entry->apic_id; 992 ID_TO_IO(entry->apic_id) = apic; 993 994 return 1; 995 } 996 997 998 static int 999 lookup_bus_type(char *name) 1000 { 1001 int x; 1002 1003 for (x = 0; x < MAX_BUSTYPE; ++x) 1004 if (strcmp(bus_type_table[x].name, name) == 0) 1005 return bus_type_table[x].type; 1006 1007 return UNKNOWN_BUSTYPE; 1008 } 1009 1010 1011 static int 1012 int_entry(int_entry_ptr entry, int intr) 1013 { 1014 io_apic_ints[intr].int_type = entry->int_type; 1015 io_apic_ints[intr].int_flags = entry->int_flags; 1016 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1017 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1018 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1019 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1020 1021 return 1; 1022 } 1023 1024 1025 static int 1026 apic_int_is_bus_type(int intr, int bus_type) 1027 { 1028 int bus; 1029 1030 for (bus = 0; bus < mp_nbusses; ++bus) 1031 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1032 && ((int) bus_data[bus].bus_type == bus_type)) 1033 return 1; 1034 1035 return 0; 1036 } 1037 1038 1039 /* 1040 * Given a traditional ISA INT mask, return an APIC mask. 1041 */ 1042 u_int 1043 isa_apic_mask(u_int isa_mask) 1044 { 1045 int isa_irq; 1046 int apic_pin; 1047 1048 #if defined(SKIP_IRQ15_REDIRECT) 1049 if (isa_mask == (1 << 15)) { 1050 printf("skipping ISA IRQ15 redirect\n"); 1051 return isa_mask; 1052 } 1053 #endif /* SKIP_IRQ15_REDIRECT */ 1054 1055 isa_irq = ffs(isa_mask); /* find its bit position */ 1056 if (isa_irq == 0) /* doesn't exist */ 1057 return 0; 1058 --isa_irq; /* make it zero based */ 1059 1060 apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ 1061 if (apic_pin == -1) 1062 return 0; 1063 1064 return (1 << apic_pin); /* convert pin# to a mask */ 1065 } 1066 1067 1068 /* 1069 * Determine which APIC pin an ISA/EISA INT is attached to. 1070 */ 1071 #define INTTYPE(I) (io_apic_ints[(I)].int_type) 1072 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1073 1074 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1075 int 1076 isa_apic_pin(int isa_irq) 1077 { 1078 int intr; 1079 1080 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1081 if (INTTYPE(intr) == 0) { /* standard INT */ 1082 if (SRCBUSIRQ(intr) == isa_irq) { 1083 if (apic_int_is_bus_type(intr, ISA) || 1084 apic_int_is_bus_type(intr, EISA)) 1085 return INTPIN(intr); /* found */ 1086 } 1087 } 1088 } 1089 return -1; /* NOT found */ 1090 } 1091 #undef SRCBUSIRQ 1092 1093 1094 /* 1095 * Determine which APIC pin a PCI INT is attached to. 1096 */ 1097 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1098 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1099 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1100 int 1101 pci_apic_pin(int pciBus, int pciDevice, int pciInt) 1102 { 1103 int intr; 1104 1105 --pciInt; /* zero based */ 1106 1107 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1108 if ((INTTYPE(intr) == 0) /* standard INT */ 1109 && (SRCBUSID(intr) == pciBus) 1110 && (SRCBUSDEVICE(intr) == pciDevice) 1111 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1112 if (apic_int_is_bus_type(intr, PCI)) 1113 return INTPIN(intr); /* exact match */ 1114 1115 return -1; /* NOT found */ 1116 } 1117 #undef SRCBUSLINE 1118 #undef SRCBUSDEVICE 1119 #undef SRCBUSID 1120 1121 #undef INTPIN 1122 #undef INTTYPE 1123 1124 1125 /* 1126 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1127 * 1128 * XXX FIXME: 1129 * Exactly what this means is unclear at this point. It is a solution 1130 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1131 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1132 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1133 * option. 1134 */ 1135 int 1136 undirect_isa_irq(int rirq) 1137 { 1138 #if defined(READY) 1139 printf("Freeing redirected ISA irq %d.\n", rirq); 1140 /** FIXME: tickle the MB redirector chip */ 1141 return ???; 1142 #else 1143 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1144 return 0; 1145 #endif /* READY */ 1146 } 1147 1148 1149 /* 1150 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1151 */ 1152 int 1153 undirect_pci_irq(int rirq) 1154 { 1155 #if defined(READY) 1156 if (bootverbose) 1157 printf("Freeing redirected PCI irq %d.\n", rirq); 1158 1159 /** FIXME: tickle the MB redirector chip */ 1160 return ???; 1161 #else 1162 if (bootverbose) 1163 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1164 rirq); 1165 return 0; 1166 #endif /* READY */ 1167 } 1168 1169 1170 /* 1171 * given a bus ID, return: 1172 * the bus type if found 1173 * -1 if NOT found 1174 */ 1175 int 1176 apic_bus_type(int id) 1177 { 1178 int x; 1179 1180 for (x = 0; x < mp_nbusses; ++x) 1181 if (bus_data[x].bus_id == id) 1182 return bus_data[x].bus_type; 1183 1184 return -1; 1185 } 1186 1187 1188 /* 1189 * given a LOGICAL APIC# and pin#, return: 1190 * the associated src bus ID if found 1191 * -1 if NOT found 1192 */ 1193 int 1194 apic_src_bus_id(int apic, int pin) 1195 { 1196 int x; 1197 1198 /* search each of the possible INTerrupt sources */ 1199 for (x = 0; x < nintrs; ++x) 1200 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1201 (pin == io_apic_ints[x].dst_apic_int)) 1202 return (io_apic_ints[x].src_bus_id); 1203 1204 return -1; /* NOT found */ 1205 } 1206 1207 1208 /* 1209 * given a LOGICAL APIC# and pin#, return: 1210 * the associated src bus IRQ if found 1211 * -1 if NOT found 1212 */ 1213 int 1214 apic_src_bus_irq(int apic, int pin) 1215 { 1216 int x; 1217 1218 for (x = 0; x < nintrs; x++) 1219 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1220 (pin == io_apic_ints[x].dst_apic_int)) 1221 return (io_apic_ints[x].src_bus_irq); 1222 1223 return -1; /* NOT found */ 1224 } 1225 1226 1227 /* 1228 * given a LOGICAL APIC# and pin#, return: 1229 * the associated INTerrupt type if found 1230 * -1 if NOT found 1231 */ 1232 int 1233 apic_int_type(int apic, int pin) 1234 { 1235 int x; 1236 1237 /* search each of the possible INTerrupt sources */ 1238 for (x = 0; x < nintrs; ++x) 1239 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1240 (pin == io_apic_ints[x].dst_apic_int)) 1241 return (io_apic_ints[x].int_type); 1242 1243 return -1; /* NOT found */ 1244 } 1245 1246 1247 /* 1248 * given a LOGICAL APIC# and pin#, return: 1249 * the associated trigger mode if found 1250 * -1 if NOT found 1251 */ 1252 int 1253 apic_trigger(int apic, int pin) 1254 { 1255 int x; 1256 1257 /* search each of the possible INTerrupt sources */ 1258 for (x = 0; x < nintrs; ++x) 1259 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1260 (pin == io_apic_ints[x].dst_apic_int)) 1261 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1262 1263 return -1; /* NOT found */ 1264 } 1265 1266 1267 /* 1268 * given a LOGICAL APIC# and pin#, return: 1269 * the associated 'active' level if found 1270 * -1 if NOT found 1271 */ 1272 int 1273 apic_polarity(int apic, int pin) 1274 { 1275 int x; 1276 1277 /* search each of the possible INTerrupt sources */ 1278 for (x = 0; x < nintrs; ++x) 1279 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1280 (pin == io_apic_ints[x].dst_apic_int)) 1281 return (io_apic_ints[x].int_flags & 0x03); 1282 1283 return -1; /* NOT found */ 1284 } 1285 1286 1287 /* 1288 * set data according to MP defaults 1289 * FIXME: probably not complete yet... 1290 */ 1291 static void 1292 default_mp_table(int type) 1293 { 1294 int ap_cpu_id; 1295 #if defined(APIC_IO) 1296 u_int32_t ux; 1297 int io_apic_id; 1298 int pin; 1299 #endif /* APIC_IO */ 1300 1301 #if 0 1302 printf(" MP default config type: %d\n", type); 1303 switch (type) { 1304 case 1: 1305 printf(" bus: ISA, APIC: 82489DX\n"); 1306 break; 1307 case 2: 1308 printf(" bus: EISA, APIC: 82489DX\n"); 1309 break; 1310 case 3: 1311 printf(" bus: EISA, APIC: 82489DX\n"); 1312 break; 1313 case 4: 1314 printf(" bus: MCA, APIC: 82489DX\n"); 1315 break; 1316 case 5: 1317 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1318 break; 1319 case 6: 1320 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1321 break; 1322 case 7: 1323 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1324 break; 1325 default: 1326 printf(" future type\n"); 1327 break; 1328 /* NOTREACHED */ 1329 } 1330 #endif /* 0 */ 1331 1332 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1333 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1334 1335 /* BSP */ 1336 CPU_TO_ID(0) = boot_cpu_id; 1337 ID_TO_CPU(boot_cpu_id) = 0; 1338 1339 /* one and only AP */ 1340 CPU_TO_ID(1) = ap_cpu_id; 1341 ID_TO_CPU(ap_cpu_id) = 1; 1342 1343 #if defined(APIC_IO) 1344 /* one and only IO APIC */ 1345 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1346 1347 /* 1348 * sanity check, refer to MP spec section 3.6.6, last paragraph 1349 * necessary as some hardware isn't properly setting up the IO APIC 1350 */ 1351 #if defined(REALLY_ANAL_IOAPICID_VALUE) 1352 if (io_apic_id != 2) { 1353 #else 1354 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1355 #endif /* REALLY_ANAL_IOAPICID_VALUE */ 1356 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1357 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1358 ux |= 0x02000000; /* set it to '2' */ 1359 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1360 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1361 if ((ux & APIC_ID_MASK) != 0x02000000) 1362 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1363 io_apic_id = 2; 1364 } 1365 IO_TO_ID(0) = io_apic_id; 1366 ID_TO_IO(io_apic_id) = 0; 1367 #endif /* APIC_IO */ 1368 1369 /* fill out bus entries */ 1370 switch (type) { 1371 case 1: 1372 case 2: 1373 case 3: 1374 case 5: 1375 case 6: 1376 bus_data[0].bus_id = default_data[type - 1][1]; 1377 bus_data[0].bus_type = default_data[type - 1][2]; 1378 bus_data[1].bus_id = default_data[type - 1][3]; 1379 bus_data[1].bus_type = default_data[type - 1][4]; 1380 break; 1381 1382 /* case 4: case 7: MCA NOT supported */ 1383 default: /* illegal/reserved */ 1384 panic("BAD default MP config: %d", type); 1385 /* NOTREACHED */ 1386 } 1387 1388 #if defined(APIC_IO) 1389 /* general cases from MP v1.4, table 5-2 */ 1390 for (pin = 0; pin < 16; ++pin) { 1391 io_apic_ints[pin].int_type = 0; 1392 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1393 io_apic_ints[pin].src_bus_id = 0; 1394 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1395 io_apic_ints[pin].dst_apic_id = io_apic_id; 1396 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1397 } 1398 1399 /* special cases from MP v1.4, table 5-2 */ 1400 if (type == 2) { 1401 io_apic_ints[2].int_type = 0xff; /* N/C */ 1402 io_apic_ints[13].int_type = 0xff; /* N/C */ 1403 #if !defined(APIC_MIXED_MODE) 1404 /** FIXME: ??? */ 1405 panic("sorry, can't support type 2 default yet"); 1406 #endif /* APIC_MIXED_MODE */ 1407 } 1408 else 1409 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1410 1411 if (type == 7) 1412 io_apic_ints[0].int_type = 0xff; /* N/C */ 1413 else 1414 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1415 #endif /* APIC_IO */ 1416 } 1417 1418 1419 /* 1420 * initialize all the SMP locks 1421 */ 1422 1423 /* critical region around IO APIC, apic_imen */ 1424 struct simplelock imen_lock; 1425 1426 /* critical region around splxx(), cpl, cil, ipending */ 1427 struct simplelock cpl_lock; 1428 1429 /* Make FAST_INTR() routines sequential */ 1430 struct simplelock fast_intr_lock; 1431 1432 /* critical region around INTR() routines */ 1433 struct simplelock intr_lock; 1434 1435 /* lock the com (tty) data structures */ 1436 struct simplelock com_lock; 1437 1438 static void 1439 init_locks(void) 1440 { 1441 /* 1442 * Get the initial mp_lock with a count of 1 for the BSP. 1443 * This uses a LOGICAL cpu ID, ie BSP == 0. 1444 */ 1445 mp_lock = 0x00000001; 1446 1447 /* ISR uses its own "giant lock" */ 1448 isr_lock = 0x00000000; 1449 1450 /* serializes FAST_INTR() accesses */ 1451 s_lock_init((struct simplelock*)&fast_intr_lock); 1452 1453 /* serializes INTR() accesses */ 1454 s_lock_init((struct simplelock*)&intr_lock); 1455 1456 /* locks the IO APIC and apic_imen accesses */ 1457 s_lock_init((struct simplelock*)&imen_lock); 1458 1459 /* locks cpl accesses */ 1460 s_lock_init((struct simplelock*)&cpl_lock); 1461 1462 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 1463 s_lock_init((struct simplelock*)&com_lock); 1464 } 1465 1466 1467 /* 1468 * start each AP in our list 1469 */ 1470 static int 1471 start_all_aps(u_int boot_addr) 1472 { 1473 int x, i; 1474 u_char mpbiosreason; 1475 u_long mpbioswarmvec; 1476 pd_entry_t newptd; 1477 pt_entry_t newpt; 1478 int *newpp; 1479 1480 POSTCODE(START_ALL_APS_POST); 1481 1482 /* initialize BSP's local APIC */ 1483 apic_initialize(); 1484 bsp_apic_ready = 1; 1485 1486 /* install the AP 1st level boot code */ 1487 install_ap_tramp(boot_addr); 1488 1489 1490 /* save the current value of the warm-start vector */ 1491 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1492 outb(CMOS_REG, BIOS_RESET); 1493 mpbiosreason = inb(CMOS_DATA); 1494 1495 /* record BSP in CPU map */ 1496 all_cpus = 1; 1497 1498 /* start each AP */ 1499 for (x = 1; x <= mp_naps; ++x) { 1500 1501 /* HACK HACK HACK !!! */ 1502 1503 /* alloc new page table directory */ 1504 newptd = (pd_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); 1505 1506 /* clone currently active one (ie: IdlePTD) */ 1507 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1508 1509 /* set up 0 -> 4MB P==V mapping for AP boot */ 1510 newptd[0] = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 1511 1512 /* store PTD for this AP */ 1513 bootPTD = (pd_entry_t)vtophys(newptd); 1514 1515 /* alloc new page table page */ 1516 newpt = (pt_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); 1517 1518 /* set the new PTD's private page to point there */ 1519 newptd[MPPTDI] = PG_V | PG_RW | vtophys(newpt); 1520 1521 /* install self referential entry */ 1522 newptd[PTDPTDI] = PG_V | PG_RW | vtophys(newptd); 1523 1524 /* get a new private data page */ 1525 newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1526 1527 /* wire it into the private page table page */ 1528 newpt[0] = PG_V | PG_RW | vtophys(newpp); 1529 1530 /* wire the ptp into itself for access */ 1531 newpt[1] = PG_V | PG_RW | vtophys(newpt); 1532 1533 /* and the local apic */ 1534 newpt[2] = SMP_prvpt[2]; 1535 1536 /* and the IO apic mapping[s] */ 1537 for (i = 16; i < 32; i++) 1538 newpt[i] = SMP_prvpt[i]; 1539 1540 /* prime data page for it to use */ 1541 newpp[0] = x; /* cpuid */ 1542 newpp[1] = 0; /* curproc */ 1543 newpp[2] = 0; /* curpcb */ 1544 newpp[3] = 0; /* npxproc */ 1545 newpp[4] = 0; /* runtime.tv_sec */ 1546 newpp[5] = 0; /* runtime.tv_usec */ 1547 newpp[6] = x << 24; /* cpu_lockid */ 1548 1549 /* XXX NOTE: ABANDON bootPTD for now!!!! */ 1550 1551 /* END REVOLTING HACKERY */ 1552 1553 /* setup a vector to our boot code */ 1554 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1555 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1556 outb(CMOS_REG, BIOS_RESET); 1557 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1558 1559 /* attempt to start the Application Processor */ 1560 CHECK_INIT(99); /* setup checkpoints */ 1561 if (!start_ap(x, boot_addr)) { 1562 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1563 CHECK_PRINT("trace"); /* show checkpoints */ 1564 /* better panic as the AP may be running loose */ 1565 printf("panic y/n? [y] "); 1566 if (cngetc() != 'n') 1567 panic("bye-bye"); 1568 } 1569 CHECK_PRINT("trace"); /* show checkpoints */ 1570 1571 /* record its version info */ 1572 cpu_apic_versions[x] = cpu_apic_versions[0]; 1573 1574 all_cpus |= (1 << x); /* record AP in CPU map */ 1575 } 1576 1577 /* build our map of 'other' CPUs */ 1578 other_cpus = all_cpus & ~(1 << cpuid); 1579 1580 /* fill in our (BSP) APIC version */ 1581 cpu_apic_versions[0] = lapic.version; 1582 1583 /* restore the warmstart vector */ 1584 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1585 outb(CMOS_REG, BIOS_RESET); 1586 outb(CMOS_DATA, mpbiosreason); 1587 1588 pmap_set_opt_bsp(); 1589 1590 /* number of APs actually started */ 1591 return mp_ncpus - 1; 1592 } 1593 1594 1595 /* 1596 * load the 1st level AP boot code into base memory. 1597 */ 1598 1599 /* targets for relocation */ 1600 extern void bigJump(void); 1601 extern void bootCodeSeg(void); 1602 extern void bootDataSeg(void); 1603 extern void MPentry(void); 1604 extern u_int MP_GDT; 1605 extern u_int mp_gdtbase; 1606 1607 static void 1608 install_ap_tramp(u_int boot_addr) 1609 { 1610 int x; 1611 int size = *(int *) ((u_long) & bootMP_size); 1612 u_char *src = (u_char *) ((u_long) bootMP); 1613 u_char *dst = (u_char *) boot_addr + KERNBASE; 1614 u_int boot_base = (u_int) bootMP; 1615 u_int8_t *dst8; 1616 u_int16_t *dst16; 1617 u_int32_t *dst32; 1618 1619 POSTCODE(INSTALL_AP_TRAMP_POST); 1620 1621 for (x = 0; x < size; ++x) 1622 *dst++ = *src++; 1623 1624 /* 1625 * modify addresses in code we just moved to basemem. unfortunately we 1626 * need fairly detailed info about mpboot.s for this to work. changes 1627 * to mpboot.s might require changes here. 1628 */ 1629 1630 /* boot code is located in KERNEL space */ 1631 dst = (u_char *) boot_addr + KERNBASE; 1632 1633 /* modify the lgdt arg */ 1634 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1635 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1636 1637 /* modify the ljmp target for MPentry() */ 1638 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1639 *dst32 = ((u_int) MPentry - KERNBASE); 1640 1641 /* modify the target for boot code segment */ 1642 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1643 dst8 = (u_int8_t *) (dst16 + 1); 1644 *dst16 = (u_int) boot_addr & 0xffff; 1645 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1646 1647 /* modify the target for boot data segment */ 1648 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1649 dst8 = (u_int8_t *) (dst16 + 1); 1650 *dst16 = (u_int) boot_addr & 0xffff; 1651 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1652 } 1653 1654 1655 /* 1656 * this function starts the AP (application processor) identified 1657 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1658 * to accomplish this. This is necessary because of the nuances 1659 * of the different hardware we might encounter. It ain't pretty, 1660 * but it seems to work. 1661 */ 1662 static int 1663 start_ap(int logical_cpu, u_int boot_addr) 1664 { 1665 int physical_cpu; 1666 int vector; 1667 int cpus; 1668 u_long icr_lo, icr_hi; 1669 1670 POSTCODE(START_AP_POST); 1671 1672 /* get the PHYSICAL APIC ID# */ 1673 physical_cpu = CPU_TO_ID(logical_cpu); 1674 1675 /* calculate the vector */ 1676 vector = (boot_addr >> 12) & 0xff; 1677 1678 /* used as a watchpoint to signal AP startup */ 1679 cpus = mp_ncpus; 1680 1681 /* 1682 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1683 * and running the target CPU. OR this INIT IPI might be latched (P5 1684 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1685 * ignored. 1686 */ 1687 1688 /* setup the address for the target AP */ 1689 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1690 icr_hi |= (physical_cpu << 24); 1691 lapic.icr_hi = icr_hi; 1692 1693 /* do an INIT IPI: assert RESET */ 1694 icr_lo = lapic.icr_lo & 0xfff00000; 1695 lapic.icr_lo = icr_lo | 0x0000c500; 1696 1697 /* wait for pending status end */ 1698 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1699 /* spin */ ; 1700 1701 /* do an INIT IPI: deassert RESET */ 1702 lapic.icr_lo = icr_lo | 0x00008500; 1703 1704 /* wait for pending status end */ 1705 u_sleep(10000); /* wait ~10mS */ 1706 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1707 /* spin */ ; 1708 1709 /* 1710 * next we do a STARTUP IPI: the previous INIT IPI might still be 1711 * latched, (P5 bug) this 1st STARTUP would then terminate 1712 * immediately, and the previously started INIT IPI would continue. OR 1713 * the previous INIT IPI has already run. and this STARTUP IPI will 1714 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1715 * will run. 1716 */ 1717 1718 /* do a STARTUP IPI */ 1719 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1720 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1721 /* spin */ ; 1722 u_sleep(200); /* wait ~200uS */ 1723 1724 /* 1725 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1726 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1727 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1728 * recognized after hardware RESET or INIT IPI. 1729 */ 1730 1731 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1732 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1733 /* spin */ ; 1734 u_sleep(200); /* wait ~200uS */ 1735 1736 /* wait for it to start */ 1737 set_apic_timer(5000000);/* == 5 seconds */ 1738 while (read_apic_timer()) 1739 if (mp_ncpus > cpus) 1740 return 1; /* return SUCCESS */ 1741 1742 return 0; /* return FAILURE */ 1743 } 1744 1745 1746 /* 1747 * Flush the TLB on all other CPU's 1748 * 1749 * XXX: Needs to handshake and wait for completion before proceding. 1750 */ 1751 void 1752 smp_invltlb(void) 1753 { 1754 #if defined(APIC_IO) 1755 if (smp_active && invltlb_ok) 1756 all_but_self_ipi(XINVLTLB_OFFSET); 1757 #endif /* APIC_IO */ 1758 } 1759 1760 void 1761 invlpg(u_int addr) 1762 { 1763 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1764 1765 /* send a message to the other CPUs */ 1766 smp_invltlb(); 1767 } 1768 1769 void 1770 invltlb(void) 1771 { 1772 u_long temp; 1773 1774 /* 1775 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1776 * inlined. 1777 */ 1778 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1779 1780 /* send a message to the other CPUs */ 1781 smp_invltlb(); 1782 } 1783 1784 1785 /* 1786 * When called the executing CPU will send an IPI to all other CPUs 1787 * requesting that they halt execution. 1788 * 1789 * Usually (but not necessarily) called with 'other_cpus' as its arg. 1790 * 1791 * - Signals all CPUs in map to stop. 1792 * - Waits for each to stop. 1793 * 1794 * Returns: 1795 * -1: error 1796 * 0: NA 1797 * 1: ok 1798 * 1799 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 1800 * from executing at same time. 1801 */ 1802 int 1803 stop_cpus( u_int map ) 1804 { 1805 if (!smp_active) 1806 return 0; 1807 1808 /* send IPI to all CPUs in map */ 1809 stopped_cpus = 0; 1810 1811 /* send the Xcpustop IPI to all CPUs in map */ 1812 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 1813 1814 while (stopped_cpus != map) 1815 /* spin */ ; 1816 1817 return 1; 1818 } 1819 1820 1821 /* 1822 * Called by a CPU to restart stopped CPUs. 1823 * 1824 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 1825 * 1826 * - Signals all CPUs in map to restart. 1827 * - Waits for each to restart. 1828 * 1829 * Returns: 1830 * -1: error 1831 * 0: NA 1832 * 1: ok 1833 */ 1834 int 1835 restart_cpus( u_int map ) 1836 { 1837 if (!smp_active) 1838 return 0; 1839 1840 started_cpus = map; /* signal other cpus to restart */ 1841 1842 while (started_cpus) /* wait for each to clear its bit */ 1843 /* spin */ ; 1844 1845 return 1; 1846 } 1847