1 /* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.53 1997/09/21 05:49:58 dyson Exp $ 26 */ 27 28 #include "opt_smp.h" 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/proc.h> 34 #include <sys/sysctl.h> 35 36 #include <vm/vm.h> 37 #include <vm/vm_param.h> 38 #include <vm/pmap.h> 39 #include <vm/vm_kern.h> 40 #include <vm/vm_extern.h> 41 42 #include <machine/smp.h> 43 #include <machine/apic.h> 44 #include <machine/mpapic.h> 45 #include <machine/segments.h> 46 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 47 #include <machine/tss.h> 48 #include <machine/specialreg.h> 49 50 #include <i386/i386/cons.h> /* cngetc() */ 51 52 #if defined(APIC_IO) 53 #include <machine/md_var.h> /* setidt() */ 54 #include <i386/isa/icu.h> /* IPIs */ 55 #include <i386/isa/intr_machdep.h> /* IPIs */ 56 #endif /* APIC_IO */ 57 58 #if defined(TEST_DEFAULT_CONFIG) 59 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 60 #else 61 #define MPFPS_MPFB1 mpfps->mpfb1 62 #endif /* TEST_DEFAULT_CONFIG */ 63 64 #define WARMBOOT_TARGET 0 65 #define WARMBOOT_OFF (KERNBASE + 0x0467) 66 #define WARMBOOT_SEG (KERNBASE + 0x0469) 67 68 #define BIOS_BASE (0xf0000) 69 #define BIOS_SIZE (0x10000) 70 #define BIOS_COUNT (BIOS_SIZE/4) 71 72 #define CMOS_REG (0x70) 73 #define CMOS_DATA (0x71) 74 #define BIOS_RESET (0x0f) 75 #define BIOS_WARM (0x0a) 76 77 #define PROCENTRY_FLAG_EN 0x01 78 #define PROCENTRY_FLAG_BP 0x02 79 #define IOAPICENTRY_FLAG_EN 0x01 80 81 82 /* MP Floating Pointer Structure */ 83 typedef struct MPFPS { 84 char signature[4]; 85 void *pap; 86 u_char length; 87 u_char spec_rev; 88 u_char checksum; 89 u_char mpfb1; 90 u_char mpfb2; 91 u_char mpfb3; 92 u_char mpfb4; 93 u_char mpfb5; 94 } *mpfps_t; 95 96 /* MP Configuration Table Header */ 97 typedef struct MPCTH { 98 char signature[4]; 99 u_short base_table_length; 100 u_char spec_rev; 101 u_char checksum; 102 u_char oem_id[8]; 103 u_char product_id[12]; 104 void *oem_table_pointer; 105 u_short oem_table_size; 106 u_short entry_count; 107 void *apic_address; 108 u_short extended_table_length; 109 u_char extended_table_checksum; 110 u_char reserved; 111 } *mpcth_t; 112 113 114 typedef struct PROCENTRY { 115 u_char type; 116 u_char apic_id; 117 u_char apic_version; 118 u_char cpu_flags; 119 u_long cpu_signature; 120 u_long feature_flags; 121 u_long reserved1; 122 u_long reserved2; 123 } *proc_entry_ptr; 124 125 typedef struct BUSENTRY { 126 u_char type; 127 u_char bus_id; 128 char bus_type[6]; 129 } *bus_entry_ptr; 130 131 typedef struct IOAPICENTRY { 132 u_char type; 133 u_char apic_id; 134 u_char apic_version; 135 u_char apic_flags; 136 void *apic_address; 137 } *io_apic_entry_ptr; 138 139 typedef struct INTENTRY { 140 u_char type; 141 u_char int_type; 142 u_short int_flags; 143 u_char src_bus_id; 144 u_char src_bus_irq; 145 u_char dst_apic_id; 146 u_char dst_apic_int; 147 } *int_entry_ptr; 148 149 /* descriptions of MP basetable entries */ 150 typedef struct BASETABLE_ENTRY { 151 u_char type; 152 u_char length; 153 char name[16]; 154 } basetable_entry; 155 156 /* 157 * this code MUST be enabled here and in mpboot.s. 158 * it follows the very early stages of AP boot by placing values in CMOS ram. 159 * it NORMALLY will never be needed and thus the primitive method for enabling. 160 * 161 #define CHECK_POINTS 162 */ 163 164 #if defined(CHECK_POINTS) 165 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 166 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 167 168 #define CHECK_INIT(D); \ 169 CHECK_WRITE(0x34, (D)); \ 170 CHECK_WRITE(0x35, (D)); \ 171 CHECK_WRITE(0x36, (D)); \ 172 CHECK_WRITE(0x37, (D)); \ 173 CHECK_WRITE(0x38, (D)); \ 174 CHECK_WRITE(0x39, (D)); 175 176 #define CHECK_PRINT(S); \ 177 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 178 (S), \ 179 CHECK_READ(0x34), \ 180 CHECK_READ(0x35), \ 181 CHECK_READ(0x36), \ 182 CHECK_READ(0x37), \ 183 CHECK_READ(0x38), \ 184 CHECK_READ(0x39)); 185 186 #else /* CHECK_POINTS */ 187 188 #define CHECK_INIT(D) 189 #define CHECK_PRINT(S) 190 191 #endif /* CHECK_POINTS */ 192 193 /* 194 * Values to send to the POST hardware. 195 */ 196 #define MP_BOOTADDRESS_POST 0x10 197 #define MP_PROBE_POST 0x11 198 #define MPTABLE_PASS1_POST 0x12 199 200 #define MP_START_POST 0x13 201 #define MP_ENABLE_POST 0x14 202 #define MPTABLE_PASS2_POST 0x15 203 204 #define START_ALL_APS_POST 0x16 205 #define INSTALL_AP_TRAMP_POST 0x17 206 #define START_AP_POST 0x18 207 208 #define MP_ANNOUNCE_POST 0x19 209 210 211 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 212 int current_postcode; 213 214 /** XXX FIXME: what system files declare these??? */ 215 extern struct region_descriptor r_gdt, r_idt; 216 217 int bsp_apic_ready = 0; /* flags useability of BSP apic */ 218 int mp_ncpus; /* # of CPUs, including BSP */ 219 int mp_naps; /* # of Applications processors */ 220 int mp_nbusses; /* # of busses */ 221 int mp_napics; /* # of IO APICs */ 222 int boot_cpu_id; /* designated BSP */ 223 vm_offset_t cpu_apic_address; 224 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 225 extern int nkpt; 226 227 u_int32_t cpu_apic_versions[NCPU]; 228 u_int32_t io_apic_versions[NAPIC]; 229 230 /* 231 * APIC ID logical/physical mapping structures. 232 * We oversize these to simplify boot-time config. 233 */ 234 int cpu_num_to_apic_id[NAPICID]; 235 int io_num_to_apic_id[NAPICID]; 236 int apic_id_to_logical[NAPICID]; 237 238 /* Bitmap of all available CPUs */ 239 u_int all_cpus; 240 241 /* AP uses this PTD during bootstrap */ 242 pd_entry_t *bootPTD; 243 244 /* Hotwire a 0->4MB V==P mapping */ 245 extern pt_entry_t *KPTphys; 246 247 /* Virtual address of per-cpu common_tss */ 248 extern struct i386tss common_tss; 249 #ifdef VM86 250 extern struct segment_descriptor common_tssd; 251 extern u_int private_tss; /* flag indicating private tss */ 252 extern u_int my_tr; 253 #endif /* VM86 */ 254 255 /* IdlePTD per cpu */ 256 pd_entry_t *IdlePTDS[NCPU]; 257 258 /* "my" private page table page, for BSP init */ 259 extern pt_entry_t SMP_prvpt[]; 260 261 /* Private page pointer to curcpu's PTD, used during BSP init */ 262 extern pd_entry_t *my_idlePTD; 263 264 static int smp_started; /* has the system started? */ 265 266 /* 267 * Local data and functions. 268 */ 269 270 static int mp_capable; 271 static u_int boot_address; 272 static u_int base_memory; 273 274 static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 275 static mpfps_t mpfps; 276 static int search_for_sig(u_int32_t target, int count); 277 static void mp_enable(u_int boot_addr); 278 279 static int mptable_pass1(void); 280 static int mptable_pass2(void); 281 static void default_mp_table(int type); 282 static void fix_mp_table(void); 283 static void init_locks(void); 284 static int start_all_aps(u_int boot_addr); 285 static void install_ap_tramp(u_int boot_addr); 286 static int start_ap(int logicalCpu, u_int boot_addr); 287 288 289 /* 290 * Calculate usable address in base memory for AP trampoline code. 291 */ 292 u_int 293 mp_bootaddress(u_int basemem) 294 { 295 POSTCODE(MP_BOOTADDRESS_POST); 296 297 base_memory = basemem * 1024; /* convert to bytes */ 298 299 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 300 if ((base_memory - boot_address) < bootMP_size) 301 boot_address -= 4096; /* not enough, lower by 4k */ 302 303 return boot_address; 304 } 305 306 307 /* 308 * Look for an Intel MP spec table (ie, SMP capable hardware). 309 */ 310 int 311 mp_probe(void) 312 { 313 int x; 314 u_long segment; 315 u_int32_t target; 316 317 POSTCODE(MP_PROBE_POST); 318 319 /* see if EBDA exists */ 320 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 321 /* search first 1K of EBDA */ 322 target = (u_int32_t) (segment << 4); 323 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 324 goto found; 325 } else { 326 /* last 1K of base memory, effective 'top of base' passed in */ 327 target = (u_int32_t) (base_memory - 0x400); 328 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 329 goto found; 330 } 331 332 /* search the BIOS */ 333 target = (u_int32_t) BIOS_BASE; 334 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 335 goto found; 336 337 /* nothing found */ 338 mpfps = (mpfps_t)0; 339 mp_capable = 0; 340 return 0; 341 342 found: 343 /* calculate needed resources */ 344 mpfps = (mpfps_t)x; 345 if (mptable_pass1()) 346 panic("you must reconfigure your kernel"); 347 348 /* flag fact that we are running multiple processors */ 349 mp_capable = 1; 350 return 1; 351 } 352 353 354 /* 355 * Startup the SMP processors. 356 */ 357 void 358 mp_start(void) 359 { 360 POSTCODE(MP_START_POST); 361 362 /* look for MP capable motherboard */ 363 if (mp_capable) 364 mp_enable(boot_address); 365 else 366 panic("MP hardware not found!"); 367 } 368 369 370 /* 371 * Print various information about the SMP system hardware and setup. 372 */ 373 void 374 mp_announce(void) 375 { 376 int x; 377 378 POSTCODE(MP_ANNOUNCE_POST); 379 380 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 381 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 382 printf(", version: 0x%08x", cpu_apic_versions[0]); 383 printf(", at 0x%08x\n", cpu_apic_address); 384 for (x = 1; x <= mp_naps; ++x) { 385 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 386 printf(", version: 0x%08x", cpu_apic_versions[x]); 387 printf(", at 0x%08x\n", cpu_apic_address); 388 } 389 390 #if defined(APIC_IO) 391 for (x = 0; x < mp_napics; ++x) { 392 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 393 printf(", version: 0x%08x", io_apic_versions[x]); 394 printf(", at 0x%08x\n", io_apic_address[x]); 395 } 396 #else 397 printf(" Warning: APIC I/O disabled\n"); 398 #endif /* APIC_IO */ 399 } 400 401 /* 402 * AP cpu's call this to sync up protected mode. 403 */ 404 void 405 init_secondary(void) 406 { 407 int gsel_tss; 408 #ifndef VM86 409 u_int my_tr; 410 #endif 411 412 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 413 r_gdt.rd_base = (int) gdt; 414 lgdt(&r_gdt); /* does magic intra-segment return */ 415 lidt(&r_idt); 416 lldt(_default_ldt); 417 418 my_tr = NGDT + cpuid; 419 gsel_tss = GSEL(my_tr, SEL_KPL); 420 gdt[my_tr].sd.sd_type = SDT_SYS386TSS; 421 common_tss.tss_esp0 = 0; /* not used until after switch */ 422 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 423 common_tss.tss_ioopt = (sizeof common_tss) << 16; 424 #ifdef VM86 425 common_tssd = gdt[my_tr].sd; 426 private_tss = 0; 427 #endif /* VM86 */ 428 ltr(gsel_tss); 429 430 load_cr0(0x8005003b); /* XXX! */ 431 432 PTD[0] = 0; 433 pmap_set_opt((unsigned *)PTD); 434 435 invltlb(); 436 } 437 438 439 #if defined(APIC_IO) 440 /* 441 * Final configuration of the BSP's local APIC: 442 * - disable 'pic mode'. 443 * - disable 'virtual wire mode'. 444 * - enable NMI. 445 */ 446 void 447 bsp_apic_configure(void) 448 { 449 u_char byte; 450 u_int32_t temp; 451 452 /* leave 'pic mode' if necessary */ 453 if (picmode) { 454 outb(0x22, 0x70); /* select IMCR */ 455 byte = inb(0x23); /* current contents */ 456 byte |= 0x01; /* mask external INTR */ 457 outb(0x23, byte); /* disconnect 8259s/NMI */ 458 } 459 460 /* mask lint0 (the 8259 'virtual wire' connection) */ 461 temp = lapic.lvt_lint0; 462 temp |= APIC_LVT_M; /* set the mask */ 463 lapic.lvt_lint0 = temp; 464 465 /* setup lint1 to handle NMI */ 466 temp = lapic.lvt_lint1; 467 temp &= ~APIC_LVT_M; /* clear the mask */ 468 lapic.lvt_lint1 = temp; 469 470 if (bootverbose) 471 apic_dump("bsp_apic_configure()"); 472 } 473 #endif /* APIC_IO */ 474 475 476 /******************************************************************* 477 * local functions and data 478 */ 479 480 /* 481 * start the SMP system 482 */ 483 static void 484 mp_enable(u_int boot_addr) 485 { 486 int x; 487 #if defined(APIC_IO) 488 int apic; 489 u_int ux; 490 #endif /* APIC_IO */ 491 492 POSTCODE(MP_ENABLE_POST); 493 494 /* turn on 4MB of V == P addressing so we can get to MP table */ 495 *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 496 invltlb(); 497 498 /* examine the MP table for needed info, uses physical addresses */ 499 x = mptable_pass2(); 500 501 *(int *)PTD = 0; 502 invltlb(); 503 504 /* can't process default configs till the CPU APIC is pmapped */ 505 if (x) 506 default_mp_table(x); 507 508 /* post scan cleanup */ 509 fix_mp_table(); 510 511 #if defined(APIC_IO) 512 513 /* fill the LOGICAL io_apic_versions table */ 514 for (apic = 0; apic < mp_napics; ++apic) { 515 ux = io_apic_read(apic, IOAPIC_VER); 516 io_apic_versions[apic] = ux; 517 } 518 519 /* program each IO APIC in the system */ 520 for (apic = 0; apic < mp_napics; ++apic) 521 if (io_apic_setup(apic) < 0) 522 panic("IO APIC setup failure"); 523 524 /* install a 'Spurious INTerrupt' vector */ 525 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 526 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 527 528 /* install an inter-CPU IPI for TLB invalidation */ 529 setidt(XINVLTLB_OFFSET, Xinvltlb, 530 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 531 532 /* install an inter-CPU IPI for CPU stop/restart */ 533 setidt(XCPUSTOP_OFFSET, Xcpustop, 534 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 535 536 #if defined(TEST_TEST1) 537 /* install a "fake hardware INTerrupt" vector */ 538 setidt(XTEST1_OFFSET, Xtest1, 539 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 540 #endif /** TEST_TEST1 */ 541 542 #endif /* APIC_IO */ 543 544 /* initialize all SMP locks */ 545 init_locks(); 546 547 /* start each Application Processor */ 548 start_all_aps(boot_addr); 549 550 /* 551 * The init process might be started on a different CPU now, 552 * and the boot CPU might not call prepare_usermode to get 553 * cr0 correctly configured. Thus we initialize cr0 here. 554 */ 555 load_cr0(rcr0() | CR0_WP | CR0_AM); 556 } 557 558 559 /* 560 * look for the MP spec signature 561 */ 562 563 /* string defined by the Intel MP Spec as identifying the MP table */ 564 #define MP_SIG 0x5f504d5f /* _MP_ */ 565 #define NEXT(X) ((X) += 4) 566 static int 567 search_for_sig(u_int32_t target, int count) 568 { 569 int x; 570 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 571 572 for (x = 0; x < count; NEXT(x)) 573 if (addr[x] == MP_SIG) 574 /* make array index a byte index */ 575 return (target + (x * sizeof(u_int32_t))); 576 577 return -1; 578 } 579 580 581 static basetable_entry basetable_entry_types[] = 582 { 583 {0, 20, "Processor"}, 584 {1, 8, "Bus"}, 585 {2, 8, "I/O APIC"}, 586 {3, 8, "I/O INT"}, 587 {4, 8, "Local INT"} 588 }; 589 590 typedef struct BUSDATA { 591 u_char bus_id; 592 enum busTypes bus_type; 593 } bus_datum; 594 595 typedef struct INTDATA { 596 u_char int_type; 597 u_short int_flags; 598 u_char src_bus_id; 599 u_char src_bus_irq; 600 u_char dst_apic_id; 601 u_char dst_apic_int; 602 } io_int, local_int; 603 604 typedef struct BUSTYPENAME { 605 u_char type; 606 char name[7]; 607 } bus_type_name; 608 609 static bus_type_name bus_type_table[] = 610 { 611 {CBUS, "CBUS"}, 612 {CBUSII, "CBUSII"}, 613 {EISA, "EISA"}, 614 {UNKNOWN_BUSTYPE, "---"}, 615 {UNKNOWN_BUSTYPE, "---"}, 616 {ISA, "ISA"}, 617 {UNKNOWN_BUSTYPE, "---"}, 618 {UNKNOWN_BUSTYPE, "---"}, 619 {UNKNOWN_BUSTYPE, "---"}, 620 {UNKNOWN_BUSTYPE, "---"}, 621 {UNKNOWN_BUSTYPE, "---"}, 622 {UNKNOWN_BUSTYPE, "---"}, 623 {PCI, "PCI"}, 624 {UNKNOWN_BUSTYPE, "---"}, 625 {UNKNOWN_BUSTYPE, "---"}, 626 {UNKNOWN_BUSTYPE, "---"}, 627 {UNKNOWN_BUSTYPE, "---"}, 628 {XPRESS, "XPRESS"}, 629 {UNKNOWN_BUSTYPE, "---"} 630 }; 631 /* from MP spec v1.4, table 5-1 */ 632 static int default_data[7][5] = 633 { 634 /* nbus, id0, type0, id1, type1 */ 635 {1, 0, ISA, 255, 255}, 636 {1, 0, EISA, 255, 255}, 637 {1, 0, EISA, 255, 255}, 638 {0, 255, 255, 255, 255},/* MCA not supported */ 639 {2, 0, ISA, 1, PCI}, 640 {2, 0, EISA, 1, PCI}, 641 {0, 255, 255, 255, 255} /* MCA not supported */ 642 }; 643 644 645 /* the bus data */ 646 bus_datum bus_data[NBUS]; 647 648 /* the IO INT data, one entry per possible APIC INTerrupt */ 649 io_int io_apic_ints[NINTR]; 650 651 static int nintrs; 652 653 static int processor_entry __P((proc_entry_ptr entry, int cpu)); 654 static int bus_entry __P((bus_entry_ptr entry, int bus)); 655 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 656 static int int_entry __P((int_entry_ptr entry, int intr)); 657 static int lookup_bus_type __P((char *name)); 658 659 660 /* 661 * 1st pass on motherboard's Intel MP specification table. 662 * 663 * initializes: 664 * mp_ncpus = 1 665 * 666 * determines: 667 * cpu_apic_address (common to all CPUs) 668 * io_apic_address[N] 669 * mp_naps 670 * mp_nbusses 671 * mp_napics 672 * nintrs 673 */ 674 static int 675 mptable_pass1(void) 676 { 677 int x; 678 mpcth_t cth; 679 int totalSize; 680 void* position; 681 int count; 682 int type; 683 int mustpanic; 684 685 POSTCODE(MPTABLE_PASS1_POST); 686 687 mustpanic = 0; 688 689 /* clear various tables */ 690 for (x = 0; x < NAPICID; ++x) { 691 io_apic_address[x] = ~0; /* IO APIC address table */ 692 } 693 694 /* init everything to empty */ 695 mp_naps = 0; 696 mp_nbusses = 0; 697 mp_napics = 0; 698 nintrs = 0; 699 700 /* check for use of 'default' configuration */ 701 if (MPFPS_MPFB1 != 0) { 702 /* use default addresses */ 703 cpu_apic_address = DEFAULT_APIC_BASE; 704 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 705 706 /* fill in with defaults */ 707 mp_naps = 2; /* includes BSP */ 708 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 709 #if defined(APIC_IO) 710 mp_napics = 1; 711 nintrs = 16; 712 #endif /* APIC_IO */ 713 } 714 else { 715 if ((cth = mpfps->pap) == 0) 716 panic("MP Configuration Table Header MISSING!"); 717 718 cpu_apic_address = (vm_offset_t) cth->apic_address; 719 720 /* walk the table, recording info of interest */ 721 totalSize = cth->base_table_length - sizeof(struct MPCTH); 722 position = (u_char *) cth + sizeof(struct MPCTH); 723 count = cth->entry_count; 724 725 while (count--) { 726 switch (type = *(u_char *) position) { 727 case 0: /* processor_entry */ 728 if (((proc_entry_ptr)position)->cpu_flags 729 & PROCENTRY_FLAG_EN) 730 ++mp_naps; 731 break; 732 case 1: /* bus_entry */ 733 ++mp_nbusses; 734 break; 735 case 2: /* io_apic_entry */ 736 if (((io_apic_entry_ptr)position)->apic_flags 737 & IOAPICENTRY_FLAG_EN) 738 io_apic_address[mp_napics++] = 739 (vm_offset_t)((io_apic_entry_ptr) 740 position)->apic_address; 741 break; 742 case 3: /* int_entry */ 743 ++nintrs; 744 break; 745 case 4: /* int_entry */ 746 break; 747 default: 748 panic("mpfps Base Table HOSED!"); 749 /* NOTREACHED */ 750 } 751 752 totalSize -= basetable_entry_types[type].length; 753 (u_char*)position += basetable_entry_types[type].length; 754 } 755 } 756 757 /* qualify the numbers */ 758 if (mp_naps > NCPU) 759 #if 0 /* XXX FIXME: kern/4255 */ 760 printf("Warning: only using %d of %d available CPUs!\n", 761 NCPU, mp_naps); 762 #else 763 { 764 printf("NCPU cannot be different than actual CPU count.\n"); 765 printf(" add 'options NCPU=%d' to your kernel config file,\n", 766 mp_naps); 767 printf(" then rerun config & rebuild your SMP kernel\n"); 768 mustpanic = 1; 769 } 770 #endif /* XXX FIXME: kern/4255 */ 771 if (mp_nbusses > NBUS) { 772 printf("found %d busses, increase NBUS\n", mp_nbusses); 773 mustpanic = 1; 774 } 775 if (mp_napics > NAPIC) { 776 printf("found %d apics, increase NAPIC\n", mp_napics); 777 mustpanic = 1; 778 } 779 if (nintrs > NINTR) { 780 printf("found %d intrs, increase NINTR\n", nintrs); 781 mustpanic = 1; 782 } 783 784 /* 785 * Count the BSP. 786 * This is also used as a counter while starting the APs. 787 */ 788 mp_ncpus = 1; 789 790 --mp_naps; /* subtract the BSP */ 791 792 return mustpanic; 793 } 794 795 796 /* 797 * 2nd pass on motherboard's Intel MP specification table. 798 * 799 * sets: 800 * boot_cpu_id 801 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 802 * CPU_TO_ID(N), logical CPU to APIC ID table 803 * IO_TO_ID(N), logical IO to APIC ID table 804 * bus_data[N] 805 * io_apic_ints[N] 806 */ 807 static int 808 mptable_pass2(void) 809 { 810 int x; 811 mpcth_t cth; 812 int totalSize; 813 void* position; 814 int count; 815 int type; 816 int apic, bus, cpu, intr; 817 818 POSTCODE(MPTABLE_PASS2_POST); 819 820 /* clear various tables */ 821 for (x = 0; x < NAPICID; ++x) { 822 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 823 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 824 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 825 } 826 827 /* clear bus data table */ 828 for (x = 0; x < NBUS; ++x) 829 bus_data[x].bus_id = 0xff; 830 831 /* clear IO APIC INT table */ 832 for (x = 0; x < NINTR; ++x) 833 io_apic_ints[x].int_type = 0xff; 834 835 /* setup the cpu/apic mapping arrays */ 836 boot_cpu_id = -1; 837 838 /* record whether PIC or virtual-wire mode */ 839 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 840 841 /* check for use of 'default' configuration */ 842 if (MPFPS_MPFB1 != 0) 843 return MPFPS_MPFB1; /* return default configuration type */ 844 845 if ((cth = mpfps->pap) == 0) 846 panic("MP Configuration Table Header MISSING!"); 847 848 /* walk the table, recording info of interest */ 849 totalSize = cth->base_table_length - sizeof(struct MPCTH); 850 position = (u_char *) cth + sizeof(struct MPCTH); 851 count = cth->entry_count; 852 apic = bus = intr = 0; 853 cpu = 1; /* pre-count the BSP */ 854 855 while (count--) { 856 switch (type = *(u_char *) position) { 857 case 0: 858 if (processor_entry(position, cpu)) 859 ++cpu; 860 break; 861 case 1: 862 if (bus_entry(position, bus)) 863 ++bus; 864 break; 865 case 2: 866 if (io_apic_entry(position, apic)) 867 ++apic; 868 break; 869 case 3: 870 if (int_entry(position, intr)) 871 ++intr; 872 break; 873 case 4: 874 /* int_entry(position); */ 875 break; 876 default: 877 panic("mpfps Base Table HOSED!"); 878 /* NOTREACHED */ 879 } 880 881 totalSize -= basetable_entry_types[type].length; 882 (u_char *) position += basetable_entry_types[type].length; 883 } 884 885 if (boot_cpu_id == -1) 886 panic("NO BSP found!"); 887 888 /* report fact that its NOT a default configuration */ 889 return 0; 890 } 891 892 893 /* 894 * parse an Intel MP specification table 895 */ 896 static void 897 fix_mp_table(void) 898 { 899 int x; 900 int id; 901 int bus_0; 902 int bus_pci; 903 int num_pci_bus; 904 905 /* 906 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 907 * did it wrong. The MP spec says that when more than 1 PCI bus 908 * exists the BIOS must begin with bus entries for the PCI bus and use 909 * actual PCI bus numbering. This implies that when only 1 PCI bus 910 * exists the BIOS can choose to ignore this ordering, and indeed many 911 * MP motherboards do ignore it. This causes a problem when the PCI 912 * sub-system makes requests of the MP sub-system based on PCI bus 913 * numbers. So here we look for the situation and renumber the 914 * busses and associated INTs in an effort to "make it right". 915 */ 916 917 /* find bus 0, PCI bus, count the number of PCI busses */ 918 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 919 if (bus_data[x].bus_id == 0) { 920 bus_0 = x; 921 } 922 if (bus_data[x].bus_type == PCI) { 923 ++num_pci_bus; 924 bus_pci = x; 925 } 926 } 927 /* 928 * bus_0 == slot of bus with ID of 0 929 * bus_pci == slot of last PCI bus encountered 930 */ 931 932 /* check the 1 PCI bus case for sanity */ 933 if (num_pci_bus == 1) { 934 935 /* if it is number 0 all is well */ 936 if (bus_data[bus_pci].bus_id == 0) 937 return; 938 939 /* mis-numbered, swap with whichever bus uses slot 0 */ 940 941 /* swap the bus entry types */ 942 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 943 bus_data[bus_0].bus_type = PCI; 944 945 /* swap each relavant INTerrupt entry */ 946 id = bus_data[bus_pci].bus_id; 947 for (x = 0; x < nintrs; ++x) { 948 if (io_apic_ints[x].src_bus_id == id) { 949 io_apic_ints[x].src_bus_id = 0; 950 } 951 else if (io_apic_ints[x].src_bus_id == 0) { 952 io_apic_ints[x].src_bus_id = id; 953 } 954 } 955 } 956 /* sanity check if more than 1 PCI bus */ 957 else if (num_pci_bus > 1) { 958 for (x = 0; x < mp_nbusses; ++x) { 959 if (bus_data[x].bus_type != PCI) 960 continue; 961 if (bus_data[x].bus_id >= num_pci_bus) 962 panic("bad PCI bus numbering"); 963 } 964 } 965 } 966 967 968 static int 969 processor_entry(proc_entry_ptr entry, int cpu) 970 { 971 /* check for usability */ 972 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 973 return 0; 974 975 /* check for BSP flag */ 976 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 977 boot_cpu_id = entry->apic_id; 978 CPU_TO_ID(0) = entry->apic_id; 979 ID_TO_CPU(entry->apic_id) = 0; 980 return 0; /* its already been counted */ 981 } 982 983 /* add another AP to list, if less than max number of CPUs */ 984 else { 985 CPU_TO_ID(cpu) = entry->apic_id; 986 ID_TO_CPU(entry->apic_id) = cpu; 987 return 1; 988 } 989 } 990 991 992 static int 993 bus_entry(bus_entry_ptr entry, int bus) 994 { 995 int x; 996 char c, name[8]; 997 998 /* encode the name into an index */ 999 for (x = 0; x < 6; ++x) { 1000 if ((c = entry->bus_type[x]) == ' ') 1001 break; 1002 name[x] = c; 1003 } 1004 name[x] = '\0'; 1005 1006 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1007 panic("unknown bus type: '%s'", name); 1008 1009 bus_data[bus].bus_id = entry->bus_id; 1010 bus_data[bus].bus_type = x; 1011 1012 return 1; 1013 } 1014 1015 1016 static int 1017 io_apic_entry(io_apic_entry_ptr entry, int apic) 1018 { 1019 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1020 return 0; 1021 1022 IO_TO_ID(apic) = entry->apic_id; 1023 ID_TO_IO(entry->apic_id) = apic; 1024 1025 return 1; 1026 } 1027 1028 1029 static int 1030 lookup_bus_type(char *name) 1031 { 1032 int x; 1033 1034 for (x = 0; x < MAX_BUSTYPE; ++x) 1035 if (strcmp(bus_type_table[x].name, name) == 0) 1036 return bus_type_table[x].type; 1037 1038 return UNKNOWN_BUSTYPE; 1039 } 1040 1041 1042 static int 1043 int_entry(int_entry_ptr entry, int intr) 1044 { 1045 io_apic_ints[intr].int_type = entry->int_type; 1046 io_apic_ints[intr].int_flags = entry->int_flags; 1047 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1048 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1049 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1050 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1051 1052 return 1; 1053 } 1054 1055 1056 static int 1057 apic_int_is_bus_type(int intr, int bus_type) 1058 { 1059 int bus; 1060 1061 for (bus = 0; bus < mp_nbusses; ++bus) 1062 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1063 && ((int) bus_data[bus].bus_type == bus_type)) 1064 return 1; 1065 1066 return 0; 1067 } 1068 1069 1070 /* 1071 * Given a traditional ISA INT mask, return an APIC mask. 1072 */ 1073 u_int 1074 isa_apic_mask(u_int isa_mask) 1075 { 1076 int isa_irq; 1077 int apic_pin; 1078 1079 #if defined(SKIP_IRQ15_REDIRECT) 1080 if (isa_mask == (1 << 15)) { 1081 printf("skipping ISA IRQ15 redirect\n"); 1082 return isa_mask; 1083 } 1084 #endif /* SKIP_IRQ15_REDIRECT */ 1085 1086 isa_irq = ffs(isa_mask); /* find its bit position */ 1087 if (isa_irq == 0) /* doesn't exist */ 1088 return 0; 1089 --isa_irq; /* make it zero based */ 1090 1091 apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ 1092 if (apic_pin == -1) 1093 return 0; 1094 1095 return (1 << apic_pin); /* convert pin# to a mask */ 1096 } 1097 1098 1099 /* 1100 * Determine which APIC pin an ISA/EISA INT is attached to. 1101 */ 1102 #define INTTYPE(I) (io_apic_ints[(I)].int_type) 1103 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1104 1105 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1106 int 1107 isa_apic_pin(int isa_irq) 1108 { 1109 int intr; 1110 1111 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1112 if (INTTYPE(intr) == 0) { /* standard INT */ 1113 if (SRCBUSIRQ(intr) == isa_irq) { 1114 if (apic_int_is_bus_type(intr, ISA) || 1115 apic_int_is_bus_type(intr, EISA)) 1116 return INTPIN(intr); /* found */ 1117 } 1118 } 1119 } 1120 return -1; /* NOT found */ 1121 } 1122 #undef SRCBUSIRQ 1123 1124 1125 /* 1126 * Determine which APIC pin a PCI INT is attached to. 1127 */ 1128 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1129 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1130 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1131 int 1132 pci_apic_pin(int pciBus, int pciDevice, int pciInt) 1133 { 1134 int intr; 1135 1136 --pciInt; /* zero based */ 1137 1138 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1139 if ((INTTYPE(intr) == 0) /* standard INT */ 1140 && (SRCBUSID(intr) == pciBus) 1141 && (SRCBUSDEVICE(intr) == pciDevice) 1142 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1143 if (apic_int_is_bus_type(intr, PCI)) 1144 return INTPIN(intr); /* exact match */ 1145 1146 return -1; /* NOT found */ 1147 } 1148 #undef SRCBUSLINE 1149 #undef SRCBUSDEVICE 1150 #undef SRCBUSID 1151 1152 #undef INTPIN 1153 #undef INTTYPE 1154 1155 1156 /* 1157 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1158 * 1159 * XXX FIXME: 1160 * Exactly what this means is unclear at this point. It is a solution 1161 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1162 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1163 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1164 * option. 1165 */ 1166 int 1167 undirect_isa_irq(int rirq) 1168 { 1169 #if defined(READY) 1170 printf("Freeing redirected ISA irq %d.\n", rirq); 1171 /** FIXME: tickle the MB redirector chip */ 1172 return ???; 1173 #else 1174 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1175 return 0; 1176 #endif /* READY */ 1177 } 1178 1179 1180 /* 1181 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1182 */ 1183 int 1184 undirect_pci_irq(int rirq) 1185 { 1186 #if defined(READY) 1187 if (bootverbose) 1188 printf("Freeing redirected PCI irq %d.\n", rirq); 1189 1190 /** FIXME: tickle the MB redirector chip */ 1191 return ???; 1192 #else 1193 if (bootverbose) 1194 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1195 rirq); 1196 return 0; 1197 #endif /* READY */ 1198 } 1199 1200 1201 /* 1202 * given a bus ID, return: 1203 * the bus type if found 1204 * -1 if NOT found 1205 */ 1206 int 1207 apic_bus_type(int id) 1208 { 1209 int x; 1210 1211 for (x = 0; x < mp_nbusses; ++x) 1212 if (bus_data[x].bus_id == id) 1213 return bus_data[x].bus_type; 1214 1215 return -1; 1216 } 1217 1218 1219 /* 1220 * given a LOGICAL APIC# and pin#, return: 1221 * the associated src bus ID if found 1222 * -1 if NOT found 1223 */ 1224 int 1225 apic_src_bus_id(int apic, int pin) 1226 { 1227 int x; 1228 1229 /* search each of the possible INTerrupt sources */ 1230 for (x = 0; x < nintrs; ++x) 1231 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1232 (pin == io_apic_ints[x].dst_apic_int)) 1233 return (io_apic_ints[x].src_bus_id); 1234 1235 return -1; /* NOT found */ 1236 } 1237 1238 1239 /* 1240 * given a LOGICAL APIC# and pin#, return: 1241 * the associated src bus IRQ if found 1242 * -1 if NOT found 1243 */ 1244 int 1245 apic_src_bus_irq(int apic, int pin) 1246 { 1247 int x; 1248 1249 for (x = 0; x < nintrs; x++) 1250 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1251 (pin == io_apic_ints[x].dst_apic_int)) 1252 return (io_apic_ints[x].src_bus_irq); 1253 1254 return -1; /* NOT found */ 1255 } 1256 1257 1258 /* 1259 * given a LOGICAL APIC# and pin#, return: 1260 * the associated INTerrupt type if found 1261 * -1 if NOT found 1262 */ 1263 int 1264 apic_int_type(int apic, int pin) 1265 { 1266 int x; 1267 1268 /* search each of the possible INTerrupt sources */ 1269 for (x = 0; x < nintrs; ++x) 1270 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1271 (pin == io_apic_ints[x].dst_apic_int)) 1272 return (io_apic_ints[x].int_type); 1273 1274 return -1; /* NOT found */ 1275 } 1276 1277 1278 /* 1279 * given a LOGICAL APIC# and pin#, return: 1280 * the associated trigger mode if found 1281 * -1 if NOT found 1282 */ 1283 int 1284 apic_trigger(int apic, int pin) 1285 { 1286 int x; 1287 1288 /* search each of the possible INTerrupt sources */ 1289 for (x = 0; x < nintrs; ++x) 1290 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1291 (pin == io_apic_ints[x].dst_apic_int)) 1292 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1293 1294 return -1; /* NOT found */ 1295 } 1296 1297 1298 /* 1299 * given a LOGICAL APIC# and pin#, return: 1300 * the associated 'active' level if found 1301 * -1 if NOT found 1302 */ 1303 int 1304 apic_polarity(int apic, int pin) 1305 { 1306 int x; 1307 1308 /* search each of the possible INTerrupt sources */ 1309 for (x = 0; x < nintrs; ++x) 1310 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1311 (pin == io_apic_ints[x].dst_apic_int)) 1312 return (io_apic_ints[x].int_flags & 0x03); 1313 1314 return -1; /* NOT found */ 1315 } 1316 1317 1318 /* 1319 * set data according to MP defaults 1320 * FIXME: probably not complete yet... 1321 */ 1322 static void 1323 default_mp_table(int type) 1324 { 1325 int ap_cpu_id; 1326 #if defined(APIC_IO) 1327 u_int32_t ux; 1328 int io_apic_id; 1329 int pin; 1330 #endif /* APIC_IO */ 1331 1332 #if 0 1333 printf(" MP default config type: %d\n", type); 1334 switch (type) { 1335 case 1: 1336 printf(" bus: ISA, APIC: 82489DX\n"); 1337 break; 1338 case 2: 1339 printf(" bus: EISA, APIC: 82489DX\n"); 1340 break; 1341 case 3: 1342 printf(" bus: EISA, APIC: 82489DX\n"); 1343 break; 1344 case 4: 1345 printf(" bus: MCA, APIC: 82489DX\n"); 1346 break; 1347 case 5: 1348 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1349 break; 1350 case 6: 1351 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1352 break; 1353 case 7: 1354 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1355 break; 1356 default: 1357 printf(" future type\n"); 1358 break; 1359 /* NOTREACHED */ 1360 } 1361 #endif /* 0 */ 1362 1363 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1364 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1365 1366 /* BSP */ 1367 CPU_TO_ID(0) = boot_cpu_id; 1368 ID_TO_CPU(boot_cpu_id) = 0; 1369 1370 /* one and only AP */ 1371 CPU_TO_ID(1) = ap_cpu_id; 1372 ID_TO_CPU(ap_cpu_id) = 1; 1373 1374 #if defined(APIC_IO) 1375 /* one and only IO APIC */ 1376 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1377 1378 /* 1379 * sanity check, refer to MP spec section 3.6.6, last paragraph 1380 * necessary as some hardware isn't properly setting up the IO APIC 1381 */ 1382 #if defined(REALLY_ANAL_IOAPICID_VALUE) 1383 if (io_apic_id != 2) { 1384 #else 1385 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1386 #endif /* REALLY_ANAL_IOAPICID_VALUE */ 1387 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1388 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1389 ux |= 0x02000000; /* set it to '2' */ 1390 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1391 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1392 if ((ux & APIC_ID_MASK) != 0x02000000) 1393 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1394 io_apic_id = 2; 1395 } 1396 IO_TO_ID(0) = io_apic_id; 1397 ID_TO_IO(io_apic_id) = 0; 1398 #endif /* APIC_IO */ 1399 1400 /* fill out bus entries */ 1401 switch (type) { 1402 case 1: 1403 case 2: 1404 case 3: 1405 case 5: 1406 case 6: 1407 bus_data[0].bus_id = default_data[type - 1][1]; 1408 bus_data[0].bus_type = default_data[type - 1][2]; 1409 bus_data[1].bus_id = default_data[type - 1][3]; 1410 bus_data[1].bus_type = default_data[type - 1][4]; 1411 break; 1412 1413 /* case 4: case 7: MCA NOT supported */ 1414 default: /* illegal/reserved */ 1415 panic("BAD default MP config: %d", type); 1416 /* NOTREACHED */ 1417 } 1418 1419 #if defined(APIC_IO) 1420 /* general cases from MP v1.4, table 5-2 */ 1421 for (pin = 0; pin < 16; ++pin) { 1422 io_apic_ints[pin].int_type = 0; 1423 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1424 io_apic_ints[pin].src_bus_id = 0; 1425 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1426 io_apic_ints[pin].dst_apic_id = io_apic_id; 1427 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1428 } 1429 1430 /* special cases from MP v1.4, table 5-2 */ 1431 if (type == 2) { 1432 io_apic_ints[2].int_type = 0xff; /* N/C */ 1433 io_apic_ints[13].int_type = 0xff; /* N/C */ 1434 #if !defined(APIC_MIXED_MODE) 1435 /** FIXME: ??? */ 1436 panic("sorry, can't support type 2 default yet"); 1437 #endif /* APIC_MIXED_MODE */ 1438 } 1439 else 1440 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1441 1442 if (type == 7) 1443 io_apic_ints[0].int_type = 0xff; /* N/C */ 1444 else 1445 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1446 #endif /* APIC_IO */ 1447 } 1448 1449 1450 /* 1451 * initialize all the SMP locks 1452 */ 1453 1454 /* critical region around IO APIC, apic_imen */ 1455 struct simplelock imen_lock; 1456 1457 /* critical region around splxx(), cpl, cml, cil, ipending */ 1458 struct simplelock cpl_lock; 1459 1460 /* Make FAST_INTR() routines sequential */ 1461 struct simplelock fast_intr_lock; 1462 1463 /* critical region around INTR() routines */ 1464 struct simplelock intr_lock; 1465 1466 /* lock regions protected in UP kernel via cli/sti */ 1467 struct simplelock mpintr_lock; 1468 1469 #ifdef USE_COMLOCK 1470 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 1471 struct simplelock com_lock; 1472 #endif /* USE_COMLOCK */ 1473 1474 #ifdef USE_CLOCKLOCK 1475 /* lock regions around the clock hardware */ 1476 struct simplelock clock_lock; 1477 #endif /* USE_CLOCKLOCK */ 1478 1479 static void 1480 init_locks(void) 1481 { 1482 /* 1483 * Get the initial mp_lock with a count of 1 for the BSP. 1484 * This uses a LOGICAL cpu ID, ie BSP == 0. 1485 */ 1486 mp_lock = 0x00000001; 1487 1488 /* ISR uses its own "giant lock" */ 1489 isr_lock = FREE_LOCK; 1490 1491 s_lock_init((struct simplelock*)&mpintr_lock); 1492 1493 s_lock_init((struct simplelock*)&fast_intr_lock); 1494 s_lock_init((struct simplelock*)&intr_lock); 1495 s_lock_init((struct simplelock*)&imen_lock); 1496 s_lock_init((struct simplelock*)&cpl_lock); 1497 1498 #ifdef USE_COMLOCK 1499 s_lock_init((struct simplelock*)&com_lock); 1500 #endif /* USE_COMLOCK */ 1501 #ifdef USE_CLOCKLOCK 1502 s_lock_init((struct simplelock*)&clock_lock); 1503 #endif /* USE_CLOCKLOCK */ 1504 } 1505 1506 1507 /* 1508 * start each AP in our list 1509 */ 1510 static int 1511 start_all_aps(u_int boot_addr) 1512 { 1513 int x, i; 1514 u_char mpbiosreason; 1515 u_long mpbioswarmvec; 1516 pd_entry_t *newptd; 1517 pt_entry_t *newpt; 1518 int *newpp; 1519 char *stack; 1520 pd_entry_t *myPTD; 1521 1522 POSTCODE(START_ALL_APS_POST); 1523 1524 /* initialize BSP's local APIC */ 1525 apic_initialize(); 1526 bsp_apic_ready = 1; 1527 1528 /* install the AP 1st level boot code */ 1529 install_ap_tramp(boot_addr); 1530 1531 1532 /* save the current value of the warm-start vector */ 1533 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1534 outb(CMOS_REG, BIOS_RESET); 1535 mpbiosreason = inb(CMOS_DATA); 1536 1537 /* record BSP in CPU map */ 1538 all_cpus = 1; 1539 1540 /* start each AP */ 1541 for (x = 1; x <= mp_naps; ++x) { 1542 1543 /* This is a bit verbose, it will go away soon. */ 1544 1545 /* alloc new page table directory */ 1546 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1547 1548 /* Store the virtual PTD address for this CPU */ 1549 IdlePTDS[x] = newptd; 1550 1551 /* clone currently active one (ie: IdlePTD) */ 1552 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1553 1554 /* set up 0 -> 4MB P==V mapping for AP boot */ 1555 newptd[0] = (pd_entry_t) (PG_V | PG_RW | 1556 ((u_long)KPTphys & PG_FRAME)); 1557 1558 /* store PTD for this AP's boot sequence */ 1559 myPTD = (pd_entry_t *)vtophys(newptd); 1560 1561 /* alloc new page table page */ 1562 newpt = (pt_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1563 1564 /* set the new PTD's private page to point there */ 1565 newptd[MPPTDI] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1566 1567 /* install self referential entry */ 1568 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1569 1570 /* allocate a new private data page */ 1571 newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1572 1573 /* wire it into the private page table page */ 1574 newpt[0] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpp)); 1575 1576 /* wire the ptp into itself for access */ 1577 newpt[1] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1578 1579 /* copy in the pointer to the local apic */ 1580 newpt[2] = SMP_prvpt[2]; 1581 1582 /* and the IO apic mapping[s] */ 1583 for (i = 16; i < 32; i++) 1584 newpt[i] = SMP_prvpt[i]; 1585 1586 /* allocate and set up an idle stack data page */ 1587 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE); 1588 for (i = 0; i < UPAGES; i++) 1589 newpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1590 1591 newpt[5] = 0; /* *prv_CMAP1 */ 1592 newpt[6] = 0; /* *prv_CMAP2 */ 1593 newpt[7] = 0; /* *prv_CMAP3 */ 1594 1595 /* prime data page for it to use */ 1596 newpp[0] = x; /* cpuid */ 1597 newpp[1] = 0; /* curproc */ 1598 newpp[2] = 0; /* curpcb */ 1599 newpp[3] = 0; /* npxproc */ 1600 newpp[4] = 0; /* runtime.tv_sec */ 1601 newpp[5] = 0; /* runtime.tv_usec */ 1602 newpp[6] = x << 24; /* cpu_lockid */ 1603 newpp[7] = 0; /* other_cpus */ 1604 newpp[8] = (int)myPTD; /* my_idlePTD */ 1605 newpp[9] = 0; /* ss_tpr */ 1606 newpp[10] = (int)&newpt[5]; /* prv_CMAP1 */ 1607 newpp[11] = (int)&newpt[6]; /* prv_CMAP2 */ 1608 newpp[12] = (int)&newpt[7]; /* prv_CMAP3 */ 1609 1610 /* setup a vector to our boot code */ 1611 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1612 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1613 outb(CMOS_REG, BIOS_RESET); 1614 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1615 1616 bootPTD = myPTD; 1617 /* attempt to start the Application Processor */ 1618 CHECK_INIT(99); /* setup checkpoints */ 1619 if (!start_ap(x, boot_addr)) { 1620 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1621 CHECK_PRINT("trace"); /* show checkpoints */ 1622 /* better panic as the AP may be running loose */ 1623 printf("panic y/n? [y] "); 1624 if (cngetc() != 'n') 1625 panic("bye-bye"); 1626 } 1627 CHECK_PRINT("trace"); /* show checkpoints */ 1628 1629 /* record its version info */ 1630 cpu_apic_versions[x] = cpu_apic_versions[0]; 1631 1632 all_cpus |= (1 << x); /* record AP in CPU map */ 1633 } 1634 1635 /* build our map of 'other' CPUs */ 1636 other_cpus = all_cpus & ~(1 << cpuid); 1637 1638 /* fill in our (BSP) APIC version */ 1639 cpu_apic_versions[0] = lapic.version; 1640 1641 /* restore the warmstart vector */ 1642 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1643 outb(CMOS_REG, BIOS_RESET); 1644 outb(CMOS_DATA, mpbiosreason); 1645 1646 /* 1647 * Set up the idle context for the BSP. Similar to above except 1648 * that some was done by locore, some by pmap.c and some is implicit 1649 * because the BSP is cpu#0 and the page is initially zero, and also 1650 * because we can refer to variables by name on the BSP.. 1651 */ 1652 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1653 1654 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1655 IdlePTDS[0] = newptd; 1656 1657 /* Point PTD[] to this page instead of IdlePTD's physical page */ 1658 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1659 1660 my_idlePTD = (pd_entry_t *)vtophys(newptd); 1661 1662 /* Allocate and setup BSP idle stack */ 1663 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE); 1664 for (i = 0; i < UPAGES; i++) 1665 SMP_prvpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1666 1667 pmap_set_opt_bsp(); 1668 1669 for (i = 0; i < mp_ncpus; i++) { 1670 bcopy( (int *) PTD + KPTDI, (int *) IdlePTDS[i] + KPTDI, NKPDE * sizeof (int)); 1671 } 1672 1673 /* number of APs actually started */ 1674 return mp_ncpus - 1; 1675 } 1676 1677 1678 /* 1679 * load the 1st level AP boot code into base memory. 1680 */ 1681 1682 /* targets for relocation */ 1683 extern void bigJump(void); 1684 extern void bootCodeSeg(void); 1685 extern void bootDataSeg(void); 1686 extern void MPentry(void); 1687 extern u_int MP_GDT; 1688 extern u_int mp_gdtbase; 1689 1690 static void 1691 install_ap_tramp(u_int boot_addr) 1692 { 1693 int x; 1694 int size = *(int *) ((u_long) & bootMP_size); 1695 u_char *src = (u_char *) ((u_long) bootMP); 1696 u_char *dst = (u_char *) boot_addr + KERNBASE; 1697 u_int boot_base = (u_int) bootMP; 1698 u_int8_t *dst8; 1699 u_int16_t *dst16; 1700 u_int32_t *dst32; 1701 1702 POSTCODE(INSTALL_AP_TRAMP_POST); 1703 1704 for (x = 0; x < size; ++x) 1705 *dst++ = *src++; 1706 1707 /* 1708 * modify addresses in code we just moved to basemem. unfortunately we 1709 * need fairly detailed info about mpboot.s for this to work. changes 1710 * to mpboot.s might require changes here. 1711 */ 1712 1713 /* boot code is located in KERNEL space */ 1714 dst = (u_char *) boot_addr + KERNBASE; 1715 1716 /* modify the lgdt arg */ 1717 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1718 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1719 1720 /* modify the ljmp target for MPentry() */ 1721 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1722 *dst32 = ((u_int) MPentry - KERNBASE); 1723 1724 /* modify the target for boot code segment */ 1725 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1726 dst8 = (u_int8_t *) (dst16 + 1); 1727 *dst16 = (u_int) boot_addr & 0xffff; 1728 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1729 1730 /* modify the target for boot data segment */ 1731 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1732 dst8 = (u_int8_t *) (dst16 + 1); 1733 *dst16 = (u_int) boot_addr & 0xffff; 1734 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1735 } 1736 1737 1738 /* 1739 * this function starts the AP (application processor) identified 1740 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1741 * to accomplish this. This is necessary because of the nuances 1742 * of the different hardware we might encounter. It ain't pretty, 1743 * but it seems to work. 1744 */ 1745 static int 1746 start_ap(int logical_cpu, u_int boot_addr) 1747 { 1748 int physical_cpu; 1749 int vector; 1750 int cpus; 1751 u_long icr_lo, icr_hi; 1752 1753 POSTCODE(START_AP_POST); 1754 1755 /* get the PHYSICAL APIC ID# */ 1756 physical_cpu = CPU_TO_ID(logical_cpu); 1757 1758 /* calculate the vector */ 1759 vector = (boot_addr >> 12) & 0xff; 1760 1761 /* used as a watchpoint to signal AP startup */ 1762 cpus = mp_ncpus; 1763 1764 /* 1765 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1766 * and running the target CPU. OR this INIT IPI might be latched (P5 1767 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1768 * ignored. 1769 */ 1770 1771 /* setup the address for the target AP */ 1772 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1773 icr_hi |= (physical_cpu << 24); 1774 lapic.icr_hi = icr_hi; 1775 1776 /* do an INIT IPI: assert RESET */ 1777 icr_lo = lapic.icr_lo & 0xfff00000; 1778 lapic.icr_lo = icr_lo | 0x0000c500; 1779 1780 /* wait for pending status end */ 1781 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1782 /* spin */ ; 1783 1784 /* do an INIT IPI: deassert RESET */ 1785 lapic.icr_lo = icr_lo | 0x00008500; 1786 1787 /* wait for pending status end */ 1788 u_sleep(10000); /* wait ~10mS */ 1789 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1790 /* spin */ ; 1791 1792 /* 1793 * next we do a STARTUP IPI: the previous INIT IPI might still be 1794 * latched, (P5 bug) this 1st STARTUP would then terminate 1795 * immediately, and the previously started INIT IPI would continue. OR 1796 * the previous INIT IPI has already run. and this STARTUP IPI will 1797 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1798 * will run. 1799 */ 1800 1801 /* do a STARTUP IPI */ 1802 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1803 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1804 /* spin */ ; 1805 u_sleep(200); /* wait ~200uS */ 1806 1807 /* 1808 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1809 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1810 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1811 * recognized after hardware RESET or INIT IPI. 1812 */ 1813 1814 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1815 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1816 /* spin */ ; 1817 u_sleep(200); /* wait ~200uS */ 1818 1819 /* wait for it to start */ 1820 set_apic_timer(5000000);/* == 5 seconds */ 1821 while (read_apic_timer()) 1822 if (mp_ncpus > cpus) 1823 return 1; /* return SUCCESS */ 1824 1825 return 0; /* return FAILURE */ 1826 } 1827 1828 1829 /* 1830 * Flush the TLB on all other CPU's 1831 * 1832 * XXX: Needs to handshake and wait for completion before proceding. 1833 */ 1834 void 1835 smp_invltlb(void) 1836 { 1837 #if defined(APIC_IO) 1838 if (smp_started && invltlb_ok) 1839 all_but_self_ipi(XINVLTLB_OFFSET); 1840 #endif /* APIC_IO */ 1841 } 1842 1843 void 1844 invlpg(u_int addr) 1845 { 1846 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1847 1848 /* send a message to the other CPUs */ 1849 smp_invltlb(); 1850 } 1851 1852 void 1853 invltlb(void) 1854 { 1855 u_long temp; 1856 1857 /* 1858 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1859 * inlined. 1860 */ 1861 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1862 1863 /* send a message to the other CPUs */ 1864 smp_invltlb(); 1865 } 1866 1867 1868 /* 1869 * When called the executing CPU will send an IPI to all other CPUs 1870 * requesting that they halt execution. 1871 * 1872 * Usually (but not necessarily) called with 'other_cpus' as its arg. 1873 * 1874 * - Signals all CPUs in map to stop. 1875 * - Waits for each to stop. 1876 * 1877 * Returns: 1878 * -1: error 1879 * 0: NA 1880 * 1: ok 1881 * 1882 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 1883 * from executing at same time. 1884 */ 1885 int 1886 stop_cpus(u_int map) 1887 { 1888 if (!smp_started) 1889 return 0; 1890 1891 /* send IPI to all CPUs in map */ 1892 stopped_cpus = 0; 1893 1894 /* send the Xcpustop IPI to all CPUs in map */ 1895 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 1896 1897 while (stopped_cpus != map) 1898 /* spin */ ; 1899 1900 return 1; 1901 } 1902 1903 1904 /* 1905 * Called by a CPU to restart stopped CPUs. 1906 * 1907 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 1908 * 1909 * - Signals all CPUs in map to restart. 1910 * - Waits for each to restart. 1911 * 1912 * Returns: 1913 * -1: error 1914 * 0: NA 1915 * 1: ok 1916 */ 1917 int 1918 restart_cpus(u_int map) 1919 { 1920 if (!smp_started) 1921 return 0; 1922 1923 started_cpus = map; /* signal other cpus to restart */ 1924 1925 while (started_cpus) /* wait for each to clear its bit */ 1926 /* spin */ ; 1927 1928 return 1; 1929 } 1930 1931 int smp_active = 0; /* are the APs allowed to run? */ 1932 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, ""); 1933 1934 /* XXX maybe should be hw.ncpu */ 1935 int smp_cpus = 1; /* how many cpu's running */ 1936 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, ""); 1937 1938 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */ 1939 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, ""); 1940 1941 int do_page_zero_idle = 0; /* bzero pages for fun and profit in idleloop */ 1942 SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW, 1943 &do_page_zero_idle, 0, ""); 1944 1945 1946 /* 1947 * This is called once the rest of the system is up and running and we're 1948 * ready to let the AP's out of the pen. 1949 */ 1950 void ap_init(void); 1951 1952 void 1953 ap_init() 1954 { 1955 u_int temp; 1956 u_int apic_id; 1957 1958 smp_cpus++; 1959 1960 /* Build our map of 'other' CPUs. */ 1961 other_cpus = all_cpus & ~(1 << cpuid); 1962 1963 printf("SMP: AP CPU #%d Launched!\n", cpuid); 1964 1965 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */ 1966 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS); 1967 1968 /* A quick check from sanity claus */ 1969 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 1970 if (cpuid != apic_id) { 1971 printf("SMP: cpuid = %d\n", cpuid); 1972 printf("SMP: apic_id = %d\n", apic_id); 1973 printf("PTD[MPPTDI] = %08x\n", PTD[MPPTDI]); 1974 panic("cpuid mismatch! boom!!"); 1975 } 1976 1977 /* Init local apic for irq's */ 1978 apic_initialize(); 1979 1980 /* 1981 * Activate smp_invltlb, although strictly speaking, this isn't 1982 * quite correct yet. We should have a bitfield for cpus willing 1983 * to accept TLB flush IPI's or something and sync them. 1984 */ 1985 invltlb_ok = 1; 1986 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */ 1987 smp_active = 1; /* historic */ 1988 1989 curproc = NULL; /* make sure */ 1990 } 1991