1 /*- 2 * Copyright (c) 2015-2016 Svatopluk Kraus 3 * Copyright (c) 2015-2016 Michal Meloun 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * New-style Interrupt Framework 33 * 34 * TODO: - add support for disconnected PICs. 35 * - to support IPI (PPI) enabling on other CPUs if already started. 36 * - to complete things for removable PICs. 37 */ 38 39 #include "opt_ddb.h" 40 #include "opt_hwpmc_hooks.h" 41 #include "opt_iommu.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/syslog.h> 49 #include <sys/malloc.h> 50 #include <sys/proc.h> 51 #include <sys/queue.h> 52 #include <sys/bus.h> 53 #include <sys/interrupt.h> 54 #include <sys/taskqueue.h> 55 #include <sys/tree.h> 56 #include <sys/conf.h> 57 #include <sys/cpuset.h> 58 #include <sys/rman.h> 59 #include <sys/sched.h> 60 #include <sys/smp.h> 61 #include <sys/vmmeter.h> 62 #ifdef HWPMC_HOOKS 63 #include <sys/pmckern.h> 64 #endif 65 66 #include <machine/atomic.h> 67 #include <machine/intr.h> 68 #include <machine/cpu.h> 69 #include <machine/smp.h> 70 #include <machine/stdarg.h> 71 72 #ifdef DDB 73 #include <ddb/ddb.h> 74 #endif 75 76 #ifdef IOMMU 77 #include <dev/iommu/iommu_msi.h> 78 #endif 79 80 #include "pic_if.h" 81 #include "msi_if.h" 82 83 #define INTRNAME_LEN (2*MAXCOMLEN + 1) 84 85 #ifdef DEBUG 86 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 87 printf(fmt,##args); } while (0) 88 #else 89 #define debugf(fmt, args...) 90 #endif 91 92 MALLOC_DECLARE(M_INTRNG); 93 MALLOC_DEFINE(M_INTRNG, "intr", "intr interrupt handling"); 94 95 /* Main interrupt handler called from assembler -> 'hidden' for C code. */ 96 void intr_irq_handler(struct trapframe *tf); 97 98 /* Root interrupt controller stuff. */ 99 device_t intr_irq_root_dev; 100 static intr_irq_filter_t *irq_root_filter; 101 static void *irq_root_arg; 102 static u_int irq_root_ipicount; 103 104 struct intr_pic_child { 105 SLIST_ENTRY(intr_pic_child) pc_next; 106 struct intr_pic *pc_pic; 107 intr_child_irq_filter_t *pc_filter; 108 void *pc_filter_arg; 109 uintptr_t pc_start; 110 uintptr_t pc_length; 111 }; 112 113 /* Interrupt controller definition. */ 114 struct intr_pic { 115 SLIST_ENTRY(intr_pic) pic_next; 116 intptr_t pic_xref; /* hardware identification */ 117 device_t pic_dev; 118 /* Only one of FLAG_PIC or FLAG_MSI may be set */ 119 #define FLAG_PIC (1 << 0) 120 #define FLAG_MSI (1 << 1) 121 #define FLAG_TYPE_MASK (FLAG_PIC | FLAG_MSI) 122 u_int pic_flags; 123 struct mtx pic_child_lock; 124 SLIST_HEAD(, intr_pic_child) pic_children; 125 }; 126 127 static struct mtx pic_list_lock; 128 static SLIST_HEAD(, intr_pic) pic_list; 129 130 static struct intr_pic *pic_lookup(device_t dev, intptr_t xref, int flags); 131 132 /* Interrupt source definition. */ 133 static struct mtx isrc_table_lock; 134 static struct intr_irqsrc *irq_sources[NIRQ]; 135 u_int irq_next_free; 136 137 #ifdef SMP 138 #ifdef EARLY_AP_STARTUP 139 static bool irq_assign_cpu = true; 140 #else 141 static bool irq_assign_cpu = false; 142 #endif 143 #endif 144 145 /* 146 * - 2 counters for each I/O interrupt. 147 * - MAXCPU counters for each IPI counters for SMP. 148 */ 149 #ifdef SMP 150 #define INTRCNT_COUNT (NIRQ * 2 + INTR_IPI_COUNT * MAXCPU) 151 #else 152 #define INTRCNT_COUNT (NIRQ * 2) 153 #endif 154 155 /* Data for MI statistics reporting. */ 156 u_long intrcnt[INTRCNT_COUNT]; 157 char intrnames[INTRCNT_COUNT * INTRNAME_LEN]; 158 size_t sintrcnt = sizeof(intrcnt); 159 size_t sintrnames = sizeof(intrnames); 160 static u_int intrcnt_index; 161 162 static struct intr_irqsrc *intr_map_get_isrc(u_int res_id); 163 static void intr_map_set_isrc(u_int res_id, struct intr_irqsrc *isrc); 164 static struct intr_map_data * intr_map_get_map_data(u_int res_id); 165 static void intr_map_copy_map_data(u_int res_id, device_t *dev, intptr_t *xref, 166 struct intr_map_data **data); 167 168 /* 169 * Interrupt framework initialization routine. 170 */ 171 static void 172 intr_irq_init(void *dummy __unused) 173 { 174 175 SLIST_INIT(&pic_list); 176 mtx_init(&pic_list_lock, "intr pic list", NULL, MTX_DEF); 177 178 mtx_init(&isrc_table_lock, "intr isrc table", NULL, MTX_DEF); 179 } 180 SYSINIT(intr_irq_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_irq_init, NULL); 181 182 static void 183 intrcnt_setname(const char *name, int index) 184 { 185 186 snprintf(intrnames + INTRNAME_LEN * index, INTRNAME_LEN, "%-*s", 187 INTRNAME_LEN - 1, name); 188 } 189 190 /* 191 * Update name for interrupt source with interrupt event. 192 */ 193 static void 194 intrcnt_updatename(struct intr_irqsrc *isrc) 195 { 196 197 /* QQQ: What about stray counter name? */ 198 mtx_assert(&isrc_table_lock, MA_OWNED); 199 intrcnt_setname(isrc->isrc_event->ie_fullname, isrc->isrc_index); 200 } 201 202 /* 203 * Virtualization for interrupt source interrupt counter increment. 204 */ 205 static inline void 206 isrc_increment_count(struct intr_irqsrc *isrc) 207 { 208 209 if (isrc->isrc_flags & INTR_ISRCF_PPI) 210 atomic_add_long(&isrc->isrc_count[0], 1); 211 else 212 isrc->isrc_count[0]++; 213 } 214 215 /* 216 * Virtualization for interrupt source interrupt stray counter increment. 217 */ 218 static inline void 219 isrc_increment_straycount(struct intr_irqsrc *isrc) 220 { 221 222 isrc->isrc_count[1]++; 223 } 224 225 /* 226 * Virtualization for interrupt source interrupt name update. 227 */ 228 static void 229 isrc_update_name(struct intr_irqsrc *isrc, const char *name) 230 { 231 char str[INTRNAME_LEN]; 232 233 mtx_assert(&isrc_table_lock, MA_OWNED); 234 235 if (name != NULL) { 236 snprintf(str, INTRNAME_LEN, "%s: %s", isrc->isrc_name, name); 237 intrcnt_setname(str, isrc->isrc_index); 238 snprintf(str, INTRNAME_LEN, "stray %s: %s", isrc->isrc_name, 239 name); 240 intrcnt_setname(str, isrc->isrc_index + 1); 241 } else { 242 snprintf(str, INTRNAME_LEN, "%s:", isrc->isrc_name); 243 intrcnt_setname(str, isrc->isrc_index); 244 snprintf(str, INTRNAME_LEN, "stray %s:", isrc->isrc_name); 245 intrcnt_setname(str, isrc->isrc_index + 1); 246 } 247 } 248 249 /* 250 * Virtualization for interrupt source interrupt counters setup. 251 */ 252 static void 253 isrc_setup_counters(struct intr_irqsrc *isrc) 254 { 255 u_int index; 256 257 /* 258 * XXX - it does not work well with removable controllers and 259 * interrupt sources !!! 260 */ 261 index = atomic_fetchadd_int(&intrcnt_index, 2); 262 isrc->isrc_index = index; 263 isrc->isrc_count = &intrcnt[index]; 264 isrc_update_name(isrc, NULL); 265 } 266 267 /* 268 * Virtualization for interrupt source interrupt counters release. 269 */ 270 static void 271 isrc_release_counters(struct intr_irqsrc *isrc) 272 { 273 274 panic("%s: not implemented", __func__); 275 } 276 277 #ifdef SMP 278 /* 279 * Virtualization for interrupt source IPI counters setup. 280 */ 281 u_long * 282 intr_ipi_setup_counters(const char *name) 283 { 284 u_int index, i; 285 char str[INTRNAME_LEN]; 286 287 index = atomic_fetchadd_int(&intrcnt_index, MAXCPU); 288 for (i = 0; i < MAXCPU; i++) { 289 snprintf(str, INTRNAME_LEN, "cpu%d:%s", i, name); 290 intrcnt_setname(str, index + i); 291 } 292 return (&intrcnt[index]); 293 } 294 #endif 295 296 /* 297 * Main interrupt dispatch handler. It's called straight 298 * from the assembler, where CPU interrupt is served. 299 */ 300 void 301 intr_irq_handler(struct trapframe *tf) 302 { 303 struct trapframe * oldframe; 304 struct thread * td; 305 306 KASSERT(irq_root_filter != NULL, ("%s: no filter", __func__)); 307 308 VM_CNT_INC(v_intr); 309 critical_enter(); 310 td = curthread; 311 oldframe = td->td_intr_frame; 312 td->td_intr_frame = tf; 313 irq_root_filter(irq_root_arg); 314 td->td_intr_frame = oldframe; 315 critical_exit(); 316 #ifdef HWPMC_HOOKS 317 if (pmc_hook && TRAPF_USERMODE(tf) && 318 (PCPU_GET(curthread)->td_pflags & TDP_CALLCHAIN)) 319 pmc_hook(PCPU_GET(curthread), PMC_FN_USER_CALLCHAIN, tf); 320 #endif 321 } 322 323 int 324 intr_child_irq_handler(struct intr_pic *parent, uintptr_t irq) 325 { 326 struct intr_pic_child *child; 327 bool found; 328 329 found = false; 330 mtx_lock_spin(&parent->pic_child_lock); 331 SLIST_FOREACH(child, &parent->pic_children, pc_next) { 332 if (child->pc_start <= irq && 333 irq < (child->pc_start + child->pc_length)) { 334 found = true; 335 break; 336 } 337 } 338 mtx_unlock_spin(&parent->pic_child_lock); 339 340 if (found) 341 return (child->pc_filter(child->pc_filter_arg, irq)); 342 343 return (FILTER_STRAY); 344 } 345 346 /* 347 * interrupt controller dispatch function for interrupts. It should 348 * be called straight from the interrupt controller, when associated interrupt 349 * source is learned. 350 */ 351 int 352 intr_isrc_dispatch(struct intr_irqsrc *isrc, struct trapframe *tf) 353 { 354 355 KASSERT(isrc != NULL, ("%s: no source", __func__)); 356 357 isrc_increment_count(isrc); 358 359 #ifdef INTR_SOLO 360 if (isrc->isrc_filter != NULL) { 361 int error; 362 error = isrc->isrc_filter(isrc->isrc_arg, tf); 363 PIC_POST_FILTER(isrc->isrc_dev, isrc); 364 if (error == FILTER_HANDLED) 365 return (0); 366 } else 367 #endif 368 if (isrc->isrc_event != NULL) { 369 if (intr_event_handle(isrc->isrc_event, tf) == 0) 370 return (0); 371 } 372 373 isrc_increment_straycount(isrc); 374 return (EINVAL); 375 } 376 377 /* 378 * Alloc unique interrupt number (resource handle) for interrupt source. 379 * 380 * There could be various strategies how to allocate free interrupt number 381 * (resource handle) for new interrupt source. 382 * 383 * 1. Handles are always allocated forward, so handles are not recycled 384 * immediately. However, if only one free handle left which is reused 385 * constantly... 386 */ 387 static inline int 388 isrc_alloc_irq(struct intr_irqsrc *isrc) 389 { 390 u_int maxirqs, irq; 391 392 mtx_assert(&isrc_table_lock, MA_OWNED); 393 394 maxirqs = nitems(irq_sources); 395 if (irq_next_free >= maxirqs) 396 return (ENOSPC); 397 398 for (irq = irq_next_free; irq < maxirqs; irq++) { 399 if (irq_sources[irq] == NULL) 400 goto found; 401 } 402 for (irq = 0; irq < irq_next_free; irq++) { 403 if (irq_sources[irq] == NULL) 404 goto found; 405 } 406 407 irq_next_free = maxirqs; 408 return (ENOSPC); 409 410 found: 411 isrc->isrc_irq = irq; 412 irq_sources[irq] = isrc; 413 414 irq_next_free = irq + 1; 415 if (irq_next_free >= maxirqs) 416 irq_next_free = 0; 417 return (0); 418 } 419 420 /* 421 * Free unique interrupt number (resource handle) from interrupt source. 422 */ 423 static inline int 424 isrc_free_irq(struct intr_irqsrc *isrc) 425 { 426 427 mtx_assert(&isrc_table_lock, MA_OWNED); 428 429 if (isrc->isrc_irq >= nitems(irq_sources)) 430 return (EINVAL); 431 if (irq_sources[isrc->isrc_irq] != isrc) 432 return (EINVAL); 433 434 irq_sources[isrc->isrc_irq] = NULL; 435 isrc->isrc_irq = INTR_IRQ_INVALID; /* just to be safe */ 436 return (0); 437 } 438 439 /* 440 * Initialize interrupt source and register it into global interrupt table. 441 */ 442 int 443 intr_isrc_register(struct intr_irqsrc *isrc, device_t dev, u_int flags, 444 const char *fmt, ...) 445 { 446 int error; 447 va_list ap; 448 449 bzero(isrc, sizeof(struct intr_irqsrc)); 450 isrc->isrc_dev = dev; 451 isrc->isrc_irq = INTR_IRQ_INVALID; /* just to be safe */ 452 isrc->isrc_flags = flags; 453 454 va_start(ap, fmt); 455 vsnprintf(isrc->isrc_name, INTR_ISRC_NAMELEN, fmt, ap); 456 va_end(ap); 457 458 mtx_lock(&isrc_table_lock); 459 error = isrc_alloc_irq(isrc); 460 if (error != 0) { 461 mtx_unlock(&isrc_table_lock); 462 return (error); 463 } 464 /* 465 * Setup interrupt counters, but not for IPI sources. Those are setup 466 * later and only for used ones (up to INTR_IPI_COUNT) to not exhaust 467 * our counter pool. 468 */ 469 if ((isrc->isrc_flags & INTR_ISRCF_IPI) == 0) 470 isrc_setup_counters(isrc); 471 mtx_unlock(&isrc_table_lock); 472 return (0); 473 } 474 475 /* 476 * Deregister interrupt source from global interrupt table. 477 */ 478 int 479 intr_isrc_deregister(struct intr_irqsrc *isrc) 480 { 481 int error; 482 483 mtx_lock(&isrc_table_lock); 484 if ((isrc->isrc_flags & INTR_ISRCF_IPI) == 0) 485 isrc_release_counters(isrc); 486 error = isrc_free_irq(isrc); 487 mtx_unlock(&isrc_table_lock); 488 return (error); 489 } 490 491 #ifdef SMP 492 /* 493 * A support function for a PIC to decide if provided ISRC should be inited 494 * on given cpu. The logic of INTR_ISRCF_BOUND flag and isrc_cpu member of 495 * struct intr_irqsrc is the following: 496 * 497 * If INTR_ISRCF_BOUND is set, the ISRC should be inited only on cpus 498 * set in isrc_cpu. If not, the ISRC should be inited on every cpu and 499 * isrc_cpu is kept consistent with it. Thus isrc_cpu is always correct. 500 */ 501 bool 502 intr_isrc_init_on_cpu(struct intr_irqsrc *isrc, u_int cpu) 503 { 504 505 if (isrc->isrc_handlers == 0) 506 return (false); 507 if ((isrc->isrc_flags & (INTR_ISRCF_PPI | INTR_ISRCF_IPI)) == 0) 508 return (false); 509 if (isrc->isrc_flags & INTR_ISRCF_BOUND) 510 return (CPU_ISSET(cpu, &isrc->isrc_cpu)); 511 512 CPU_SET(cpu, &isrc->isrc_cpu); 513 return (true); 514 } 515 #endif 516 517 #ifdef INTR_SOLO 518 /* 519 * Setup filter into interrupt source. 520 */ 521 static int 522 iscr_setup_filter(struct intr_irqsrc *isrc, const char *name, 523 intr_irq_filter_t *filter, void *arg, void **cookiep) 524 { 525 526 if (filter == NULL) 527 return (EINVAL); 528 529 mtx_lock(&isrc_table_lock); 530 /* 531 * Make sure that we do not mix the two ways 532 * how we handle interrupt sources. 533 */ 534 if (isrc->isrc_filter != NULL || isrc->isrc_event != NULL) { 535 mtx_unlock(&isrc_table_lock); 536 return (EBUSY); 537 } 538 isrc->isrc_filter = filter; 539 isrc->isrc_arg = arg; 540 isrc_update_name(isrc, name); 541 mtx_unlock(&isrc_table_lock); 542 543 *cookiep = isrc; 544 return (0); 545 } 546 #endif 547 548 /* 549 * Interrupt source pre_ithread method for MI interrupt framework. 550 */ 551 static void 552 intr_isrc_pre_ithread(void *arg) 553 { 554 struct intr_irqsrc *isrc = arg; 555 556 PIC_PRE_ITHREAD(isrc->isrc_dev, isrc); 557 } 558 559 /* 560 * Interrupt source post_ithread method for MI interrupt framework. 561 */ 562 static void 563 intr_isrc_post_ithread(void *arg) 564 { 565 struct intr_irqsrc *isrc = arg; 566 567 PIC_POST_ITHREAD(isrc->isrc_dev, isrc); 568 } 569 570 /* 571 * Interrupt source post_filter method for MI interrupt framework. 572 */ 573 static void 574 intr_isrc_post_filter(void *arg) 575 { 576 struct intr_irqsrc *isrc = arg; 577 578 PIC_POST_FILTER(isrc->isrc_dev, isrc); 579 } 580 581 /* 582 * Interrupt source assign_cpu method for MI interrupt framework. 583 */ 584 static int 585 intr_isrc_assign_cpu(void *arg, int cpu) 586 { 587 #ifdef SMP 588 struct intr_irqsrc *isrc = arg; 589 int error; 590 591 if (isrc->isrc_dev != intr_irq_root_dev) 592 return (EINVAL); 593 594 mtx_lock(&isrc_table_lock); 595 if (cpu == NOCPU) { 596 CPU_ZERO(&isrc->isrc_cpu); 597 isrc->isrc_flags &= ~INTR_ISRCF_BOUND; 598 } else { 599 CPU_SETOF(cpu, &isrc->isrc_cpu); 600 isrc->isrc_flags |= INTR_ISRCF_BOUND; 601 } 602 603 /* 604 * In NOCPU case, it's up to PIC to either leave ISRC on same CPU or 605 * re-balance it to another CPU or enable it on more CPUs. However, 606 * PIC is expected to change isrc_cpu appropriately to keep us well 607 * informed if the call is successful. 608 */ 609 if (irq_assign_cpu) { 610 error = PIC_BIND_INTR(isrc->isrc_dev, isrc); 611 if (error) { 612 CPU_ZERO(&isrc->isrc_cpu); 613 mtx_unlock(&isrc_table_lock); 614 return (error); 615 } 616 } 617 mtx_unlock(&isrc_table_lock); 618 return (0); 619 #else 620 return (EOPNOTSUPP); 621 #endif 622 } 623 624 /* 625 * Create interrupt event for interrupt source. 626 */ 627 static int 628 isrc_event_create(struct intr_irqsrc *isrc) 629 { 630 struct intr_event *ie; 631 int error; 632 633 error = intr_event_create(&ie, isrc, 0, isrc->isrc_irq, 634 intr_isrc_pre_ithread, intr_isrc_post_ithread, intr_isrc_post_filter, 635 intr_isrc_assign_cpu, "%s:", isrc->isrc_name); 636 if (error) 637 return (error); 638 639 mtx_lock(&isrc_table_lock); 640 /* 641 * Make sure that we do not mix the two ways 642 * how we handle interrupt sources. Let contested event wins. 643 */ 644 #ifdef INTR_SOLO 645 if (isrc->isrc_filter != NULL || isrc->isrc_event != NULL) { 646 #else 647 if (isrc->isrc_event != NULL) { 648 #endif 649 mtx_unlock(&isrc_table_lock); 650 intr_event_destroy(ie); 651 return (isrc->isrc_event != NULL ? EBUSY : 0); 652 } 653 isrc->isrc_event = ie; 654 mtx_unlock(&isrc_table_lock); 655 656 return (0); 657 } 658 #ifdef notyet 659 /* 660 * Destroy interrupt event for interrupt source. 661 */ 662 static void 663 isrc_event_destroy(struct intr_irqsrc *isrc) 664 { 665 struct intr_event *ie; 666 667 mtx_lock(&isrc_table_lock); 668 ie = isrc->isrc_event; 669 isrc->isrc_event = NULL; 670 mtx_unlock(&isrc_table_lock); 671 672 if (ie != NULL) 673 intr_event_destroy(ie); 674 } 675 #endif 676 /* 677 * Add handler to interrupt source. 678 */ 679 static int 680 isrc_add_handler(struct intr_irqsrc *isrc, const char *name, 681 driver_filter_t filter, driver_intr_t handler, void *arg, 682 enum intr_type flags, void **cookiep) 683 { 684 int error; 685 686 if (isrc->isrc_event == NULL) { 687 error = isrc_event_create(isrc); 688 if (error) 689 return (error); 690 } 691 692 error = intr_event_add_handler(isrc->isrc_event, name, filter, handler, 693 arg, intr_priority(flags), flags, cookiep); 694 if (error == 0) { 695 mtx_lock(&isrc_table_lock); 696 intrcnt_updatename(isrc); 697 mtx_unlock(&isrc_table_lock); 698 } 699 700 return (error); 701 } 702 703 /* 704 * Lookup interrupt controller locked. 705 */ 706 static inline struct intr_pic * 707 pic_lookup_locked(device_t dev, intptr_t xref, int flags) 708 { 709 struct intr_pic *pic; 710 711 mtx_assert(&pic_list_lock, MA_OWNED); 712 713 if (dev == NULL && xref == 0) 714 return (NULL); 715 716 /* Note that pic->pic_dev is never NULL on registered PIC. */ 717 SLIST_FOREACH(pic, &pic_list, pic_next) { 718 if ((pic->pic_flags & FLAG_TYPE_MASK) != 719 (flags & FLAG_TYPE_MASK)) 720 continue; 721 722 if (dev == NULL) { 723 if (xref == pic->pic_xref) 724 return (pic); 725 } else if (xref == 0 || pic->pic_xref == 0) { 726 if (dev == pic->pic_dev) 727 return (pic); 728 } else if (xref == pic->pic_xref && dev == pic->pic_dev) 729 return (pic); 730 } 731 return (NULL); 732 } 733 734 /* 735 * Lookup interrupt controller. 736 */ 737 static struct intr_pic * 738 pic_lookup(device_t dev, intptr_t xref, int flags) 739 { 740 struct intr_pic *pic; 741 742 mtx_lock(&pic_list_lock); 743 pic = pic_lookup_locked(dev, xref, flags); 744 mtx_unlock(&pic_list_lock); 745 return (pic); 746 } 747 748 /* 749 * Create interrupt controller. 750 */ 751 static struct intr_pic * 752 pic_create(device_t dev, intptr_t xref, int flags) 753 { 754 struct intr_pic *pic; 755 756 mtx_lock(&pic_list_lock); 757 pic = pic_lookup_locked(dev, xref, flags); 758 if (pic != NULL) { 759 mtx_unlock(&pic_list_lock); 760 return (pic); 761 } 762 pic = malloc(sizeof(*pic), M_INTRNG, M_NOWAIT | M_ZERO); 763 if (pic == NULL) { 764 mtx_unlock(&pic_list_lock); 765 return (NULL); 766 } 767 pic->pic_xref = xref; 768 pic->pic_dev = dev; 769 pic->pic_flags = flags; 770 mtx_init(&pic->pic_child_lock, "pic child lock", NULL, MTX_SPIN); 771 SLIST_INSERT_HEAD(&pic_list, pic, pic_next); 772 mtx_unlock(&pic_list_lock); 773 774 return (pic); 775 } 776 #ifdef notyet 777 /* 778 * Destroy interrupt controller. 779 */ 780 static void 781 pic_destroy(device_t dev, intptr_t xref, int flags) 782 { 783 struct intr_pic *pic; 784 785 mtx_lock(&pic_list_lock); 786 pic = pic_lookup_locked(dev, xref, flags); 787 if (pic == NULL) { 788 mtx_unlock(&pic_list_lock); 789 return; 790 } 791 SLIST_REMOVE(&pic_list, pic, intr_pic, pic_next); 792 mtx_unlock(&pic_list_lock); 793 794 free(pic, M_INTRNG); 795 } 796 #endif 797 /* 798 * Register interrupt controller. 799 */ 800 struct intr_pic * 801 intr_pic_register(device_t dev, intptr_t xref) 802 { 803 struct intr_pic *pic; 804 805 if (dev == NULL) 806 return (NULL); 807 pic = pic_create(dev, xref, FLAG_PIC); 808 if (pic == NULL) 809 return (NULL); 810 811 debugf("PIC %p registered for %s <dev %p, xref %jx>\n", pic, 812 device_get_nameunit(dev), dev, (uintmax_t)xref); 813 return (pic); 814 } 815 816 /* 817 * Unregister interrupt controller. 818 */ 819 int 820 intr_pic_deregister(device_t dev, intptr_t xref) 821 { 822 823 panic("%s: not implemented", __func__); 824 } 825 826 /* 827 * Mark interrupt controller (itself) as a root one. 828 * 829 * Note that only an interrupt controller can really know its position 830 * in interrupt controller's tree. So root PIC must claim itself as a root. 831 * 832 * In FDT case, according to ePAPR approved version 1.1 from 08 April 2011, 833 * page 30: 834 * "The root of the interrupt tree is determined when traversal 835 * of the interrupt tree reaches an interrupt controller node without 836 * an interrupts property and thus no explicit interrupt parent." 837 */ 838 int 839 intr_pic_claim_root(device_t dev, intptr_t xref, intr_irq_filter_t *filter, 840 void *arg, u_int ipicount) 841 { 842 struct intr_pic *pic; 843 844 pic = pic_lookup(dev, xref, FLAG_PIC); 845 if (pic == NULL) { 846 device_printf(dev, "not registered\n"); 847 return (EINVAL); 848 } 849 850 KASSERT((pic->pic_flags & FLAG_TYPE_MASK) == FLAG_PIC, 851 ("%s: Found a non-PIC controller: %s", __func__, 852 device_get_name(pic->pic_dev))); 853 854 if (filter == NULL) { 855 device_printf(dev, "filter missing\n"); 856 return (EINVAL); 857 } 858 859 /* 860 * Only one interrupt controllers could be on the root for now. 861 * Note that we further suppose that there is not threaded interrupt 862 * routine (handler) on the root. See intr_irq_handler(). 863 */ 864 if (intr_irq_root_dev != NULL) { 865 device_printf(dev, "another root already set\n"); 866 return (EBUSY); 867 } 868 869 intr_irq_root_dev = dev; 870 irq_root_filter = filter; 871 irq_root_arg = arg; 872 irq_root_ipicount = ipicount; 873 874 debugf("irq root set to %s\n", device_get_nameunit(dev)); 875 return (0); 876 } 877 878 /* 879 * Add a handler to manage a sub range of a parents interrupts. 880 */ 881 struct intr_pic * 882 intr_pic_add_handler(device_t parent, struct intr_pic *pic, 883 intr_child_irq_filter_t *filter, void *arg, uintptr_t start, 884 uintptr_t length) 885 { 886 struct intr_pic *parent_pic; 887 struct intr_pic_child *newchild; 888 #ifdef INVARIANTS 889 struct intr_pic_child *child; 890 #endif 891 892 /* Find the parent PIC */ 893 parent_pic = pic_lookup(parent, 0, FLAG_PIC); 894 if (parent_pic == NULL) 895 return (NULL); 896 897 newchild = malloc(sizeof(*newchild), M_INTRNG, M_WAITOK | M_ZERO); 898 newchild->pc_pic = pic; 899 newchild->pc_filter = filter; 900 newchild->pc_filter_arg = arg; 901 newchild->pc_start = start; 902 newchild->pc_length = length; 903 904 mtx_lock_spin(&parent_pic->pic_child_lock); 905 #ifdef INVARIANTS 906 SLIST_FOREACH(child, &parent_pic->pic_children, pc_next) { 907 KASSERT(child->pc_pic != pic, ("%s: Adding a child PIC twice", 908 __func__)); 909 } 910 #endif 911 SLIST_INSERT_HEAD(&parent_pic->pic_children, newchild, pc_next); 912 mtx_unlock_spin(&parent_pic->pic_child_lock); 913 914 return (pic); 915 } 916 917 static int 918 intr_resolve_irq(device_t dev, intptr_t xref, struct intr_map_data *data, 919 struct intr_irqsrc **isrc) 920 { 921 struct intr_pic *pic; 922 struct intr_map_data_msi *msi; 923 924 if (data == NULL) 925 return (EINVAL); 926 927 pic = pic_lookup(dev, xref, 928 (data->type == INTR_MAP_DATA_MSI) ? FLAG_MSI : FLAG_PIC); 929 if (pic == NULL) 930 return (ESRCH); 931 932 switch (data->type) { 933 case INTR_MAP_DATA_MSI: 934 KASSERT((pic->pic_flags & FLAG_TYPE_MASK) == FLAG_MSI, 935 ("%s: Found a non-MSI controller: %s", __func__, 936 device_get_name(pic->pic_dev))); 937 msi = (struct intr_map_data_msi *)data; 938 *isrc = msi->isrc; 939 return (0); 940 941 default: 942 KASSERT((pic->pic_flags & FLAG_TYPE_MASK) == FLAG_PIC, 943 ("%s: Found a non-PIC controller: %s", __func__, 944 device_get_name(pic->pic_dev))); 945 return (PIC_MAP_INTR(pic->pic_dev, data, isrc)); 946 } 947 } 948 949 int 950 intr_activate_irq(device_t dev, struct resource *res) 951 { 952 device_t map_dev; 953 intptr_t map_xref; 954 struct intr_map_data *data; 955 struct intr_irqsrc *isrc; 956 u_int res_id; 957 int error; 958 959 KASSERT(rman_get_start(res) == rman_get_end(res), 960 ("%s: more interrupts in resource", __func__)); 961 962 res_id = (u_int)rman_get_start(res); 963 if (intr_map_get_isrc(res_id) != NULL) 964 panic("Attempt to double activation of resource id: %u\n", 965 res_id); 966 intr_map_copy_map_data(res_id, &map_dev, &map_xref, &data); 967 error = intr_resolve_irq(map_dev, map_xref, data, &isrc); 968 if (error != 0) { 969 free(data, M_INTRNG); 970 /* XXX TODO DISCONECTED PICs */ 971 /* if (error == EINVAL) return(0); */ 972 return (error); 973 } 974 intr_map_set_isrc(res_id, isrc); 975 rman_set_virtual(res, data); 976 return (PIC_ACTIVATE_INTR(isrc->isrc_dev, isrc, res, data)); 977 } 978 979 int 980 intr_deactivate_irq(device_t dev, struct resource *res) 981 { 982 struct intr_map_data *data; 983 struct intr_irqsrc *isrc; 984 u_int res_id; 985 int error; 986 987 KASSERT(rman_get_start(res) == rman_get_end(res), 988 ("%s: more interrupts in resource", __func__)); 989 990 res_id = (u_int)rman_get_start(res); 991 isrc = intr_map_get_isrc(res_id); 992 if (isrc == NULL) 993 panic("Attempt to deactivate non-active resource id: %u\n", 994 res_id); 995 996 data = rman_get_virtual(res); 997 error = PIC_DEACTIVATE_INTR(isrc->isrc_dev, isrc, res, data); 998 intr_map_set_isrc(res_id, NULL); 999 rman_set_virtual(res, NULL); 1000 free(data, M_INTRNG); 1001 return (error); 1002 } 1003 1004 int 1005 intr_setup_irq(device_t dev, struct resource *res, driver_filter_t filt, 1006 driver_intr_t hand, void *arg, int flags, void **cookiep) 1007 { 1008 int error; 1009 struct intr_map_data *data; 1010 struct intr_irqsrc *isrc; 1011 const char *name; 1012 u_int res_id; 1013 1014 KASSERT(rman_get_start(res) == rman_get_end(res), 1015 ("%s: more interrupts in resource", __func__)); 1016 1017 res_id = (u_int)rman_get_start(res); 1018 isrc = intr_map_get_isrc(res_id); 1019 if (isrc == NULL) { 1020 /* XXX TODO DISCONECTED PICs */ 1021 return (EINVAL); 1022 } 1023 1024 data = rman_get_virtual(res); 1025 name = device_get_nameunit(dev); 1026 1027 #ifdef INTR_SOLO 1028 /* 1029 * Standard handling is done through MI interrupt framework. However, 1030 * some interrupts could request solely own special handling. This 1031 * non standard handling can be used for interrupt controllers without 1032 * handler (filter only), so in case that interrupt controllers are 1033 * chained, MI interrupt framework is called only in leaf controller. 1034 * 1035 * Note that root interrupt controller routine is served as well, 1036 * however in intr_irq_handler(), i.e. main system dispatch routine. 1037 */ 1038 if (flags & INTR_SOLO && hand != NULL) { 1039 debugf("irq %u cannot solo on %s\n", irq, name); 1040 return (EINVAL); 1041 } 1042 1043 if (flags & INTR_SOLO) { 1044 error = iscr_setup_filter(isrc, name, (intr_irq_filter_t *)filt, 1045 arg, cookiep); 1046 debugf("irq %u setup filter error %d on %s\n", isrc->isrc_irq, error, 1047 name); 1048 } else 1049 #endif 1050 { 1051 error = isrc_add_handler(isrc, name, filt, hand, arg, flags, 1052 cookiep); 1053 debugf("irq %u add handler error %d on %s\n", isrc->isrc_irq, error, name); 1054 } 1055 if (error != 0) 1056 return (error); 1057 1058 mtx_lock(&isrc_table_lock); 1059 error = PIC_SETUP_INTR(isrc->isrc_dev, isrc, res, data); 1060 if (error == 0) { 1061 isrc->isrc_handlers++; 1062 if (isrc->isrc_handlers == 1) 1063 PIC_ENABLE_INTR(isrc->isrc_dev, isrc); 1064 } 1065 mtx_unlock(&isrc_table_lock); 1066 if (error != 0) 1067 intr_event_remove_handler(*cookiep); 1068 return (error); 1069 } 1070 1071 int 1072 intr_teardown_irq(device_t dev, struct resource *res, void *cookie) 1073 { 1074 int error; 1075 struct intr_map_data *data; 1076 struct intr_irqsrc *isrc; 1077 u_int res_id; 1078 1079 KASSERT(rman_get_start(res) == rman_get_end(res), 1080 ("%s: more interrupts in resource", __func__)); 1081 1082 res_id = (u_int)rman_get_start(res); 1083 isrc = intr_map_get_isrc(res_id); 1084 if (isrc == NULL || isrc->isrc_handlers == 0) 1085 return (EINVAL); 1086 1087 data = rman_get_virtual(res); 1088 1089 #ifdef INTR_SOLO 1090 if (isrc->isrc_filter != NULL) { 1091 if (isrc != cookie) 1092 return (EINVAL); 1093 1094 mtx_lock(&isrc_table_lock); 1095 isrc->isrc_filter = NULL; 1096 isrc->isrc_arg = NULL; 1097 isrc->isrc_handlers = 0; 1098 PIC_DISABLE_INTR(isrc->isrc_dev, isrc); 1099 PIC_TEARDOWN_INTR(isrc->isrc_dev, isrc, res, data); 1100 isrc_update_name(isrc, NULL); 1101 mtx_unlock(&isrc_table_lock); 1102 return (0); 1103 } 1104 #endif 1105 if (isrc != intr_handler_source(cookie)) 1106 return (EINVAL); 1107 1108 error = intr_event_remove_handler(cookie); 1109 if (error == 0) { 1110 mtx_lock(&isrc_table_lock); 1111 isrc->isrc_handlers--; 1112 if (isrc->isrc_handlers == 0) 1113 PIC_DISABLE_INTR(isrc->isrc_dev, isrc); 1114 PIC_TEARDOWN_INTR(isrc->isrc_dev, isrc, res, data); 1115 intrcnt_updatename(isrc); 1116 mtx_unlock(&isrc_table_lock); 1117 } 1118 return (error); 1119 } 1120 1121 int 1122 intr_describe_irq(device_t dev, struct resource *res, void *cookie, 1123 const char *descr) 1124 { 1125 int error; 1126 struct intr_irqsrc *isrc; 1127 u_int res_id; 1128 1129 KASSERT(rman_get_start(res) == rman_get_end(res), 1130 ("%s: more interrupts in resource", __func__)); 1131 1132 res_id = (u_int)rman_get_start(res); 1133 isrc = intr_map_get_isrc(res_id); 1134 if (isrc == NULL || isrc->isrc_handlers == 0) 1135 return (EINVAL); 1136 #ifdef INTR_SOLO 1137 if (isrc->isrc_filter != NULL) { 1138 if (isrc != cookie) 1139 return (EINVAL); 1140 1141 mtx_lock(&isrc_table_lock); 1142 isrc_update_name(isrc, descr); 1143 mtx_unlock(&isrc_table_lock); 1144 return (0); 1145 } 1146 #endif 1147 error = intr_event_describe_handler(isrc->isrc_event, cookie, descr); 1148 if (error == 0) { 1149 mtx_lock(&isrc_table_lock); 1150 intrcnt_updatename(isrc); 1151 mtx_unlock(&isrc_table_lock); 1152 } 1153 return (error); 1154 } 1155 1156 #ifdef SMP 1157 int 1158 intr_bind_irq(device_t dev, struct resource *res, int cpu) 1159 { 1160 struct intr_irqsrc *isrc; 1161 u_int res_id; 1162 1163 KASSERT(rman_get_start(res) == rman_get_end(res), 1164 ("%s: more interrupts in resource", __func__)); 1165 1166 res_id = (u_int)rman_get_start(res); 1167 isrc = intr_map_get_isrc(res_id); 1168 if (isrc == NULL || isrc->isrc_handlers == 0) 1169 return (EINVAL); 1170 #ifdef INTR_SOLO 1171 if (isrc->isrc_filter != NULL) 1172 return (intr_isrc_assign_cpu(isrc, cpu)); 1173 #endif 1174 return (intr_event_bind(isrc->isrc_event, cpu)); 1175 } 1176 1177 /* 1178 * Return the CPU that the next interrupt source should use. 1179 * For now just returns the next CPU according to round-robin. 1180 */ 1181 u_int 1182 intr_irq_next_cpu(u_int last_cpu, cpuset_t *cpumask) 1183 { 1184 u_int cpu; 1185 1186 KASSERT(!CPU_EMPTY(cpumask), ("%s: Empty CPU mask", __func__)); 1187 if (!irq_assign_cpu || mp_ncpus == 1) { 1188 cpu = PCPU_GET(cpuid); 1189 1190 if (CPU_ISSET(cpu, cpumask)) 1191 return (curcpu); 1192 1193 return (CPU_FFS(cpumask) - 1); 1194 } 1195 1196 do { 1197 last_cpu++; 1198 if (last_cpu > mp_maxid) 1199 last_cpu = 0; 1200 } while (!CPU_ISSET(last_cpu, cpumask)); 1201 return (last_cpu); 1202 } 1203 1204 #ifndef EARLY_AP_STARTUP 1205 /* 1206 * Distribute all the interrupt sources among the available 1207 * CPUs once the AP's have been launched. 1208 */ 1209 static void 1210 intr_irq_shuffle(void *arg __unused) 1211 { 1212 struct intr_irqsrc *isrc; 1213 u_int i; 1214 1215 if (mp_ncpus == 1) 1216 return; 1217 1218 mtx_lock(&isrc_table_lock); 1219 irq_assign_cpu = true; 1220 for (i = 0; i < NIRQ; i++) { 1221 isrc = irq_sources[i]; 1222 if (isrc == NULL || isrc->isrc_handlers == 0 || 1223 isrc->isrc_flags & (INTR_ISRCF_PPI | INTR_ISRCF_IPI)) 1224 continue; 1225 1226 if (isrc->isrc_event != NULL && 1227 isrc->isrc_flags & INTR_ISRCF_BOUND && 1228 isrc->isrc_event->ie_cpu != CPU_FFS(&isrc->isrc_cpu) - 1) 1229 panic("%s: CPU inconsistency", __func__); 1230 1231 if ((isrc->isrc_flags & INTR_ISRCF_BOUND) == 0) 1232 CPU_ZERO(&isrc->isrc_cpu); /* start again */ 1233 1234 /* 1235 * We are in wicked position here if the following call fails 1236 * for bound ISRC. The best thing we can do is to clear 1237 * isrc_cpu so inconsistency with ie_cpu will be detectable. 1238 */ 1239 if (PIC_BIND_INTR(isrc->isrc_dev, isrc) != 0) 1240 CPU_ZERO(&isrc->isrc_cpu); 1241 } 1242 mtx_unlock(&isrc_table_lock); 1243 } 1244 SYSINIT(intr_irq_shuffle, SI_SUB_SMP, SI_ORDER_SECOND, intr_irq_shuffle, NULL); 1245 #endif /* !EARLY_AP_STARTUP */ 1246 1247 #else 1248 u_int 1249 intr_irq_next_cpu(u_int current_cpu, cpuset_t *cpumask) 1250 { 1251 1252 return (PCPU_GET(cpuid)); 1253 } 1254 #endif /* SMP */ 1255 1256 /* 1257 * Allocate memory for new intr_map_data structure. 1258 * Initialize common fields. 1259 */ 1260 struct intr_map_data * 1261 intr_alloc_map_data(enum intr_map_data_type type, size_t len, int flags) 1262 { 1263 struct intr_map_data *data; 1264 1265 data = malloc(len, M_INTRNG, flags); 1266 data->type = type; 1267 data->len = len; 1268 return (data); 1269 } 1270 1271 void intr_free_intr_map_data(struct intr_map_data *data) 1272 { 1273 1274 free(data, M_INTRNG); 1275 } 1276 1277 /* 1278 * Register a MSI/MSI-X interrupt controller 1279 */ 1280 int 1281 intr_msi_register(device_t dev, intptr_t xref) 1282 { 1283 struct intr_pic *pic; 1284 1285 if (dev == NULL) 1286 return (EINVAL); 1287 pic = pic_create(dev, xref, FLAG_MSI); 1288 if (pic == NULL) 1289 return (ENOMEM); 1290 1291 debugf("PIC %p registered for %s <dev %p, xref %jx>\n", pic, 1292 device_get_nameunit(dev), dev, (uintmax_t)xref); 1293 return (0); 1294 } 1295 1296 int 1297 intr_alloc_msi(device_t pci, device_t child, intptr_t xref, int count, 1298 int maxcount, int *irqs) 1299 { 1300 #ifdef IOMMU 1301 struct iommu_domain *domain; 1302 #endif 1303 struct intr_irqsrc **isrc; 1304 struct intr_pic *pic; 1305 device_t pdev; 1306 struct intr_map_data_msi *msi; 1307 int err, i; 1308 1309 pic = pic_lookup(NULL, xref, FLAG_MSI); 1310 if (pic == NULL) 1311 return (ESRCH); 1312 1313 KASSERT((pic->pic_flags & FLAG_TYPE_MASK) == FLAG_MSI, 1314 ("%s: Found a non-MSI controller: %s", __func__, 1315 device_get_name(pic->pic_dev))); 1316 1317 #ifdef IOMMU 1318 /* 1319 * If this is the first time we have used this context ask the 1320 * interrupt controller to map memory the msi source will need. 1321 */ 1322 err = MSI_IOMMU_INIT(pic->pic_dev, child, &domain); 1323 if (err != 0) 1324 return (err); 1325 #endif 1326 1327 isrc = malloc(sizeof(*isrc) * count, M_INTRNG, M_WAITOK); 1328 err = MSI_ALLOC_MSI(pic->pic_dev, child, count, maxcount, &pdev, isrc); 1329 if (err != 0) { 1330 free(isrc, M_INTRNG); 1331 return (err); 1332 } 1333 1334 for (i = 0; i < count; i++) { 1335 #ifdef IOMMU 1336 isrc[i]->isrc_iommu = domain; 1337 #endif 1338 msi = (struct intr_map_data_msi *)intr_alloc_map_data( 1339 INTR_MAP_DATA_MSI, sizeof(*msi), M_WAITOK | M_ZERO); 1340 msi-> isrc = isrc[i]; 1341 1342 irqs[i] = intr_map_irq(pic->pic_dev, xref, 1343 (struct intr_map_data *)msi); 1344 } 1345 free(isrc, M_INTRNG); 1346 1347 return (err); 1348 } 1349 1350 int 1351 intr_release_msi(device_t pci, device_t child, intptr_t xref, int count, 1352 int *irqs) 1353 { 1354 struct intr_irqsrc **isrc; 1355 struct intr_pic *pic; 1356 struct intr_map_data_msi *msi; 1357 int i, err; 1358 1359 pic = pic_lookup(NULL, xref, FLAG_MSI); 1360 if (pic == NULL) 1361 return (ESRCH); 1362 1363 KASSERT((pic->pic_flags & FLAG_TYPE_MASK) == FLAG_MSI, 1364 ("%s: Found a non-MSI controller: %s", __func__, 1365 device_get_name(pic->pic_dev))); 1366 1367 isrc = malloc(sizeof(*isrc) * count, M_INTRNG, M_WAITOK); 1368 1369 for (i = 0; i < count; i++) { 1370 msi = (struct intr_map_data_msi *) 1371 intr_map_get_map_data(irqs[i]); 1372 KASSERT(msi->hdr.type == INTR_MAP_DATA_MSI, 1373 ("%s: irq %d map data is not MSI", __func__, 1374 irqs[i])); 1375 isrc[i] = msi->isrc; 1376 } 1377 1378 err = MSI_RELEASE_MSI(pic->pic_dev, child, count, isrc); 1379 1380 for (i = 0; i < count; i++) { 1381 if (isrc[i] != NULL) 1382 intr_unmap_irq(irqs[i]); 1383 } 1384 1385 free(isrc, M_INTRNG); 1386 return (err); 1387 } 1388 1389 int 1390 intr_alloc_msix(device_t pci, device_t child, intptr_t xref, int *irq) 1391 { 1392 #ifdef IOMMU 1393 struct iommu_domain *domain; 1394 #endif 1395 struct intr_irqsrc *isrc; 1396 struct intr_pic *pic; 1397 device_t pdev; 1398 struct intr_map_data_msi *msi; 1399 int err; 1400 1401 pic = pic_lookup(NULL, xref, FLAG_MSI); 1402 if (pic == NULL) 1403 return (ESRCH); 1404 1405 KASSERT((pic->pic_flags & FLAG_TYPE_MASK) == FLAG_MSI, 1406 ("%s: Found a non-MSI controller: %s", __func__, 1407 device_get_name(pic->pic_dev))); 1408 1409 #ifdef IOMMU 1410 /* 1411 * If this is the first time we have used this context ask the 1412 * interrupt controller to map memory the msi source will need. 1413 */ 1414 err = MSI_IOMMU_INIT(pic->pic_dev, child, &domain); 1415 if (err != 0) 1416 return (err); 1417 #endif 1418 1419 err = MSI_ALLOC_MSIX(pic->pic_dev, child, &pdev, &isrc); 1420 if (err != 0) 1421 return (err); 1422 1423 #ifdef IOMMU 1424 isrc->isrc_iommu = domain; 1425 #endif 1426 msi = (struct intr_map_data_msi *)intr_alloc_map_data( 1427 INTR_MAP_DATA_MSI, sizeof(*msi), M_WAITOK | M_ZERO); 1428 msi->isrc = isrc; 1429 *irq = intr_map_irq(pic->pic_dev, xref, (struct intr_map_data *)msi); 1430 return (0); 1431 } 1432 1433 int 1434 intr_release_msix(device_t pci, device_t child, intptr_t xref, int irq) 1435 { 1436 struct intr_irqsrc *isrc; 1437 struct intr_pic *pic; 1438 struct intr_map_data_msi *msi; 1439 int err; 1440 1441 pic = pic_lookup(NULL, xref, FLAG_MSI); 1442 if (pic == NULL) 1443 return (ESRCH); 1444 1445 KASSERT((pic->pic_flags & FLAG_TYPE_MASK) == FLAG_MSI, 1446 ("%s: Found a non-MSI controller: %s", __func__, 1447 device_get_name(pic->pic_dev))); 1448 1449 msi = (struct intr_map_data_msi *) 1450 intr_map_get_map_data(irq); 1451 KASSERT(msi->hdr.type == INTR_MAP_DATA_MSI, 1452 ("%s: irq %d map data is not MSI", __func__, 1453 irq)); 1454 isrc = msi->isrc; 1455 if (isrc == NULL) { 1456 intr_unmap_irq(irq); 1457 return (EINVAL); 1458 } 1459 1460 err = MSI_RELEASE_MSIX(pic->pic_dev, child, isrc); 1461 intr_unmap_irq(irq); 1462 1463 return (err); 1464 } 1465 1466 int 1467 intr_map_msi(device_t pci, device_t child, intptr_t xref, int irq, 1468 uint64_t *addr, uint32_t *data) 1469 { 1470 struct intr_irqsrc *isrc; 1471 struct intr_pic *pic; 1472 int err; 1473 1474 pic = pic_lookup(NULL, xref, FLAG_MSI); 1475 if (pic == NULL) 1476 return (ESRCH); 1477 1478 KASSERT((pic->pic_flags & FLAG_TYPE_MASK) == FLAG_MSI, 1479 ("%s: Found a non-MSI controller: %s", __func__, 1480 device_get_name(pic->pic_dev))); 1481 1482 isrc = intr_map_get_isrc(irq); 1483 if (isrc == NULL) 1484 return (EINVAL); 1485 1486 err = MSI_MAP_MSI(pic->pic_dev, child, isrc, addr, data); 1487 1488 #ifdef IOMMU 1489 if (isrc->isrc_iommu != NULL) 1490 iommu_translate_msi(isrc->isrc_iommu, addr); 1491 #endif 1492 1493 return (err); 1494 } 1495 1496 void dosoftints(void); 1497 void 1498 dosoftints(void) 1499 { 1500 } 1501 1502 #ifdef SMP 1503 /* 1504 * Init interrupt controller on another CPU. 1505 */ 1506 void 1507 intr_pic_init_secondary(void) 1508 { 1509 1510 /* 1511 * QQQ: Only root PIC is aware of other CPUs ??? 1512 */ 1513 KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__)); 1514 1515 //mtx_lock(&isrc_table_lock); 1516 PIC_INIT_SECONDARY(intr_irq_root_dev); 1517 //mtx_unlock(&isrc_table_lock); 1518 } 1519 #endif 1520 1521 #ifdef DDB 1522 DB_SHOW_COMMAND(irqs, db_show_irqs) 1523 { 1524 u_int i, irqsum; 1525 u_long num; 1526 struct intr_irqsrc *isrc; 1527 1528 for (irqsum = 0, i = 0; i < NIRQ; i++) { 1529 isrc = irq_sources[i]; 1530 if (isrc == NULL) 1531 continue; 1532 1533 num = isrc->isrc_count != NULL ? isrc->isrc_count[0] : 0; 1534 db_printf("irq%-3u <%s>: cpu %02lx%s cnt %lu\n", i, 1535 isrc->isrc_name, isrc->isrc_cpu.__bits[0], 1536 isrc->isrc_flags & INTR_ISRCF_BOUND ? " (bound)" : "", num); 1537 irqsum += num; 1538 } 1539 db_printf("irq total %u\n", irqsum); 1540 } 1541 #endif 1542 1543 /* 1544 * Interrupt mapping table functions. 1545 * 1546 * Please, keep this part separately, it can be transformed to 1547 * extension of standard resources. 1548 */ 1549 struct intr_map_entry 1550 { 1551 device_t dev; 1552 intptr_t xref; 1553 struct intr_map_data *map_data; 1554 struct intr_irqsrc *isrc; 1555 /* XXX TODO DISCONECTED PICs */ 1556 /*int flags */ 1557 }; 1558 1559 /* XXX Convert irq_map[] to dynamicaly expandable one. */ 1560 static struct intr_map_entry *irq_map[2 * NIRQ]; 1561 static int irq_map_count = nitems(irq_map); 1562 static int irq_map_first_free_idx; 1563 static struct mtx irq_map_lock; 1564 1565 static struct intr_irqsrc * 1566 intr_map_get_isrc(u_int res_id) 1567 { 1568 struct intr_irqsrc *isrc; 1569 1570 isrc = NULL; 1571 mtx_lock(&irq_map_lock); 1572 if (res_id < irq_map_count && irq_map[res_id] != NULL) 1573 isrc = irq_map[res_id]->isrc; 1574 mtx_unlock(&irq_map_lock); 1575 1576 return (isrc); 1577 } 1578 1579 static void 1580 intr_map_set_isrc(u_int res_id, struct intr_irqsrc *isrc) 1581 { 1582 1583 mtx_lock(&irq_map_lock); 1584 if (res_id < irq_map_count && irq_map[res_id] != NULL) 1585 irq_map[res_id]->isrc = isrc; 1586 mtx_unlock(&irq_map_lock); 1587 } 1588 1589 /* 1590 * Get a copy of intr_map_entry data 1591 */ 1592 static struct intr_map_data * 1593 intr_map_get_map_data(u_int res_id) 1594 { 1595 struct intr_map_data *data; 1596 1597 data = NULL; 1598 mtx_lock(&irq_map_lock); 1599 if (res_id >= irq_map_count || irq_map[res_id] == NULL) 1600 panic("Attempt to copy invalid resource id: %u\n", res_id); 1601 data = irq_map[res_id]->map_data; 1602 mtx_unlock(&irq_map_lock); 1603 1604 return (data); 1605 } 1606 1607 /* 1608 * Get a copy of intr_map_entry data 1609 */ 1610 static void 1611 intr_map_copy_map_data(u_int res_id, device_t *map_dev, intptr_t *map_xref, 1612 struct intr_map_data **data) 1613 { 1614 size_t len; 1615 1616 len = 0; 1617 mtx_lock(&irq_map_lock); 1618 if (res_id >= irq_map_count || irq_map[res_id] == NULL) 1619 panic("Attempt to copy invalid resource id: %u\n", res_id); 1620 if (irq_map[res_id]->map_data != NULL) 1621 len = irq_map[res_id]->map_data->len; 1622 mtx_unlock(&irq_map_lock); 1623 1624 if (len == 0) 1625 *data = NULL; 1626 else 1627 *data = malloc(len, M_INTRNG, M_WAITOK | M_ZERO); 1628 mtx_lock(&irq_map_lock); 1629 if (irq_map[res_id] == NULL) 1630 panic("Attempt to copy invalid resource id: %u\n", res_id); 1631 if (len != 0) { 1632 if (len != irq_map[res_id]->map_data->len) 1633 panic("Resource id: %u has changed.\n", res_id); 1634 memcpy(*data, irq_map[res_id]->map_data, len); 1635 } 1636 *map_dev = irq_map[res_id]->dev; 1637 *map_xref = irq_map[res_id]->xref; 1638 mtx_unlock(&irq_map_lock); 1639 } 1640 1641 /* 1642 * Allocate and fill new entry in irq_map table. 1643 */ 1644 u_int 1645 intr_map_irq(device_t dev, intptr_t xref, struct intr_map_data *data) 1646 { 1647 u_int i; 1648 struct intr_map_entry *entry; 1649 1650 /* Prepare new entry first. */ 1651 entry = malloc(sizeof(*entry), M_INTRNG, M_WAITOK | M_ZERO); 1652 1653 entry->dev = dev; 1654 entry->xref = xref; 1655 entry->map_data = data; 1656 entry->isrc = NULL; 1657 1658 mtx_lock(&irq_map_lock); 1659 for (i = irq_map_first_free_idx; i < irq_map_count; i++) { 1660 if (irq_map[i] == NULL) { 1661 irq_map[i] = entry; 1662 irq_map_first_free_idx = i + 1; 1663 mtx_unlock(&irq_map_lock); 1664 return (i); 1665 } 1666 } 1667 mtx_unlock(&irq_map_lock); 1668 1669 /* XXX Expand irq_map table */ 1670 panic("IRQ mapping table is full."); 1671 } 1672 1673 /* 1674 * Remove and free mapping entry. 1675 */ 1676 void 1677 intr_unmap_irq(u_int res_id) 1678 { 1679 struct intr_map_entry *entry; 1680 1681 mtx_lock(&irq_map_lock); 1682 if ((res_id >= irq_map_count) || (irq_map[res_id] == NULL)) 1683 panic("Attempt to unmap invalid resource id: %u\n", res_id); 1684 entry = irq_map[res_id]; 1685 irq_map[res_id] = NULL; 1686 irq_map_first_free_idx = res_id; 1687 mtx_unlock(&irq_map_lock); 1688 intr_free_intr_map_data(entry->map_data); 1689 free(entry, M_INTRNG); 1690 } 1691 1692 /* 1693 * Clone mapping entry. 1694 */ 1695 u_int 1696 intr_map_clone_irq(u_int old_res_id) 1697 { 1698 device_t map_dev; 1699 intptr_t map_xref; 1700 struct intr_map_data *data; 1701 1702 intr_map_copy_map_data(old_res_id, &map_dev, &map_xref, &data); 1703 return (intr_map_irq(map_dev, map_xref, data)); 1704 } 1705 1706 static void 1707 intr_map_init(void *dummy __unused) 1708 { 1709 1710 mtx_init(&irq_map_lock, "intr map table", NULL, MTX_DEF); 1711 } 1712 SYSINIT(intr_map_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_map_init, NULL); 1713