xref: /freebsd/sys/isa/pnpreg.h (revision 6990ffd8a95caaba6858ad44ff1b3157d1efba8f)
1 /*
2  * Copyright (c) 1996, Sujal M. Patel
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. All advertising materials mentioning features or use of this software
14  *    must display the following acknowledgement:
15  *      This product includes software developed by Sujal M. Patel
16  * 4. Neither the name of the author nor the names of any co-contributors
17  *    may be used to endorse or promote products derived from this software
18  *    without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30  * SUCH DAMAGE.
31  *
32  *	$FreeBSD$
33  *      from: pnp.h,v 1.7 1998/09/13 22:15:44 eivind Exp
34  */
35 
36 #ifndef _ISA_PNPREG_H_
37 #define _ISA_PNPREG_H_
38 
39 /* Maximum Number of PnP Devices.  8 should be plenty */
40 #define PNP_MAX_CARDS 8
41 
42 #if 0
43 /*
44  * the following is the maximum number of PnP Logical devices that
45  * userconfig can handle.
46  */
47 #define MAX_PNP_LDN	20
48 #endif
49 
50 /* Static ports to access PnP state machine */
51 #ifdef PC98
52 #define _PNP_ADDRESS		0x259
53 #define _PNP_WRITE_DATA		0xa59
54 #else
55 #define _PNP_ADDRESS		0x279
56 #define _PNP_WRITE_DATA		0xa79
57 #endif
58 
59 /* PnP Registers.  Write to ADDRESS and then use WRITE/READ_DATA */
60 #define PNP_SET_RD_DATA		0x00
61 	/***
62 	Writing to this location modifies the address of the port used for
63 	reading from the Plug and Play ISA cards.   Bits[7:0] become I/O
64 	read port address bits[9:2].  Reads from this register are ignored.
65 	***/
66 
67 #define PNP_SERIAL_ISOLATION	0x01
68 	/***
69 	A read to this register causes a Plug and Play cards in the Isolation
70 	state to compare one bit of the boards ID.
71 	This register is read only.
72 	***/
73 
74 #define	PNP_CONFIG_CONTROL	0x02
75 #define PNP_CONFIG_CONTROL_RESET_CSN	0x04
76 #define PNP_CONFIG_CONTROL_WAIT_FOR_KEY	0x02
77 #define PNP_CONFIG_CONTROL_RESET	0x01
78 	/***
79 	Bit[2]  Reset CSN to 0
80 	Bit[1]  Return to the Wait for Key state
81 	Bit[0]  Reset all logical devices and restore configuration
82 		registers to their power-up values.
83 
84 	A write to bit[0] of this register performs a reset function on
85 	all logical devices.  This resets the contents of configuration
86 	registers to  their default state.  All card's logical devices
87 	enter their default state and the CSN is preserved.
88 
89 	A write to bit[1] of this register causes all cards to enter the
90 	Wait for Key state but all CSNs are preserved and logical devices
91 	are not affected.
92 
93 	A write to bit[2] of this register causes all cards to reset their
94 	CSN to zero .
95 
96 	This register is write-only.  The values are not sticky, that is,
97 	hardware will automatically clear them and there is no need for
98 	software to clear the bits.
99 	***/
100 
101 #define PNP_WAKE		0x03
102 	/***
103 	A write to this port will cause all cards that have a CSN that
104 	matches the write data[7:0] to go from the Sleep state to the either
105 	the Isolation state if the write data for this command is zero or
106 	the Config state if the write data is not zero.  Additionally, the
107 	pointer to the byte-serial device is reset.  This register is
108 	writeonly.
109 	***/
110 
111 #define	PNP_RESOURCE_DATA	0x04
112 	/***
113 	A read from this address reads the next byte of resource information.
114 	The Status register must be polled until bit[0] is set before this
115 	register may be read.  This register is read only.
116 	***/
117 
118 #define PNP_STATUS		0x05
119 	/***
120 	Bit[0] when set indicates it is okay to read the next data byte
121 	from the Resource Data register.  This register is readonly.
122 	***/
123 
124 #define PNP_SET_CSN		0x06
125 	/***
126 	A write to this port sets a card's CSN.  The CSN is a value uniquely
127 	assigned to each ISA card after the serial identification process
128 	so that each card may be individually selected during a Wake[CSN]
129 	command. This register is read/write.
130 	***/
131 
132 #define PNP_SET_LDN		0x07
133 	/***
134 	Selects the current logical device.  All reads and writes of memory,
135 	I/O, interrupt and DMA configuration information access the registers
136 	of the logical device written here.  In addition, the I/O Range
137 	Check and Activate  commands operate only on the selected logical
138 	device.  This register is read/write. If a card has only 1 logical
139 	device, this location should be a read-only value of 0x00.
140 	***/
141 
142 /*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/
143 /*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/
144 
145 #define PNP_ACTIVATE		0x30
146 	/***
147 	For each logical device there is one activate register that controls
148 	whether or not the logical device is active on the ISA bus.  Bit[0],
149 	if set, activates the logical device.  Bits[7:1] are reserved and
150 	must return 0 on reads.  This is a read/write register. Before a
151 	logical device is activated, I/O range check must be disabled.
152 	***/
153 
154 #define PNP_IO_RANGE_CHECK	0x31
155 #define PNP_IO_RANGE_CHECK_ENABLE	0x02
156 #define PNP_IO_RANGE_CHECK_READ_AS_55	0x01
157 	/***
158 	This register is used to perform a conflict check on the I/O port
159 	range programmed for use by a logical device.
160 
161 	Bit[7:2]  Reserved and must return 0 on reads
162 	Bit[1]    Enable I/O Range check, if set then I/O Range Check
163 	is enabled. I/O range check is only valid when the logical
164 	device is inactive.
165 
166 	Bit[0], if set, forces the logical device to respond to I/O reads
167 	of the logical device's assigned I/O range with a 0x55 when I/O
168 	range check is in operation.  If clear, the logical device drives
169 	0xAA.  This register is read/write.
170 	***/
171 
172 /*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/
173 /*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/
174 
175 #define PNP_MEM_BASE_HIGH(i)	(0x40 + 8*(i))
176 #define PNP_MEM_BASE_LOW(i)	(0x41 + 8*(i))
177 #define PNP_MEM_CONTROL(i)	(0x42 * 8*(i))
178 #define PNP_MEM_CONTROL_16BIT	0x2
179 #define PNP_MEM_CONTROL_LIMIT	0x1
180 #define PNP_MEM_RANGE_HIGH(i)	(0x43 + 8*(i))
181 #define PNP_MEM_RANGE_LOW(i)	(0x44 + 8*(i))
182 	/***
183 	Four memory resource registers per range, four ranges.
184 	Fill with 0 if no ranges are enabled.
185 
186 	Offset 0:	RW Memory base address bits[23:16]
187 	Offset 1:	RW Memory base address bits[15:8]
188 	Offset 2:	Memory control
189 	    Bit[1] specifies 8/16-bit control.  This bit is set to indicate
190 	    16-bit memory, and cleared to indicate 8-bit memory.
191 	    Bit[0], if cleared, indicates the next field can be used as a range
192 	    length for decode (implies range length and base alignment of memory
193 	    descriptor are equal).
194 	    Bit[0], if set, indicates the next field is the upper limit for
195 	    the address. -  - Bit[0] is read-only.
196 	Offset 3:	RW upper limit or range len, bits[23:16]
197 	Offset 4:	RW upper limit or range len, bits[15:8]
198 	Offset 5-Offset 7: filler, unused.
199 	***/
200 
201 #define PNP_IO_BASE_HIGH(i)	(0x60 + 2*(i))
202 #define PNP_IO_BASE_LOW(i)	(0x61 + 2*(i))
203 	/***
204 	Eight ranges, two bytes per range.
205 	Offset 0:		I/O port base address bits[15:8]
206 	Offset 1:		I/O port base address bits[7:0]
207 	***/
208 
209 #define PNP_IRQ_LEVEL(i)	(0x70 + 2*(i))
210 #define PNP_IRQ_TYPE(i)		(0x71 + 2*(i))
211 	/***
212 	Two entries, two bytes per entry.
213 	Offset 0:	RW interrupt level (1..15, 0=unused).
214 	Offset 1:	Bit[1]: level(1:hi, 0:low),
215 			Bit[0]: type (1:level, 0:edge)
216 		byte 1 can be readonly if 1 type of int is used.
217 	***/
218 
219 #define PNP_DMA_CHANNEL(i)	(0x74 + 1*(i))
220 	/***
221 	Two entries, one byte per entry. Bits[2:0] select
222 	which DMA channel is in use for DMA 0.  Zero selects DMA channel
223 	0, seven selects DMA channel 7. DMA channel 4, the cascade channel
224 	is used to indicate no DMA channel is active.
225 	***/
226 
227 /*** 32-bit memory accesses are at 0x76 ***/
228 
229 /* Macros to parse Resource IDs */
230 #define PNP_RES_TYPE(a)		(a >> 7)
231 #define PNP_SRES_NUM(a)		(a >> 3)
232 #define PNP_SRES_LEN(a)		(a & 0x07)
233 #define PNP_LRES_NUM(a)		(a & 0x7f)
234 
235 /* Small Resource Item names */
236 #define PNP_TAG_VERSION		0x1
237 #define PNP_TAG_LOGICAL_DEVICE	0x2
238 #define PNP_TAG_COMPAT_DEVICE	0x3
239 #define PNP_TAG_IRQ_FORMAT	0x4
240 #define PNP_TAG_DMA_FORMAT	0x5
241 #define PNP_TAG_START_DEPENDANT	0x6
242 #define PNP_TAG_END_DEPENDANT	0x7
243 #define PNP_TAG_IO_RANGE	0x8
244 #define PNP_TAG_IO_FIXED	0x9
245 #define PNP_TAG_RESERVED	0xa-0xd
246 #define PNP_TAG_VENDOR		0xe
247 #define PNP_TAG_END		0xf
248 
249 /* Large Resource Item names */
250 #define PNP_TAG_MEMORY_RANGE	0x1
251 #define PNP_TAG_ID_ANSI		0x2
252 #define PNP_TAG_ID_UNICODE	0x3
253 #define PNP_TAG_LARGE_VENDOR	0x4
254 #define PNP_TAG_MEMORY32_RANGE	0x5
255 #define PNP_TAG_MEMORY32_FIXED	0x6
256 #define PNP_TAG_LARGE_RESERVED	0x7-0x7f
257 
258 #endif /* !_ISA_PNPREG_H_ */
259