1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2005 TAKAHASHI Yoshihiro. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _ISA_ISA_DMAREG_H_ 29 #define _ISA_ISA_DMAREG_H_ 30 31 #include <dev/ic/i8237.h> 32 33 #define IO_DMA1 0x00 /* 8237A DMA Controller #1 */ 34 #define IO_DMA2 0xC0 /* 8237A DMA Controller #2 */ 35 36 /* 37 * Register definitions for DMA controller 1 (channels 0..3): 38 */ 39 #define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 40 #define DMA1_STATUS (IO_DMA1 + 1*8) /* status register */ 41 #define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 42 #define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 43 #define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 44 #define DMA1_RESET (IO_DMA1 + 1*13) /* reset */ 45 46 /* 47 * Register definitions for DMA controller 2 (channels 4..7): 48 */ 49 #define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 50 #define DMA2_STATUS (IO_DMA2 + 2*8) /* status register */ 51 #define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 52 #define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 53 #define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 54 #define DMA2_RESET (IO_DMA2 + 2*13) /* reset */ 55 56 #endif /* _ISA_ISA_DMAREG_H_ */ 57