1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> /* XXX trim includes */ 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sysctl.h> 41 #include <vm/vm.h> 42 #include <vm/pmap.h> 43 #include <machine/md_var.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <isa/isavar.h> 47 #include <machine/pci_cfgreg.h> 48 #include <machine/segments.h> 49 #include <machine/pc/bios.h> 50 51 #ifdef APIC_IO 52 #include <machine/smp.h> 53 #endif /* APIC_IO */ 54 55 #include "pcib_if.h" 56 57 #define PRVERB(a) do { \ 58 if (bootverbose) \ 59 printf a ; \ 60 } while(0) 61 62 static int cfgmech; 63 static int devmax; 64 65 static int pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq); 66 static int pci_cfgintr_unique(struct PIR_entry *pe, int pin); 67 static int pci_cfgintr_linked(struct PIR_entry *pe, int pin); 68 static int pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin); 69 static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin); 70 71 static void pci_print_irqmask(u_int16_t irqs); 72 static void pci_print_route_table(struct PIR_table *prt, int size); 73 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes); 74 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes); 75 static int pcireg_cfgopen(void); 76 77 static struct PIR_table *pci_route_table; 78 static int pci_route_count; 79 80 static struct mtx pcicfg_mtx; 81 82 /* sysctl vars */ 83 SYSCTL_DECL(_hw_pci); 84 85 #ifdef PC98 86 #define PCI_IRQ_OVERRIDE_MASK 0x3e68 87 #else 88 #define PCI_IRQ_OVERRIDE_MASK 0xdef4 89 #endif 90 91 static uint32_t pci_irq_override_mask = PCI_IRQ_OVERRIDE_MASK; 92 TUNABLE_INT("hw.pci.irq_override_mask", &pci_irq_override_mask); 93 SYSCTL_INT(_hw_pci, OID_AUTO, irq_override_mask, CTLFLAG_RD, 94 &pci_irq_override_mask, PCI_IRQ_OVERRIDE_MASK, 95 "Mask of allowed irqs to try to route when it has no good clue about\n" 96 "which irqs it should use."); 97 98 99 /* 100 * Some BIOS writers seem to want to ignore the spec and put 101 * 0 in the intline rather than 255 to indicate none. Some use 102 * numbers in the range 128-254 to indicate something strange and 103 * apparently undocumented anywhere. Assume these are completely bogus 104 * and map them to 255, which means "none". 105 */ 106 static __inline__ int 107 pci_i386_map_intline(int line) 108 { 109 if (line == 0 || line >= 128) 110 return (PCI_INVALID_IRQ); 111 return (line); 112 } 113 114 static u_int16_t 115 pcibios_get_version(void) 116 { 117 struct bios_regs args; 118 119 if (PCIbios.ventry == 0) { 120 PRVERB(("pcibios: No call entry point\n")); 121 return (0); 122 } 123 args.eax = PCIBIOS_BIOS_PRESENT; 124 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) { 125 PRVERB(("pcibios: BIOS_PRESENT call failed\n")); 126 return (0); 127 } 128 if (args.edx != 0x20494350) { 129 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n")); 130 return (0); 131 } 132 return (args.ebx & 0xffff); 133 } 134 135 /* 136 * Initialise access to PCI configuration space 137 */ 138 int 139 pci_cfgregopen(void) 140 { 141 static int opened = 0; 142 u_long sigaddr; 143 static struct PIR_table *pt; 144 u_int16_t v; 145 u_int8_t ck, *cv; 146 int i; 147 148 if (opened) 149 return(1); 150 151 if (pcireg_cfgopen() == 0) 152 return(0); 153 154 v = pcibios_get_version(); 155 if (v > 0) 156 printf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8, 157 v & 0xff); 158 159 /* 160 * Look for the interrupt routing table. 161 * 162 * We use PCI BIOS's PIR table if it's available $PIR is the 163 * standard way to do this. Sadly, some machines are not 164 * standards conforming and have _PIR instead. We shrug and cope 165 * by looking for both. 166 */ 167 if (pcibios_get_version() >= 0x0210 && pt == NULL) { 168 sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0); 169 if (sigaddr == 0) 170 sigaddr = bios_sigsearch(0, "_PIR", 4, 16, 0); 171 if (sigaddr != 0) { 172 pt = (struct PIR_table *)(uintptr_t) 173 BIOS_PADDRTOVADDR(sigaddr); 174 for (cv = (u_int8_t *)pt, ck = 0, i = 0; 175 i < (pt->pt_header.ph_length); i++) { 176 ck += cv[i]; 177 } 178 if (ck == 0 && pt->pt_header.ph_length > 179 sizeof(struct PIR_header)) { 180 pci_route_table = pt; 181 pci_route_count = (pt->pt_header.ph_length - 182 sizeof(struct PIR_header)) / 183 sizeof(struct PIR_entry); 184 printf("Using $PIR table, %d entries at %p\n", 185 pci_route_count, pci_route_table); 186 if (bootverbose) 187 pci_print_route_table(pci_route_table, 188 pci_route_count); 189 } 190 } 191 } 192 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 193 opened = 1; 194 return(1); 195 } 196 197 /* 198 * Read configuration space register 199 */ 200 u_int32_t 201 pci_cfgregread(int bus, int slot, int func, int reg, int bytes) 202 { 203 uint32_t line; 204 #ifdef APIC_IO 205 uint32_t pin; 206 207 /* 208 * If we are using the APIC, the contents of the intline 209 * register will probably be wrong (since they are set up for 210 * use with the PIC. Rather than rewrite these registers 211 * (maybe that would be smarter) we trap attempts to read them 212 * and translate to our private vector numbers. 213 */ 214 if ((reg == PCIR_INTLINE) && (bytes == 1)) { 215 216 pin = pcireg_cfgread(bus, slot, func, PCIR_INTPIN, 1); 217 line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1); 218 219 if (pin != 0) { 220 int airq; 221 222 airq = pci_apic_irq(bus, slot, pin); 223 if (airq >= 0) { 224 /* PCI specific entry found in MP table */ 225 if (airq != line) 226 undirect_pci_irq(line); 227 return(airq); 228 } else { 229 /* 230 * PCI interrupts might be redirected 231 * to the ISA bus according to some MP 232 * tables. Use the same methods as 233 * used by the ISA devices devices to 234 * find the proper IOAPIC int pin. 235 */ 236 airq = isa_apic_irq(line); 237 if ((airq >= 0) && (airq != line)) { 238 /* XXX: undirect_pci_irq() ? */ 239 undirect_isa_irq(line); 240 return(airq); 241 } 242 } 243 } 244 return(line); 245 } 246 #else 247 /* 248 * Some BIOS writers seem to want to ignore the spec and put 249 * 0 in the intline rather than 255 to indicate none. The rest of 250 * the code uses 255 as an invalid IRQ. 251 */ 252 if (reg == PCIR_INTLINE && bytes == 1) { 253 line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1); 254 return pci_i386_map_intline(line); 255 } 256 #endif /* APIC_IO */ 257 return(pcireg_cfgread(bus, slot, func, reg, bytes)); 258 } 259 260 /* 261 * Write configuration space register 262 */ 263 void 264 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) 265 { 266 267 pcireg_cfgwrite(bus, slot, func, reg, data, bytes); 268 } 269 270 /* 271 * Route a PCI interrupt 272 */ 273 int 274 pci_cfgintr(int bus, int device, int pin, int oldirq) 275 { 276 struct PIR_entry *pe; 277 int i, irq; 278 struct bios_regs args; 279 u_int16_t v; 280 int already = 0; 281 int errok = 0; 282 283 v = pcibios_get_version(); 284 if (v < 0x0210) { 285 PRVERB(( 286 "pci_cfgintr: BIOS %x.%02x doesn't support interrupt routing\n", 287 (v & 0xff00) >> 8, v & 0xff)); 288 return (PCI_INVALID_IRQ); 289 } 290 if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) || 291 (pin < 1) || (pin > 4)) 292 return(PCI_INVALID_IRQ); 293 294 /* 295 * Scan the entry table for a contender 296 */ 297 for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count; 298 i++, pe++) { 299 if ((bus != pe->pe_bus) || (device != pe->pe_device)) 300 continue; 301 /* 302 * A link of 0 means that this intpin is not connected to 303 * any other device's interrupt pins and is not connected to 304 * any of the Interrupt Router's interrupt pins, so we can't 305 * route it. 306 */ 307 if (pe->pe_intpin[pin - 1].link == 0) 308 continue; 309 310 if (pci_cfgintr_valid(pe, pin, oldirq)) { 311 printf("pci_cfgintr: %d:%d INT%c BIOS irq %d\n", bus, 312 device, 'A' + pin - 1, oldirq); 313 return (oldirq); 314 } 315 316 /* 317 * We try to find a linked interrupt, then we look to see 318 * if the interrupt is uniquely routed, then we look for 319 * a virgin interrupt. The virgin interrupt should return 320 * an interrupt we can route, but if that fails, maybe we 321 * should try harder to route a different interrupt. 322 * However, experience has shown that that's rarely the 323 * failure mode we see. 324 */ 325 irq = pci_cfgintr_linked(pe, pin); 326 if (irq != PCI_INVALID_IRQ) 327 already = 1; 328 if (irq == PCI_INVALID_IRQ) { 329 irq = pci_cfgintr_unique(pe, pin); 330 if (irq != PCI_INVALID_IRQ) 331 errok = 1; 332 } 333 if (irq == PCI_INVALID_IRQ) 334 irq = pci_cfgintr_virgin(pe, pin); 335 if (irq == PCI_INVALID_IRQ) 336 break; 337 338 /* 339 * Ask the BIOS to route the interrupt. If we picked an 340 * interrupt that failed, we should really try other 341 * choices that the BIOS offers us. 342 * 343 * For uniquely routed interrupts, we need to try 344 * to route them on some machines. Yet other machines 345 * fail to route, so we have to pretend that in that 346 * case it worked. Isn't pc hardware fun? 347 * 348 * NOTE: if we want to whack hardware to do this, then 349 * I think the right way to do that would be to have 350 * bridge drivers that do this. I'm not sure that the 351 * $PIR table would be valid for those interrupt 352 * routers. 353 */ 354 args.eax = PCIBIOS_ROUTE_INTERRUPT; 355 args.ebx = (bus << 8) | (device << 3); 356 /* pin value is 0xa - 0xd */ 357 args.ecx = (irq << 8) | (0xa + pin - 1); 358 if (!already && 359 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)) && 360 !errok) { 361 PRVERB(("pci_cfgintr: ROUTE_INTERRUPT failed.\n")); 362 return(PCI_INVALID_IRQ); 363 } 364 printf("pci_cfgintr: %d:%d INT%c routed to irq %d\n", bus, 365 device, 'A' + pin - 1, irq); 366 return(irq); 367 } 368 369 PRVERB(("pci_cfgintr: can't route an interrupt to %d:%d INT%c\n", bus, 370 device, 'A' + pin - 1)); 371 return(PCI_INVALID_IRQ); 372 } 373 374 /* 375 * Check to see if an existing IRQ setting is valid. 376 */ 377 static int 378 pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq) 379 { 380 uint32_t irqmask; 381 382 if (!PCI_INTERRUPT_VALID(irq)) 383 return (0); 384 irqmask = pe->pe_intpin[pin - 1].irqs; 385 if (irqmask & (1 << irq)) { 386 PRVERB(("pci_cfgintr_valid: BIOS irq %d is valid\n", irq)); 387 return (1); 388 } 389 return (0); 390 } 391 392 /* 393 * Look to see if the routing table claims this pin is uniquely routed. 394 */ 395 static int 396 pci_cfgintr_unique(struct PIR_entry *pe, int pin) 397 { 398 int irq; 399 uint32_t irqmask; 400 401 irqmask = pe->pe_intpin[pin - 1].irqs; 402 if (irqmask != 0 && powerof2(irqmask)) { 403 irq = ffs(irqmask) - 1; 404 PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq)); 405 return(irq); 406 } 407 return(PCI_INVALID_IRQ); 408 } 409 410 /* 411 * Look for another device which shares the same link byte and 412 * already has a unique IRQ, or which has had one routed already. 413 */ 414 static int 415 pci_cfgintr_linked(struct PIR_entry *pe, int pin) 416 { 417 struct PIR_entry *oe; 418 struct PIR_intpin *pi; 419 int i, j, irq; 420 421 /* 422 * Scan table slots. 423 */ 424 for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count; 425 i++, oe++) { 426 /* scan interrupt pins */ 427 for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) { 428 429 /* don't look at the entry we're trying to match */ 430 if ((pe == oe) && (i == (pin - 1))) 431 continue; 432 /* compare link bytes */ 433 if (pi->link != pe->pe_intpin[pin - 1].link) 434 continue; 435 /* link destination mapped to a unique interrupt? */ 436 if (pi->irqs != 0 && powerof2(pi->irqs)) { 437 irq = ffs(pi->irqs) - 1; 438 PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n", 439 pi->link, irq)); 440 return(irq); 441 } 442 443 /* 444 * look for the real PCI device that matches this 445 * table entry 446 */ 447 irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device, 448 j + 1, pin); 449 if (irq != PCI_INVALID_IRQ) 450 return(irq); 451 } 452 } 453 return(PCI_INVALID_IRQ); 454 } 455 456 /* 457 * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and 458 * see if it has already been assigned an interrupt. 459 */ 460 static int 461 pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin) 462 { 463 devclass_t pci_devclass; 464 device_t *pci_devices; 465 int pci_count; 466 device_t *pci_children; 467 int pci_childcount; 468 device_t *busp, *childp; 469 int i, j, irq; 470 471 /* 472 * Find all the PCI busses. 473 */ 474 pci_count = 0; 475 if ((pci_devclass = devclass_find("pci")) != NULL) 476 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 477 478 /* 479 * Scan all the PCI busses/devices looking for this one. 480 */ 481 irq = PCI_INVALID_IRQ; 482 for (i = 0, busp = pci_devices; (i < pci_count) && (irq == PCI_INVALID_IRQ); 483 i++, busp++) { 484 pci_childcount = 0; 485 device_get_children(*busp, &pci_children, &pci_childcount); 486 487 for (j = 0, childp = pci_children; j < pci_childcount; j++, 488 childp++) { 489 if ((pci_get_bus(*childp) == bus) && 490 (pci_get_slot(*childp) == device) && 491 (pci_get_intpin(*childp) == matchpin)) { 492 irq = pci_i386_map_intline(pci_get_irq(*childp)); 493 if (irq != PCI_INVALID_IRQ) 494 PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n", 495 pe->pe_intpin[pin - 1].link, irq, 496 pci_get_bus(*childp), 497 pci_get_slot(*childp), 498 pci_get_function(*childp))); 499 break; 500 } 501 } 502 if (pci_children != NULL) 503 free(pci_children, M_TEMP); 504 } 505 if (pci_devices != NULL) 506 free(pci_devices, M_TEMP); 507 return(irq); 508 } 509 510 /* 511 * Pick a suitable IRQ from those listed as routable to this device. 512 */ 513 static int 514 pci_cfgintr_virgin(struct PIR_entry *pe, int pin) 515 { 516 int irq, ibit; 517 518 /* 519 * first scan the set of PCI-only interrupts and see if any of these 520 * are routable 521 */ 522 for (irq = 0; irq < 16; irq++) { 523 ibit = (1 << irq); 524 525 /* can we use this interrupt? */ 526 if ((pci_route_table->pt_header.ph_pci_irqs & ibit) && 527 (pe->pe_intpin[pin - 1].irqs & ibit)) { 528 PRVERB(("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq)); 529 return(irq); 530 } 531 } 532 533 /* life is tough, so just pick an interrupt */ 534 for (irq = 0; irq < 16; irq++) { 535 ibit = (1 << irq); 536 if ((ibit & pci_irq_override_mask) == 0) 537 continue; 538 if (pe->pe_intpin[pin - 1].irqs & ibit) { 539 PRVERB(("pci_cfgintr_virgin: using routable interrupt %d\n", irq)); 540 return(irq); 541 } 542 } 543 return(PCI_INVALID_IRQ); 544 } 545 546 static void 547 pci_print_irqmask(u_int16_t irqs) 548 { 549 int i, first; 550 551 if (irqs == 0) { 552 printf("none"); 553 return; 554 } 555 first = 1; 556 for (i = 0; i < 16; i++, irqs >>= 1) 557 if (irqs & 1) { 558 if (!first) 559 printf(" "); 560 else 561 first = 0; 562 printf("%d", i); 563 } 564 } 565 566 /* 567 * Dump the contents of a PCI BIOS Interrupt Routing Table to the console. 568 */ 569 static void 570 pci_print_route_table(struct PIR_table *prt, int size) 571 { 572 struct PIR_entry *entry; 573 struct PIR_intpin *intpin; 574 int i, pin; 575 576 printf("PCI-Only Interrupts: "); 577 pci_print_irqmask(prt->pt_header.ph_pci_irqs); 578 printf("\nLocation Bus Device Pin Link IRQs\n"); 579 entry = &prt->pt_entry[0]; 580 for (i = 0; i < size; i++, entry++) { 581 intpin = &entry->pe_intpin[0]; 582 for (pin = 0; pin < 4; pin++, intpin++) 583 if (intpin->link != 0) { 584 if (entry->pe_slot == 0) 585 printf("embedded "); 586 else 587 printf("slot %-3d ", entry->pe_slot); 588 printf(" %3d %3d %c 0x%02x ", 589 entry->pe_bus, entry->pe_device, 590 'A' + pin, intpin->link); 591 pci_print_irqmask(intpin->irqs); 592 printf("\n"); 593 } 594 } 595 } 596 597 /* 598 * See if any interrupts for a given PCI bus are routed in the PIR. Don't 599 * even bother looking if the BIOS doesn't support routing anyways. 600 */ 601 int 602 pci_probe_route_table(int bus) 603 { 604 int i; 605 u_int16_t v; 606 607 v = pcibios_get_version(); 608 if (v < 0x0210) 609 return (0); 610 for (i = 0; i < pci_route_count; i++) 611 if (pci_route_table->pt_entry[i].pe_bus == bus) 612 return (1); 613 return (0); 614 } 615 616 /* 617 * Configuration space access using direct register operations 618 */ 619 620 /* enable configuration space accesses and return data port address */ 621 static int 622 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes) 623 { 624 int dataport = 0; 625 626 if (bus <= PCI_BUSMAX 627 && slot < devmax 628 && func <= PCI_FUNCMAX 629 && reg <= PCI_REGMAX 630 && bytes != 3 631 && (unsigned) bytes <= 4 632 && (reg & (bytes - 1)) == 0) { 633 switch (cfgmech) { 634 case 1: 635 outl(CONF1_ADDR_PORT, (1 << 31) 636 | (bus << 16) | (slot << 11) 637 | (func << 8) | (reg & ~0x03)); 638 dataport = CONF1_DATA_PORT + (reg & 0x03); 639 break; 640 case 2: 641 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1)); 642 outb(CONF2_FORWARD_PORT, bus); 643 dataport = 0xc000 | (slot << 8) | reg; 644 break; 645 } 646 } 647 return (dataport); 648 } 649 650 /* disable configuration space accesses */ 651 static void 652 pci_cfgdisable(void) 653 { 654 switch (cfgmech) { 655 case 1: 656 outl(CONF1_ADDR_PORT, 0); 657 break; 658 case 2: 659 outb(CONF2_ENABLE_PORT, 0); 660 outb(CONF2_FORWARD_PORT, 0); 661 break; 662 } 663 } 664 665 static int 666 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes) 667 { 668 int data = -1; 669 int port; 670 671 mtx_lock_spin(&pcicfg_mtx); 672 port = pci_cfgenable(bus, slot, func, reg, bytes); 673 if (port != 0) { 674 switch (bytes) { 675 case 1: 676 data = inb(port); 677 break; 678 case 2: 679 data = inw(port); 680 break; 681 case 4: 682 data = inl(port); 683 break; 684 } 685 pci_cfgdisable(); 686 } 687 mtx_unlock_spin(&pcicfg_mtx); 688 return (data); 689 } 690 691 static void 692 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) 693 { 694 int port; 695 696 mtx_lock_spin(&pcicfg_mtx); 697 port = pci_cfgenable(bus, slot, func, reg, bytes); 698 if (port != 0) { 699 switch (bytes) { 700 case 1: 701 outb(port, data); 702 break; 703 case 2: 704 outw(port, data); 705 break; 706 case 4: 707 outl(port, data); 708 break; 709 } 710 pci_cfgdisable(); 711 } 712 mtx_unlock_spin(&pcicfg_mtx); 713 } 714 715 /* check whether the configuration mechanism has been correctly identified */ 716 static int 717 pci_cfgcheck(int maxdev) 718 { 719 uint32_t id, class; 720 uint8_t header; 721 uint8_t device; 722 int port; 723 724 if (bootverbose) 725 printf("pci_cfgcheck:\tdevice "); 726 727 for (device = 0; device < maxdev; device++) { 728 if (bootverbose) 729 printf("%d ", device); 730 731 port = pci_cfgenable(0, device, 0, 0, 4); 732 id = inl(port); 733 if (id == 0 || id == 0xffffffff) 734 continue; 735 736 port = pci_cfgenable(0, device, 0, 8, 4); 737 class = inl(port) >> 8; 738 if (bootverbose) 739 printf("[class=%06x] ", class); 740 if (class == 0 || (class & 0xf870ff) != 0) 741 continue; 742 743 port = pci_cfgenable(0, device, 0, 14, 1); 744 header = inb(port); 745 if (bootverbose) 746 printf("[hdr=%02x] ", header); 747 if ((header & 0x7e) != 0) 748 continue; 749 750 if (bootverbose) 751 printf("is there (id=%08x)\n", id); 752 753 pci_cfgdisable(); 754 return (1); 755 } 756 if (bootverbose) 757 printf("-- nothing found\n"); 758 759 pci_cfgdisable(); 760 return (0); 761 } 762 763 static int 764 pcireg_cfgopen(void) 765 { 766 uint32_t mode1res, oldval1; 767 uint8_t mode2res, oldval2; 768 769 oldval1 = inl(CONF1_ADDR_PORT); 770 771 if (bootverbose) { 772 printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n", 773 oldval1); 774 } 775 776 if ((oldval1 & CONF1_ENABLE_MSK) == 0) { 777 778 cfgmech = 1; 779 devmax = 32; 780 781 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK); 782 outb(CONF1_ADDR_PORT + 3, 0); 783 mode1res = inl(CONF1_ADDR_PORT); 784 outl(CONF1_ADDR_PORT, oldval1); 785 786 if (bootverbose) 787 printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n", 788 mode1res, CONF1_ENABLE_CHK); 789 790 if (mode1res) { 791 if (pci_cfgcheck(32)) 792 return (cfgmech); 793 } 794 795 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1); 796 mode1res = inl(CONF1_ADDR_PORT); 797 outl(CONF1_ADDR_PORT, oldval1); 798 799 if (bootverbose) 800 printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n", 801 mode1res, CONF1_ENABLE_CHK1); 802 803 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) { 804 if (pci_cfgcheck(32)) 805 return (cfgmech); 806 } 807 } 808 809 oldval2 = inb(CONF2_ENABLE_PORT); 810 811 if (bootverbose) { 812 printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n", 813 oldval2); 814 } 815 816 if ((oldval2 & 0xf0) == 0) { 817 818 cfgmech = 2; 819 devmax = 16; 820 821 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK); 822 mode2res = inb(CONF2_ENABLE_PORT); 823 outb(CONF2_ENABLE_PORT, oldval2); 824 825 if (bootverbose) 826 printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n", 827 mode2res, CONF2_ENABLE_CHK); 828 829 if (mode2res == CONF2_ENABLE_RES) { 830 if (bootverbose) 831 printf("pci_open(2a):\tnow trying mechanism 2\n"); 832 833 if (pci_cfgcheck(16)) 834 return (cfgmech); 835 } 836 } 837 838 cfgmech = 0; 839 devmax = 0; 840 return (cfgmech); 841 } 842 843