1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * Copyright (c) 2004, Scott Long <scottl@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_xbox.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/lock.h> 39 #include <sys/kernel.h> 40 #include <sys/mutex.h> 41 #include <sys/malloc.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/pci_cfgreg.h> 47 #include <machine/pc/bios.h> 48 49 #include <vm/vm.h> 50 #include <vm/vm_param.h> 51 #include <vm/vm_kern.h> 52 #include <vm/vm_extern.h> 53 #include <vm/pmap.h> 54 #include <machine/pmap.h> 55 56 #ifdef XBOX 57 #include <machine/xbox.h> 58 #endif 59 60 #define PRVERB(a) do { \ 61 if (bootverbose) \ 62 printf a ; \ 63 } while(0) 64 65 #define PCIE_CACHE 8 66 struct pcie_cfg_elem { 67 TAILQ_ENTRY(pcie_cfg_elem) elem; 68 vm_offset_t vapage; 69 vm_paddr_t papage; 70 }; 71 72 enum { 73 CFGMECH_NONE = 0, 74 CFGMECH_1, 75 CFGMECH_2, 76 CFGMECH_PCIE, 77 }; 78 79 SYSCTL_DECL(_hw_pci); 80 81 static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU]; 82 static uint64_t pcie_base; 83 static int pcie_minbus, pcie_maxbus; 84 static uint32_t pcie_badslots; 85 static int cfgmech; 86 static int devmax; 87 static struct mtx pcicfg_mtx; 88 static int mcfg_enable = 1; 89 SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0, 90 "Enable support for PCI-e memory mapped config access"); 91 92 static uint32_t pci_docfgregread(int bus, int slot, int func, int reg, 93 int bytes); 94 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes); 95 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes); 96 #ifndef XEN 97 static int pcireg_cfgopen(void); 98 #endif 99 static int pciereg_cfgread(int bus, unsigned slot, unsigned func, 100 unsigned reg, unsigned bytes); 101 static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func, 102 unsigned reg, int data, unsigned bytes); 103 104 /* 105 * Some BIOS writers seem to want to ignore the spec and put 106 * 0 in the intline rather than 255 to indicate none. Some use 107 * numbers in the range 128-254 to indicate something strange and 108 * apparently undocumented anywhere. Assume these are completely bogus 109 * and map them to 255, which means "none". 110 */ 111 static __inline int 112 pci_i386_map_intline(int line) 113 { 114 if (line == 0 || line >= 128) 115 return (PCI_INVALID_IRQ); 116 return (line); 117 } 118 119 #ifndef XEN 120 static u_int16_t 121 pcibios_get_version(void) 122 { 123 struct bios_regs args; 124 125 if (PCIbios.ventry == 0) { 126 PRVERB(("pcibios: No call entry point\n")); 127 return (0); 128 } 129 args.eax = PCIBIOS_BIOS_PRESENT; 130 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) { 131 PRVERB(("pcibios: BIOS_PRESENT call failed\n")); 132 return (0); 133 } 134 if (args.edx != 0x20494350) { 135 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n")); 136 return (0); 137 } 138 return (args.ebx & 0xffff); 139 } 140 #endif 141 142 /* 143 * Initialise access to PCI configuration space 144 */ 145 int 146 pci_cfgregopen(void) 147 { 148 #ifdef XEN 149 return (0); 150 #else 151 static int opened = 0; 152 uint64_t pciebar; 153 u_int16_t vid, did; 154 u_int16_t v; 155 156 if (opened) 157 return (1); 158 159 if (cfgmech == CFGMECH_NONE && pcireg_cfgopen() == 0) 160 return (0); 161 162 v = pcibios_get_version(); 163 if (v > 0) 164 PRVERB(("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8, 165 v & 0xff)); 166 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 167 opened = 1; 168 169 /* $PIR requires PCI BIOS 2.10 or greater. */ 170 if (v >= 0x0210) 171 pci_pir_open(); 172 173 if (cfgmech == CFGMECH_PCIE) 174 return (1); 175 176 /* 177 * Grope around in the PCI config space to see if this is a 178 * chipset that is capable of doing memory-mapped config cycles. 179 * This also implies that it can do PCIe extended config cycles. 180 */ 181 182 /* Check for supported chipsets */ 183 vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2); 184 did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2); 185 switch (vid) { 186 case 0x8086: 187 switch (did) { 188 case 0x3590: 189 case 0x3592: 190 /* Intel 7520 or 7320 */ 191 pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16; 192 pcie_cfgregopen(pciebar, 0, 255); 193 break; 194 case 0x2580: 195 case 0x2584: 196 case 0x2590: 197 /* Intel 915, 925, or 915GM */ 198 pciebar = pci_cfgregread(0, 0, 0, 0x48, 4); 199 pcie_cfgregopen(pciebar, 0, 255); 200 break; 201 } 202 } 203 204 return(1); 205 #endif 206 } 207 208 static uint32_t 209 pci_docfgregread(int bus, int slot, int func, int reg, int bytes) 210 { 211 212 if (cfgmech == CFGMECH_PCIE && 213 (bus >= pcie_minbus && bus <= pcie_maxbus) && 214 (bus != 0 || !(1 << slot & pcie_badslots))) 215 return (pciereg_cfgread(bus, slot, func, reg, bytes)); 216 else 217 return (pcireg_cfgread(bus, slot, func, reg, bytes)); 218 } 219 220 /* 221 * Read configuration space register 222 */ 223 u_int32_t 224 pci_cfgregread(int bus, int slot, int func, int reg, int bytes) 225 { 226 uint32_t line; 227 228 /* 229 * Some BIOS writers seem to want to ignore the spec and put 230 * 0 in the intline rather than 255 to indicate none. The rest of 231 * the code uses 255 as an invalid IRQ. 232 */ 233 if (reg == PCIR_INTLINE && bytes == 1) { 234 line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1); 235 return (pci_i386_map_intline(line)); 236 } 237 return (pci_docfgregread(bus, slot, func, reg, bytes)); 238 } 239 240 /* 241 * Write configuration space register 242 */ 243 void 244 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) 245 { 246 247 if (cfgmech == CFGMECH_PCIE && 248 (bus >= pcie_minbus && bus <= pcie_maxbus) && 249 (bus != 0 || !(1 << slot & pcie_badslots))) 250 pciereg_cfgwrite(bus, slot, func, reg, data, bytes); 251 else 252 pcireg_cfgwrite(bus, slot, func, reg, data, bytes); 253 } 254 255 /* 256 * Configuration space access using direct register operations 257 */ 258 259 /* enable configuration space accesses and return data port address */ 260 static int 261 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes) 262 { 263 int dataport = 0; 264 265 #ifdef XBOX 266 if (arch_i386_is_xbox) { 267 /* 268 * The Xbox MCPX chipset is a derivative of the nForce 1 269 * chipset. It almost has the same bus layout; some devices 270 * cannot be used, because they have been removed. 271 */ 272 273 /* 274 * Devices 00:00.1 and 00:00.2 used to be memory controllers on 275 * the nForce chipset, but on the Xbox, using them will lockup 276 * the chipset. 277 */ 278 if (bus == 0 && slot == 0 && (func == 1 || func == 2)) 279 return dataport; 280 281 /* 282 * Bus 1 only contains a VGA controller at 01:00.0. When you try 283 * to probe beyond that device, you only get garbage, which 284 * could cause lockups. 285 */ 286 if (bus == 1 && (slot != 0 || func != 0)) 287 return dataport; 288 289 /* 290 * Bus 2 used to contain the AGP controller, but the Xbox MCPX 291 * doesn't have one. Probing it can cause lockups. 292 */ 293 if (bus >= 2) 294 return dataport; 295 } 296 #endif 297 298 if (bus <= PCI_BUSMAX 299 && slot < devmax 300 && func <= PCI_FUNCMAX 301 && (unsigned)reg <= PCI_REGMAX 302 && bytes != 3 303 && (unsigned)bytes <= 4 304 && (reg & (bytes - 1)) == 0) { 305 switch (cfgmech) { 306 case CFGMECH_PCIE: 307 case CFGMECH_1: 308 outl(CONF1_ADDR_PORT, (1U << 31) 309 | (bus << 16) | (slot << 11) 310 | (func << 8) | (reg & ~0x03)); 311 dataport = CONF1_DATA_PORT + (reg & 0x03); 312 break; 313 case CFGMECH_2: 314 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1)); 315 outb(CONF2_FORWARD_PORT, bus); 316 dataport = 0xc000 | (slot << 8) | reg; 317 break; 318 } 319 } 320 return (dataport); 321 } 322 323 /* disable configuration space accesses */ 324 static void 325 pci_cfgdisable(void) 326 { 327 switch (cfgmech) { 328 case CFGMECH_PCIE: 329 case CFGMECH_1: 330 /* 331 * Do nothing for the config mechanism 1 case. 332 * Writing a 0 to the address port can apparently 333 * confuse some bridges and cause spurious 334 * access failures. 335 */ 336 break; 337 case CFGMECH_2: 338 outb(CONF2_ENABLE_PORT, 0); 339 break; 340 } 341 } 342 343 static int 344 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes) 345 { 346 int data = -1; 347 int port; 348 349 mtx_lock_spin(&pcicfg_mtx); 350 port = pci_cfgenable(bus, slot, func, reg, bytes); 351 if (port != 0) { 352 switch (bytes) { 353 case 1: 354 data = inb(port); 355 break; 356 case 2: 357 data = inw(port); 358 break; 359 case 4: 360 data = inl(port); 361 break; 362 } 363 pci_cfgdisable(); 364 } 365 mtx_unlock_spin(&pcicfg_mtx); 366 return (data); 367 } 368 369 static void 370 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) 371 { 372 int port; 373 374 mtx_lock_spin(&pcicfg_mtx); 375 port = pci_cfgenable(bus, slot, func, reg, bytes); 376 if (port != 0) { 377 switch (bytes) { 378 case 1: 379 outb(port, data); 380 break; 381 case 2: 382 outw(port, data); 383 break; 384 case 4: 385 outl(port, data); 386 break; 387 } 388 pci_cfgdisable(); 389 } 390 mtx_unlock_spin(&pcicfg_mtx); 391 } 392 393 #ifndef XEN 394 /* check whether the configuration mechanism has been correctly identified */ 395 static int 396 pci_cfgcheck(int maxdev) 397 { 398 uint32_t id, class; 399 uint8_t header; 400 uint8_t device; 401 int port; 402 403 if (bootverbose) 404 printf("pci_cfgcheck:\tdevice "); 405 406 for (device = 0; device < maxdev; device++) { 407 if (bootverbose) 408 printf("%d ", device); 409 410 port = pci_cfgenable(0, device, 0, 0, 4); 411 id = inl(port); 412 if (id == 0 || id == 0xffffffff) 413 continue; 414 415 port = pci_cfgenable(0, device, 0, 8, 4); 416 class = inl(port) >> 8; 417 if (bootverbose) 418 printf("[class=%06x] ", class); 419 if (class == 0 || (class & 0xf870ff) != 0) 420 continue; 421 422 port = pci_cfgenable(0, device, 0, 14, 1); 423 header = inb(port); 424 if (bootverbose) 425 printf("[hdr=%02x] ", header); 426 if ((header & 0x7e) != 0) 427 continue; 428 429 if (bootverbose) 430 printf("is there (id=%08x)\n", id); 431 432 pci_cfgdisable(); 433 return (1); 434 } 435 if (bootverbose) 436 printf("-- nothing found\n"); 437 438 pci_cfgdisable(); 439 return (0); 440 } 441 442 static int 443 pcireg_cfgopen(void) 444 { 445 uint32_t mode1res, oldval1; 446 uint8_t mode2res, oldval2; 447 448 /* Check for type #1 first. */ 449 oldval1 = inl(CONF1_ADDR_PORT); 450 451 if (bootverbose) { 452 printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n", 453 oldval1); 454 } 455 456 cfgmech = CFGMECH_1; 457 devmax = 32; 458 459 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK); 460 DELAY(1); 461 mode1res = inl(CONF1_ADDR_PORT); 462 outl(CONF1_ADDR_PORT, oldval1); 463 464 if (bootverbose) 465 printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n", mode1res, 466 CONF1_ENABLE_CHK); 467 468 if (mode1res) { 469 if (pci_cfgcheck(32)) 470 return (cfgmech); 471 } 472 473 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1); 474 mode1res = inl(CONF1_ADDR_PORT); 475 outl(CONF1_ADDR_PORT, oldval1); 476 477 if (bootverbose) 478 printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n", mode1res, 479 CONF1_ENABLE_CHK1); 480 481 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) { 482 if (pci_cfgcheck(32)) 483 return (cfgmech); 484 } 485 486 /* Type #1 didn't work, so try type #2. */ 487 oldval2 = inb(CONF2_ENABLE_PORT); 488 489 if (bootverbose) { 490 printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n", 491 oldval2); 492 } 493 494 if ((oldval2 & 0xf0) == 0) { 495 496 cfgmech = CFGMECH_2; 497 devmax = 16; 498 499 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK); 500 mode2res = inb(CONF2_ENABLE_PORT); 501 outb(CONF2_ENABLE_PORT, oldval2); 502 503 if (bootverbose) 504 printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n", 505 mode2res, CONF2_ENABLE_CHK); 506 507 if (mode2res == CONF2_ENABLE_RES) { 508 if (bootverbose) 509 printf("pci_open(2a):\tnow trying mechanism 2\n"); 510 511 if (pci_cfgcheck(16)) 512 return (cfgmech); 513 } 514 } 515 516 /* Nothing worked, so punt. */ 517 cfgmech = CFGMECH_NONE; 518 devmax = 0; 519 return (cfgmech); 520 } 521 522 int 523 pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) 524 { 525 struct pcie_cfg_list *pcielist; 526 struct pcie_cfg_elem *pcie_array, *elem; 527 #ifdef SMP 528 struct pcpu *pc; 529 #endif 530 vm_offset_t va; 531 uint32_t val1, val2; 532 int i, slot; 533 534 if (!mcfg_enable) 535 return (0); 536 537 if (minbus != 0) 538 return (0); 539 540 #ifndef PAE 541 if (base >= 0x100000000) { 542 if (bootverbose) 543 printf( 544 "PCI: Memory Mapped PCI configuration area base 0x%jx too high\n", 545 (uintmax_t)base); 546 return (0); 547 } 548 #endif 549 550 if (bootverbose) 551 printf("PCIe: Memory Mapped configuration base @ 0x%jx\n", 552 (uintmax_t)base); 553 554 #ifdef SMP 555 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) 556 #endif 557 { 558 559 pcie_array = malloc(sizeof(struct pcie_cfg_elem) * PCIE_CACHE, 560 M_DEVBUF, M_NOWAIT); 561 if (pcie_array == NULL) 562 return (0); 563 564 va = kva_alloc(PCIE_CACHE * PAGE_SIZE); 565 if (va == 0) { 566 free(pcie_array, M_DEVBUF); 567 return (0); 568 } 569 570 #ifdef SMP 571 pcielist = &pcie_list[pc->pc_cpuid]; 572 #else 573 pcielist = &pcie_list[0]; 574 #endif 575 TAILQ_INIT(pcielist); 576 for (i = 0; i < PCIE_CACHE; i++) { 577 elem = &pcie_array[i]; 578 elem->vapage = va + (i * PAGE_SIZE); 579 elem->papage = 0; 580 TAILQ_INSERT_HEAD(pcielist, elem, elem); 581 } 582 } 583 584 pcie_base = base; 585 pcie_minbus = minbus; 586 pcie_maxbus = maxbus; 587 cfgmech = CFGMECH_PCIE; 588 devmax = 32; 589 590 /* 591 * On some AMD systems, some of the devices on bus 0 are 592 * inaccessible using memory-mapped PCI config access. Walk 593 * bus 0 looking for such devices. For these devices, we will 594 * fall back to using type 1 config access instead. 595 */ 596 if (pci_cfgregopen() != 0) { 597 for (slot = 0; slot <= PCI_SLOTMAX; slot++) { 598 val1 = pcireg_cfgread(0, slot, 0, 0, 4); 599 if (val1 == 0xffffffff) 600 continue; 601 602 val2 = pciereg_cfgread(0, slot, 0, 0, 4); 603 if (val2 != val1) 604 pcie_badslots |= (1 << slot); 605 } 606 } 607 608 return (1); 609 } 610 #endif /* !XEN */ 611 612 #define PCIE_PADDR(base, reg, bus, slot, func) \ 613 ((base) + \ 614 ((((bus) & 0xff) << 20) | \ 615 (((slot) & 0x1f) << 15) | \ 616 (((func) & 0x7) << 12) | \ 617 ((reg) & 0xfff))) 618 619 static __inline vm_offset_t 620 pciereg_findaddr(int bus, unsigned slot, unsigned func, unsigned reg) 621 { 622 struct pcie_cfg_list *pcielist; 623 struct pcie_cfg_elem *elem; 624 vm_paddr_t pa, papage; 625 626 pa = PCIE_PADDR(pcie_base, reg, bus, slot, func); 627 papage = pa & ~PAGE_MASK; 628 629 /* 630 * Find an element in the cache that matches the physical page desired, 631 * or create a new mapping from the least recently used element. 632 * A very simple LRU algorithm is used here, does it need to be more 633 * efficient? 634 */ 635 pcielist = &pcie_list[PCPU_GET(cpuid)]; 636 TAILQ_FOREACH(elem, pcielist, elem) { 637 if (elem->papage == papage) 638 break; 639 } 640 641 if (elem == NULL) { 642 elem = TAILQ_LAST(pcielist, pcie_cfg_list); 643 if (elem->papage != 0) { 644 pmap_kremove(elem->vapage); 645 invlpg(elem->vapage); 646 } 647 pmap_kenter(elem->vapage, papage); 648 elem->papage = papage; 649 } 650 651 if (elem != TAILQ_FIRST(pcielist)) { 652 TAILQ_REMOVE(pcielist, elem, elem); 653 TAILQ_INSERT_HEAD(pcielist, elem, elem); 654 } 655 return (elem->vapage | (pa & PAGE_MASK)); 656 } 657 658 /* 659 * AMD BIOS And Kernel Developer's Guides for CPU families starting with 10h 660 * have a requirement that all accesses to the memory mapped PCI configuration 661 * space are done using AX class of registers. 662 * Since other vendors do not currently have any contradicting requirements 663 * the AMD access pattern is applied universally. 664 */ 665 666 static int 667 pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg, 668 unsigned bytes) 669 { 670 vm_offset_t va; 671 int data = -1; 672 673 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX || 674 func > PCI_FUNCMAX || reg > PCIE_REGMAX) 675 return (-1); 676 677 critical_enter(); 678 va = pciereg_findaddr(bus, slot, func, reg); 679 680 switch (bytes) { 681 case 4: 682 __asm("movl %1, %0" : "=a" (data) 683 : "m" (*(volatile uint32_t *)va)); 684 break; 685 case 2: 686 __asm("movzwl %1, %0" : "=a" (data) 687 : "m" (*(volatile uint16_t *)va)); 688 break; 689 case 1: 690 __asm("movzbl %1, %0" : "=a" (data) 691 : "m" (*(volatile uint8_t *)va)); 692 break; 693 } 694 695 critical_exit(); 696 return (data); 697 } 698 699 static void 700 pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data, 701 unsigned bytes) 702 { 703 vm_offset_t va; 704 705 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX || 706 func > PCI_FUNCMAX || reg > PCIE_REGMAX) 707 return; 708 709 critical_enter(); 710 va = pciereg_findaddr(bus, slot, func, reg); 711 712 switch (bytes) { 713 case 4: 714 __asm("movl %1, %0" : "=m" (*(volatile uint32_t *)va) 715 : "a" (data)); 716 break; 717 case 2: 718 __asm("movw %1, %0" : "=m" (*(volatile uint16_t *)va) 719 : "a" ((uint16_t)data)); 720 break; 721 case 1: 722 __asm("movb %1, %0" : "=m" (*(volatile uint8_t *)va) 723 : "a" ((uint8_t)data)); 724 break; 725 } 726 727 critical_exit(); 728 } 729