1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD$ 31 */ 32 33 #ifndef _MACHINE_SPECIALREG_H_ 34 #define _MACHINE_SPECIALREG_H_ 35 36 /* 37 * Bits in 386 special registers: 38 */ 39 #define CR0_PE 0x00000001 /* Protected mode Enable */ 40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43 #define CR0_PG 0x80000000 /* PaGing enable */ 44 45 /* 46 * Bits in 486 special registers: 47 */ 48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 /* 56 * Bits in PPro special registers 57 */ 58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60 #define CR4_TSD 0x00000004 /* Time stamp disable */ 61 #define CR4_DE 0x00000008 /* Debugging extensions */ 62 #define CR4_PSE 0x00000010 /* Page size extensions */ 63 #define CR4_PAE 0x00000020 /* Physical address extension */ 64 #define CR4_MCE 0x00000040 /* Machine check enable */ 65 #define CR4_PGE 0x00000080 /* Page global enable */ 66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69 70 /* 71 * CPUID instruction features register 72 */ 73 #define CPUID_FPU 0x00000001 74 #define CPUID_VME 0x00000002 75 #define CPUID_DE 0x00000004 76 #define CPUID_PSE 0x00000008 77 #define CPUID_TSC 0x00000010 78 #define CPUID_MSR 0x00000020 79 #define CPUID_PAE 0x00000040 80 #define CPUID_MCE 0x00000080 81 #define CPUID_CX8 0x00000100 82 #define CPUID_APIC 0x00000200 83 #define CPUID_B10 0x00000400 84 #define CPUID_SEP 0x00000800 85 #define CPUID_MTRR 0x00001000 86 #define CPUID_PGE 0x00002000 87 #define CPUID_MCA 0x00004000 88 #define CPUID_CMOV 0x00008000 89 #define CPUID_PAT 0x00010000 90 #define CPUID_PSE36 0x00020000 91 #define CPUID_PSN 0x00040000 92 #define CPUID_CLFSH 0x00080000 93 #define CPUID_B20 0x00100000 94 #define CPUID_DS 0x00200000 95 #define CPUID_ACPI 0x00400000 96 #define CPUID_MMX 0x00800000 97 #define CPUID_FXSR 0x01000000 98 #define CPUID_SSE 0x02000000 99 #define CPUID_XMM 0x02000000 100 #define CPUID_SSE2 0x04000000 101 #define CPUID_SS 0x08000000 102 #define CPUID_HTT 0x10000000 103 #define CPUID_TM 0x20000000 104 #define CPUID_IA64 0x40000000 105 #define CPUID_PBE 0x80000000 106 107 #define CPUID2_SSE3 0x00000001 108 #define CPUID2_MON 0x00000008 109 #define CPUID2_DS_CPL 0x00000010 110 #define CPUID2_VMX 0x00000020 111 #define CPUID2_EST 0x00000080 112 #define CPUID2_TM2 0x00000100 113 #define CPUID2_CNTXID 0x00000400 114 #define CPUID2_CX16 0x00002000 115 #define CPUID2_XTPR 0x00004000 116 117 /* 118 * Important bits in the AMD extended cpuid flags 119 */ 120 #define AMDID_SYSCALL 0x00000800 121 #define AMDID_MP 0x00080000 122 #define AMDID_NX 0x00100000 123 #define AMDID_EXT_MMX 0x00400000 124 #define AMDID_FFXSR 0x01000000 125 #define AMDID_RDTSCP 0x08000000 126 #define AMDID_LM 0x20000000 127 #define AMDID_EXT_3DNOW 0x40000000 128 #define AMDID_3DNOW 0x80000000 129 130 #define AMDID2_LAHF 0x00000001 131 #define AMDID2_CMP 0x00000002 132 #define AMDID2_SVM 0x00000004 133 #define AMDID2_EXT_APIC 0x00000008 134 #define AMDID2_CR8 0x00000010 135 136 /* 137 * CPUID instruction 1 ebx info 138 */ 139 #define CPUID_BRAND_INDEX 0x000000ff 140 #define CPUID_CLFUSH_SIZE 0x0000ff00 141 #define CPUID_HTT_CORES 0x00ff0000 142 #define CPUID_LOCAL_APIC_ID 0xff000000 143 144 /* 145 * AMD extended function 8000_0008h ecx info 146 */ 147 #define AMDID_CMP_CORES 0x000000ff 148 149 /* 150 * Model-specific registers for the i386 family 151 */ 152 #define MSR_P5_MC_ADDR 0x000 153 #define MSR_P5_MC_TYPE 0x001 154 #define MSR_TSC 0x010 155 #define MSR_P5_CESR 0x011 156 #define MSR_P5_CTR0 0x012 157 #define MSR_P5_CTR1 0x013 158 #define MSR_IA32_PLATFORM_ID 0x017 159 #define MSR_APICBASE 0x01b 160 #define MSR_EBL_CR_POWERON 0x02a 161 #define MSR_TEST_CTL 0x033 162 #define MSR_BIOS_UPDT_TRIG 0x079 163 #define MSR_BBL_CR_D0 0x088 164 #define MSR_BBL_CR_D1 0x089 165 #define MSR_BBL_CR_D2 0x08a 166 #define MSR_BIOS_SIGN 0x08b 167 #define MSR_PERFCTR0 0x0c1 168 #define MSR_PERFCTR1 0x0c2 169 #define MSR_MTRRcap 0x0fe 170 #define MSR_BBL_CR_ADDR 0x116 171 #define MSR_BBL_CR_DECC 0x118 172 #define MSR_BBL_CR_CTL 0x119 173 #define MSR_BBL_CR_TRIG 0x11a 174 #define MSR_BBL_CR_BUSY 0x11b 175 #define MSR_BBL_CR_CTL3 0x11e 176 #define MSR_SYSENTER_CS_MSR 0x174 177 #define MSR_SYSENTER_ESP_MSR 0x175 178 #define MSR_SYSENTER_EIP_MSR 0x176 179 #define MSR_MCG_CAP 0x179 180 #define MSR_MCG_STATUS 0x17a 181 #define MSR_MCG_CTL 0x17b 182 #define MSR_EVNTSEL0 0x186 183 #define MSR_EVNTSEL1 0x187 184 #define MSR_THERM_CONTROL 0x19a 185 #define MSR_THERM_INTERRUPT 0x19b 186 #define MSR_THERM_STATUS 0x19c 187 #define MSR_IA32_MISC_ENABLE 0x1a0 188 #define MSR_DEBUGCTLMSR 0x1d9 189 #define MSR_LASTBRANCHFROMIP 0x1db 190 #define MSR_LASTBRANCHTOIP 0x1dc 191 #define MSR_LASTINTFROMIP 0x1dd 192 #define MSR_LASTINTTOIP 0x1de 193 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 194 #define MSR_MTRRVarBase 0x200 195 #define MSR_MTRR64kBase 0x250 196 #define MSR_MTRR16kBase 0x258 197 #define MSR_MTRR4kBase 0x268 198 #define MSR_PAT 0x277 199 #define MSR_MTRRdefType 0x2ff 200 #define MSR_MC0_CTL 0x400 201 #define MSR_MC0_STATUS 0x401 202 #define MSR_MC0_ADDR 0x402 203 #define MSR_MC0_MISC 0x403 204 #define MSR_MC1_CTL 0x404 205 #define MSR_MC1_STATUS 0x405 206 #define MSR_MC1_ADDR 0x406 207 #define MSR_MC1_MISC 0x407 208 #define MSR_MC2_CTL 0x408 209 #define MSR_MC2_STATUS 0x409 210 #define MSR_MC2_ADDR 0x40a 211 #define MSR_MC2_MISC 0x40b 212 #define MSR_MC3_CTL 0x40c 213 #define MSR_MC3_STATUS 0x40d 214 #define MSR_MC3_ADDR 0x40e 215 #define MSR_MC3_MISC 0x40f 216 #define MSR_MC4_CTL 0x410 217 #define MSR_MC4_STATUS 0x411 218 #define MSR_MC4_ADDR 0x412 219 #define MSR_MC4_MISC 0x413 220 221 /* 222 * Constants related to MSR's. 223 */ 224 #define APICBASE_RESERVED 0x000006ff 225 #define APICBASE_BSP 0x00000100 226 #define APICBASE_ENABLED 0x00000800 227 #define APICBASE_ADDRESS 0xfffff000 228 229 /* 230 * PAT modes. 231 */ 232 #define PAT_UNCACHEABLE 0x00 233 #define PAT_WRITE_COMBINING 0x01 234 #define PAT_WRITE_THROUGH 0x04 235 #define PAT_WRITE_PROTECTED 0x05 236 #define PAT_WRITE_BACK 0x06 237 #define PAT_UNCACHED 0x07 238 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 239 #define PAT_MASK(i) PAT_VALUE(i, 0xff) 240 241 /* 242 * Constants related to MTRRs 243 */ 244 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 245 #define MTRR_N16K 16 246 #define MTRR_N4K 64 247 248 /* 249 * Cyrix configuration registers, accessible as IO ports. 250 */ 251 #define CCR0 0xc0 /* Configuration control register 0 */ 252 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 253 non-cacheable */ 254 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 255 #define CCR0_A20M 0x04 /* Enables A20M# input pin */ 256 #define CCR0_KEN 0x08 /* Enables KEN# input pin */ 257 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 258 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 259 state */ 260 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 261 assoc */ 262 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 263 264 #define CCR1 0xc1 /* Configuration control register 1 */ 265 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 266 #define CCR1_SMI 0x02 /* Enables SMM pins */ 267 #define CCR1_SMAC 0x04 /* System management memory access */ 268 #define CCR1_MMAC 0x08 /* Main memory access */ 269 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 270 #define CCR1_SM3 0x80 /* SMM address space address region 3 */ 271 272 #define CCR2 0xc2 273 #define CCR2_WB 0x02 /* Enables WB cache interface pins */ 274 #define CCR2_SADS 0x02 /* Slow ADS */ 275 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 276 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 277 #define CCR2_WT1 0x10 /* WT region 1 */ 278 #define CCR2_WPR1 0x10 /* Write-protect region 1 */ 279 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering 280 hold state. */ 281 #define CCR2_BWRT 0x40 /* Enables burst write cycles */ 282 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 283 284 #define CCR3 0xc3 285 #define CCR3_SMILOCK 0x01 /* SMM register lock */ 286 #define CCR3_NMI 0x02 /* Enables NMI during SMM */ 287 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 288 #define CCR3_SMMMODE 0x08 /* SMM Mode */ 289 #define CCR3_MAPEN0 0x10 /* Enables Map0 */ 290 #define CCR3_MAPEN1 0x20 /* Enables Map1 */ 291 #define CCR3_MAPEN2 0x40 /* Enables Map2 */ 292 #define CCR3_MAPEN3 0x80 /* Enables Map3 */ 293 294 #define CCR4 0xe8 295 #define CCR4_IOMASK 0x07 296 #define CCR4_MEM 0x08 /* Enables momory bypassing */ 297 #define CCR4_DTE 0x10 /* Enables directory table entry cache */ 298 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 299 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 300 301 #define CCR5 0xe9 302 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 303 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 304 #define CCR5_LBR1 0x10 /* Local bus region 1 */ 305 #define CCR5_ARREN 0x20 /* Enables ARR region */ 306 307 #define CCR6 0xea 308 309 #define CCR7 0xeb 310 311 /* Performance Control Register (5x86 only). */ 312 #define PCR0 0x20 313 #define PCR0_RSTK 0x01 /* Enables return stack */ 314 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 315 #define PCR0_LOOP 0x04 /* Enables loop */ 316 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 317 serialize pipe. */ 318 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 319 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 320 #define PCR0_LSSER 0x80 /* Disable reorder */ 321 322 /* Device Identification Registers */ 323 #define DIR0 0xfe 324 #define DIR1 0xff 325 326 /* 327 * The following four 3-byte registers control the non-cacheable regions. 328 * These registers must be written as three separate bytes. 329 * 330 * NCRx+0: A31-A24 of starting address 331 * NCRx+1: A23-A16 of starting address 332 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 333 * 334 * The non-cacheable region's starting address must be aligned to the 335 * size indicated by the NCR_SIZE_xx field. 336 */ 337 #define NCR1 0xc4 338 #define NCR2 0xc7 339 #define NCR3 0xca 340 #define NCR4 0xcd 341 342 #define NCR_SIZE_0K 0 343 #define NCR_SIZE_4K 1 344 #define NCR_SIZE_8K 2 345 #define NCR_SIZE_16K 3 346 #define NCR_SIZE_32K 4 347 #define NCR_SIZE_64K 5 348 #define NCR_SIZE_128K 6 349 #define NCR_SIZE_256K 7 350 #define NCR_SIZE_512K 8 351 #define NCR_SIZE_1M 9 352 #define NCR_SIZE_2M 10 353 #define NCR_SIZE_4M 11 354 #define NCR_SIZE_8M 12 355 #define NCR_SIZE_16M 13 356 #define NCR_SIZE_32M 14 357 #define NCR_SIZE_4G 15 358 359 /* 360 * The address region registers are used to specify the location and 361 * size for the eight address regions. 362 * 363 * ARRx + 0: A31-A24 of start address 364 * ARRx + 1: A23-A16 of start address 365 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 366 */ 367 #define ARR0 0xc4 368 #define ARR1 0xc7 369 #define ARR2 0xca 370 #define ARR3 0xcd 371 #define ARR4 0xd0 372 #define ARR5 0xd3 373 #define ARR6 0xd6 374 #define ARR7 0xd9 375 376 #define ARR_SIZE_0K 0 377 #define ARR_SIZE_4K 1 378 #define ARR_SIZE_8K 2 379 #define ARR_SIZE_16K 3 380 #define ARR_SIZE_32K 4 381 #define ARR_SIZE_64K 5 382 #define ARR_SIZE_128K 6 383 #define ARR_SIZE_256K 7 384 #define ARR_SIZE_512K 8 385 #define ARR_SIZE_1M 9 386 #define ARR_SIZE_2M 10 387 #define ARR_SIZE_4M 11 388 #define ARR_SIZE_8M 12 389 #define ARR_SIZE_16M 13 390 #define ARR_SIZE_32M 14 391 #define ARR_SIZE_4G 15 392 393 /* 394 * The region control registers specify the attributes associated with 395 * the ARRx addres regions. 396 */ 397 #define RCR0 0xdc 398 #define RCR1 0xdd 399 #define RCR2 0xde 400 #define RCR3 0xdf 401 #define RCR4 0xe0 402 #define RCR5 0xe1 403 #define RCR6 0xe2 404 #define RCR7 0xe3 405 406 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 407 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 408 #define RCR_WWO 0x02 /* Weak write ordering. */ 409 #define RCR_WL 0x04 /* Weak locking. */ 410 #define RCR_WG 0x08 /* Write gathering. */ 411 #define RCR_WT 0x10 /* Write-through. */ 412 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 413 414 /* AMD Write Allocate Top-Of-Memory and Control Register */ 415 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 416 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 417 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 418 419 /* VIA ACE crypto featureset: for via_feature_rng */ 420 #define VIA_HAS_RNG 1 /* cpu has RNG */ 421 422 /* VIA ACE crypto featureset: for via_feature_xcrypt */ 423 #define VIA_HAS_AES 1 /* cpu has AES */ 424 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 425 #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 426 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 427 428 /* Centaur Extended Feature flags */ 429 #define VIA_CPUID_HAS_RNG 0x000004 430 #define VIA_CPUID_DO_RNG 0x000008 431 #define VIA_CPUID_HAS_ACE 0x000040 432 #define VIA_CPUID_DO_ACE 0x000080 433 #define VIA_CPUID_HAS_ACE2 0x000100 434 #define VIA_CPUID_DO_ACE2 0x000200 435 #define VIA_CPUID_HAS_PHE 0x000400 436 #define VIA_CPUID_DO_PHE 0x000800 437 #define VIA_CPUID_HAS_PMM 0x001000 438 #define VIA_CPUID_DO_PMM 0x002000 439 440 /* VIA ACE xcrypt-* instruction context control options */ 441 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 442 #define VIA_CRYPT_CWLO_ALG_M 0x00000070 443 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000 444 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 445 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 446 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 447 #define VIA_CRYPT_CWLO_NORMAL 0x00000000 448 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 449 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 450 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200 451 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 452 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 453 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 454 455 #ifndef LOCORE 456 static __inline u_char 457 read_cyrix_reg(u_char reg) 458 { 459 outb(0x22, reg); 460 return inb(0x23); 461 } 462 463 static __inline void 464 write_cyrix_reg(u_char reg, u_char data) 465 { 466 outb(0x22, reg); 467 outb(0x23, data); 468 } 469 #endif 470 471 #endif /* !_MACHINE_SPECIALREG_H_ */ 472