1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 34 * $Id: specialreg.h,v 1.4 1994/09/04 19:59:24 pst Exp $ 35 */ 36 37 #ifndef _MACHINE_SPECIALREG_H_ 38 #define _MACHINE_SPECIALREG_H_ 1 39 40 /* 41 * Bits in 386 special registers: 42 */ 43 44 #define CR0_PE 0x00000001 /* Protected mode Enable */ 45 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 46 #ifdef notused 47 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 48 #endif 49 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 50 #ifdef notused 51 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 52 #endif 53 #define CR0_PG 0x80000000 /* PaGing enable */ 54 55 /* 56 * Bits in 486 special registers: 57 */ 58 59 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 60 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */ 61 #ifdef notyet 62 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 63 #endif 64 65 /* 66 * Cyrix 486 DLC special registers, accessable as IO ports. 67 */ 68 #define CCR0 0xc0 /* configuration control register 0 */ 69 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is 70 non-cacheable */ 71 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 72 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 73 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 74 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 75 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold 76 state */ 77 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 78 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 79 80 #define CCR1 0xc1 /* configuration control register 1 */ 81 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 82 /* the remaining 7 bits of this register are reserved */ 83 84 /* 85 * the following four 3-byte registers control the non-cacheable regions. 86 * These registers must be written as three seperate bytes. 87 * 88 * NCRx+0: A31-A24 of starting address 89 * NCRx+1: A23-A16 of starting address 90 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 91 * 92 * The non-cacheable region's starting address must be aligned to the 93 * size indicated by the NCR_SIZE_xx field. 94 */ 95 #define NCR1 0xc4 96 #define NCR2 0xc7 97 #define NCR3 0xca 98 #define NCR4 0xcd 99 100 #define NCR_SIZE_0K 0 101 #define NCR_SIZE_4K 1 102 #define NCR_SIZE_8K 2 103 #define NCR_SIZE_16K 3 104 #define NCR_SIZE_32K 4 105 #define NCR_SIZE_64K 5 106 #define NCR_SIZE_128K 6 107 #define NCR_SIZE_256K 7 108 #define NCR_SIZE_512K 8 109 #define NCR_SIZE_1M 9 110 #define NCR_SIZE_2M 10 111 #define NCR_SIZE_4M 11 112 #define NCR_SIZE_8M 12 113 #define NCR_SIZE_16M 13 114 #define NCR_SIZE_32M 14 115 #define NCR_SIZE_4G 15 116 117 #endif /* _MACHINE_SPECIALREG_H_ */ 118