xref: /freebsd/sys/i386/include/specialreg.h (revision 3642298923e528d795e3a30ec165d2b469e28b40)
1 /*-
2  * Copyright (c) 1991 The Regents of the University of California.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 4. Neither the name of the University nor the names of its contributors
14  *    may be used to endorse or promote products derived from this software
15  *    without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  *	from: @(#)specialreg.h	7.1 (Berkeley) 5/9/91
30  * $FreeBSD$
31  */
32 
33 #ifndef _MACHINE_SPECIALREG_H_
34 #define	_MACHINE_SPECIALREG_H_
35 
36 /*
37  * Bits in 386 special registers:
38  */
39 #define	CR0_PE	0x00000001	/* Protected mode Enable */
40 #define	CR0_MP	0x00000002	/* "Math" Present (NPX or NPX emulator) */
41 #define	CR0_EM	0x00000004	/* EMulate non-NPX coproc. (trap ESC only) */
42 #define	CR0_TS	0x00000008	/* Task Switched (if MP, trap ESC and WAIT) */
43 #ifdef notused
44 #define	CR0_ET	0x00000010	/* Extension Type (387 (if set) vs 287) */
45 #endif
46 #define	CR0_PG	0x80000000	/* PaGing enable */
47 
48 /*
49  * Bits in 486 special registers:
50  */
51 #define	CR0_NE	0x00000020	/* Numeric Error enable (EX16 vs IRQ13) */
52 #define	CR0_WP	0x00010000	/* Write Protect (honor page protect in
53 							   all modes) */
54 #define	CR0_AM	0x00040000	/* Alignment Mask (set to enable AC flag) */
55 #define	CR0_NW  0x20000000	/* Not Write-through */
56 #define	CR0_CD  0x40000000	/* Cache Disable */
57 
58 /*
59  * Bits in PPro special registers
60  */
61 #define	CR4_VME	0x00000001	/* Virtual 8086 mode extensions */
62 #define	CR4_PVI	0x00000002	/* Protected-mode virtual interrupts */
63 #define	CR4_TSD	0x00000004	/* Time stamp disable */
64 #define	CR4_DE	0x00000008	/* Debugging extensions */
65 #define	CR4_PSE	0x00000010	/* Page size extensions */
66 #define	CR4_PAE	0x00000020	/* Physical address extension */
67 #define	CR4_MCE	0x00000040	/* Machine check enable */
68 #define	CR4_PGE	0x00000080	/* Page global enable */
69 #define	CR4_PCE	0x00000100	/* Performance monitoring counter enable */
70 #define	CR4_FXSR 0x00000200	/* Fast FPU save/restore used by OS */
71 #define	CR4_XMM	0x00000400	/* enable SIMD/MMX2 to use except 16 */
72 
73 /*
74  * CPUID instruction features register
75  */
76 #define	CPUID_FPU	0x00000001
77 #define	CPUID_VME	0x00000002
78 #define	CPUID_DE	0x00000004
79 #define	CPUID_PSE	0x00000008
80 #define	CPUID_TSC	0x00000010
81 #define	CPUID_MSR	0x00000020
82 #define	CPUID_PAE	0x00000040
83 #define	CPUID_MCE	0x00000080
84 #define	CPUID_CX8	0x00000100
85 #define	CPUID_APIC	0x00000200
86 #define	CPUID_B10	0x00000400
87 #define	CPUID_SEP	0x00000800
88 #define	CPUID_MTRR	0x00001000
89 #define	CPUID_PGE	0x00002000
90 #define	CPUID_MCA	0x00004000
91 #define	CPUID_CMOV	0x00008000
92 #define	CPUID_PAT	0x00010000
93 #define	CPUID_PSE36	0x00020000
94 #define	CPUID_PSN	0x00040000
95 #define	CPUID_CLFSH	0x00080000
96 #define	CPUID_B20	0x00100000
97 #define	CPUID_DS	0x00200000
98 #define	CPUID_ACPI	0x00400000
99 #define	CPUID_MMX	0x00800000
100 #define	CPUID_FXSR	0x01000000
101 #define	CPUID_SSE	0x02000000
102 #define	CPUID_XMM	0x02000000
103 #define	CPUID_SSE2	0x04000000
104 #define	CPUID_SS	0x08000000
105 #define	CPUID_HTT	0x10000000
106 #define	CPUID_TM	0x20000000
107 #define	CPUID_IA64	0x40000000
108 #define	CPUID_PBE	0x80000000
109 
110 /*
111  * CPUID instruction 1 ebx info
112  */
113 #define	CPUID_BRAND_INDEX	0x000000ff
114 #define	CPUID_CLFUSH_SIZE	0x0000ff00
115 #define	CPUID_HTT_CORES		0x00ff0000
116 #define	CPUID_LOCAL_APIC_ID	0xff000000
117 
118 /*
119  * Model-specific registers for the i386 family
120  */
121 #define MSR_P5_MC_ADDR		0x000
122 #define MSR_P5_MC_TYPE		0x001
123 #define MSR_TSC			0x010
124 #define	MSR_P5_CESR		0x011
125 #define	MSR_P5_CTR0		0x012
126 #define	MSR_P5_CTR1		0x013
127 #define	MSR_IA32_PLATFORM_ID	0x017
128 #define MSR_APICBASE		0x01b
129 #define MSR_EBL_CR_POWERON	0x02a
130 #define	MSR_TEST_CTL		0x033
131 #define MSR_BIOS_UPDT_TRIG	0x079
132 #define	MSR_BBL_CR_D0		0x088
133 #define	MSR_BBL_CR_D1		0x089
134 #define	MSR_BBL_CR_D2		0x08a
135 #define MSR_BIOS_SIGN		0x08b
136 #define MSR_PERFCTR0		0x0c1
137 #define MSR_PERFCTR1		0x0c2
138 #define MSR_MTRRcap		0x0fe
139 #define	MSR_BBL_CR_ADDR		0x116
140 #define	MSR_BBL_CR_DECC		0x118
141 #define	MSR_BBL_CR_CTL		0x119
142 #define	MSR_BBL_CR_TRIG		0x11a
143 #define	MSR_BBL_CR_BUSY		0x11b
144 #define	MSR_BBL_CR_CTL3		0x11e
145 #define	MSR_SYSENTER_CS_MSR	0x174
146 #define	MSR_SYSENTER_ESP_MSR	0x175
147 #define	MSR_SYSENTER_EIP_MSR	0x176
148 #define MSR_MCG_CAP		0x179
149 #define MSR_MCG_STATUS		0x17a
150 #define MSR_MCG_CTL		0x17b
151 #define MSR_EVNTSEL0		0x186
152 #define MSR_EVNTSEL1		0x187
153 #define MSR_THERM_CONTROL	0x19a
154 #define MSR_THERM_INTERRUPT	0x19b
155 #define MSR_THERM_STATUS	0x19c
156 #define MSR_DEBUGCTLMSR		0x1d9
157 #define MSR_LASTBRANCHFROMIP	0x1db
158 #define MSR_LASTBRANCHTOIP	0x1dc
159 #define MSR_LASTINTFROMIP	0x1dd
160 #define MSR_LASTINTTOIP		0x1de
161 #define MSR_ROB_CR_BKUPTMPDR6	0x1e0
162 #define MSR_MTRRVarBase		0x200
163 #define MSR_MTRR64kBase		0x250
164 #define MSR_MTRR16kBase		0x258
165 #define MSR_MTRR4kBase		0x268
166 #define MSR_MTRRdefType		0x2ff
167 #define MSR_MC0_CTL		0x400
168 #define MSR_MC0_STATUS		0x401
169 #define MSR_MC0_ADDR		0x402
170 #define MSR_MC0_MISC		0x403
171 #define MSR_MC1_CTL		0x404
172 #define MSR_MC1_STATUS		0x405
173 #define MSR_MC1_ADDR		0x406
174 #define MSR_MC1_MISC		0x407
175 #define MSR_MC2_CTL		0x408
176 #define MSR_MC2_STATUS		0x409
177 #define MSR_MC2_ADDR		0x40a
178 #define MSR_MC2_MISC		0x40b
179 #define MSR_MC4_CTL		0x40c
180 #define MSR_MC4_STATUS		0x40d
181 #define MSR_MC4_ADDR		0x40e
182 #define MSR_MC4_MISC		0x40f
183 #define MSR_MC3_CTL		0x410
184 #define MSR_MC3_STATUS		0x411
185 #define MSR_MC3_ADDR		0x412
186 #define MSR_MC3_MISC		0x413
187 
188 /*
189  * Constants related to MSR's.
190  */
191 #define	APICBASE_RESERVED	0x000006ff
192 #define	APICBASE_BSP		0x00000100
193 #define	APICBASE_ENABLED	0x00000800
194 #define	APICBASE_ADDRESS	0xfffff000
195 
196 /*
197  * Constants related to MTRRs
198  */
199 #define MTRR_N64K		8	/* numbers of fixed-size entries */
200 #define MTRR_N16K		16
201 #define MTRR_N4K		64
202 
203 /*
204  * Cyrix configuration registers, accessible as IO ports.
205  */
206 #define	CCR0			0xc0	/* Configuration control register 0 */
207 #define	CCR0_NC0		0x01	/* First 64K of each 1M memory region is
208 								   non-cacheable */
209 #define	CCR0_NC1		0x02	/* 640K-1M region is non-cacheable */
210 #define	CCR0_A20M		0x04	/* Enables A20M# input pin */
211 #define	CCR0_KEN		0x08	/* Enables KEN# input pin */
212 #define	CCR0_FLUSH		0x10	/* Enables FLUSH# input pin */
213 #define	CCR0_BARB		0x20	/* Flushes internal cache when entering hold
214 								   state */
215 #define	CCR0_CO			0x40	/* Cache org: 1=direct mapped, 0=2x set
216 								   assoc */
217 #define	CCR0_SUSPEND	0x80	/* Enables SUSP# and SUSPA# pins */
218 
219 #define	CCR1			0xc1	/* Configuration control register 1 */
220 #define	CCR1_RPL		0x01	/* Enables RPLSET and RPLVAL# pins */
221 #define	CCR1_SMI		0x02	/* Enables SMM pins */
222 #define	CCR1_SMAC		0x04	/* System management memory access */
223 #define	CCR1_MMAC		0x08	/* Main memory access */
224 #define	CCR1_NO_LOCK	0x10	/* Negate LOCK# */
225 #define	CCR1_SM3		0x80	/* SMM address space address region 3 */
226 
227 #define	CCR2			0xc2
228 #define	CCR2_WB			0x02	/* Enables WB cache interface pins */
229 #define	CCR2_SADS		0x02	/* Slow ADS */
230 #define	CCR2_LOCK_NW	0x04	/* LOCK NW Bit */
231 #define	CCR2_SUSP_HLT	0x08	/* Suspend on HALT */
232 #define	CCR2_WT1		0x10	/* WT region 1 */
233 #define	CCR2_WPR1		0x10	/* Write-protect region 1 */
234 #define CCR2_BARB		0x20	/* Flushes write-back cache when entering
235 								   hold state. */
236 #define	CCR2_BWRT		0x40	/* Enables burst write cycles */
237 #define	CCR2_USE_SUSP	0x80	/* Enables suspend pins */
238 
239 #define	CCR3			0xc3
240 #define	CCR3_SMILOCK	0x01	/* SMM register lock */
241 #define	CCR3_NMI		0x02	/* Enables NMI during SMM */
242 #define	CCR3_LINBRST	0x04	/* Linear address burst cycles */
243 #define	CCR3_SMMMODE	0x08	/* SMM Mode */
244 #define	CCR3_MAPEN0		0x10	/* Enables Map0 */
245 #define	CCR3_MAPEN1		0x20	/* Enables Map1 */
246 #define	CCR3_MAPEN2		0x40	/* Enables Map2 */
247 #define	CCR3_MAPEN3		0x80	/* Enables Map3 */
248 
249 #define	CCR4			0xe8
250 #define	CCR4_IOMASK		0x07
251 #define	CCR4_MEM		0x08	/* Enables momory bypassing */
252 #define	CCR4_DTE		0x10	/* Enables directory table entry cache */
253 #define	CCR4_FASTFPE	0x20	/* Fast FPU exception */
254 #define	CCR4_CPUID		0x80	/* Enables CPUID instruction */
255 
256 #define	CCR5			0xe9
257 #define	CCR5_WT_ALLOC	0x01	/* Write-through allocate */
258 #define	CCR5_SLOP		0x02	/* LOOP instruction slowed down */
259 #define	CCR5_LBR1		0x10	/* Local bus region 1 */
260 #define	CCR5_ARREN		0x20	/* Enables ARR region */
261 
262 #define	CCR6			0xea
263 
264 #define	CCR7			0xeb
265 
266 /* Performance Control Register (5x86 only). */
267 #define	PCR0			0x20
268 #define	PCR0_RSTK		0x01	/* Enables return stack */
269 #define	PCR0_BTB		0x02	/* Enables branch target buffer */
270 #define	PCR0_LOOP		0x04	/* Enables loop */
271 #define	PCR0_AIS		0x08	/* Enables all instrcutions stalled to
272 								   serialize pipe. */
273 #define	PCR0_MLR		0x10	/* Enables reordering of misaligned loads */
274 #define	PCR0_BTBRT		0x40	/* Enables BTB test register. */
275 #define	PCR0_LSSER		0x80	/* Disable reorder */
276 
277 /* Device Identification Registers */
278 #define	DIR0			0xfe
279 #define	DIR1			0xff
280 
281 /*
282  * The following four 3-byte registers control the non-cacheable regions.
283  * These registers must be written as three separate bytes.
284  *
285  * NCRx+0: A31-A24 of starting address
286  * NCRx+1: A23-A16 of starting address
287  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
288  *
289  * The non-cacheable region's starting address must be aligned to the
290  * size indicated by the NCR_SIZE_xx field.
291  */
292 #define	NCR1	0xc4
293 #define	NCR2	0xc7
294 #define	NCR3	0xca
295 #define	NCR4	0xcd
296 
297 #define	NCR_SIZE_0K	0
298 #define	NCR_SIZE_4K	1
299 #define	NCR_SIZE_8K	2
300 #define	NCR_SIZE_16K	3
301 #define	NCR_SIZE_32K	4
302 #define	NCR_SIZE_64K	5
303 #define	NCR_SIZE_128K	6
304 #define	NCR_SIZE_256K	7
305 #define	NCR_SIZE_512K	8
306 #define	NCR_SIZE_1M	9
307 #define	NCR_SIZE_2M	10
308 #define	NCR_SIZE_4M	11
309 #define	NCR_SIZE_8M	12
310 #define	NCR_SIZE_16M	13
311 #define	NCR_SIZE_32M	14
312 #define	NCR_SIZE_4G	15
313 
314 /*
315  * The address region registers are used to specify the location and
316  * size for the eight address regions.
317  *
318  * ARRx + 0: A31-A24 of start address
319  * ARRx + 1: A23-A16 of start address
320  * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
321  */
322 #define	ARR0	0xc4
323 #define	ARR1	0xc7
324 #define	ARR2	0xca
325 #define	ARR3	0xcd
326 #define	ARR4	0xd0
327 #define	ARR5	0xd3
328 #define	ARR6	0xd6
329 #define	ARR7	0xd9
330 
331 #define	ARR_SIZE_0K		0
332 #define	ARR_SIZE_4K		1
333 #define	ARR_SIZE_8K		2
334 #define	ARR_SIZE_16K	3
335 #define	ARR_SIZE_32K	4
336 #define	ARR_SIZE_64K	5
337 #define	ARR_SIZE_128K	6
338 #define	ARR_SIZE_256K	7
339 #define	ARR_SIZE_512K	8
340 #define	ARR_SIZE_1M		9
341 #define	ARR_SIZE_2M		10
342 #define	ARR_SIZE_4M		11
343 #define	ARR_SIZE_8M		12
344 #define	ARR_SIZE_16M	13
345 #define	ARR_SIZE_32M	14
346 #define	ARR_SIZE_4G		15
347 
348 /*
349  * The region control registers specify the attributes associated with
350  * the ARRx addres regions.
351  */
352 #define	RCR0	0xdc
353 #define	RCR1	0xdd
354 #define	RCR2	0xde
355 #define	RCR3	0xdf
356 #define	RCR4	0xe0
357 #define	RCR5	0xe1
358 #define	RCR6	0xe2
359 #define	RCR7	0xe3
360 
361 #define RCR_RCD	0x01	/* Disables caching for ARRx (x = 0-6). */
362 #define RCR_RCE	0x01	/* Enables caching for ARR7. */
363 #define RCR_WWO	0x02	/* Weak write ordering. */
364 #define	RCR_WL	0x04	/* Weak locking. */
365 #define RCR_WG	0x08	/* Write gathering. */
366 #define	RCR_WT	0x10	/* Write-through. */
367 #define	RCR_NLB	0x20	/* LBA# pin is not asserted. */
368 
369 /* AMD Write Allocate Top-Of-Memory and Control Register */
370 #define	AMD_WT_ALLOC_TME	0x40000	/* top-of-memory enable */
371 #define	AMD_WT_ALLOC_PRE	0x20000	/* programmable range enable */
372 #define	AMD_WT_ALLOC_FRE	0x10000	/* fixed (A0000-FFFFF) range enable */
373 
374 
375 #ifndef LOCORE
376 static __inline u_char
377 read_cyrix_reg(u_char reg)
378 {
379 	outb(0x22, reg);
380 	return inb(0x23);
381 }
382 
383 static __inline void
384 write_cyrix_reg(u_char reg, u_char data)
385 {
386 	outb(0x22, reg);
387 	outb(0x23, data);
388 }
389 #endif
390 
391 #endif /* !_MACHINE_SPECIALREG_H_ */
392