xref: /freebsd/sys/i386/include/perfmon.h (revision f7c32ed617858bcd22f8d1b03199099d50125721)
1 /*-
2  * Copyright 1996 Massachusetts Institute of Technology
3  *
4  * Permission to use, copy, modify, and distribute this software and
5  * its documentation for any purpose and without fee is hereby
6  * granted, provided that both the above copyright notice and this
7  * permission notice appear in all copies, that both the above
8  * copyright notice and this permission notice appear in all
9  * supporting documentation, and that the name of M.I.T. not be used
10  * in advertising or publicity pertaining to distribution of the
11  * software without specific, written prior permission.  M.I.T. makes
12  * no representations about the suitability of this software for any
13  * purpose.  It is provided "as is" without express or implied
14  * warranty.
15  *
16  * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''.  M.I.T. DISCLAIMS
17  * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
18  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
20  * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  * $FreeBSD$
30  */
31 
32 /*
33  * Interface to performance-monitoring counters for Intel Pentium and
34  * Pentium Pro CPUs.
35  */
36 
37 #ifndef	_MACHINE_PERFMON_H_
38 #define	_MACHINE_PERFMON_H_
39 
40 #ifndef _KERNEL
41 #include <sys/types.h>
42 #endif
43 #include <sys/ioccom.h>
44 
45 #define	NPMC	2
46 
47 #define	PMIOSETUP	_IOW('5', 1, struct pmc)
48 #define	PMIOGET		_IOWR('5', 7, struct pmc)
49 #define	PMIOSTART	_IOW('5', 2, int)
50 #define	PMIOSTOP	_IOW('5', 3, int)
51 #define PMIOREAD	_IOWR('5', 4, struct pmc_data)
52 #define	PMIORESET	_IOW('5', 5, int)
53 #define	PMIOTSTAMP	_IOR('5', 6, struct pmc_tstamp)
54 
55 struct pmc {
56 	int pmc_num;
57 	union {
58 		struct {
59 			unsigned char pmcus_event;
60 			unsigned char pmcus_unit;
61 			unsigned char pmcus_flags;
62 			unsigned char pmcus_mask;
63 		} pmcu_s;
64 		unsigned int pmcu_val;
65 	} pmc_pmcu;
66 };
67 
68 #define	PMC_ALL		(-1)
69 
70 #define	pmc_event	pmc_pmcu.pmcu_s.pmcus_event
71 #define	pmc_unit	pmc_pmcu.pmcu_s.pmcus_unit
72 #define	pmc_flags	pmc_pmcu.pmcu_s.pmcus_flags
73 #define	pmc_mask	pmc_pmcu.pmcu_s.pmcus_mask
74 #define	pmc_val		pmc_pmcu.pmcu_val
75 
76 #define	PMCF_USR	0x01	/* count events in user mode */
77 #define	PMCF_OS		0x02	/* count events in kernel mode */
78 #define	PMCF_E		0x04	/* use edge-detection mode */
79 #define	PMCF_PC		0x08	/* PMx output pin control */
80 #define	PMCF_INT	0x10	/* APIC interrupt enable (do not use) */
81 #define	PMCF_EN		0x40	/* enable counters */
82 #define	PMCF_INV	0x80	/* invert counter mask comparison */
83 
84 #define	PMCF_SYS_FLAGS	(PMCF_INT | PMCF_EN) /* user cannot set */
85 
86 struct pmc_data {
87 	int pmcd_num;
88 	quad_t pmcd_value;
89 };
90 
91 struct pmc_tstamp {
92 	int pmct_rate;
93 	quad_t pmct_value;
94 };
95 
96 #ifndef _KERNEL
97 
98 #define	_PATH_PERFMON	"/dev/perfmon"
99 
100 #else
101 
102 /*
103  * Intra-kernel interface to performance monitoring counters
104  */
105 void	perfmon_init(void);
106 int	perfmon_avail(void);
107 int	perfmon_setup(int, unsigned int);
108 int	perfmon_get(int, unsigned int *);
109 int	perfmon_fini(int);
110 int	perfmon_start(int);
111 int	perfmon_stop(int);
112 int	perfmon_read(int, quad_t *);
113 int	perfmon_reset(int);
114 
115 #endif /* _KERNEL */
116 
117 /*
118  * Pentium Pro performance counters, from Appendix B.
119  */
120 /* Data Cache Unit */
121 #define	PMC6_DATA_MEM_REFS	0x43
122 #define	PMC6_DCU_LINES_IN	0x45
123 #define	PMC6_DCU_M_LINES_IN	0x46
124 #define	PMC6_DCU_M_LINES_OUT	0x47
125 #define	PMC6_DCU_MISS_OUTSTANDING 0x48
126 
127 /* Instruction Fetch Unit */
128 #define	PMC6_IFU_IFETCH		0x80
129 #define	PMC6_IFU_IFETCH_MISS	0x81
130 #define	PMC6_ITLB_MISS		0x85
131 #define	PMC6_IFU_MEM_STALL	0x86
132 #define	PMC6_ILD_STALL		0x87
133 
134 /* L2 Cache */
135 #define	PMC6_L2_IFETCH		0x28 /* MESI */
136 #define	PMC6_L2_LD		0x29 /* MESI */
137 #define	PMC6_L2_ST		0x2a /* MESI */
138 #define	PMC6_L2_LINES_IN	0x24
139 #define	PMC6_L2_LINES_OUT	0x26
140 #define	PMC6_L2_M_LINES_INM	0x25
141 #define	PMC6_L2_M_LINES_OUTM	0x27
142 #define	PMC6_L2_RQSTS		0x2e /* MESI */
143 #define	PMC6_L2_ADS		0x21
144 #define	PMC6_L2_DBUS_BUSY	0x22
145 #define	PMC6_L2_DBUS_BUSY_RD	0x23
146 
147 /* External Bus Logic */
148 #define	PMC6_BUS_DRDY_CLOCKS	0x62
149 #define	PMC6_BUS_LOCK_CLOCKS	0x63
150 #define	PMC6_BUS_REQ_OUTSTANDING 0x60
151 #define	PMC6_BUS_TRAN_BRD	0x65
152 #define	PMC6_BUS_TRAN_RFO	0x66
153 #define	PMC6_BUS_TRAN_WB	0x67
154 #define	PMC6_BUS_TRAN_IFETCH	0x68
155 #define	PMC6_BUS_TRAN_INVAL	0x69
156 #define	PMC6_BUS_TRAN_PWR	0x6a
157 #define	PMC6_BUS_TRAN_P		0x6b
158 #define	PMC6_BUS_TRAN_IO	0x6c
159 #define	PMC6_BUS_TRAN_DEF	0x6d
160 #define	PMC6_BUS_TRAN_BURST	0x6e
161 #define	PMC6_BUS_TRAN_ANY	0x70
162 #define	PMC6_BUS_TRAN_MEM	0x6f
163 #define	PMC6_BUS_DATA_RCV	0x64
164 #define	PMC6_BUS_BNR_DRV	0x61
165 #define	PMC6_BUS_HIT_DRV	0x7a
166 #define	PMC6_BUS_HITM_DRV	0x7b
167 #define	PMC6_BUS_SNOOP_STALL	0x7e
168 
169 /* Floating Point Unit */
170 #define	PMC6_FLOPS		0xc1 /* counter 0 only */
171 #define	PMC6_FP_COMP_OPS_EXE	0x10 /* counter 0 only */
172 #define	PMC6_FP_ASSIST		0x11 /* counter 1 only */
173 #define	PMC6_MUL		0x12 /* counter 1 only */
174 #define	PMC6_DIV		0x13 /* counter 1 only */
175 #define	PMC6_CYCLES_DIV_BUSY	0x14 /* counter 0 only */
176 
177 /* Memory Ordering */
178 #define	PMC6_LD_BLOCKS		0x03
179 #define	PMC6_SB_DRAINS		0x04
180 #define	PMC6_MISALIGN_MEM_REF	0x05
181 
182 /* Instruction Decoding and Retirement */
183 #define	PMC6_INST_RETIRED	0xc0
184 #define	PMC6_UOPS_RETIRED	0xc2
185 #define	PMC6_INST_DECODER	0xd0 /* (sic) */
186 
187 /* Interrupts */
188 #define	PMC6_HW_INT_RX		0xc8
189 #define	PMC6_CYCLES_INT_MASKED	0xc6
190 #define	PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
191 
192 /* Branches */
193 #define	PMC6_BR_INST_RETIRED	0xc4
194 #define	PMC6_BR_MISS_PRED_RETIRED 0xc5
195 #define	PMC6_BR_TAKEN_RETIRED	0xc9
196 #define	PMC6_BR_MISS_PRED_TAKEN_RET 0xca
197 #define	PMC6_BR_INST_DECODED	0xe0
198 #define	PMC6_BTB_MISSES		0xe2
199 #define	PMC6_BR_BOGUS		0xe4
200 #define	PMC6_BACLEARS		0xe6
201 
202 /* Stalls */
203 #define	PMC6_RESOURCE_STALLS	0xa2
204 #define	PMC6_PARTIAL_RAT_STALLS	0xd2
205 
206 /* Segment Register Loads */
207 #define	PMC6_SEGMENT_REG_LOADS	0x06
208 
209 /* Clocks */
210 #define	PMC6_CPU_CLK_UNHALTED	0x79
211 
212 /*
213  * Pentium Performance Counters
214  * This list comes from the Harvard people, not Intel.
215  */
216 #define	PMC5_DATA_READ		0
217 #define	PMC5_DATA_WRITE		1
218 #define	PMC5_DATA_TLB_MISS	2
219 #define	PMC5_DATA_READ_MISS	3
220 #define	PMC5_DATA_WRITE_MISS	4
221 #define	PMC5_WRITE_M_E		5
222 #define	PMC5_DATA_LINES_WBACK	6
223 #define	PMC5_DATA_CACHE_SNOOP	7
224 #define	PMC5_DATA_CACHE_SNOOP_HIT 8
225 #define	PMC5_MEM_ACCESS_BOTH	9
226 #define	PMC5_BANK_CONFLICTS	10
227 #define	PMC5_MISALIGNED_DATA	11
228 #define	PMC5_INST_READ		12
229 #define	PMC5_INST_TLB_MISS	13
230 #define	PMC5_INST_CACHE_MISS	14
231 #define	PMC5_SEGMENT_REG_LOAD	15
232 #define	PMC5_BRANCHES		18
233 #define	PMC5_BTB_HITS		19
234 #define	PMC5_BRANCH_TAKEN	20
235 #define	PMC5_PIPELINE_FLUSH	21
236 #define	PMC5_INST_EXECUTED	22
237 #define PMC5_INST_EXECUTED_V	23
238 #define	PMC5_BUS_UTILIZATION	24
239 #define	PMC5_WRITE_BACKUP_STALL	25
240 #define	PMC5_DATA_READ_STALL	26
241 #define	PMC5_WRITE_E_M_STALL	27
242 #define	PMC5_LOCKED_BUS		28
243 #define	PMC5_IO_CYCLE		29
244 #define	PMC5_NONCACHE_MEMORY	30
245 #define	PMC5_ADDR_GEN_INTERLOCK	31
246 #define	PMC5_FLOPS		34
247 #define	PMC5_BP0_MATCH		35
248 #define	PMC5_BP1_MATCH		36
249 #define	PMC5_BP2_MATCH		37
250 #define	PMC5_BP3_MATCH		38
251 #define	PMC5_HW_INTR		39
252 #define	PMC5_DATA_RW		40
253 #define	PMC5_DATA_RW_MISS	41
254 
255 #endif /* !_MACHINE_PERFMON_H_ */
256