1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 Konstantin Belousov <kib@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __MACHINE_COUNTER_H__ 32 #define __MACHINE_COUNTER_H__ 33 34 #include <sys/pcpu.h> 35 #ifdef INVARIANTS 36 #include <sys/proc.h> 37 #endif 38 #include <sys/systm.h> 39 #include <machine/md_var.h> 40 #include <machine/specialreg.h> 41 42 #define EARLY_COUNTER &__pcpu[0].pc_early_dummy_counter 43 44 #define counter_enter() do { \ 45 if ((cpu_feature & CPUID_CX8) == 0) \ 46 critical_enter(); \ 47 } while (0) 48 49 #define counter_exit() do { \ 50 if ((cpu_feature & CPUID_CX8) == 0) \ 51 critical_exit(); \ 52 } while (0) 53 54 static inline void 55 counter_64_inc_8b(uint64_t *p, int64_t inc) 56 { 57 58 __asm __volatile( 59 "movl %%fs:(%%esi),%%eax\n\t" 60 "movl %%fs:4(%%esi),%%edx\n" 61 "1:\n\t" 62 "movl %%eax,%%ebx\n\t" 63 "movl %%edx,%%ecx\n\t" 64 "addl (%%edi),%%ebx\n\t" 65 "adcl 4(%%edi),%%ecx\n\t" 66 "cmpxchg8b %%fs:(%%esi)\n\t" 67 "jnz 1b" 68 : 69 : "S" ((char *)p - (char *)&__pcpu[0]), "D" (&inc) 70 : "memory", "cc", "eax", "edx", "ebx", "ecx"); 71 } 72 73 #ifdef IN_SUBR_COUNTER_C 74 struct counter_u64_fetch_cx8_arg { 75 uint64_t res; 76 uint64_t *p; 77 }; 78 79 static uint64_t 80 counter_u64_read_one_8b(uint64_t *p) 81 { 82 uint32_t res_lo, res_high; 83 84 __asm __volatile( 85 "movl %%eax,%%ebx\n\t" 86 "movl %%edx,%%ecx\n\t" 87 "cmpxchg8b (%2)" 88 : "=a" (res_lo), "=d"(res_high) 89 : "SD" (p) 90 : "cc", "ebx", "ecx"); 91 return (res_lo + ((uint64_t)res_high << 32)); 92 } 93 94 static void 95 counter_u64_fetch_cx8_one(void *arg1) 96 { 97 struct counter_u64_fetch_cx8_arg *arg; 98 uint64_t val; 99 100 arg = arg1; 101 val = counter_u64_read_one_8b((uint64_t *)((char *)arg->p + 102 UMA_PCPU_ALLOC_SIZE * PCPU_GET(cpuid))); 103 atomic_add_64(&arg->res, val); 104 } 105 106 static inline uint64_t 107 counter_u64_fetch_inline(uint64_t *p) 108 { 109 struct counter_u64_fetch_cx8_arg arg; 110 uint64_t res; 111 int i; 112 113 res = 0; 114 if ((cpu_feature & CPUID_CX8) == 0) { 115 /* 116 * The machines without cmpxchg8b are not SMP. 117 * Disabling the preemption provides atomicity of the 118 * counter reading, since update is done in the 119 * critical section as well. 120 */ 121 critical_enter(); 122 CPU_FOREACH(i) { 123 res += *(uint64_t *)((char *)p + 124 UMA_PCPU_ALLOC_SIZE * i); 125 } 126 critical_exit(); 127 } else { 128 arg.p = p; 129 arg.res = 0; 130 smp_rendezvous(NULL, counter_u64_fetch_cx8_one, NULL, &arg); 131 res = arg.res; 132 } 133 return (res); 134 } 135 136 static inline void 137 counter_u64_zero_one_8b(uint64_t *p) 138 { 139 140 __asm __volatile( 141 "movl (%0),%%eax\n\t" 142 "movl 4(%0),%%edx\n" 143 "xorl %%ebx,%%ebx\n\t" 144 "xorl %%ecx,%%ecx\n\t" 145 "1:\n\t" 146 "cmpxchg8b (%0)\n\t" 147 "jnz 1b" 148 : 149 : "SD" (p) 150 : "memory", "cc", "eax", "edx", "ebx", "ecx"); 151 } 152 153 static void 154 counter_u64_zero_one_cpu(void *arg) 155 { 156 uint64_t *p; 157 158 p = (uint64_t *)((char *)arg + UMA_PCPU_ALLOC_SIZE * PCPU_GET(cpuid)); 159 counter_u64_zero_one_8b(p); 160 } 161 162 static inline void 163 counter_u64_zero_inline(counter_u64_t c) 164 { 165 int i; 166 167 if ((cpu_feature & CPUID_CX8) == 0) { 168 critical_enter(); 169 CPU_FOREACH(i) 170 *(uint64_t *)((char *)c + UMA_PCPU_ALLOC_SIZE * i) = 0; 171 critical_exit(); 172 } else { 173 smp_rendezvous(smp_no_rendezvous_barrier, 174 counter_u64_zero_one_cpu, smp_no_rendezvous_barrier, c); 175 } 176 } 177 #endif 178 179 #define counter_u64_add_protected(c, inc) do { \ 180 if ((cpu_feature & CPUID_CX8) == 0) { \ 181 CRITICAL_ASSERT(curthread); \ 182 *(uint64_t *)zpcpu_get(c) += (inc); \ 183 } else \ 184 counter_64_inc_8b((c), (inc)); \ 185 } while (0) 186 187 static inline void 188 counter_u64_add(counter_u64_t c, int64_t inc) 189 { 190 191 if ((cpu_feature & CPUID_CX8) == 0) { 192 critical_enter(); 193 *(uint64_t *)zpcpu_get(c) += inc; 194 critical_exit(); 195 } else { 196 counter_64_inc_8b(c, inc); 197 } 198 } 199 200 #endif /* ! __MACHINE_COUNTER_H__ */ 201