1/* 2 * P5020 Silicon Device Tree Source 3 * 4 * Copyright 2010-2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/dts-v1/; 36 37/ { 38 compatible = "fsl,P5020"; 39 #address-cells = <2>; 40 #size-cells = <2>; 41 interrupt-parent = <&mpic>; 42 43 aliases { 44 ccsr = &soc; 45 dcsr = &dcsr; 46 47 ethernet0 = &enet0; 48 ethernet1 = &enet1; 49 ethernet2 = &enet2; 50 ethernet3 = &enet3; 51 ethernet4 = &enet4; 52 ethernet5 = &enet5; 53 serial0 = &serial0; 54 serial1 = &serial1; 55 serial2 = &serial2; 56 serial3 = &serial3; 57 pci0 = &pci0; 58 pci1 = &pci1; 59 pci2 = &pci2; 60 pci3 = &pci3; 61 usb0 = &usb0; 62 usb1 = &usb1; 63 dma0 = &dma0; 64 dma1 = &dma1; 65 bman = &bman; 66 qman = &qman; 67 pme = &pme; 68 rman = &rman; 69 sdhc = &sdhc; 70 msi0 = &msi0; 71 msi1 = &msi1; 72 msi2 = &msi2; 73 74 crypto = &crypto; 75 sec_jr0 = &sec_jr0; 76 sec_jr1 = &sec_jr1; 77 sec_jr2 = &sec_jr2; 78 sec_jr3 = &sec_jr3; 79 rtic_a = &rtic_a; 80 rtic_b = &rtic_b; 81 rtic_c = &rtic_c; 82 rtic_d = &rtic_d; 83 sec_mon = &sec_mon; 84 85 raideng = &raideng; 86 raideng_jr0 = &raideng_jr0; 87 raideng_jr1 = &raideng_jr1; 88 raideng_jr2 = &raideng_jr2; 89 raideng_jr3 = &raideng_jr3; 90 91 fman0 = &fman0; 92 fman0_oh0 = &fman0_oh0; 93 fman0_oh1 = &fman0_oh1; 94 fman0_oh2 = &fman0_oh2; 95 fman0_oh3 = &fman0_oh3; 96 fman0_oh4 = &fman0_oh4; 97 fman0_oh5 = &fman0_oh5; 98 fman0_oh6 = &fman0_oh6; 99 fman0_rx0 = &fman0_rx0; 100 fman0_rx1 = &fman0_rx1; 101 fman0_rx2 = &fman0_rx2; 102 fman0_rx3 = &fman0_rx3; 103 fman0_rx4 = &fman0_rx4; 104 fman0_rx5 = &fman0_rx5; 105 }; 106 107 cpus { 108 #address-cells = <1>; 109 #size-cells = <0>; 110 111 cpu0: PowerPC,e5500@0 { 112 device_type = "cpu"; 113 reg = <0>; 114 bus-frequency = <799999998>; 115 next-level-cache = <&L2_0>; 116 L2_0: l2-cache { 117 next-level-cache = <&cpc>; 118 }; 119 }; 120 cpu1: PowerPC,e5500@1 { 121 device_type = "cpu"; 122 reg = <1>; 123 next-level-cache = <&L2_1>; 124 L2_1: l2-cache { 125 next-level-cache = <&cpc>; 126 }; 127 }; 128 }; 129 130 dcsr: dcsr@f00000000 { 131 #address-cells = <1>; 132 #size-cells = <1>; 133 compatible = "fsl,dcsr", "simple-bus"; 134 135 dcsr-epu@0 { 136 compatible = "fsl,dcsr-epu"; 137 interrupts = <52 2 0 0 138 84 2 0 0 139 85 2 0 0>; 140 interrupt-parent = <&mpic>; 141 reg = <0x0 0x1000>; 142 }; 143 dcsr-npc { 144 compatible = "fsl,dcsr-npc"; 145 reg = <0x1000 0x1000 0x1000000 0x8000>; 146 }; 147 dcsr-nxc@2000 { 148 compatible = "fsl,dcsr-nxc"; 149 reg = <0x2000 0x1000>; 150 }; 151 dcsr-corenet { 152 compatible = "fsl,dcsr-corenet"; 153 reg = <0x8000 0x1000 0xB0000 0x1000>; 154 }; 155 dcsr-dpaa@9000 { 156 compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa"; 157 reg = <0x9000 0x1000>; 158 }; 159 dcsr-ocn@11000 { 160 compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn"; 161 reg = <0x11000 0x1000>; 162 }; 163 dcsr-ddr@12000 { 164 compatible = "fsl,dcsr-ddr"; 165 dev-handle = <&ddr1>; 166 reg = <0x12000 0x1000>; 167 }; 168 dcsr-ddr@13000 { 169 compatible = "fsl,dcsr-ddr"; 170 dev-handle = <&ddr2>; 171 reg = <0x13000 0x1000>; 172 }; 173 dcsr-nal@18000 { 174 compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal"; 175 reg = <0x18000 0x1000>; 176 }; 177 dcsr-rcpm@22000 { 178 compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm"; 179 reg = <0x22000 0x1000>; 180 }; 181 dcsr-cpu-sb-proxy@40000 { 182 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 183 cpu-handle = <&cpu0>; 184 reg = <0x40000 0x1000>; 185 }; 186 dcsr-cpu-sb-proxy@41000 { 187 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 188 cpu-handle = <&cpu1>; 189 reg = <0x41000 0x1000>; 190 }; 191 }; 192 193 bman-portals@ff4000000 { 194 #address-cells = <0x1>; 195 #size-cells = <0x1>; 196 compatible = "fsl,bman-portals"; 197 ranges = <0x0 0xf 0xfde00000 0x200000>; 198 bman-portal@0 { 199 cell-index = <0x0>; 200 compatible = "fsl,p5020-bman-portal", "fsl,bman-portal"; 201 reg = <0x0 0x4000 0x100000 0x1000>; 202 interrupts = <105 2 0 0>; 203 }; 204 bman-portal@4000 { 205 cell-index = <0x1>; 206 compatible = "fsl,p5020-bman-portal", "fsl,bman-portal"; 207 reg = <0x4000 0x4000 0x101000 0x1000>; 208 interrupts = <107 2 0 0>; 209 }; 210 bman-portal@8000 { 211 cell-index = <2>; 212 compatible = "fsl,p5020-bman-portal", "fsl,bman-portal"; 213 reg = <0x8000 0x4000 0x102000 0x1000>; 214 interrupts = <109 2 0 0>; 215 }; 216 bman-portal@c000 { 217 cell-index = <0x3>; 218 compatible = "fsl,p5020-bman-portal", "fsl,bman-portal"; 219 reg = <0xc000 0x4000 0x103000 0x1000>; 220 interrupts = <111 2 0 0>; 221 }; 222 bman-portal@10000 { 223 cell-index = <0x4>; 224 compatible = "fsl,p5020-bman-portal", "fsl,bman-portal"; 225 reg = <0x10000 0x4000 0x104000 0x1000>; 226 interrupts = <113 2 0 0>; 227 }; 228 bman-portal@14000 { 229 cell-index = <0x5>; 230 compatible = "fsl,p5020-bman-portal", "fsl,bman-portal"; 231 reg = <0x14000 0x4000 0x105000 0x1000>; 232 interrupts = <115 2 0 0>; 233 }; 234 bman-portal@18000 { 235 cell-index = <0x6>; 236 compatible = "fsl,p5020-bman-portal", "fsl,bman-portal"; 237 reg = <0x18000 0x4000 0x106000 0x1000>; 238 interrupts = <117 2 0 0>; 239 }; 240 bman-portal@1c000 { 241 cell-index = <0x7>; 242 compatible = "fsl,p5020-bman-portal", "fsl,bman-portal"; 243 reg = <0x1c000 0x4000 0x107000 0x1000>; 244 interrupts = <119 2 0 0>; 245 }; 246 bman-portal@20000 { 247 cell-index = <0x8>; 248 compatible = "fsl,p5020-bman-portal", "fsl,bman-portal"; 249 reg = <0x20000 0x4000 0x108000 0x1000>; 250 interrupts = <121 2 0 0>; 251 }; 252 bman-portal@24000 { 253 cell-index = <0x9>; 254 compatible = "fsl,p5020-bman-portal", "fsl,bman-portal"; 255 reg = <0x24000 0x4000 0x109000 0x1000>; 256 interrupts = <123 2 0 0>; 257 }; 258 259 buffer-pool@0 { 260 compatible = "fsl,p5020-bpool", "fsl,bpool"; 261 fsl,bpid = <0>; 262 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>; 263 }; 264 }; 265 266 qman-portals@ff4200000 { 267 #address-cells = <0x1>; 268 #size-cells = <0x1>; 269 compatible = "fsl,qman-portals"; 270 ranges = <0x0 0xf 0xfdc00000 0x200000>; 271 qportal0: qman-portal@0 { 272 cell-index = <0x0>; 273 compatible = "fsl,p5020-qman-portal", "fsl,qman-portal"; 274 reg = <0x0 0x4000 0x100000 0x1000>; 275 interrupts = <104 0x2 0 0>; 276 fsl,qman-channel-id = <0x0>; 277 }; 278 279 qportal1: qman-portal@4000 { 280 cell-index = <0x1>; 281 compatible = "fsl,p5020-qman-portal", "fsl,qman-portal"; 282 reg = <0x4000 0x4000 0x101000 0x1000>; 283 interrupts = <106 0x2 0 0>; 284 fsl,qman-channel-id = <0x1>; 285 }; 286 287 qportal2: qman-portal@8000 { 288 cell-index = <0x2>; 289 compatible = "fsl,p5020-qman-portal", "fsl,qman-portal"; 290 reg = <0x8000 0x4000 0x102000 0x1000>; 291 interrupts = <108 0x2 0 0>; 292 fsl,qman-channel-id = <0x2>; 293 }; 294 295 qportal3: qman-portal@c000 { 296 cell-index = <0x3>; 297 compatible = "fsl,p5020-qman-portal", "fsl,qman-portal"; 298 reg = <0xc000 0x4000 0x103000 0x1000>; 299 interrupts = <110 0x2 0 0>; 300 fsl,qman-channel-id = <0x3>; 301 }; 302 303 qportal4: qman-portal@10000 { 304 cell-index = <0x4>; 305 compatible = "fsl,p5020-qman-portal", "fsl,qman-portal"; 306 reg = <0x10000 0x4000 0x104000 0x1000>; 307 interrupts = <112 0x2 0 0>; 308 fsl,qman-channel-id = <0x4>; 309 }; 310 311 qportal5: qman-portal@14000 { 312 cell-index = <0x5>; 313 compatible = "fsl,p5020-qman-portal", "fsl,qman-portal"; 314 reg = <0x14000 0x4000 0x105000 0x1000>; 315 interrupts = <114 0x2 0 0>; 316 fsl,qman-channel-id = <0x5>; 317 }; 318 319 qportal6: qman-portal@18000 { 320 cell-index = <0x6>; 321 compatible = "fsl,p5020-qman-portal", "fsl,qman-portal"; 322 reg = <0x18000 0x4000 0x106000 0x1000>; 323 interrupts = <116 0x2 0 0>; 324 fsl,qman-channel-id = <0x6>; 325 }; 326 327 qportal7: qman-portal@1c000 { 328 cell-index = <0x7>; 329 compatible = "fsl,p5020-qman-portal", "fsl,qman-portal"; 330 reg = <0x1c000 0x4000 0x107000 0x1000>; 331 interrupts = <118 0x2 0 0>; 332 fsl,qman-channel-id = <0x7>; 333 }; 334 335 qportal8: qman-portal@20000 { 336 cell-index = <0x8>; 337 compatible = "fsl,p5020-qman-portal", "fsl,qman-portal"; 338 reg = <0x20000 0x4000 0x108000 0x1000>; 339 interrupts = <120 0x2 0 0>; 340 fsl,qman-channel-id = <0x8>; 341 }; 342 343 qportal9: qman-portal@24000 { 344 cell-index = <0x9>; 345 compatible = "fsl,p5020-qman-portal", "fsl,qman-portal"; 346 reg = <0x24000 0x4000 0x109000 0x1000>; 347 interrupts = <122 0x2 0 0>; 348 fsl,qman-channel-id = <0x9>; 349 }; 350 351 qpool1: qman-pool@1 { 352 cell-index = <1>; 353 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 354 fsl,qman-channel-id = <0x21>; 355 }; 356 357 qpool2: qman-pool@2 { 358 cell-index = <2>; 359 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 360 fsl,qman-channel-id = <0x22>; 361 }; 362 363 qpool3: qman-pool@3 { 364 cell-index = <3>; 365 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 366 fsl,qman-channel-id = <0x23>; 367 }; 368 369 qpool4: qman-pool@4 { 370 cell-index = <4>; 371 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 372 fsl,qman-channel-id = <0x24>; 373 }; 374 375 qpool5: qman-pool@5 { 376 cell-index = <5>; 377 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 378 fsl,qman-channel-id = <0x25>; 379 }; 380 381 qpool6: qman-pool@6 { 382 cell-index = <6>; 383 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 384 fsl,qman-channel-id = <0x26>; 385 }; 386 387 qpool7: qman-pool@7 { 388 cell-index = <7>; 389 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 390 fsl,qman-channel-id = <0x27>; 391 }; 392 393 qpool8: qman-pool@8 { 394 cell-index = <8>; 395 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 396 fsl,qman-channel-id = <0x28>; 397 }; 398 399 qpool9: qman-pool@9 { 400 cell-index = <9>; 401 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 402 fsl,qman-channel-id = <0x29>; 403 }; 404 405 qpool10: qman-pool@10 { 406 cell-index = <10>; 407 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 408 fsl,qman-channel-id = <0x2a>; 409 }; 410 411 qpool11: qman-pool@11 { 412 cell-index = <11>; 413 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 414 fsl,qman-channel-id = <0x2b>; 415 }; 416 417 qpool12: qman-pool@12 { 418 cell-index = <12>; 419 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 420 fsl,qman-channel-id = <0x2c>; 421 }; 422 423 qpool13: qman-pool@13 { 424 cell-index = <13>; 425 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 426 fsl,qman-channel-id = <0x2d>; 427 }; 428 429 qpool14: qman-pool@14 { 430 cell-index = <14>; 431 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 432 fsl,qman-channel-id = <0x2e>; 433 }; 434 435 qpool15: qman-pool@15 { 436 cell-index = <15>; 437 compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel"; 438 fsl,qman-channel-id = <0x2f>; 439 }; 440 }; 441 442 soc: soc@ffe000000 { 443 #address-cells = <1>; 444 #size-cells = <1>; 445 device_type = "soc"; 446 compatible = "simple-bus"; 447 448 bus-frequency = <0>; // Filled out by kernel. 449 450 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 451 reg = <0xf 0xfe000000 0 0x00001000>; 452 453 soc-sram-error { 454 compatible = "fsl,soc-sram-error"; 455 interrupts = <16 2 1 29>; 456 }; 457 458 corenet-law@0 { 459 compatible = "fsl,corenet-law"; 460 reg = <0x0 0x1000>; 461 fsl,num-laws = <32>; 462 }; 463 464 ddr1: memory-controller@8000 { 465 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; 466 reg = <0x8000 0x1000>; 467 interrupts = <16 2 1 23>; 468 }; 469 470 ddr2: memory-controller@9000 { 471 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; 472 reg = <0x9000 0x1000>; 473 interrupts = <16 2 1 22>; 474 }; 475 476 cpc: l3-cache-controller@10000 { 477 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache"; 478 reg = <0x10000 0x1000 479 0x11000 0x1000>; 480 interrupts = <16 2 1 27 481 16 2 1 26>; 482 }; 483 484 corenet-cf@18000 { 485 compatible = "fsl,corenet-cf"; 486 reg = <0x18000 0x1000>; 487 interrupts = <16 2 1 31>; 488 fsl,ccf-num-csdids = <32>; 489 fsl,ccf-num-snoopids = <32>; 490 }; 491 492 iommu@20000 { 493 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 494 reg = <0x20000 0x4000>; 495 interrupts = < 496 24 2 0 0 497 16 2 1 30>; 498 }; 499 500 mpic: pic@40000 { 501 clock-frequency = <0>; 502 interrupt-controller; 503 #address-cells = <0>; 504 #interrupt-cells = <4>; 505 reg = <0x40000 0x40000>; 506 compatible = "fsl,mpic", "chrp,open-pic"; 507 device_type = "open-pic"; 508 }; 509 510 msi0: msi@41600 { 511 compatible = "fsl,mpic-msi"; 512 reg = <0x41600 0x200>; 513 msi-available-ranges = <0 0x100>; 514 interrupts = < 515 0xe0 0 0 0 516 0xe1 0 0 0 517 0xe2 0 0 0 518 0xe3 0 0 0 519 0xe4 0 0 0 520 0xe5 0 0 0 521 0xe6 0 0 0 522 0xe7 0 0 0>; 523 }; 524 525 msi1: msi@41800 { 526 compatible = "fsl,mpic-msi"; 527 reg = <0x41800 0x200>; 528 msi-available-ranges = <0 0x100>; 529 interrupts = < 530 0xe8 0 0 0 531 0xe9 0 0 0 532 0xea 0 0 0 533 0xeb 0 0 0 534 0xec 0 0 0 535 0xed 0 0 0 536 0xee 0 0 0 537 0xef 0 0 0>; 538 }; 539 540 msi2: msi@41a00 { 541 compatible = "fsl,mpic-msi"; 542 reg = <0x41a00 0x200>; 543 msi-available-ranges = <0 0x100>; 544 interrupts = < 545 0xf0 0 0 0 546 0xf1 0 0 0 547 0xf2 0 0 0 548 0xf3 0 0 0 549 0xf4 0 0 0 550 0xf5 0 0 0 551 0xf6 0 0 0 552 0xf7 0 0 0>; 553 }; 554 555 guts: global-utilities@e0000 { 556 compatible = "fsl,qoriq-device-config-1.0"; 557 reg = <0xe0000 0xe00>; 558 fsl,has-rstcr; 559 #sleep-cells = <1>; 560 fsl,liodn-bits = <12>; 561 }; 562 563 pins: global-utilities@e0e00 { 564 compatible = "fsl,qoriq-pin-control-1.0"; 565 reg = <0xe0e00 0x200>; 566 #sleep-cells = <2>; 567 }; 568 569 clockgen: global-utilities@e1000 { 570 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; 571 reg = <0xe1000 0x1000>; 572 clock-frequency = <0>; 573 }; 574 575 rcpm: global-utilities@e2000 { 576 compatible = "fsl,qoriq-rcpm-1.0"; 577 reg = <0xe2000 0x1000>; 578 #sleep-cells = <1>; 579 }; 580 581 sfp: sfp@e8000 { 582 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0"; 583 reg = <0xe8000 0x1000>; 584 }; 585 586 serdes: serdes@ea000 { 587 compatible = "fsl,p5020-serdes"; 588 reg = <0xea000 0x1000>; 589 }; 590 591 dma0: dma@100300 { 592 #address-cells = <1>; 593 #size-cells = <1>; 594 compatible = "fsl,p5020-dma", "fsl,eloplus-dma"; 595 reg = <0x100300 0x4>; 596 ranges = <0x0 0x100100 0x200>; 597 cell-index = <0>; 598 dma-channel@0 { 599 compatible = "fsl,p5020-dma-channel", 600 "fsl,eloplus-dma-channel"; 601 reg = <0x0 0x80>; 602 cell-index = <0>; 603 interrupts = <28 2 0 0>; 604 }; 605 dma-channel@80 { 606 compatible = "fsl,p5020-dma-channel", 607 "fsl,eloplus-dma-channel"; 608 reg = <0x80 0x80>; 609 cell-index = <1>; 610 interrupts = <29 2 0 0>; 611 }; 612 dma-channel@100 { 613 compatible = "fsl,p5020-dma-channel", 614 "fsl,eloplus-dma-channel"; 615 reg = <0x100 0x80>; 616 cell-index = <2>; 617 interrupts = <30 2 0 0>; 618 }; 619 dma-channel@180 { 620 compatible = "fsl,p5020-dma-channel", 621 "fsl,eloplus-dma-channel"; 622 reg = <0x180 0x80>; 623 cell-index = <3>; 624 interrupts = <31 2 0 0>; 625 }; 626 }; 627 628 dma1: dma@101300 { 629 #address-cells = <1>; 630 #size-cells = <1>; 631 compatible = "fsl,p5020-dma", "fsl,eloplus-dma"; 632 reg = <0x101300 0x4>; 633 ranges = <0x0 0x101100 0x200>; 634 cell-index = <1>; 635 dma-channel@0 { 636 compatible = "fsl,p5020-dma-channel", 637 "fsl,eloplus-dma-channel"; 638 reg = <0x0 0x80>; 639 cell-index = <0>; 640 interrupts = <32 2 0 0>; 641 }; 642 dma-channel@80 { 643 compatible = "fsl,p5020-dma-channel", 644 "fsl,eloplus-dma-channel"; 645 reg = <0x80 0x80>; 646 cell-index = <1>; 647 interrupts = <33 2 0 0>; 648 }; 649 dma-channel@100 { 650 compatible = "fsl,p5020-dma-channel", 651 "fsl,eloplus-dma-channel"; 652 reg = <0x100 0x80>; 653 cell-index = <2>; 654 interrupts = <34 2 0 0>; 655 }; 656 dma-channel@180 { 657 compatible = "fsl,p5020-dma-channel", 658 "fsl,eloplus-dma-channel"; 659 reg = <0x180 0x80>; 660 cell-index = <3>; 661 interrupts = <35 2 0 0>; 662 }; 663 }; 664 665 spi@110000 { 666 #address-cells = <1>; 667 #size-cells = <0>; 668 compatible = "fsl,p5020-espi", "fsl,mpc8536-espi"; 669 reg = <0x110000 0x1000>; 670 interrupts = <53 0x2 0 0>; 671 fsl,espi-num-chipselects = <4>; 672 }; 673 674 sdhc: sdhc@114000 { 675 compatible = "fsl,p5020-esdhc", "fsl,esdhc"; 676 reg = <0x114000 0x1000>; 677 interrupts = <48 2 0 0>; 678 sdhci,auto-cmd12; 679 clock-frequency = <0>; 680 }; 681 682 i2c@118000 { 683 #address-cells = <1>; 684 #size-cells = <0>; 685 cell-index = <0>; 686 compatible = "fsl-i2c"; 687 reg = <0x118000 0x100>; 688 interrupts = <38 2 0 0>; 689 dfsrr; 690 }; 691 692 i2c@118100 { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 cell-index = <1>; 696 compatible = "fsl-i2c"; 697 reg = <0x118100 0x100>; 698 interrupts = <38 2 0 0>; 699 dfsrr; 700 }; 701 702 i2c@119000 { 703 #address-cells = <1>; 704 #size-cells = <0>; 705 cell-index = <2>; 706 compatible = "fsl-i2c"; 707 reg = <0x119000 0x100>; 708 interrupts = <39 2 0 0>; 709 dfsrr; 710 }; 711 712 i2c@119100 { 713 #address-cells = <1>; 714 #size-cells = <0>; 715 cell-index = <3>; 716 compatible = "fsl-i2c"; 717 reg = <0x119100 0x100>; 718 interrupts = <39 2 0 0>; 719 dfsrr; 720 }; 721 722 serial0: serial@11c500 { 723 cell-index = <0>; 724 device_type = "serial"; 725 compatible = "ns16550"; 726 reg = <0x11c500 0x100>; 727 clock-frequency = <0>; 728 interrupts = <36 2 0 0>; 729 }; 730 731 serial1: serial@11c600 { 732 cell-index = <1>; 733 device_type = "serial"; 734 compatible = "ns16550"; 735 reg = <0x11c600 0x100>; 736 clock-frequency = <0>; 737 interrupts = <36 2 0 0>; 738 }; 739 740 serial2: serial@11d500 { 741 cell-index = <2>; 742 device_type = "serial"; 743 compatible = "ns16550"; 744 reg = <0x11d500 0x100>; 745 clock-frequency = <0>; 746 interrupts = <37 2 0 0>; 747 }; 748 749 serial3: serial@11d600 { 750 cell-index = <3>; 751 device_type = "serial"; 752 compatible = "ns16550"; 753 reg = <0x11d600 0x100>; 754 clock-frequency = <0>; 755 interrupts = <37 2 0 0>; 756 }; 757 758 gpio0: gpio@130000 { 759 compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio"; 760 reg = <0x130000 0x1000>; 761 interrupts = <55 2 0 0>; 762 #gpio-cells = <2>; 763 gpio-controller; 764 }; 765 766 rman: rman@1e0000 { 767 compatible = "fsl,rman"; 768 #address-cells = <1>; 769 #size-cells = <1>; 770 ranges = <0x0 0x1e0000 0x20000>; 771 reg = <0x1e0000 0x20000>; 772 interrupts = <16 2 1 11>; /* err_irq */ 773 fsl,qman-channels-id = <0x62 0x63>; 774 775 inbound-block@0 { 776 compatible = "fsl,rman-inbound-block"; 777 reg = <0x0 0x800>; 778 }; 779 global-cfg@b00 { 780 compatible = "fsl,rman-global-cfg"; 781 reg = <0xb00 0x500>; 782 }; 783 inbound-block@1000 { 784 compatible = "fsl,rman-inbound-block"; 785 reg = <0x1000 0x800>; 786 }; 787 inbound-block@2000 { 788 compatible = "fsl,rman-inbound-block"; 789 reg = <0x2000 0x800>; 790 }; 791 inbound-block@3000 { 792 compatible = "fsl,rman-inbound-block"; 793 reg = <0x3000 0x800>; 794 }; 795 }; 796 797 usb0: usb@210000 { 798 compatible = "fsl,p5020-usb2-mph", 799 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; 800 reg = <0x210000 0x1000>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 interrupts = <44 0x2 0 0>; 804 phy_type = "utmi"; 805 port0; 806 }; 807 808 usb1: usb@211000 { 809 compatible = "fsl,p5020-usb2-dr", 810 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; 811 reg = <0x211000 0x1000>; 812 #address-cells = <1>; 813 #size-cells = <0>; 814 interrupts = <45 0x2 0 0>; 815 dr_mode = "host"; 816 phy_type = "utmi"; 817 }; 818 819 sata@220000 { 820 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2"; 821 reg = <0x220000 0x1000>; 822 interrupts = <68 0x2 0 0>; 823 }; 824 825 sata@221000 { 826 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2"; 827 reg = <0x221000 0x1000>; 828 interrupts = <69 0x2 0 0>; 829 }; 830 831 crypto: crypto@300000 { 832 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0"; 833 #address-cells = <1>; 834 #size-cells = <1>; 835 reg = <0x300000 0x10000>; 836 ranges = <0 0x300000 0x10000>; 837 interrupts = <92 2 0 0>; 838 839 sec_jr0: jr@1000 { 840 compatible = "fsl,sec-v4.2-job-ring", 841 "fsl,sec-v4.0-job-ring"; 842 reg = <0x1000 0x1000>; 843 interrupts = <88 2 0 0>; 844 }; 845 846 sec_jr1: jr@2000 { 847 compatible = "fsl,sec-v4.2-job-ring", 848 "fsl,sec-v4.0-job-ring"; 849 reg = <0x2000 0x1000>; 850 interrupts = <89 2 0 0>; 851 }; 852 853 sec_jr2: jr@3000 { 854 compatible = "fsl,sec-v4.2-job-ring", 855 "fsl,sec-v4.0-job-ring"; 856 reg = <0x3000 0x1000>; 857 interrupts = <90 2 0 0>; 858 }; 859 860 sec_jr3: jr@4000 { 861 compatible = "fsl,sec-v4.2-job-ring", 862 "fsl,sec-v4.0-job-ring"; 863 reg = <0x4000 0x1000>; 864 interrupts = <91 2 0 0>; 865 }; 866 867 rtic@6000 { 868 compatible = "fsl,sec-v4.2-rtic", 869 "fsl,sec-v4.0-rtic"; 870 #address-cells = <1>; 871 #size-cells = <1>; 872 reg = <0x6000 0x100>; 873 ranges = <0x0 0x6100 0xe00>; 874 875 rtic_a: rtic-a@0 { 876 compatible = "fsl,sec-v4.2-rtic-memory", 877 "fsl,sec-v4.0-rtic-memory"; 878 reg = <0x00 0x20 0x100 0x80>; 879 }; 880 881 rtic_b: rtic-b@20 { 882 compatible = "fsl,sec-v4.2-rtic-memory", 883 "fsl,sec-v4.0-rtic-memory"; 884 reg = <0x20 0x20 0x200 0x80>; 885 }; 886 887 rtic_c: rtic-c@40 { 888 compatible = "fsl,sec-v4.2-rtic-memory", 889 "fsl,sec-v4.0-rtic-memory"; 890 reg = <0x40 0x20 0x300 0x80>; 891 }; 892 893 rtic_d: rtic-d@60 { 894 compatible = "fsl,sec-v4.2-rtic-memory", 895 "fsl,sec-v4.0-rtic-memory"; 896 reg = <0x60 0x20 0x500 0x80>; 897 }; 898 }; 899 }; 900 901 sec_mon: sec_mon@314000 { 902 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon"; 903 reg = <0x314000 0x1000>; 904 interrupts = <93 2 0 0>; 905 }; 906 907 raideng: raideng@320000 { 908 compatible = "fsl,raideng-v1.0"; 909 #address-cells = <1>; 910 #size-cells = <1>; 911 reg = <0x320000 0x10000>; 912 ranges = <0 0x320000 0x10000>; 913 914 raideng_jq0@1000 { 915 compatible = "fsl,raideng-v1.0-job-queue"; 916 #address-cells = <1>; 917 #size-cells = <1>; 918 reg = <0x1000 0x1000>; 919 ranges = <0x0 0x1000 0x1000>; 920 921 raideng_jr0: jr@0 { 922 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring"; 923 reg = <0x0 0x400>; 924 interrupts = <139 2 0 0>; 925 interrupt-parent = <&mpic>; 926 }; 927 928 raideng_jr1: jr@400 { 929 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring"; 930 reg = <0x400 0x400>; 931 interrupts = <140 2 0 0>; 932 interrupt-parent = <&mpic>; 933 }; 934 }; 935 936 raideng_jq1@2000 { 937 compatible = "fsl,raideng-v1.0-job-queue"; 938 #address-cells = <1>; 939 #size-cells = <1>; 940 reg = <0x2000 0x1000>; 941 ranges = <0x0 0x2000 0x1000>; 942 943 raideng_jr2: jr@0 { 944 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring"; 945 reg = <0x0 0x400>; 946 interrupts = <141 2 0 0>; 947 interrupt-parent = <&mpic>; 948 }; 949 950 raideng_jr3: jr@400 { 951 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring"; 952 reg = <0x400 0x400>; 953 interrupts = <142 2 0 0>; 954 interrupt-parent = <&mpic>; 955 }; 956 }; 957 }; 958 959 pme: pme@316000 { 960 compatible = "fsl,pme"; 961 reg = <0x316000 0x10000>; 962 /* "fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */ 963 /* "fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */ 964 interrupts = <16 2 1 5>; 965 }; 966 967 qman: qman@318000 { 968 compatible = "fsl,p5020-qman", "fsl,qman"; 969 reg = <0x318000 0x1000>; 970 interrupts = <16 2 1 3>; 971 /* Commented out, use default allocation */ 972 /* "fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */ 973 /* "fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */ 974 }; 975 976 bman: bman@31a000 { 977 compatible = "fsl,p5020-bman", "fsl,bman"; 978 reg = <0x31a000 0x1000>; 979 interrupts = <16 2 1 2>; 980 /* Same as "fsl,qman-*, use default allocation */ 981 /* "fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */ 982 }; 983 984 fman0: fman@400000 { 985 #address-cells = <1>; 986 #size-cells = <1>; 987 cell-index = <0>; 988 compatible = "fsl,p5020-fman", "fsl,fman", "simple-bus"; 989 ranges = <0 0x400000 0x100000>; 990 reg = <0x400000 0x100000>; 991 clock-frequency = <0>; 992 interrupts = < 993 96 2 0 0 994 16 2 1 1>; 995 996 cc@0 { 997 compatible = "fsl,p5020-fman-cc", "fsl,fman-cc"; 998 }; 999 1000 parser@c7000 { 1001 compatible = "fsl,p5020-fman-parser", "fsl,fman-parser"; 1002 reg = <0xc7000 0x1000>; 1003 }; 1004 1005 keygen@c1000 { 1006 compatible = "fsl,p5020-fman-keygen", "fsl,fman-keygen"; 1007 reg = <0xc1000 0x1000>; 1008 }; 1009 1010 policer@c0000 { 1011 compatible = "fsl,p5020-fman-policer", "fsl,fman-policer"; 1012 reg = <0xc0000 0x1000>; 1013 }; 1014 1015 muram@0 { 1016 compatible = "fsl,p5020-fman-muram", "fsl,fman-muram"; 1017 reg = <0x0 0x28000>; 1018 }; 1019 1020 bmi@80000 { 1021 compatible = "fsl,p5020-fman-bmi", "fsl,fman-bmi"; 1022 reg = <0x80000 0x400>; 1023 }; 1024 1025 qmi@80400 { 1026 compatible = "fsl,p5020-fman-qmi", "fsl,fman-qmi"; 1027 reg = <0x80400 0x400>; 1028 }; 1029 1030 fman0_rx0: port@88000 { 1031 cell-index = <0>; 1032 compatible = "fsl,p5020-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 1033 reg = <0x88000 0x1000>; 1034 }; 1035 fman0_rx1: port@89000 { 1036 cell-index = <1>; 1037 compatible = "fsl,p5020-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 1038 reg = <0x89000 0x1000>; 1039 }; 1040 fman0_rx2: port@8a000 { 1041 cell-index = <2>; 1042 compatible = "fsl,p5020-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 1043 reg = <0x8a000 0x1000>; 1044 }; 1045 fman0_rx3: port@8b000 { 1046 cell-index = <3>; 1047 compatible = "fsl,p5020-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 1048 reg = <0x8b000 0x1000>; 1049 }; 1050 fman0_rx4: port@8c000 { 1051 cell-index = <4>; 1052 compatible = "fsl,p5020-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 1053 reg = <0x8c000 0x1000>; 1054 }; 1055 fman0_rx5: port@90000 { 1056 cell-index = <0>; 1057 compatible = "fsl,p5020-fman-port-10g-rx", "fsl,fman-port-10g-rx"; 1058 reg = <0x90000 0x1000>; 1059 }; 1060 1061 fman0_tx5: port@b0000 { 1062 cell-index = <0>; 1063 compatible = "fsl,p5020-fman-port-10g-tx", "fsl,fman-port-10g-tx"; 1064 reg = <0xb0000 0x1000>; 1065 fsl,qman-channel-id = <0x40>; 1066 }; 1067 fman0_tx0: port@a8000 { 1068 cell-index = <0>; 1069 compatible = "fsl,p5020-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1070 reg = <0xa8000 0x1000>; 1071 fsl,qman-channel-id = <0x41>; 1072 }; 1073 fman0_tx1: port@a9000 { 1074 cell-index = <1>; 1075 compatible = "fsl,p5020-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1076 reg = <0xa9000 0x1000>; 1077 fsl,qman-channel-id = <0x42>; 1078 }; 1079 fman0_tx2: port@aa000 { 1080 cell-index = <2>; 1081 compatible = "fsl,p5020-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1082 reg = <0xaa000 0x1000>; 1083 fsl,qman-channel-id = <0x43>; 1084 }; 1085 fman0_tx3: port@ab000 { 1086 cell-index = <3>; 1087 compatible = "fsl,p5020-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1088 reg = <0xab000 0x1000>; 1089 fsl,qman-channel-id = <0x44>; 1090 }; 1091 fman0_tx4: port@ac000 { 1092 cell-index = <4>; 1093 compatible = "fsl,p5020-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1094 reg = <0xac000 0x1000>; 1095 fsl,qman-channel-id = <0x45>; 1096 }; 1097 1098 fman0_oh0: port@81000 { 1099 cell-index = <0>; 1100 compatible = "fsl,p5020-fman-port-oh", "fsl,fman-port-oh"; 1101 reg = <0x81000 0x1000>; 1102 fsl,qman-channel-id = <0x46>; 1103 }; 1104 fman0_oh1: port@82000 { 1105 cell-index = <1>; 1106 compatible = "fsl,p5020-fman-port-oh", "fsl,fman-port-oh"; 1107 reg = <0x82000 0x1000>; 1108 fsl,qman-channel-id = <0x47>; 1109 }; 1110 fman0_oh2: port@83000 { 1111 cell-index = <2>; 1112 compatible = "fsl,p5020-fman-port-oh", "fsl,fman-port-oh"; 1113 reg = <0x83000 0x1000>; 1114 fsl,qman-channel-id = <0x48>; 1115 }; 1116 fman0_oh3: port@84000 { 1117 cell-index = <3>; 1118 compatible = "fsl,p5020-fman-port-oh", "fsl,fman-port-oh"; 1119 reg = <0x84000 0x1000>; 1120 fsl,qman-channel-id = <0x49>; 1121 }; 1122 fman0_oh4: port@85000 { 1123 cell-index = <4>; 1124 compatible = "fsl,p5020-fman-port-oh", "fsl,fman-port-oh"; 1125 reg = <0x85000 0x1000>; 1126 fsl,qman-channel-id = <0x4a>; 1127 }; 1128 fman0_oh5: port@86000 { 1129 cell-index = <5>; 1130 compatible = "fsl,p5020-fman-port-oh", "fsl,fman-port-oh"; 1131 reg = <0x86000 0x1000>; 1132 fsl,qman-channel-id = <0x4b>; 1133 }; 1134 fman0_oh6: port@87000 { 1135 cell-index = <6>; 1136 compatible = "fsl,p5020-fman-port-oh", "fsl,fman-port-oh"; 1137 reg = <0x87000 0x1000>; 1138 }; 1139 1140 enet0: ethernet@e0000 { 1141 cell-index = <0>; 1142 compatible = "fsl,p5020-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1143 reg = <0xe0000 0x1000>; 1144 fsl,port-handles = <&fman0_rx0 &fman0_tx0>; 1145 ptimer-handle = <&ptp_timer0>; 1146 }; 1147 1148 mdio0: mdio@e1120 { 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 compatible = "fsl,fman-mdio"; 1152 reg = <0xe1120 0xee0>; 1153 interrupts = <100 1 0 0>; 1154 }; 1155 1156 enet1: ethernet@e2000 { 1157 cell-index = <1>; 1158 compatible = "fsl,p5020-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1159 reg = <0xe2000 0x1000>; 1160 fsl,port-handles = <&fman0_rx1 &fman0_tx1>; 1161 ptimer-handle = <&ptp_timer0>; 1162 }; 1163 1164 mdio@e3120 { 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 compatible = "fsl,fman-tbi"; 1168 reg = <0xe3120 0xee0>; 1169 interrupts = <100 1 0 0>; 1170 }; 1171 1172 enet2: ethernet@e4000 { 1173 cell-index = <2>; 1174 compatible = "fsl,p5020-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1175 reg = <0xe4000 0x1000>; 1176 fsl,port-handles = <&fman0_rx2 &fman0_tx2>; 1177 ptimer-handle = <&ptp_timer0>; 1178 }; 1179 1180 mdio@e5120 { 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 compatible = "fsl,fman-tbi"; 1184 reg = <0xe5120 0xee0>; 1185 interrupts = <100 1 0 0>; 1186 }; 1187 1188 enet3: ethernet@e6000 { 1189 cell-index = <3>; 1190 compatible = "fsl,p5020-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1191 reg = <0xe6000 0x1000>; 1192 fsl,port-handles = <&fman0_rx3 &fman0_tx3>; 1193 ptimer-handle = <&ptp_timer0>; 1194 }; 1195 1196 mdio@e7120 { 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 compatible = "fsl,fman-tbi"; 1200 reg = <0xe7120 0xee0>; 1201 interrupts = <100 1 0 0>; 1202 }; 1203 1204 enet4: ethernet@e8000 { 1205 cell-index = <4>; 1206 compatible = "fsl,p5020-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1207 reg = <0xe8000 0x1000>; 1208 fsl,port-handles = <&fman0_rx4 &fman0_tx4>; 1209 ptimer-handle = <&ptp_timer0>; 1210 }; 1211 1212 mdio@e9120 { 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 compatible = "fsl,fman-tbi"; 1216 reg = <0xe9120 0xee0>; 1217 interrupts = <100 1 0 0>; 1218 }; 1219 1220 enet5: ethernet@f0000 { 1221 cell-index = <0>; 1222 compatible = "fsl,p5020-fman-10g-mac", "fsl,fman-10g-mac", "fsl,fman-xgec"; 1223 reg = <0xf0000 0x1000>; 1224 fsl,port-handles = <&fman0_rx5 &fman0_tx5>; 1225 }; 1226 1227 mdio@f1000 { 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 compatible = "fsl,fman-xmdio"; 1231 reg = <0xf1000 0x1000>; 1232 interrupts = <100 1 0 0>; 1233 }; 1234 1235 ptp_timer0: rtc@fe000 { 1236 compatible = "fsl,fman-rtc"; 1237 reg = <0xfe000 0x1000>; 1238 }; 1239 }; 1240 }; 1241 1242 rapidio@ffe0c0000 { 1243 compatible = "fsl,srio"; 1244 interrupts = <16 2 1 11>; 1245 #address-cells = <2>; 1246 #size-cells = <2>; 1247 ranges; 1248 1249 port1 { 1250 #address-cells = <2>; 1251 #size-cells = <2>; 1252 cell-index = <1>; 1253 }; 1254 1255 port2 { 1256 #address-cells = <2>; 1257 #size-cells = <2>; 1258 cell-index = <2>; 1259 }; 1260 }; 1261 1262 localbus@ffe124000 { 1263 compatible = "fsl,p5020-rev1.0-elbc", "simple-bus", "fsl,elbc"; 1264 interrupts = < 1265 25 2 0 0 1266 16 2 1 19 1267 >; 1268 #address-cells = <2>; 1269 #size-cells = <1>; 1270 }; 1271 1272 pci0: pcie@ffe200000 { 1273 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; 1274 device_type = "pci"; 1275 status = "okay"; 1276 #size-cells = <2>; 1277 #address-cells = <3>; 1278 cell-index = <0>; 1279 bus-range = <0x0 0xff>; 1280 clock-frequency = <0x1fca055>; 1281 fsl,msi = <&msi0>; 1282 interrupts = <16 2 1 15>; 1283 1284 pcie@0 { 1285 reg = <0 0 0 0 0>; 1286 #interrupt-cells = <1>; 1287 #size-cells = <2>; 1288 #address-cells = <3>; 1289 device_type = "pci"; 1290 interrupts = <16 2 1 15>; 1291 interrupt-map-mask = <0xf800 0 0 7>; 1292 interrupt-map = < 1293 /* IDSEL 0x0 */ 1294 0000 0 0 1 &mpic 40 1 0 0 1295 0000 0 0 2 &mpic 1 1 0 0 1296 0000 0 0 3 &mpic 2 1 0 0 1297 0000 0 0 4 &mpic 3 1 0 0 1298 >; 1299 }; 1300 }; 1301 1302 pci1: pcie@ffe201000 { 1303 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; 1304 device_type = "pci"; 1305 status = "disabled"; 1306 #size-cells = <2>; 1307 #address-cells = <3>; 1308 cell-index = <1>; 1309 bus-range = <0 0xff>; 1310 clock-frequency = <0x1fca055>; 1311 fsl,msi = <&msi1>; 1312 interrupts = <16 2 1 14>; 1313 pcie@0 { 1314 reg = <0 0 0 0 0>; 1315 #interrupt-cells = <1>; 1316 #size-cells = <2>; 1317 #address-cells = <3>; 1318 device_type = "pci"; 1319 interrupts = <16 2 1 14>; 1320 interrupt-map-mask = <0xf800 0 0 7>; 1321 interrupt-map = < 1322 /* IDSEL 0x0 */ 1323 0000 0 0 1 &mpic 41 1 0 0 1324 0000 0 0 2 &mpic 5 1 0 0 1325 0000 0 0 3 &mpic 6 1 0 0 1326 0000 0 0 4 &mpic 7 1 0 0 1327 >; 1328 }; 1329 }; 1330 1331 pci2: pcie@ffe202000 { 1332 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; 1333 device_type = "pci"; 1334 status = "okay"; 1335 #size-cells = <2>; 1336 #address-cells = <3>; 1337 cell-index = <2>; 1338 bus-range = <0x0 0xff>; 1339 clock-frequency = <0x1fca055>; 1340 fsl,msi = <&msi2>; 1341 interrupts = <16 2 1 13>; 1342 pcie@0 { 1343 reg = <0 0 0 0 0>; 1344 #interrupt-cells = <1>; 1345 #size-cells = <2>; 1346 #address-cells = <3>; 1347 device_type = "pci"; 1348 interrupts = <16 2 1 13>; 1349 interrupt-map-mask = <0xf800 0 0 7>; 1350 interrupt-map = < 1351 /* IDSEL 0x0 */ 1352 0000 0 0 1 &mpic 42 1 0 0 1353 0000 0 0 2 &mpic 9 1 0 0 1354 0000 0 0 3 &mpic 10 1 0 0 1355 0000 0 0 4 &mpic 11 1 0 0 1356 >; 1357 }; 1358 }; 1359 1360 pci3: pcie@ffe203000 { 1361 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; 1362 device_type = "pci"; 1363 status = "disabled"; 1364 #size-cells = <2>; 1365 #address-cells = <3>; 1366 cell-index = <3>; 1367 bus-range = <0x0 0xff>; 1368 clock-frequency = <0x1fca055>; 1369 fsl,msi = <&msi2>; 1370 interrupts = <16 2 1 12>; 1371 pcie@0 { 1372 reg = <0 0 0 0 0>; 1373 #interrupt-cells = <1>; 1374 #size-cells = <2>; 1375 #address-cells = <3>; 1376 device_type = "pci"; 1377 interrupts = <16 2 1 12>; 1378 interrupt-map-mask = <0xf800 0 0 7>; 1379 interrupt-map = < 1380 /* IDSEL 0x0 */ 1381 0000 0 0 1 &mpic 43 1 0 0 1382 0000 0 0 2 &mpic 0 1 0 0 1383 0000 0 0 3 &mpic 4 1 0 0 1384 0000 0 0 4 &mpic 8 1 0 0 1385 >; 1386 }; 1387 }; 1388}; 1389