1/* 2 * P5020DS Device Tree Source 3 * 4 * Copyright 2010-2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/include/ "p5020si.dtsi" 36 37/ { 38 model = "fsl,P5020DS"; 39 compatible = "fsl,P5020DS"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 aliases { 45 phy_rgmii_0 = &phy_rgmii_0; 46 phy_rgmii_1 = &phy_rgmii_1; 47 phy_sgmii_1c = &phy_sgmii_1c; 48 phy_sgmii_1d = &phy_sgmii_1d; 49 phy_sgmii_1e = &phy_sgmii_1e; 50 phy_sgmii_1f = &phy_sgmii_1f; 51 phy_xgmii_1 = &phy_xgmii_1; 52 phy_xgmii_2 = &phy_xgmii_2; 53 emi1_rgmii = &hydra_mdio_rgmii; 54 emi1_sgmii = &hydra_mdio_sgmii; 55 emi2_xgmii = &hydra_mdio_xgmii; 56 }; 57 58 memory { 59 device_type = "memory"; 60 reg = <0x00000000 0x00000000 0x00000000 0x80000000>; 61 }; 62 63 dcsr: dcsr@f00000000 { 64 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 65 }; 66 67 bman-portals@ff4000000 { 68 bman-portal@0 { 69 cpu-handle = <&cpu0>; 70 }; 71 bman-portal@4000 { 72 cpu-handle = <&cpu1>; 73 }; 74 bman-portal@8000 { 75 }; 76 bman-portal@c000 { 77 }; 78 bman-portal@10000 { 79 }; 80 bman-portal@14000 { 81 }; 82 bman-portal@18000 { 83 }; 84 bman-portal@1c000 { 85 }; 86 bman-portal@20000 { 87 }; 88 bman-portal@24000 { 89 }; 90 91 buffer-pool@0 { 92 compatible = "fsl,p5020-bpool", "fsl,bpool"; 93 fsl,bpid = <0>; 94 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>; 95 }; 96 }; 97 98 qman-portals@ff4200000 { 99 qportal0: qman-portal@0 { 100 cpu-handle = <&cpu0>; 101 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 102 &qpool4 &qpool5 &qpool6 103 &qpool7 &qpool8 &qpool9 104 &qpool10 &qpool11 &qpool12 105 &qpool13 &qpool14 &qpool15>; 106 }; 107 108 qportal1: qman-portal@4000 { 109 cpu-handle = <&cpu1>; 110 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 111 &qpool4 &qpool5 &qpool6 112 &qpool7 &qpool8 &qpool9 113 &qpool10 &qpool11 &qpool12 114 &qpool13 &qpool14 &qpool15>; 115 }; 116 117 qportal2: qman-portal@8000 { 118 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 119 &qpool4 &qpool5 &qpool6 120 &qpool7 &qpool8 &qpool9 121 &qpool10 &qpool11 &qpool12 122 &qpool13 &qpool14 &qpool15>; 123 }; 124 125 qportal3: qman-portal@c000 { 126 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 127 &qpool4 &qpool5 &qpool6 128 &qpool7 &qpool8 &qpool9 129 &qpool10 &qpool11 &qpool12 130 &qpool13 &qpool14 &qpool15>; 131 }; 132 133 qportal4: qman-portal@10000 { 134 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 135 &qpool4 &qpool5 &qpool6 136 &qpool7 &qpool8 &qpool9 137 &qpool10 &qpool11 &qpool12 138 &qpool13 &qpool14 &qpool15>; 139 }; 140 141 qportal5: qman-portal@14000 { 142 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 143 &qpool4 &qpool5 &qpool6 144 &qpool7 &qpool8 &qpool9 145 &qpool10 &qpool11 &qpool12 146 &qpool13 &qpool14 &qpool15>; 147 }; 148 149 qportal6: qman-portal@18000 { 150 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 151 &qpool4 &qpool5 &qpool6 152 &qpool7 &qpool8 &qpool9 153 &qpool10 &qpool11 &qpool12 154 &qpool13 &qpool14 &qpool15>; 155 }; 156 157 qportal7: qman-portal@1c000 { 158 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 159 &qpool4 &qpool5 &qpool6 160 &qpool7 &qpool8 &qpool9 161 &qpool10 &qpool11 &qpool12 162 &qpool13 &qpool14 &qpool15>; 163 }; 164 165 qportal8: qman-portal@20000 { 166 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 167 &qpool4 &qpool5 &qpool6 168 &qpool7 &qpool8 &qpool9 169 &qpool10 &qpool11 &qpool12 170 &qpool13 &qpool14 &qpool15>; 171 }; 172 173 qportal9: qman-portal@24000 { 174 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 175 &qpool4 &qpool5 &qpool6 176 &qpool7 &qpool8 &qpool9 177 &qpool10 &qpool11 &qpool12 178 &qpool13 &qpool14 &qpool15>; 179 }; 180 }; 181 182 soc: soc@ffe000000 { 183 spi@110000 { 184 flash@0 { 185 #address-cells = <1>; 186 #size-cells = <1>; 187 compatible = "spansion,s25sl12801"; 188 reg = <0>; 189 spi-max-frequency = <40000000>; /* input clock */ 190 partition@u-boot { 191 label = "u-boot"; 192 reg = <0x00000000 0x00100000>; 193 read-only; 194 }; 195 partition@kernel { 196 label = "kernel"; 197 reg = <0x00100000 0x00500000>; 198 read-only; 199 }; 200 partition@dtb { 201 label = "dtb"; 202 reg = <0x00600000 0x00100000>; 203 read-only; 204 }; 205 partition@fs { 206 label = "file system"; 207 reg = <0x00700000 0x00900000>; 208 }; 209 }; 210 }; 211 212 i2c@118100 { 213 eeprom@51 { 214 compatible = "at24,24c256"; 215 reg = <0x51>; 216 }; 217 eeprom@52 { 218 compatible = "at24,24c256"; 219 reg = <0x52>; 220 }; 221 }; 222 223 i2c@119100 { 224 rtc@68 { 225 compatible = "dallas,ds3232"; 226 reg = <0x68>; 227 interrupts = <0x1 0x1 0 0>; 228 }; 229 }; 230 231 pme: pme@316000 { 232 /* Commented out, use default allocation */ 233 /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */ 234 /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */ 235 }; 236 237 qman: qman@318000 { 238 /* Commented out, use default allocation */ 239 /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */ 240 /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */ 241 }; 242 243 bman: bman@31a000 { 244 /* Same as fsl,qman-*, use default allocation */ 245 /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */ 246 }; 247 248 fman0: fman@400000 { 249 enet0: ethernet@e0000 { 250 tbi-handle = <&tbi0>; 251 phy-handle = <&phy_rgmii_0>; 252 phy-connection-type = "rgmii"; 253 }; 254 255 mdio0: mdio@e1120 { 256 tbi0: tbi-phy@8 { 257 reg = <0x8>; 258 device_type = "tbi-phy"; 259 }; 260 261 /* 262 * Virtual MDIO for the two on-board RGMII 263 * ports. The fsl,hydra-mdio-muxval property 264 * is already correct. 265 */ 266 hydra_mdio_rgmii: hydra-mdio-rgmii { 267 #address-cells = <1>; 268 #size-cells = <0>; 269 compatible = "fsl,hydra-mdio"; 270 fsl,mdio-handle = <&mdio0>; 271 fsl,hydra-mdio-muxval = <0x00>; 272 status = "disabled"; 273 274 phy_rgmii_0: ethernet-phy@0 { 275 reg = <0x0>; 276 }; 277 phy_rgmii_1: ethernet-phy@1 { 278 reg = <0x1>; 279 }; 280 }; 281 282 /* 283 * Virtual MDIO for the four-port SGMII card. 284 * The fsl,hydra-mdio-muxval property will be 285 * fixed-up by U-Boot based on the slot that 286 * the SGMII card is in. 287 * 288 * Note: we do not support DTSEC5 connected to 289 * SGMII, so this is the only SGMII node. 290 */ 291 hydra_mdio_sgmii: hydra-mdio-sgmii { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 compatible = "fsl,hydra-mdio"; 295 fsl,mdio-handle = <&mdio0>; 296 fsl,hydra-mdio-muxval = <0x00>; 297 status = "disabled"; 298 299 phy_sgmii_1c: ethernet-phy@1c { 300 reg = <0x1c>; 301 }; 302 phy_sgmii_1d: ethernet-phy@1d { 303 reg = <0x1d>; 304 }; 305 phy_sgmii_1e: ethernet-phy@1e { 306 reg = <0x1e>; 307 }; 308 phy_sgmii_1f: ethernet-phy@1f { 309 reg = <0x1f>; 310 }; 311 }; 312 }; 313 314 enet1: ethernet@e2000 { 315 tbi-handle = <&tbi1>; 316 phy-handle = <&phy_sgmii_1d>; 317 phy-connection-type = "sgmii"; 318 }; 319 320 mdio@e3120 { 321 tbi1: tbi-phy@8 { 322 reg = <8>; 323 device_type = "tbi-phy"; 324 }; 325 }; 326 327 enet2: ethernet@e4000 { 328 tbi-handle = <&tbi2>; 329 phy-handle = <&phy_sgmii_1e>; 330 phy-connection-type = "sgmii"; 331 }; 332 333 mdio@e5120 { 334 tbi2: tbi-phy@8 { 335 reg = <8>; 336 device_type = "tbi-phy"; 337 }; 338 }; 339 340 enet3: ethernet@e6000 { 341 tbi-handle = <&tbi3>; 342 phy-handle = <&phy_sgmii_1f>; 343 phy-connection-type = "sgmii"; 344 }; 345 346 mdio@e7120 { 347 #address-cells = <1>; 348 #size-cells = <0>; 349 compatible = "fsl,fman-tbi"; 350 reg = <0xe7120 0xee0>; 351 interrupts = <100 1 0 0>; 352 353 tbi3: tbi-phy@8 { 354 reg = <8>; 355 device_type = "tbi-phy"; 356 }; 357 }; 358 359 enet4: ethernet@e8000 { 360 tbi-handle = <&tbi4>; 361 phy-handle = <&phy_rgmii_1>; 362 phy-connection-type = "rgmii"; 363 }; 364 365 mdio@e9120 { 366 tbi4: tbi-phy@8 { 367 reg = <8>; 368 device_type = "tbi-phy"; 369 }; 370 }; 371 372 enet5: ethernet@f0000 { 373 /* 374 * phy-handle will be updated by U-Boot to 375 * reflect the actual slot the XAUI card is in. 376 */ 377 phy-handle = <&phy_xgmii_1>; 378 phy-connection-type = "xgmii"; 379 }; 380 381 /* 382 * We only support one XAUI card, so the MDIO muxing 383 * is set by U-Boot, and Linux never touches it. 384 * Therefore, we don't need a virtual MDIO node. 385 * However, the phy address depends on the slot, so 386 * only one of the ethernet-phy nodes below will be 387 * used. 388 */ 389 hydra_mdio_xgmii: mdio@f1000 { 390 status = "disabled"; 391 392 /* XAUI card in slot 1 */ 393 phy_xgmii_1: ethernet-phy@4 { 394 reg = <0x4>; 395 }; 396 397 /* XAUI card in slot 2 */ 398 phy_xgmii_2: ethernet-phy@0 { 399 reg = <0x0>; 400 }; 401 }; 402 }; 403 }; 404 405 rapidio@ffe0c0000 { 406 reg = <0xf 0xfe0c0000 0 0x11000>; 407 408 port1 { 409 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 410 }; 411 port2 { 412 ranges = <0 0 0xc 0x30000000 0 0x10000000>; 413 }; 414 }; 415 416 localbus@ffe124000 { 417 reg = <0xf 0xfe124000 0 0x1000>; 418 ranges = <0 0 0xf 0xb8000000 0x04000000>; 419 420 flash@0,0 { 421 compatible = "cfi-flash"; 422 /* 423 * Map 64Mb of 128MB NOR flash memory. Since highest 424 * line of address of NOR flash memory are set by 425 * FPGA, memory are divided into two pages equal to 426 * 64MB. One of the pages can be accessed at once. 427 */ 428 reg = <0 0 0x04000000>; 429 bank-width = <2>; 430 device-width = <2>; 431 }; 432 433 nand@2,0 { 434 #address-cells = <1>; 435 #size-cells = <1>; 436 compatible = "fsl,elbc-fcm-nand"; 437 reg = <0x2 0x0 0x40000>; 438 439 partition@0 { 440 label = "NAND U-Boot Image"; 441 reg = <0x0 0x02000000>; 442 read-only; 443 }; 444 445 partition@2000000 { 446 label = "NAND Root File System"; 447 reg = <0x02000000 0x10000000>; 448 }; 449 450 partition@12000000 { 451 label = "NAND Compressed RFS Image"; 452 reg = <0x12000000 0x08000000>; 453 }; 454 455 partition@1a000000 { 456 label = "NAND Linux Kernel Image"; 457 reg = <0x1a000000 0x04000000>; 458 }; 459 460 partition@1e000000 { 461 label = "NAND DTB Image"; 462 reg = <0x1e000000 0x01000000>; 463 }; 464 465 partition@1f000000 { 466 label = "NAND Writable User area"; 467 reg = <0x1f000000 0x21000000>; 468 }; 469 }; 470 471 board-control@3,0 { 472 compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis"; 473 reg = <3 0 0x30>; 474 }; 475 }; 476 477 pci0: pcie@ffe200000 { 478 reg = <0xf 0xfe200000 0 0x1000>; 479 ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000 480 0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>; 481 pcie@0 { 482 ranges = <0x02000000 0 0x80000000 483 0x02000000 0 0x80000000 484 0 0x10000000 485 486 0x01000000 0 0x00000000 487 0x01000000 0 0xff000000 488 0 0x00010000>; 489 }; 490 }; 491 492 pci1: pcie@ffe201000 { 493 reg = <0xf 0xfe201000 0 0x1000>; 494 ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000 495 0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>; 496 pcie@0 { 497 ranges = <0x02000000 0 0x90000000 498 0x02000000 0 0x90000000 499 0 0x10000000 500 501 0x01000000 0 0x00000000 502 0x01000000 0 0xff010000 503 0 0x00010000>; 504 }; 505 }; 506 507 pci2: pcie@ffe202000 { 508 reg = <0xf 0xfe202000 0 0x1000>; 509 ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000 510 0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>; 511 pcie@0 { 512 ranges = <0x02000000 0 0xa0000000 513 0x02000000 0 0xa0000000 514 0 0x10000000 515 516 0x01000000 0 0x00000000 517 0x01000000 0 0xff020000 518 0 0x00010000>; 519 }; 520 }; 521 522 pci3: pcie@ffe203000 { 523 reg = <0xf 0xfe203000 0 0x1000>; 524 ranges = <0x02000000 0 0xb0000000 0x0 0xb0000000 0 0x08000000 525 0x01000000 0 0x00000000 0x0 0xff030000 0 0x00010000>; 526 pcie@0 { 527 ranges = <0x02000000 0 0xb0000000 528 0x02000000 0 0xb0000000 529 0 0x08000000 530 531 0x01000000 0 0x00000000 532 0x01000000 0 0xff030000 533 0 0x00010000>; 534 }; 535 }; 536 537 chosen { 538 stdin = "serial0"; 539 stdout = "serial0"; 540 }; 541}; 542