1/* 2 * P3041DS Device Tree Source 3 * 4 * Copyright 2010-2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/include/ "p3041si.dtsi" 36 37/ { 38 model = "fsl,P3041DS"; 39 compatible = "fsl,P3041DS"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 aliases { 45 phy_rgmii_0 = &phy_rgmii_0; 46 phy_rgmii_1 = &phy_rgmii_1; 47 phy_sgmii_1c = &phy_sgmii_1c; 48 phy_sgmii_1d = &phy_sgmii_1d; 49 phy_sgmii_1e = &phy_sgmii_1e; 50 phy_sgmii_1f = &phy_sgmii_1f; 51 phy_xgmii_1 = &phy_xgmii_1; 52 phy_xgmii_2 = &phy_xgmii_2; 53 emi1_rgmii = &hydra_mdio_rgmii; 54 emi1_sgmii = &hydra_mdio_sgmii; 55 emi2_xgmii = &hydra_mdio_xgmii; 56 }; 57 58 memory { 59 device_type = "memory"; 60 reg = <0x00000000 0x00000000 0x00000000 0x80000000>; 61 }; 62 63 dcsr: dcsr@f00000000 { 64 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 65 }; 66 67 bman-portals@ff4000000 { 68 bman-portal@0 { 69 cpu-handle = <&cpu0>; 70 }; 71 bman-portal@4000 { 72 cpu-handle = <&cpu1>; 73 }; 74 bman-portal@8000 { 75 cpu-handle = <&cpu2>; 76 }; 77 bman-portal@c000 { 78 cpu-handle = <&cpu3>; 79 }; 80 bman-portal@10000 { 81 }; 82 bman-portal@14000 { 83 }; 84 bman-portal@18000 { 85 }; 86 bman-portal@1c000 { 87 }; 88 bman-portal@20000 { 89 }; 90 bman-portal@24000 { 91 }; 92 93 buffer-pool@0 { 94 compatible = "fsl,p3041-bpool", "fsl,bpool"; 95 fsl,bpid = <0>; 96 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>; 97 }; 98 }; 99 100 qman-portals@ff4200000 { 101 qportal0: qman-portal@0 { 102 cpu-handle = <&cpu0>; 103 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 104 &qpool4 &qpool5 &qpool6 105 &qpool7 &qpool8 &qpool9 106 &qpool10 &qpool11 &qpool12 107 &qpool13 &qpool14 &qpool15>; 108 }; 109 110 qportal1: qman-portal@4000 { 111 cpu-handle = <&cpu1>; 112 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 113 &qpool4 &qpool5 &qpool6 114 &qpool7 &qpool8 &qpool9 115 &qpool10 &qpool11 &qpool12 116 &qpool13 &qpool14 &qpool15>; 117 }; 118 119 qportal2: qman-portal@8000 { 120 cpu-handle = <&cpu2>; 121 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 122 &qpool4 &qpool5 &qpool6 123 &qpool7 &qpool8 &qpool9 124 &qpool10 &qpool11 &qpool12 125 &qpool13 &qpool14 &qpool15>; 126 }; 127 128 qportal3: qman-portal@c000 { 129 cpu-handle = <&cpu3>; 130 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 131 &qpool4 &qpool5 &qpool6 132 &qpool7 &qpool8 &qpool9 133 &qpool10 &qpool11 &qpool12 134 &qpool13 &qpool14 &qpool15>; 135 }; 136 137 qportal4: qman-portal@10000 { 138 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 139 &qpool4 &qpool5 &qpool6 140 &qpool7 &qpool8 &qpool9 141 &qpool10 &qpool11 &qpool12 142 &qpool13 &qpool14 &qpool15>; 143 }; 144 145 qportal5: qman-portal@14000 { 146 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 147 &qpool4 &qpool5 &qpool6 148 &qpool7 &qpool8 &qpool9 149 &qpool10 &qpool11 &qpool12 150 &qpool13 &qpool14 &qpool15>; 151 }; 152 153 qportal6: qman-portal@18000 { 154 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 155 &qpool4 &qpool5 &qpool6 156 &qpool7 &qpool8 &qpool9 157 &qpool10 &qpool11 &qpool12 158 &qpool13 &qpool14 &qpool15>; 159 }; 160 161 qportal7: qman-portal@1c000 { 162 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 163 &qpool4 &qpool5 &qpool6 164 &qpool7 &qpool8 &qpool9 165 &qpool10 &qpool11 &qpool12 166 &qpool13 &qpool14 &qpool15>; 167 }; 168 169 qportal8: qman-portal@20000 { 170 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 171 &qpool4 &qpool5 &qpool6 172 &qpool7 &qpool8 &qpool9 173 &qpool10 &qpool11 &qpool12 174 &qpool13 &qpool14 &qpool15>; 175 }; 176 177 qportal9: qman-portal@24000 { 178 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 179 &qpool4 &qpool5 &qpool6 180 &qpool7 &qpool8 &qpool9 181 &qpool10 &qpool11 &qpool12 182 &qpool13 &qpool14 &qpool15>; 183 }; 184 }; 185 186 soc: soc@ffe000000 { 187 spi@110000 { 188 flash@0 { 189 #address-cells = <1>; 190 #size-cells = <1>; 191 compatible = "spansion,s25sl12801"; 192 reg = <0>; 193 spi-max-frequency = <35000000>; /* input clock */ 194 partition@u-boot { 195 label = "u-boot"; 196 reg = <0x00000000 0x00100000>; 197 read-only; 198 }; 199 partition@kernel { 200 label = "kernel"; 201 reg = <0x00100000 0x00500000>; 202 read-only; 203 }; 204 partition@dtb { 205 label = "dtb"; 206 reg = <0x00600000 0x00100000>; 207 read-only; 208 }; 209 partition@fs { 210 label = "file system"; 211 reg = <0x00700000 0x00900000>; 212 }; 213 }; 214 }; 215 216 i2c@118100 { 217 eeprom@51 { 218 compatible = "at24,24c256"; 219 reg = <0x51>; 220 }; 221 eeprom@52 { 222 compatible = "at24,24c256"; 223 reg = <0x52>; 224 }; 225 }; 226 227 i2c@119100 { 228 rtc@68 { 229 compatible = "dallas,ds3232"; 230 reg = <0x68>; 231 interrupts = <0x1 0x1 0 0>; 232 }; 233 }; 234 235 pme: pme@316000 { 236 /* Commented out, use default allocation */ 237 /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */ 238 /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */ 239 }; 240 241 qman: qman@318000 { 242 /* Commented out, use default allocation */ 243 /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */ 244 /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */ 245 }; 246 247 bman: bman@31a000 { 248 /* Same as fsl,qman-*, use default allocation */ 249 /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */ 250 }; 251 252 fman0: fman@400000 { 253 enet0: ethernet@e0000 { 254 tbi-handle = <&tbi0>; 255 phy-handle = <&phy_rgmii_0>; 256 phy-connection-type = "rgmii"; 257 }; 258 259 mdio0: mdio@e1120 { 260 tbi0: tbi-phy@8 { 261 reg = <0x8>; 262 device_type = "tbi-phy"; 263 }; 264 265 /* 266 * Virtual MDIO for the two on-board RGMII 267 * ports. The fsl,hydra-mdio-muxval property 268 * is already correct. 269 */ 270 hydra_mdio_rgmii: hydra-mdio-rgmii { 271 #address-cells = <1>; 272 #size-cells = <0>; 273 compatible = "fsl,hydra-mdio"; 274 fsl,mdio-handle = <&mdio0>; 275 fsl,hydra-mdio-muxval = <0x00>; 276 status = "disabled"; 277 278 phy_rgmii_0: ethernet-phy@0 { 279 reg = <0x0>; 280 }; 281 phy_rgmii_1: ethernet-phy@1 { 282 reg = <0x1>; 283 }; 284 }; 285 286 /* 287 * Virtual MDIO for the four-port SGMII card. 288 * The fsl,hydra-mdio-muxval property will be 289 * fixed-up by U-Boot based on the slot that 290 * the SGMII card is in. 291 * 292 * Note: we do not support DTSEC5 connected to 293 * SGMII, so this is the only SGMII node. 294 */ 295 hydra_mdio_sgmii: hydra-mdio-sgmii { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 compatible = "fsl,hydra-mdio"; 299 fsl,mdio-handle = <&mdio0>; 300 fsl,hydra-mdio-muxval = <0x00>; 301 status = "disabled"; 302 303 phy_sgmii_1c: ethernet-phy@1c { 304 reg = <0x1c>; 305 }; 306 phy_sgmii_1d: ethernet-phy@1d { 307 reg = <0x1d>; 308 }; 309 phy_sgmii_1e: ethernet-phy@1e { 310 reg = <0x1e>; 311 }; 312 phy_sgmii_1f: ethernet-phy@1f { 313 reg = <0x1f>; 314 }; 315 }; 316 }; 317 318 enet1: ethernet@e2000 { 319 tbi-handle = <&tbi1>; 320 phy-handle = <&phy_sgmii_1d>; 321 phy-connection-type = "sgmii"; 322 }; 323 324 mdio@e3120 { 325 tbi1: tbi-phy@8 { 326 reg = <8>; 327 device_type = "tbi-phy"; 328 }; 329 }; 330 331 enet2: ethernet@e4000 { 332 tbi-handle = <&tbi2>; 333 phy-handle = <&phy_sgmii_1e>; 334 phy-connection-type = "sgmii"; 335 }; 336 337 mdio@e5120 { 338 tbi2: tbi-phy@8 { 339 reg = <8>; 340 device_type = "tbi-phy"; 341 }; 342 }; 343 344 enet3: ethernet@e6000 { 345 tbi-handle = <&tbi3>; 346 phy-handle = <&phy_sgmii_1f>; 347 phy-connection-type = "sgmii"; 348 }; 349 350 mdio@e7120 { 351 #address-cells = <1>; 352 #size-cells = <0>; 353 compatible = "fsl,fman-tbi"; 354 reg = <0xe7120 0xee0>; 355 interrupts = <100 1 0 0>; 356 357 tbi3: tbi-phy@8 { 358 reg = <8>; 359 device_type = "tbi-phy"; 360 }; 361 }; 362 363 enet4: ethernet@e8000 { 364 tbi-handle = <&tbi4>; 365 phy-handle = <&phy_rgmii_1>; 366 phy-connection-type = "rgmii"; 367 }; 368 369 mdio@e9120 { 370 tbi4: tbi-phy@8 { 371 reg = <8>; 372 device_type = "tbi-phy"; 373 }; 374 }; 375 376 enet5: ethernet@f0000 { 377 /* 378 * phy-handle will be updated by U-Boot to 379 * reflect the actual slot the XAUI card is in. 380 */ 381 phy-handle = <&phy_xgmii_1>; 382 phy-connection-type = "xgmii"; 383 }; 384 385 /* 386 * We only support one XAUI card, so the MDIO muxing 387 * is set by U-Boot, and Linux never touches it. 388 * Therefore, we don't need a virtual MDIO node. 389 * However, the phy address depends on the slot, so 390 * only one of the ethernet-phy nodes below will be 391 * used. 392 */ 393 hydra_mdio_xgmii: mdio@f1000 { 394 status = "disabled"; 395 396 /* XAUI card in slot 1 */ 397 phy_xgmii_1: ethernet-phy@4 { 398 reg = <0x4>; 399 }; 400 401 /* XAUI card in slot 2 */ 402 phy_xgmii_2: ethernet-phy@0 { 403 reg = <0x0>; 404 }; 405 }; 406 }; 407 }; 408 409 rapidio@ffe0c0000 { 410 reg = <0xf 0xfe0c0000 0 0x11000>; 411 412 port1 { 413 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 414 }; 415 port2 { 416 ranges = <0 0 0xc 0x30000000 0 0x10000000>; 417 }; 418 }; 419 420 localbus@ffe124000 { 421 reg = <0xf 0xfe124000 0 0x1000>; 422 ranges = <0 0 0xf 0xb8000000 0x04000000>; 423 424 flash@0,0 { 425 compatible = "cfi-flash"; 426 /* 427 * Map 64Mb of 128MB NOR flash memory. Since highest 428 * line of address of NOR flash memory are set by 429 * FPGA, memory are divided into two pages equal to 430 * 64MB. One of the pages can be accessed at once. 431 */ 432 reg = <0 0 0x04000000>; 433 bank-width = <2>; 434 device-width = <2>; 435 }; 436 437 nand@2,0 { 438 #address-cells = <1>; 439 #size-cells = <1>; 440 compatible = "fsl,elbc-fcm-nand"; 441 reg = <0x2 0x0 0x40000>; 442 443 partition@0 { 444 label = "NAND U-Boot Image"; 445 reg = <0x0 0x02000000>; 446 read-only; 447 }; 448 449 partition@2000000 { 450 label = "NAND Root File System"; 451 reg = <0x02000000 0x10000000>; 452 }; 453 454 partition@12000000 { 455 label = "NAND Compressed RFS Image"; 456 reg = <0x12000000 0x08000000>; 457 }; 458 459 partition@1a000000 { 460 label = "NAND Linux Kernel Image"; 461 reg = <0x1a000000 0x04000000>; 462 }; 463 464 partition@1e000000 { 465 label = "NAND DTB Image"; 466 reg = <0x1e000000 0x01000000>; 467 }; 468 469 partition@1f000000 { 470 label = "NAND Writable User area"; 471 reg = <0x1f000000 0x21000000>; 472 }; 473 }; 474 475 board-control@3,0 { 476 compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis"; 477 reg = <3 0 0x30>; 478 }; 479 }; 480 481 pci0: pcie@ffe200000 { 482 reg = <0xf 0xfe200000 0 0x1000>; 483 ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000 484 0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>; 485 pcie@0 { 486 ranges = <0x02000000 0 0x80000000 487 0x02000000 0 0x80000000 488 0 0x10000000 489 490 0x01000000 0 0x00000000 491 0x01000000 0 0xff000000 492 0 0x00010000>; 493 }; 494 }; 495 496 pci1: pcie@ffe201000 { 497 reg = <0xf 0xfe201000 0 0x1000>; 498 ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000 499 0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>; 500 pcie@0 { 501 ranges = <0x02000000 0 0x90000000 502 0x02000000 0 0x90000000 503 0 0x10000000 504 505 0x01000000 0 0x00000000 506 0x01000000 0 0xff010000 507 0 0x00010000>; 508 }; 509 }; 510 511 pci2: pcie@ffe202000 { 512 reg = <0xf 0xfe202000 0 0x1000>; 513 ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000 514 0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>; 515 pcie@0 { 516 ranges = <0x02000000 0 0xa0000000 517 0x02000000 0 0xa0000000 518 0 0x10000000 519 520 0x01000000 0 0x00000000 521 0x01000000 0 0xff020000 522 0 0x00010000>; 523 }; 524 }; 525 526 pci3: pcie@ffe203000 { 527 reg = <0xf 0xfe203000 0 0x1000>; 528 ranges = <0x02000000 0 0xb0000000 0x0 0xb0000000 0 0x08000000 529 0x01000000 0 0x00000000 0x0 0xff030000 0 0x00010000>; 530 pcie@0 { 531 ranges = <0x02000000 0 0xb0000000 532 0x02000000 0 0xb0000000 533 0 0x08000000 534 535 0x01000000 0 0x00000000 536 0x01000000 0 0xff030000 537 0 0x00010000>; 538 }; 539 }; 540 541 chosen { 542 stdin = "serial0"; 543 stdout = "serial0"; 544 }; 545}; 546