1/* 2 * P2041 Silicon Device Tree Source 3 * 4 * Copyright 2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/dts-v1/; 36 37/ { 38 compatible = "fsl,P2041"; 39 #address-cells = <2>; 40 #size-cells = <2>; 41 interrupt-parent = <&mpic>; 42 43 aliases { 44 ccsr = &soc; 45 dcsr = &dcsr; 46 47 ethernet0 = &enet0; 48 ethernet1 = &enet1; 49 ethernet2 = &enet2; 50 ethernet3 = &enet3; 51 ethernet4 = &enet4; 52 ethernet5 = &enet5; 53 serial0 = &serial0; 54 serial1 = &serial1; 55 serial2 = &serial2; 56 serial3 = &serial3; 57 pci0 = &pci0; 58 pci1 = &pci1; 59 pci2 = &pci2; 60 usb0 = &usb0; 61 usb1 = &usb1; 62 dma0 = &dma0; 63 dma1 = &dma1; 64 bman = &bman; 65 qman = &qman; 66 pme = &pme; 67 rman = &rman; 68 sdhc = &sdhc; 69 msi0 = &msi0; 70 msi1 = &msi1; 71 msi2 = &msi2; 72 73 crypto = &crypto; 74 sec_jr0 = &sec_jr0; 75 sec_jr1 = &sec_jr1; 76 sec_jr2 = &sec_jr2; 77 sec_jr3 = &sec_jr3; 78 rtic_a = &rtic_a; 79 rtic_b = &rtic_b; 80 rtic_c = &rtic_c; 81 rtic_d = &rtic_d; 82 sec_mon = &sec_mon; 83 84 fman0 = &fman0; 85 fman0_oh0 = &fman0_oh0; 86 fman0_oh1 = &fman0_oh1; 87 fman0_oh2 = &fman0_oh2; 88 fman0_oh3 = &fman0_oh3; 89 fman0_oh4 = &fman0_oh4; 90 fman0_oh5 = &fman0_oh5; 91 fman0_oh6 = &fman0_oh6; 92 fman0_rx0 = &fman0_rx0; 93 fman0_rx1 = &fman0_rx1; 94 fman0_rx2 = &fman0_rx2; 95 fman0_rx3 = &fman0_rx3; 96 fman0_rx4 = &fman0_rx4; 97 fman0_rx5 = &fman0_rx5; 98 }; 99 100 cpus { 101 #address-cells = <1>; 102 #size-cells = <0>; 103 104 cpu0: PowerPC,e500mc@0 { 105 device_type = "cpu"; 106 reg = <0>; 107 bus-frequency = <749999996>; 108 next-level-cache = <&L2_0>; 109 L2_0: l2-cache { 110 next-level-cache = <&cpc>; 111 }; 112 }; 113 cpu1: PowerPC,e500mc@1 { 114 device_type = "cpu"; 115 reg = <1>; 116 next-level-cache = <&L2_1>; 117 L2_1: l2-cache { 118 next-level-cache = <&cpc>; 119 }; 120 }; 121 cpu2: PowerPC,e500mc@2 { 122 device_type = "cpu"; 123 reg = <2>; 124 next-level-cache = <&L2_2>; 125 L2_2: l2-cache { 126 next-level-cache = <&cpc>; 127 }; 128 }; 129 cpu3: PowerPC,e500mc@3 { 130 device_type = "cpu"; 131 reg = <3>; 132 next-level-cache = <&L2_3>; 133 L2_3: l2-cache { 134 next-level-cache = <&cpc>; 135 }; 136 }; 137 }; 138 139 dcsr: dcsr@f00000000 { 140 #address-cells = <1>; 141 #size-cells = <1>; 142 compatible = "fsl,dcsr", "simple-bus"; 143 144 dcsr-epu@0 { 145 compatible = "fsl,dcsr-epu"; 146 interrupts = <52 2 0 0 147 84 2 0 0 148 85 2 0 0>; 149 interrupt-parent = <&mpic>; 150 reg = <0x0 0x1000>; 151 }; 152 dcsr-npc { 153 compatible = "fsl,dcsr-npc"; 154 reg = <0x1000 0x1000 0x1000000 0x8000>; 155 }; 156 dcsr-nxc@2000 { 157 compatible = "fsl,dcsr-nxc"; 158 reg = <0x2000 0x1000>; 159 }; 160 dcsr-corenet { 161 compatible = "fsl,dcsr-corenet"; 162 reg = <0x8000 0x1000 0xB0000 0x1000>; 163 }; 164 dcsr-dpaa@9000 { 165 compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa"; 166 reg = <0x9000 0x1000>; 167 }; 168 dcsr-ocn@11000 { 169 compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn"; 170 reg = <0x11000 0x1000>; 171 }; 172 dcsr-ddr@12000 { 173 compatible = "fsl,dcsr-ddr"; 174 dev-handle = <&ddr>; 175 reg = <0x12000 0x1000>; 176 }; 177 dcsr-nal@18000 { 178 compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal"; 179 reg = <0x18000 0x1000>; 180 }; 181 dcsr-rcpm@22000 { 182 compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm"; 183 reg = <0x22000 0x1000>; 184 }; 185 dcsr-cpu-sb-proxy@40000 { 186 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 187 cpu-handle = <&cpu0>; 188 reg = <0x40000 0x1000>; 189 }; 190 dcsr-cpu-sb-proxy@41000 { 191 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 192 cpu-handle = <&cpu1>; 193 reg = <0x41000 0x1000>; 194 }; 195 dcsr-cpu-sb-proxy@42000 { 196 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 197 cpu-handle = <&cpu2>; 198 reg = <0x42000 0x1000>; 199 }; 200 dcsr-cpu-sb-proxy@43000 { 201 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 202 cpu-handle = <&cpu3>; 203 reg = <0x43000 0x1000>; 204 }; 205 }; 206 207 bman-portals@ff4000000 { 208 #address-cells = <0x1>; 209 #size-cells = <0x1>; 210 compatible = "fsl,bman-portals"; 211 ranges = <0x0 0xf 0xfde00000 0x200000>; 212 bman-portal@0 { 213 cell-index = <0x0>; 214 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal"; 215 reg = <0x0 0x4000 0x100000 0x1000>; 216 interrupts = <105 2 0 0>; 217 }; 218 bman-portal@4000 { 219 cell-index = <0x1>; 220 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal"; 221 reg = <0x4000 0x4000 0x101000 0x1000>; 222 interrupts = <107 2 0 0>; 223 }; 224 bman-portal@8000 { 225 cell-index = <2>; 226 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal"; 227 reg = <0x8000 0x4000 0x102000 0x1000>; 228 interrupts = <109 2 0 0>; 229 }; 230 bman-portal@c000 { 231 cell-index = <0x3>; 232 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal"; 233 reg = <0xc000 0x4000 0x103000 0x1000>; 234 interrupts = <111 2 0 0>; 235 }; 236 bman-portal@10000 { 237 cell-index = <0x4>; 238 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal"; 239 reg = <0x10000 0x4000 0x104000 0x1000>; 240 interrupts = <113 2 0 0>; 241 }; 242 bman-portal@14000 { 243 cell-index = <0x5>; 244 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal"; 245 reg = <0x14000 0x4000 0x105000 0x1000>; 246 interrupts = <115 2 0 0>; 247 }; 248 bman-portal@18000 { 249 cell-index = <0x6>; 250 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal"; 251 reg = <0x18000 0x4000 0x106000 0x1000>; 252 interrupts = <117 2 0 0>; 253 }; 254 bman-portal@1c000 { 255 cell-index = <0x7>; 256 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal"; 257 reg = <0x1c000 0x4000 0x107000 0x1000>; 258 interrupts = <119 2 0 0>; 259 }; 260 bman-portal@20000 { 261 cell-index = <0x8>; 262 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal"; 263 reg = <0x20000 0x4000 0x108000 0x1000>; 264 interrupts = <121 2 0 0>; 265 }; 266 bman-portal@24000 { 267 cell-index = <0x9>; 268 compatible = "fsl,p2041-bman-portal", "fsl,bman-portal"; 269 reg = <0x24000 0x4000 0x109000 0x1000>; 270 interrupts = <123 2 0 0>; 271 }; 272 273 buffer-pool@0 { 274 compatible = "fsl,p2041-bpool", "fsl,bpool"; 275 fsl,bpid = <0>; 276 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>; 277 }; 278 }; 279 280 qman-portals@ff4200000 { 281 #address-cells = <0x1>; 282 #size-cells = <0x1>; 283 compatible = "fsl,qman-portals"; 284 ranges = <0x0 0xf 0xfdc00000 0x200000>; 285 qportal0: qman-portal@0 { 286 cell-index = <0x0>; 287 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal"; 288 reg = <0x0 0x4000 0x100000 0x1000>; 289 interrupts = <104 0x2 0 0>; 290 fsl,qman-channel-id = <0x0>; 291 }; 292 293 qportal1: qman-portal@4000 { 294 cell-index = <0x1>; 295 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal"; 296 reg = <0x4000 0x4000 0x101000 0x1000>; 297 interrupts = <106 0x2 0 0>; 298 fsl,qman-channel-id = <0x1>; 299 }; 300 301 qportal2: qman-portal@8000 { 302 cell-index = <0x2>; 303 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal"; 304 reg = <0x8000 0x4000 0x102000 0x1000>; 305 interrupts = <108 0x2 0 0>; 306 fsl,qman-channel-id = <0x2>; 307 }; 308 309 qportal3: qman-portal@c000 { 310 cell-index = <0x3>; 311 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal"; 312 reg = <0xc000 0x4000 0x103000 0x1000>; 313 interrupts = <110 0x2 0 0>; 314 fsl,qman-channel-id = <0x3>; 315 }; 316 317 qportal4: qman-portal@10000 { 318 cell-index = <0x4>; 319 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal"; 320 reg = <0x10000 0x4000 0x104000 0x1000>; 321 interrupts = <112 0x2 0 0>; 322 fsl,qman-channel-id = <0x4>; 323 }; 324 325 qportal5: qman-portal@14000 { 326 cell-index = <0x5>; 327 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal"; 328 reg = <0x14000 0x4000 0x105000 0x1000>; 329 interrupts = <114 0x2 0 0>; 330 fsl,qman-channel-id = <0x5>; 331 }; 332 333 qportal6: qman-portal@18000 { 334 cell-index = <0x6>; 335 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal"; 336 reg = <0x18000 0x4000 0x106000 0x1000>; 337 interrupts = <116 0x2 0 0>; 338 fsl,qman-channel-id = <0x6>; 339 }; 340 341 qportal7: qman-portal@1c000 { 342 cell-index = <0x7>; 343 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal"; 344 reg = <0x1c000 0x4000 0x107000 0x1000>; 345 interrupts = <118 0x2 0 0>; 346 fsl,qman-channel-id = <0x7>; 347 }; 348 349 qportal8: qman-portal@20000 { 350 cell-index = <0x8>; 351 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal"; 352 reg = <0x20000 0x4000 0x108000 0x1000>; 353 interrupts = <120 0x2 0 0>; 354 fsl,qman-channel-id = <0x8>; 355 }; 356 357 qportal9: qman-portal@24000 { 358 cell-index = <0x9>; 359 compatible = "fsl,p2041-qman-portal", "fsl,qman-portal"; 360 reg = <0x24000 0x4000 0x109000 0x1000>; 361 interrupts = <122 0x2 0 0>; 362 fsl,qman-channel-id = <0x9>; 363 }; 364 365 qpool1: qman-pool@1 { 366 cell-index = <1>; 367 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 368 fsl,qman-channel-id = <0x21>; 369 }; 370 371 qpool2: qman-pool@2 { 372 cell-index = <2>; 373 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 374 fsl,qman-channel-id = <0x22>; 375 }; 376 377 qpool3: qman-pool@3 { 378 cell-index = <3>; 379 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 380 fsl,qman-channel-id = <0x23>; 381 }; 382 383 qpool4: qman-pool@4 { 384 cell-index = <4>; 385 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 386 fsl,qman-channel-id = <0x24>; 387 }; 388 389 qpool5: qman-pool@5 { 390 cell-index = <5>; 391 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 392 fsl,qman-channel-id = <0x25>; 393 }; 394 395 qpool6: qman-pool@6 { 396 cell-index = <6>; 397 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 398 fsl,qman-channel-id = <0x26>; 399 }; 400 401 qpool7: qman-pool@7 { 402 cell-index = <7>; 403 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 404 fsl,qman-channel-id = <0x27>; 405 }; 406 407 qpool8: qman-pool@8 { 408 cell-index = <8>; 409 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 410 fsl,qman-channel-id = <0x28>; 411 }; 412 413 qpool9: qman-pool@9 { 414 cell-index = <9>; 415 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 416 fsl,qman-channel-id = <0x29>; 417 }; 418 419 qpool10: qman-pool@10 { 420 cell-index = <10>; 421 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 422 fsl,qman-channel-id = <0x2a>; 423 }; 424 425 qpool11: qman-pool@11 { 426 cell-index = <11>; 427 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 428 fsl,qman-channel-id = <0x2b>; 429 }; 430 431 qpool12: qman-pool@12 { 432 cell-index = <12>; 433 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 434 fsl,qman-channel-id = <0x2c>; 435 }; 436 437 qpool13: qman-pool@13 { 438 cell-index = <13>; 439 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 440 fsl,qman-channel-id = <0x2d>; 441 }; 442 443 qpool14: qman-pool@14 { 444 cell-index = <14>; 445 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 446 fsl,qman-channel-id = <0x2e>; 447 }; 448 449 qpool15: qman-pool@15 { 450 cell-index = <15>; 451 compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel"; 452 fsl,qman-channel-id = <0x2f>; 453 }; 454 }; 455 456 soc: soc@ffe000000 { 457 #address-cells = <1>; 458 #size-cells = <1>; 459 device_type = "soc"; 460 compatible = "simple-bus"; 461 462 bus-frequency = <0>; // Filled out by kernel. 463 464 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 465 reg = <0xf 0xfe000000 0 0x00001000>; 466 467 soc-sram-error { 468 compatible = "fsl,soc-sram-error"; 469 interrupts = <16 2 1 29>; 470 }; 471 472 corenet-law@0 { 473 compatible = "fsl,corenet-law"; 474 reg = <0x0 0x1000>; 475 fsl,num-laws = <32>; 476 }; 477 478 ddr: memory-controller@8000 { 479 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; 480 reg = <0x8000 0x1000>; 481 interrupts = <16 2 1 23>; 482 }; 483 484 cpc: l3-cache-controller@10000 { 485 compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache"; 486 reg = <0x10000 0x1000>; 487 interrupts = <16 2 1 27>; 488 }; 489 490 corenet-cf@18000 { 491 compatible = "fsl,corenet-cf"; 492 reg = <0x18000 0x1000>; 493 interrupts = <16 2 1 31>; 494 fsl,ccf-num-csdids = <32>; 495 fsl,ccf-num-snoopids = <32>; 496 }; 497 498 iommu@20000 { 499 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 500 reg = <0x20000 0x4000>; 501 interrupts = < 502 24 2 0 0 503 16 2 1 30>; 504 }; 505 506 mpic: pic@40000 { 507 clock-frequency = <0>; 508 interrupt-controller; 509 #address-cells = <0>; 510 #interrupt-cells = <4>; 511 reg = <0x40000 0x40000>; 512 compatible = "fsl,mpic", "chrp,open-pic"; 513 device_type = "open-pic"; 514 }; 515 516 msi0: msi@41600 { 517 compatible = "fsl,mpic-msi"; 518 reg = <0x41600 0x200>; 519 msi-available-ranges = <0 0x100>; 520 interrupts = < 521 0xe0 0 0 0 522 0xe1 0 0 0 523 0xe2 0 0 0 524 0xe3 0 0 0 525 0xe4 0 0 0 526 0xe5 0 0 0 527 0xe6 0 0 0 528 0xe7 0 0 0>; 529 }; 530 531 msi1: msi@41800 { 532 compatible = "fsl,mpic-msi"; 533 reg = <0x41800 0x200>; 534 msi-available-ranges = <0 0x100>; 535 interrupts = < 536 0xe8 0 0 0 537 0xe9 0 0 0 538 0xea 0 0 0 539 0xeb 0 0 0 540 0xec 0 0 0 541 0xed 0 0 0 542 0xee 0 0 0 543 0xef 0 0 0>; 544 }; 545 546 msi2: msi@41a00 { 547 compatible = "fsl,mpic-msi"; 548 reg = <0x41a00 0x200>; 549 msi-available-ranges = <0 0x100>; 550 interrupts = < 551 0xf0 0 0 0 552 0xf1 0 0 0 553 0xf2 0 0 0 554 0xf3 0 0 0 555 0xf4 0 0 0 556 0xf5 0 0 0 557 0xf6 0 0 0 558 0xf7 0 0 0>; 559 }; 560 561 guts: global-utilities@e0000 { 562 compatible = "fsl,qoriq-device-config-1.0"; 563 reg = <0xe0000 0xe00>; 564 fsl,has-rstcr; 565 #sleep-cells = <1>; 566 fsl,liodn-bits = <12>; 567 }; 568 569 pins: global-utilities@e0e00 { 570 compatible = "fsl,qoriq-pin-control-1.0"; 571 reg = <0xe0e00 0x200>; 572 #sleep-cells = <2>; 573 }; 574 575 clockgen: global-utilities@e1000 { 576 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0"; 577 reg = <0xe1000 0x1000>; 578 clock-frequency = <0>; 579 }; 580 581 rcpm: global-utilities@e2000 { 582 compatible = "fsl,qoriq-rcpm-1.0"; 583 reg = <0xe2000 0x1000>; 584 #sleep-cells = <1>; 585 }; 586 587 sfp: sfp@e8000 { 588 compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0"; 589 reg = <0xe8000 0x1000>; 590 }; 591 592 serdes: serdes@ea000 { 593 compatible = "fsl,p2041-serdes"; 594 reg = <0xea000 0x1000>; 595 }; 596 597 dma0: dma@100300 { 598 #address-cells = <1>; 599 #size-cells = <1>; 600 compatible = "fsl,p2041-dma", "fsl,eloplus-dma"; 601 reg = <0x100300 0x4>; 602 ranges = <0x0 0x100100 0x200>; 603 cell-index = <0>; 604 dma-channel@0 { 605 compatible = "fsl,p2041-dma-channel", 606 "fsl,eloplus-dma-channel"; 607 reg = <0x0 0x80>; 608 cell-index = <0>; 609 interrupts = <28 2 0 0>; 610 }; 611 dma-channel@80 { 612 compatible = "fsl,p2041-dma-channel", 613 "fsl,eloplus-dma-channel"; 614 reg = <0x80 0x80>; 615 cell-index = <1>; 616 interrupts = <29 2 0 0>; 617 }; 618 dma-channel@100 { 619 compatible = "fsl,p2041-dma-channel", 620 "fsl,eloplus-dma-channel"; 621 reg = <0x100 0x80>; 622 cell-index = <2>; 623 interrupts = <30 2 0 0>; 624 }; 625 dma-channel@180 { 626 compatible = "fsl,p2041-dma-channel", 627 "fsl,eloplus-dma-channel"; 628 reg = <0x180 0x80>; 629 cell-index = <3>; 630 interrupts = <31 2 0 0>; 631 }; 632 }; 633 634 dma1: dma@101300 { 635 #address-cells = <1>; 636 #size-cells = <1>; 637 compatible = "fsl,p2041-dma", "fsl,eloplus-dma"; 638 reg = <0x101300 0x4>; 639 ranges = <0x0 0x101100 0x200>; 640 cell-index = <1>; 641 dma-channel@0 { 642 compatible = "fsl,p2041-dma-channel", 643 "fsl,eloplus-dma-channel"; 644 reg = <0x0 0x80>; 645 cell-index = <0>; 646 interrupts = <32 2 0 0>; 647 }; 648 dma-channel@80 { 649 compatible = "fsl,p2041-dma-channel", 650 "fsl,eloplus-dma-channel"; 651 reg = <0x80 0x80>; 652 cell-index = <1>; 653 interrupts = <33 2 0 0>; 654 }; 655 dma-channel@100 { 656 compatible = "fsl,p2041-dma-channel", 657 "fsl,eloplus-dma-channel"; 658 reg = <0x100 0x80>; 659 cell-index = <2>; 660 interrupts = <34 2 0 0>; 661 }; 662 dma-channel@180 { 663 compatible = "fsl,p2041-dma-channel", 664 "fsl,eloplus-dma-channel"; 665 reg = <0x180 0x80>; 666 cell-index = <3>; 667 interrupts = <35 2 0 0>; 668 }; 669 }; 670 671 spi@110000 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 compatible = "fsl,p2041-espi", "fsl,mpc8536-espi"; 675 reg = <0x110000 0x1000>; 676 interrupts = <53 0x2 0 0>; 677 fsl,espi-num-chipselects = <4>; 678 }; 679 680 sdhc: sdhc@114000 { 681 compatible = "fsl,p2041-esdhc", "fsl,esdhc"; 682 reg = <0x114000 0x1000>; 683 interrupts = <48 2 0 0>; 684 sdhci,auto-cmd12; 685 clock-frequency = <0>; 686 }; 687 688 i2c@118000 { 689 #address-cells = <1>; 690 #size-cells = <0>; 691 cell-index = <0>; 692 compatible = "fsl-i2c"; 693 reg = <0x118000 0x100>; 694 interrupts = <38 2 0 0>; 695 dfsrr; 696 }; 697 698 i2c@118100 { 699 #address-cells = <1>; 700 #size-cells = <0>; 701 cell-index = <1>; 702 compatible = "fsl-i2c"; 703 reg = <0x118100 0x100>; 704 interrupts = <38 2 0 0>; 705 dfsrr; 706 }; 707 708 i2c@119000 { 709 #address-cells = <1>; 710 #size-cells = <0>; 711 cell-index = <2>; 712 compatible = "fsl-i2c"; 713 reg = <0x119000 0x100>; 714 interrupts = <39 2 0 0>; 715 dfsrr; 716 }; 717 718 i2c@119100 { 719 #address-cells = <1>; 720 #size-cells = <0>; 721 cell-index = <3>; 722 compatible = "fsl-i2c"; 723 reg = <0x119100 0x100>; 724 interrupts = <39 2 0 0>; 725 dfsrr; 726 }; 727 728 serial0: serial@11c500 { 729 cell-index = <0>; 730 device_type = "serial"; 731 compatible = "ns16550"; 732 reg = <0x11c500 0x100>; 733 clock-frequency = <0>; 734 interrupts = <36 2 0 0>; 735 }; 736 737 serial1: serial@11c600 { 738 cell-index = <1>; 739 device_type = "serial"; 740 compatible = "ns16550"; 741 reg = <0x11c600 0x100>; 742 clock-frequency = <0>; 743 interrupts = <36 2 0 0>; 744 }; 745 746 serial2: serial@11d500 { 747 cell-index = <2>; 748 device_type = "serial"; 749 compatible = "ns16550"; 750 reg = <0x11d500 0x100>; 751 clock-frequency = <0>; 752 interrupts = <37 2 0 0>; 753 }; 754 755 serial3: serial@11d600 { 756 cell-index = <3>; 757 device_type = "serial"; 758 compatible = "ns16550"; 759 reg = <0x11d600 0x100>; 760 clock-frequency = <0>; 761 interrupts = <37 2 0 0>; 762 }; 763 764 gpio0: gpio@130000 { 765 compatible = "fsl,p2041-gpio", "fsl,qoriq-gpio"; 766 reg = <0x130000 0x1000>; 767 interrupts = <55 2 0 0>; 768 #gpio-cells = <2>; 769 gpio-controller; 770 }; 771 772 rman: rman@1e0000 { 773 compatible = "fsl,rman"; 774 #address-cells = <1>; 775 #size-cells = <1>; 776 ranges = <0x0 0x1e0000 0x20000>; 777 reg = <0x1e0000 0x20000>; 778 interrupts = <16 2 1 11>; /* err_irq */ 779 fsl,qman-channels-id = <0x62 0x63>; 780 781 inbound-block@0 { 782 compatible = "fsl,rman-inbound-block"; 783 reg = <0x0 0x800>; 784 }; 785 global-cfg@b00 { 786 compatible = "fsl,rman-global-cfg"; 787 reg = <0xb00 0x500>; 788 }; 789 inbound-block@1000 { 790 compatible = "fsl,rman-inbound-block"; 791 reg = <0x1000 0x800>; 792 }; 793 inbound-block@2000 { 794 compatible = "fsl,rman-inbound-block"; 795 reg = <0x2000 0x800>; 796 }; 797 inbound-block@3000 { 798 compatible = "fsl,rman-inbound-block"; 799 reg = <0x3000 0x800>; 800 }; 801 }; 802 803 usb0: usb@210000 { 804 compatible = "fsl,p2041-usb2-mph", 805 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; 806 reg = <0x210000 0x1000>; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 interrupts = <44 0x2 0 0>; 810 phy_type = "utmi"; 811 port0; 812 }; 813 814 usb1: usb@211000 { 815 compatible = "fsl,p2041-usb2-dr", 816 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; 817 reg = <0x211000 0x1000>; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 interrupts = <45 0x2 0 0>; 821 phy_type = "utmi"; 822 }; 823 824 sata@220000 { 825 compatible = "fsl,p2041-sata", "fsl,pq-sata-v2"; 826 reg = <0x220000 0x1000>; 827 interrupts = <68 0x2 0 0>; 828 }; 829 830 sata@221000 { 831 compatible = "fsl,p2041-sata", "fsl,pq-sata-v2"; 832 reg = <0x221000 0x1000>; 833 interrupts = <69 0x2 0 0>; 834 }; 835 836 crypto: crypto@300000 { 837 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0"; 838 #address-cells = <1>; 839 #size-cells = <1>; 840 reg = <0x300000 0x10000>; 841 ranges = <0 0x300000 0x10000>; 842 interrupts = <92 2 0 0>; 843 844 sec_jr0: jr@1000 { 845 compatible = "fsl,sec-v4.2-job-ring", 846 "fsl,sec-v4.0-job-ring"; 847 reg = <0x1000 0x1000>; 848 interrupts = <88 2 0 0>; 849 }; 850 851 sec_jr1: jr@2000 { 852 compatible = "fsl,sec-v4.2-job-ring", 853 "fsl,sec-v4.0-job-ring"; 854 reg = <0x2000 0x1000>; 855 interrupts = <89 2 0 0>; 856 }; 857 858 sec_jr2: jr@3000 { 859 compatible = "fsl,sec-v4.2-job-ring", 860 "fsl,sec-v4.0-job-ring"; 861 reg = <0x3000 0x1000>; 862 interrupts = <90 2 0 0>; 863 }; 864 865 sec_jr3: jr@4000 { 866 compatible = "fsl,sec-v4.2-job-ring", 867 "fsl,sec-v4.0-job-ring"; 868 reg = <0x4000 0x1000>; 869 interrupts = <91 2 0 0>; 870 }; 871 872 rtic@6000 { 873 compatible = "fsl,sec-v4.2-rtic", 874 "fsl,sec-v4.0-rtic"; 875 #address-cells = <1>; 876 #size-cells = <1>; 877 reg = <0x6000 0x100>; 878 ranges = <0x0 0x6100 0xe00>; 879 880 rtic_a: rtic-a@0 { 881 compatible = "fsl,sec-v4.2-rtic-memory", 882 "fsl,sec-v4.0-rtic-memory"; 883 reg = <0x00 0x20 0x100 0x80>; 884 }; 885 886 rtic_b: rtic-b@20 { 887 compatible = "fsl,sec-v4.2-rtic-memory", 888 "fsl,sec-v4.0-rtic-memory"; 889 reg = <0x20 0x20 0x200 0x80>; 890 }; 891 892 rtic_c: rtic-c@40 { 893 compatible = "fsl,sec-v4.2-rtic-memory", 894 "fsl,sec-v4.0-rtic-memory"; 895 reg = <0x40 0x20 0x300 0x80>; 896 }; 897 898 rtic_d: rtic-d@60 { 899 compatible = "fsl,sec-v4.2-rtic-memory", 900 "fsl,sec-v4.0-rtic-memory"; 901 reg = <0x60 0x20 0x500 0x80>; 902 }; 903 }; 904 }; 905 906 sec_mon: sec_mon@314000 { 907 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon"; 908 reg = <0x314000 0x1000>; 909 interrupts = <93 2 0 0>; 910 }; 911 912 pme: pme@316000 { 913 compatible = "fsl,pme"; 914 reg = <0x316000 0x10000>; 915 /* "fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */ 916 /* "fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */ 917 interrupts = <16 2 1 5>; 918 }; 919 920 qman: qman@318000 { 921 compatible = "fsl,p2041-qman", "fsl,qman"; 922 reg = <0x318000 0x1000>; 923 interrupts = <16 2 1 3>; 924 /* Commented out, use default allocation */ 925 /* "fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */ 926 /* "fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */ 927 }; 928 929 bman: bman@31a000 { 930 compatible = "fsl,p2041-bman", "fsl,bman"; 931 reg = <0x31a000 0x1000>; 932 interrupts = <16 2 1 2>; 933 /* Same as "fsl,qman-*, use default allocation */ 934 /* "fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */ 935 }; 936 937 fman0: fman@400000 { 938 #address-cells = <1>; 939 #size-cells = <1>; 940 cell-index = <0>; 941 compatible = "fsl,p2041-fman", "fsl,fman", "simple-bus"; 942 ranges = <0 0x400000 0x100000>; 943 reg = <0x400000 0x100000>; 944 clock-frequency = <0>; 945 interrupts = < 946 96 2 0 0 947 16 2 1 1>; 948 949 cc@0 { 950 compatible = "fsl,p2041-fman-cc", "fsl,fman-cc"; 951 }; 952 953 parser@c7000 { 954 compatible = "fsl,p2041-fman-parser", "fsl,fman-parser"; 955 reg = <0xc7000 0x1000>; 956 }; 957 958 keygen@c1000 { 959 compatible = "fsl,p2041-fman-keygen", "fsl,fman-keygen"; 960 reg = <0xc1000 0x1000>; 961 }; 962 963 policer@c0000 { 964 compatible = "fsl,p2041-fman-policer", "fsl,fman-policer"; 965 reg = <0xc0000 0x1000>; 966 }; 967 968 muram@0 { 969 compatible = "fsl,p2041-fman-muram", "fsl,fman-muram"; 970 reg = <0x0 0x28000>; 971 }; 972 973 bmi@80000 { 974 compatible = "fsl,p2041-fman-bmi", "fsl,fman-bmi"; 975 reg = <0x80000 0x400>; 976 }; 977 978 qmi@80400 { 979 compatible = "fsl,p2041-fman-qmi", "fsl,fman-qmi"; 980 reg = <0x80400 0x400>; 981 }; 982 983 fman0_rx0: port@88000 { 984 cell-index = <0>; 985 compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 986 reg = <0x88000 0x1000>; 987 }; 988 fman0_rx1: port@89000 { 989 cell-index = <1>; 990 compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 991 reg = <0x89000 0x1000>; 992 }; 993 fman0_rx2: port@8a000 { 994 cell-index = <2>; 995 compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 996 reg = <0x8a000 0x1000>; 997 }; 998 fman0_rx3: port@8b000 { 999 cell-index = <3>; 1000 compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 1001 reg = <0x8b000 0x1000>; 1002 }; 1003 fman0_rx4: port@8c000 { 1004 cell-index = <4>; 1005 compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 1006 reg = <0x8c000 0x1000>; 1007 }; 1008 fman0_rx5: port@90000 { 1009 cell-index = <0>; 1010 compatible = "fsl,p2041-fman-port-10g-rx", "fsl,fman-port-10g-rx"; 1011 reg = <0x90000 0x1000>; 1012 }; 1013 1014 fman0_tx5: port@b0000 { 1015 cell-index = <0>; 1016 compatible = "fsl,p2041-fman-port-10g-tx", "fsl,fman-port-10g-tx"; 1017 reg = <0xb0000 0x1000>; 1018 fsl,qman-channel-id = <0x40>; 1019 }; 1020 fman0_tx0: port@a8000 { 1021 cell-index = <0>; 1022 compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1023 reg = <0xa8000 0x1000>; 1024 fsl,qman-channel-id = <0x41>; 1025 }; 1026 fman0_tx1: port@a9000 { 1027 cell-index = <1>; 1028 compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1029 reg = <0xa9000 0x1000>; 1030 fsl,qman-channel-id = <0x42>; 1031 }; 1032 fman0_tx2: port@aa000 { 1033 cell-index = <2>; 1034 compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1035 reg = <0xaa000 0x1000>; 1036 fsl,qman-channel-id = <0x43>; 1037 }; 1038 fman0_tx3: port@ab000 { 1039 cell-index = <3>; 1040 compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1041 reg = <0xab000 0x1000>; 1042 fsl,qman-channel-id = <0x44>; 1043 }; 1044 fman0_tx4: port@ac000 { 1045 cell-index = <4>; 1046 compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1047 reg = <0xac000 0x1000>; 1048 fsl,qman-channel-id = <0x45>; 1049 }; 1050 1051 fman0_oh0: port@81000 { 1052 cell-index = <0>; 1053 compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh"; 1054 reg = <0x81000 0x1000>; 1055 fsl,qman-channel-id = <0x46>; 1056 }; 1057 fman0_oh1: port@82000 { 1058 cell-index = <1>; 1059 compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh"; 1060 reg = <0x82000 0x1000>; 1061 fsl,qman-channel-id = <0x47>; 1062 }; 1063 fman0_oh2: port@83000 { 1064 cell-index = <2>; 1065 compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh"; 1066 reg = <0x83000 0x1000>; 1067 fsl,qman-channel-id = <0x48>; 1068 }; 1069 fman0_oh3: port@84000 { 1070 cell-index = <3>; 1071 compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh"; 1072 reg = <0x84000 0x1000>; 1073 fsl,qman-channel-id = <0x49>; 1074 }; 1075 fman0_oh4: port@85000 { 1076 cell-index = <4>; 1077 compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh"; 1078 reg = <0x85000 0x1000>; 1079 fsl,qman-channel-id = <0x4a>; 1080 }; 1081 fman0_oh5: port@86000 { 1082 cell-index = <5>; 1083 compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh"; 1084 reg = <0x86000 0x1000>; 1085 fsl,qman-channel-id = <0x4b>; 1086 }; 1087 fman0_oh6: port@87000 { 1088 cell-index = <6>; 1089 compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh"; 1090 reg = <0x87000 0x1000>; 1091 }; 1092 1093 enet0: ethernet@e0000 { 1094 cell-index = <0>; 1095 compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1096 reg = <0xe0000 0x1000>; 1097 fsl,port-handles = <&fman0_rx0 &fman0_tx0>; 1098 }; 1099 1100 mdio0: mdio@e1120 { 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 compatible = "fsl,fman-mdio"; 1104 reg = <0xe1120 0xee0>; 1105 interrupts = <100 1 0 0>; 1106 }; 1107 1108 enet1: ethernet@e2000 { 1109 cell-index = <1>; 1110 compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1111 reg = <0xe2000 0x1000>; 1112 fsl,port-handles = <&fman0_rx1 &fman0_tx1>; 1113 }; 1114 1115 mdio@e3120 { 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 compatible = "fsl,fman-tbi"; 1119 reg = <0xe3120 0xee0>; 1120 interrupts = <100 1 0 0>; 1121 }; 1122 1123 enet2: ethernet@e4000 { 1124 cell-index = <2>; 1125 compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1126 reg = <0xe4000 0x1000>; 1127 fsl,port-handles = <&fman0_rx2 &fman0_tx2>; 1128 }; 1129 1130 mdio@e5120 { 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 compatible = "fsl,fman-tbi"; 1134 reg = <0xe5120 0xee0>; 1135 interrupts = <100 1 0 0>; 1136 }; 1137 1138 enet3: ethernet@e6000 { 1139 cell-index = <3>; 1140 compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1141 reg = <0xe6000 0x1000>; 1142 fsl,port-handles = <&fman0_rx3 &fman0_tx3>; 1143 }; 1144 1145 mdio@e7120 { 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 compatible = "fsl,fman-tbi"; 1149 reg = <0xe7120 0xee0>; 1150 interrupts = <100 1 0 0>; 1151 }; 1152 1153 enet4: ethernet@e8000 { 1154 cell-index = <4>; 1155 compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1156 reg = <0xe8000 0x1000>; 1157 fsl,port-handles = <&fman0_rx4 &fman0_tx4>; 1158 }; 1159 1160 mdio@e9120 { 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 compatible = "fsl,fman-tbi"; 1164 reg = <0xe9120 0xee0>; 1165 interrupts = <100 1 0 0>; 1166 }; 1167 1168 enet5: ethernet@f0000 { 1169 cell-index = <0>; 1170 compatible = "fsl,p2041-fman-10g-mac", "fsl,fman-10g-mac", "fsl,fman-xgec"; 1171 reg = <0xf0000 0x1000>; 1172 fsl,port-handles = <&fman0_rx5 &fman0_tx5>; 1173 }; 1174 1175 mdio@f1000 { 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 compatible = "fsl,fman-xmdio"; 1179 reg = <0xf1000 0x1000>; 1180 interrupts = <100 1 0 0>; 1181 }; 1182 }; 1183 }; 1184 1185 rapidio@ffe0c0000 { 1186 compatible = "fsl,srio"; 1187 interrupts = <16 2 1 11>; 1188 #address-cells = <2>; 1189 #size-cells = <2>; 1190 ranges; 1191 1192 port1 { 1193 #address-cells = <2>; 1194 #size-cells = <2>; 1195 cell-index = <1>; 1196 }; 1197 1198 port2 { 1199 #address-cells = <2>; 1200 #size-cells = <2>; 1201 cell-index = <2>; 1202 }; 1203 }; 1204 1205 localbus@ffe124000 { 1206 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus"; 1207 interrupts = <25 2 0 0>; 1208 #address-cells = <2>; 1209 #size-cells = <1>; 1210 }; 1211 1212 pci0: pcie@ffe200000 { 1213 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2"; 1214 device_type = "pci"; 1215 status = "disabled"; 1216 #size-cells = <2>; 1217 #address-cells = <3>; 1218 bus-range = <0x0 0xff>; 1219 clock-frequency = <33333333>; 1220 fsl,msi = <&msi0>; 1221 interrupts = <16 2 1 15>; 1222 pcie@0 { 1223 reg = <0 0 0 0 0>; 1224 #interrupt-cells = <1>; 1225 #size-cells = <2>; 1226 #address-cells = <3>; 1227 device_type = "pci"; 1228 interrupts = <16 2 1 15>; 1229 interrupt-map-mask = <0xf800 0 0 7>; 1230 interrupt-map = < 1231 /* IDSEL 0x0 */ 1232 0000 0 0 1 &mpic 40 1 0 0 1233 0000 0 0 2 &mpic 1 1 0 0 1234 0000 0 0 3 &mpic 2 1 0 0 1235 0000 0 0 4 &mpic 3 1 0 0 1236 >; 1237 }; 1238 }; 1239 1240 pci1: pcie@ffe201000 { 1241 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2"; 1242 device_type = "pci"; 1243 status = "okay"; 1244 #size-cells = <2>; 1245 #address-cells = <3>; 1246 bus-range = <0 0xff>; 1247 clock-frequency = <33333333>; 1248 fsl,msi = <&msi1>; 1249 interrupts = <16 2 1 14>; 1250 pcie@0 { 1251 reg = <0 0 0 0 0>; 1252 #interrupt-cells = <1>; 1253 #size-cells = <2>; 1254 #address-cells = <3>; 1255 device_type = "pci"; 1256 interrupts = <16 2 1 14>; 1257 interrupt-map-mask = <0xf800 0 0 7>; 1258 interrupt-map = < 1259 /* IDSEL 0x0 */ 1260 0000 0 0 1 &mpic 41 1 0 0 1261 0000 0 0 2 &mpic 5 1 0 0 1262 0000 0 0 3 &mpic 6 1 0 0 1263 0000 0 0 4 &mpic 7 1 0 0 1264 >; 1265 }; 1266 }; 1267 1268 pci2: pcie@ffe202000 { 1269 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2"; 1270 device_type = "pci"; 1271 status = "disabled"; 1272 #size-cells = <2>; 1273 #address-cells = <3>; 1274 bus-range = <0x0 0xff>; 1275 clock-frequency = <33333333>; 1276 fsl,msi = <&msi2>; 1277 interrupts = <16 2 1 13>; 1278 pcie@0 { 1279 reg = <0 0 0 0 0>; 1280 #interrupt-cells = <1>; 1281 #size-cells = <2>; 1282 #address-cells = <3>; 1283 device_type = "pci"; 1284 interrupts = <16 2 1 13>; 1285 interrupt-map-mask = <0xf800 0 0 7>; 1286 interrupt-map = < 1287 /* IDSEL 0x0 */ 1288 0000 0 0 1 &mpic 42 1 0 0 1289 0000 0 0 2 &mpic 9 1 0 0 1290 0000 0 0 3 &mpic 10 1 0 0 1291 0000 0 0 4 &mpic 11 1 0 0 1292 >; 1293 }; 1294 }; 1295}; 1296