1/* 2 * P2041RDB Device Tree Source 3 * 4 * Copyright 2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/include/ "p2041si.dtsi" 36 37/ { 38 model = "fsl,P2041RDB"; 39 compatible = "fsl,P2041RDB"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 aliases { 45 phy_rgmii_0 = &phy_rgmii_0; 46 phy_rgmii_1 = &phy_rgmii_1; 47 phy_sgmii_2 = &phy_sgmii_2; 48 phy_sgmii_3 = &phy_sgmii_3; 49 phy_sgmii_4 = &phy_sgmii_4; 50 phy_sgmii_1c = &phy_sgmii_1c; 51 phy_sgmii_1d = &phy_sgmii_1d; 52 phy_sgmii_1e = &phy_sgmii_1e; 53 phy_sgmii_1f = &phy_sgmii_1f; 54 phy_xgmii_2 = &phy_xgmii_2; 55 }; 56 57 memory { 58 device_type = "memory"; 59 reg = <0x00000000 0x00000000 0x00000000 0x80000000>; 60 }; 61 62 dcsr: dcsr@f00000000 { 63 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 64 }; 65 66 bman-portals@ff4000000 { 67 bman-portal@0 { 68 cpu-handle = <&cpu0>; 69 }; 70 bman-portal@4000 { 71 cpu-handle = <&cpu1>; 72 }; 73 bman-portal@8000 { 74 cpu-handle = <&cpu2>; 75 }; 76 bman-portal@c000 { 77 cpu-handle = <&cpu3>; 78 }; 79 bman-portal@10000 { 80 }; 81 bman-portal@14000 { 82 }; 83 bman-portal@18000 { 84 }; 85 bman-portal@1c000 { 86 }; 87 bman-portal@20000 { 88 }; 89 bman-portal@24000 { 90 }; 91 92 buffer-pool@0 { 93 compatible = "fsl,p2041-bpool", "fsl,bpool"; 94 fsl,bpid = <0>; 95 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>; 96 }; 97 }; 98 99 qman-portals@ff4200000 { 100 qportal0: qman-portal@0 { 101 cpu-handle = <&cpu0>; 102 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 103 &qpool4 &qpool5 &qpool6 104 &qpool7 &qpool8 &qpool9 105 &qpool10 &qpool11 &qpool12 106 &qpool13 &qpool14 &qpool15>; 107 }; 108 109 qportal1: qman-portal@4000 { 110 cpu-handle = <&cpu1>; 111 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 112 &qpool4 &qpool5 &qpool6 113 &qpool7 &qpool8 &qpool9 114 &qpool10 &qpool11 &qpool12 115 &qpool13 &qpool14 &qpool15>; 116 }; 117 118 qportal2: qman-portal@8000 { 119 cpu-handle = <&cpu2>; 120 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 121 &qpool4 &qpool5 &qpool6 122 &qpool7 &qpool8 &qpool9 123 &qpool10 &qpool11 &qpool12 124 &qpool13 &qpool14 &qpool15>; 125 }; 126 127 qportal3: qman-portal@c000 { 128 cpu-handle = <&cpu3>; 129 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 130 &qpool4 &qpool5 &qpool6 131 &qpool7 &qpool8 &qpool9 132 &qpool10 &qpool11 &qpool12 133 &qpool13 &qpool14 &qpool15>; 134 }; 135 136 qportal4: qman-portal@10000 { 137 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 138 &qpool4 &qpool5 &qpool6 139 &qpool7 &qpool8 &qpool9 140 &qpool10 &qpool11 &qpool12 141 &qpool13 &qpool14 &qpool15>; 142 }; 143 144 qportal5: qman-portal@14000 { 145 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 146 &qpool4 &qpool5 &qpool6 147 &qpool7 &qpool8 &qpool9 148 &qpool10 &qpool11 &qpool12 149 &qpool13 &qpool14 &qpool15>; 150 }; 151 152 qportal6: qman-portal@18000 { 153 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 154 &qpool4 &qpool5 &qpool6 155 &qpool7 &qpool8 &qpool9 156 &qpool10 &qpool11 &qpool12 157 &qpool13 &qpool14 &qpool15>; 158 }; 159 160 qportal7: qman-portal@1c000 { 161 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 162 &qpool4 &qpool5 &qpool6 163 &qpool7 &qpool8 &qpool9 164 &qpool10 &qpool11 &qpool12 165 &qpool13 &qpool14 &qpool15>; 166 }; 167 168 qportal8: qman-portal@20000 { 169 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 170 &qpool4 &qpool5 &qpool6 171 &qpool7 &qpool8 &qpool9 172 &qpool10 &qpool11 &qpool12 173 &qpool13 &qpool14 &qpool15>; 174 }; 175 176 qportal9: qman-portal@24000 { 177 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 178 &qpool4 &qpool5 &qpool6 179 &qpool7 &qpool8 &qpool9 180 &qpool10 &qpool11 &qpool12 181 &qpool13 &qpool14 &qpool15>; 182 }; 183 }; 184 185 soc: soc@ffe000000 { 186 spi@110000 { 187 flash@0 { 188 #address-cells = <1>; 189 #size-cells = <1>; 190 compatible = "spansion,s25sl12801"; 191 reg = <0>; 192 spi-max-frequency = <40000000>; /* input clock */ 193 partition@u-boot { 194 label = "u-boot"; 195 reg = <0x00000000 0x00100000>; 196 read-only; 197 }; 198 partition@kernel { 199 label = "kernel"; 200 reg = <0x00100000 0x00500000>; 201 read-only; 202 }; 203 partition@dtb { 204 label = "dtb"; 205 reg = <0x00600000 0x00100000>; 206 read-only; 207 }; 208 partition@fs { 209 label = "file system"; 210 reg = <0x00700000 0x00900000>; 211 }; 212 }; 213 }; 214 215 i2c@118000 { 216 lm75b@48 { 217 compatible = "nxp,lm75a"; 218 reg = <0x48>; 219 }; 220 eeprom@50 { 221 compatible = "at24,24c256"; 222 reg = <0x50>; 223 }; 224 rtc@68 { 225 compatible = "pericom,pt7c4338"; 226 reg = <0x68>; 227 }; 228 }; 229 230 i2c@118100 { 231 eeprom@50 { 232 compatible = "at24,24c256"; 233 reg = <0x50>; 234 }; 235 }; 236 237 usb1: usb@211000 { 238 dr_mode = "host"; 239 }; 240 241 pme: pme@316000 { 242 /* Commented out, use default allocation */ 243 /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */ 244 /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */ 245 }; 246 247 qman: qman@318000 { 248 /* Commented out, use default allocation */ 249 /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */ 250 /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */ 251 }; 252 253 bman: bman@31a000 { 254 /* Same as fsl,qman-*, use default allocation */ 255 /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */ 256 }; 257 258 fman0: fman@400000 { 259 enet0: ethernet@e0000 { 260 tbi-handle = <&tbi0>; 261 phy-handle = <&phy_sgmii_2>; 262 phy-connection-type = "sgmii"; 263 }; 264 265 mdio0: mdio@e1120 { 266 tbi0: tbi-phy@8 { 267 reg = <0x8>; 268 device_type = "tbi-phy"; 269 }; 270 271 phy_rgmii_0: ethernet-phy@0 { 272 reg = <0x0>; 273 }; 274 phy_rgmii_1: ethernet-phy@1 { 275 reg = <0x1>; 276 }; 277 phy_sgmii_2: ethernet-phy@2 { 278 reg = <0x2>; 279 }; 280 phy_sgmii_3: ethernet-phy@3 { 281 reg = <0x3>; 282 }; 283 phy_sgmii_4: ethernet-phy@4 { 284 reg = <0x4>; 285 }; 286 phy_sgmii_1c: ethernet-phy@1c { 287 reg = <0x1c>; 288 }; 289 phy_sgmii_1d: ethernet-phy@1d { 290 reg = <0x1d>; 291 }; 292 phy_sgmii_1e: ethernet-phy@1e { 293 reg = <0x1e>; 294 }; 295 phy_sgmii_1f: ethernet-phy@1f { 296 reg = <0x1f>; 297 }; 298 }; 299 300 enet1: ethernet@e2000 { 301 tbi-handle = <&tbi1>; 302 phy-handle = <&phy_sgmii_3>; 303 phy-connection-type = "sgmii"; 304 }; 305 306 mdio@e3120 { 307 tbi1: tbi-phy@8 { 308 reg = <8>; 309 device_type = "tbi-phy"; 310 }; 311 }; 312 313 enet2: ethernet@e4000 { 314 tbi-handle = <&tbi2>; 315 phy-handle = <&phy_sgmii_4>; 316 phy-connection-type = "sgmii"; 317 }; 318 319 mdio@e5120 { 320 tbi2: tbi-phy@8 { 321 reg = <8>; 322 device_type = "tbi-phy"; 323 }; 324 }; 325 326 enet3: ethernet@e6000 { 327 tbi-handle = <&tbi3>; 328 phy-handle = <&phy_rgmii_1>; 329 phy-connection-type = "rgmii"; 330 }; 331 332 mdio@e7120 { 333 tbi3: tbi-phy@8 { 334 reg = <8>; 335 device_type = "tbi-phy"; 336 }; 337 }; 338 339 enet4: ethernet@e8000 { 340 tbi-handle = <&tbi4>; 341 phy-handle = <&phy_rgmii_0>; 342 phy-connection-type = "rgmii"; 343 }; 344 345 mdio@e9120 { 346 tbi4: tbi-phy@8 { 347 reg = <8>; 348 device_type = "tbi-phy"; 349 }; 350 }; 351 352 enet5: ethernet@f0000 { 353 /* 354 * phy-handle will be updated by U-Boot to 355 * reflect the actual slot the XAUI card is in. 356 */ 357 phy-handle = <&phy_xgmii_2>; 358 phy-connection-type = "xgmii"; 359 }; 360 361 mdio@f1000 { 362 /* XAUI card in slot 2 */ 363 phy_xgmii_2: ethernet-phy@0 { 364 reg = <0x0>; 365 }; 366 }; 367 }; 368 }; 369 370 rapidio@ffe0c0000 { 371 reg = <0xf 0xfe0c0000 0 0x11000>; 372 373 port1 { 374 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 375 }; 376 port2 { 377 ranges = <0 0 0xc 0x30000000 0 0x10000000>; 378 }; 379 }; 380 381 localbus@ffe124000 { 382 reg = <0xf 0xfe124000 0 0x1000>; 383 ranges = <0 0 0xf 0xb8000000 0x04000000>; 384 385 flash@0,0 { 386 compatible = "cfi-flash"; 387 /* 388 * Map 64Mb of 128MB NOR flash memory. Since highest 389 * line of address of NOR flash memory are set by 390 * FPGA, memory are divided into two pages equal to 391 * 64MB. One of the pages can be accessed at once. 392 */ 393 reg = <0 0 0x04000000>; 394 bank-width = <2>; 395 device-width = <2>; 396 }; 397 }; 398 399 pci0: pcie@ffe200000 { 400 reg = <0xf 0xfe200000 0 0x1000>; 401 ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000 402 0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>; 403 pcie@0 { 404 ranges = <0x02000000 0 0x80000000 405 0x02000000 0 0x80000000 406 0 0x10000000 407 408 0x01000000 0 0x00000000 409 0x01000000 0 0xff000000 410 0 0x00010000>; 411 }; 412 }; 413 414 pci1: pcie@ffe201000 { 415 reg = <0xf 0xfe201000 0 0x1000>; 416 ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000 417 0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>; 418 pcie@0 { 419 ranges = <0x02000000 0 0x90000000 420 0x02000000 0 0x90000000 421 0 0x10000000 422 423 0x01000000 0 0x00000000 424 0x01000000 0 0xff010000 425 0 0x00010000>; 426 }; 427 }; 428 429 pci2: pcie@ffe202000 { 430 reg = <0xf 0xfe202000 0 0x1000>; 431 ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000 432 0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>; 433 pcie@0 { 434 ranges = <0x02000000 0 0xa0000000 435 0x02000000 0 0xa0000000 436 0 0x10000000 437 438 0x01000000 0 0x00000000 439 0x01000000 0 0xff020000 440 0 0x00010000>; 441 }; 442 }; 443 444 chosen { 445 stdin = "serial0"; 446 stdout = "serial0"; 447 }; 448}; 449