1/* 2 * MPC8572 DS Device Tree Source 3 * 4 * Copyright 2007-2009 Freescale Semiconductor Inc. All rights reserved 5 * 6 * Neither the name of Freescale Semiconductor, Inc nor the names of 7 * its contributors may be used to endorse or promote products derived 8 * from this software without specific prior written permission. 9 * 10 * Freescale hereby publishes it under the following licenses: 11 * 12 * BSD License 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 21 * Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in 23 * the documentation and/or other materials provided with the 24 * distribution. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 27 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 33 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 35 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * GNU General Public License, version 2 41 * 42 * This program is free software; you can redistribute it and/or 43 * modify it under the terms of the GNU General Public License 44 * as published by the Free Software Foundation; either version 2 45 * of the License, or (at your option) any later version. 46 * 47 * This program is distributed in the hope that it will be useful, 48 * but WITHOUT ANY WARRANTY; without even the implied warranty of 49 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 50 * GNU General Public License for more details. 51 * 52 * You should have received a copy of the GNU General Public License 53 * along with this program; if not, write to the Free Software 54 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 55 * MA 02110-1301, USA. 56 * 57 * You may select the license of your choice. 58 *------------------------------------------------------------------ 59 */ 60 61/dts-v1/; 62/ { 63 model = "fsl,MPC8572DS"; 64 compatible = "fsl,MPC8572DS"; 65 #address-cells = <2>; 66 #size-cells = <2>; 67 68 aliases { 69 ethernet0 = &enet0; 70 ethernet1 = &enet1; 71 ethernet2 = &enet2; 72 ethernet3 = &enet3; 73 serial0 = &serial0; 74 serial1 = &serial1; 75 pci0 = &pci0; 76 pci1 = &pci1; 77 pci2 = &pci2; 78 }; 79 80 cpus { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 84 PowerPC,8572@0 { 85 device_type = "cpu"; 86 reg = <0x0>; 87 d-cache-line-size = <32>; // 32 bytes 88 i-cache-line-size = <32>; // 32 bytes 89 d-cache-size = <0x8000>; // L1, 32K 90 i-cache-size = <0x8000>; // L1, 32K 91 timebase-frequency = <0>; 92 bus-frequency = <0>; 93 clock-frequency = <0>; 94 next-level-cache = <&L2>; 95 }; 96 97 PowerPC,8572@1 { 98 device_type = "cpu"; 99 reg = <0x1>; 100 d-cache-line-size = <32>; // 32 bytes 101 i-cache-line-size = <32>; // 32 bytes 102 d-cache-size = <0x8000>; // L1, 32K 103 i-cache-size = <0x8000>; // L1, 32K 104 timebase-frequency = <0>; 105 bus-frequency = <0>; 106 clock-frequency = <0>; 107 next-level-cache = <&L2>; 108 }; 109 }; 110 111 memory { 112 device_type = "memory"; 113 }; 114 115 localbus@ffe05000 { 116 #address-cells = <2>; 117 #size-cells = <1>; 118 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; 119 reg = <0 0xffe05000 0 0x1000>; 120 interrupts = <19 2>; 121 interrupt-parent = <&mpic>; 122 123 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000>; 124 125 nor@0,0 { 126 #address-cells = <1>; 127 #size-cells = <1>; 128 compatible = "cfi-flash"; 129 reg = <0x0 0x0 0x8000000>; 130 bank-width = <2>; 131 device-width = <1>; 132 133 partition@0 { 134 reg = <0x0 0x03000000>; 135 label = "ramdisk-nor"; 136 read-only; 137 }; 138 139 partition@3000000 { 140 reg = <0x03000000 0x00e00000>; 141 label = "diagnostic-nor"; 142 read-only; 143 }; 144 145 partition@3e00000 { 146 reg = <0x03e00000 0x00200000>; 147 label = "dink-nor"; 148 read-only; 149 }; 150 151 partition@4000000 { 152 reg = <0x04000000 0x00400000>; 153 label = "kernel-nor"; 154 read-only; 155 }; 156 157 partition@4400000 { 158 reg = <0x04400000 0x03b00000>; 159 label = "jffs2-nor"; 160 }; 161 162 partition@7f00000 { 163 reg = <0x07f00000 0x00080000>; 164 label = "dtb-nor"; 165 read-only; 166 }; 167 168 partition@7f80000 { 169 reg = <0x07f80000 0x00080000>; 170 label = "u-boot-nor"; 171 read-only; 172 }; 173 }; 174 175 nand@2,0 { 176 #address-cells = <1>; 177 #size-cells = <1>; 178 compatible = "fsl,mpc8572-fcm-nand", 179 "fsl,elbc-fcm-nand"; 180 reg = <0x2 0x0 0x40000>; 181 182 partition@0 { 183 reg = <0x0 0x02000000>; 184 label = "u-boot-nand"; 185 read-only; 186 }; 187 188 partition@2000000 { 189 reg = <0x02000000 0x10000000>; 190 label = "jffs2-nand"; 191 }; 192 193 partition@12000000 { 194 reg = <0x12000000 0x08000000>; 195 label = "ramdisk-nand"; 196 read-only; 197 }; 198 199 partition@1a000000 { 200 reg = <0x1a000000 0x04000000>; 201 label = "kernel-nand"; 202 }; 203 204 partition@1e000000 { 205 reg = <0x1e000000 0x01000000>; 206 label = "dtb-nand"; 207 read-only; 208 }; 209 210 partition@1f000000 { 211 reg = <0x1f000000 0x21000000>; 212 label = "reserved-nand"; 213 }; 214 }; 215 216 nand@4,0 { 217 compatible = "fsl,mpc8572-fcm-nand", 218 "fsl,elbc-fcm-nand"; 219 reg = <0x4 0x0 0x40000>; 220 }; 221 222 nand@5,0 { 223 compatible = "fsl,mpc8572-fcm-nand", 224 "fsl,elbc-fcm-nand"; 225 reg = <0x5 0x0 0x40000>; 226 }; 227 228 nand@6,0 { 229 compatible = "fsl,mpc8572-fcm-nand", 230 "fsl,elbc-fcm-nand"; 231 reg = <0x6 0x0 0x40000>; 232 }; 233 }; 234 235 soc8572@ffe00000 { 236 #address-cells = <1>; 237 #size-cells = <1>; 238 device_type = "soc"; 239 compatible = "simple-bus"; 240 ranges = <0x0 0 0xffe00000 0x100000>; 241 bus-frequency = <0>; // Filled out by uboot. 242 243 ecm-law@0 { 244 compatible = "fsl,ecm-law"; 245 reg = <0x0 0x1000>; 246 fsl,num-laws = <12>; 247 }; 248 249 ecm@1000 { 250 compatible = "fsl,mpc8572-ecm", "fsl,ecm"; 251 reg = <0x1000 0x1000>; 252 interrupts = <17 2>; 253 interrupt-parent = <&mpic>; 254 }; 255 256 memory-controller@2000 { 257 compatible = "fsl,mpc8572-memory-controller"; 258 reg = <0x2000 0x1000>; 259 interrupt-parent = <&mpic>; 260 interrupts = <18 2>; 261 }; 262 263 memory-controller@6000 { 264 compatible = "fsl,mpc8572-memory-controller"; 265 reg = <0x6000 0x1000>; 266 interrupt-parent = <&mpic>; 267 interrupts = <18 2>; 268 }; 269 270 L2: l2-cache-controller@20000 { 271 compatible = "fsl,mpc8572-l2-cache-controller"; 272 reg = <0x20000 0x1000>; 273 cache-line-size = <32>; // 32 bytes 274 cache-size = <0x100000>; // L2, 1M 275 interrupt-parent = <&mpic>; 276 interrupts = <16 2>; 277 }; 278 279 i2c@3000 { 280 #address-cells = <1>; 281 #size-cells = <0>; 282 cell-index = <0>; 283 compatible = "fsl-i2c"; 284 reg = <0x3000 0x100>; 285 interrupts = <43 2>; 286 interrupt-parent = <&mpic>; 287 dfsrr; 288 }; 289 290 i2c@3100 { 291 #address-cells = <1>; 292 #size-cells = <0>; 293 cell-index = <1>; 294 compatible = "fsl-i2c"; 295 reg = <0x3100 0x100>; 296 interrupts = <43 2>; 297 interrupt-parent = <&mpic>; 298 dfsrr; 299 }; 300 301 dma@c300 { 302 #address-cells = <1>; 303 #size-cells = <1>; 304 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 305 reg = <0xc300 0x4>; 306 ranges = <0x0 0xc100 0x200>; 307 cell-index = <1>; 308 dma-channel@0 { 309 compatible = "fsl,mpc8572-dma-channel", 310 "fsl,eloplus-dma-channel"; 311 reg = <0x0 0x80>; 312 cell-index = <0>; 313 interrupt-parent = <&mpic>; 314 interrupts = <76 2>; 315 }; 316 dma-channel@80 { 317 compatible = "fsl,mpc8572-dma-channel", 318 "fsl,eloplus-dma-channel"; 319 reg = <0x80 0x80>; 320 cell-index = <1>; 321 interrupt-parent = <&mpic>; 322 interrupts = <77 2>; 323 }; 324 dma-channel@100 { 325 compatible = "fsl,mpc8572-dma-channel", 326 "fsl,eloplus-dma-channel"; 327 reg = <0x100 0x80>; 328 cell-index = <2>; 329 interrupt-parent = <&mpic>; 330 interrupts = <78 2>; 331 }; 332 dma-channel@180 { 333 compatible = "fsl,mpc8572-dma-channel", 334 "fsl,eloplus-dma-channel"; 335 reg = <0x180 0x80>; 336 cell-index = <3>; 337 interrupt-parent = <&mpic>; 338 interrupts = <79 2>; 339 }; 340 }; 341 342 dma@21300 { 343 #address-cells = <1>; 344 #size-cells = <1>; 345 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 346 reg = <0x21300 0x4>; 347 ranges = <0x0 0x21100 0x200>; 348 cell-index = <0>; 349 dma-channel@0 { 350 compatible = "fsl,mpc8572-dma-channel", 351 "fsl,eloplus-dma-channel"; 352 reg = <0x0 0x80>; 353 cell-index = <0>; 354 interrupt-parent = <&mpic>; 355 interrupts = <20 2>; 356 }; 357 dma-channel@80 { 358 compatible = "fsl,mpc8572-dma-channel", 359 "fsl,eloplus-dma-channel"; 360 reg = <0x80 0x80>; 361 cell-index = <1>; 362 interrupt-parent = <&mpic>; 363 interrupts = <21 2>; 364 }; 365 dma-channel@100 { 366 compatible = "fsl,mpc8572-dma-channel", 367 "fsl,eloplus-dma-channel"; 368 reg = <0x100 0x80>; 369 cell-index = <2>; 370 interrupt-parent = <&mpic>; 371 interrupts = <22 2>; 372 }; 373 dma-channel@180 { 374 compatible = "fsl,mpc8572-dma-channel", 375 "fsl,eloplus-dma-channel"; 376 reg = <0x180 0x80>; 377 cell-index = <3>; 378 interrupt-parent = <&mpic>; 379 interrupts = <23 2>; 380 }; 381 }; 382 383 ptp_timer: ptimer@24e00 { 384 compatible = "fsl,gianfar-ptp-timer"; 385 reg = <0x24e00 0xb0>; 386 }; 387 388 enet0: ethernet@24000 { 389 #address-cells = <1>; 390 #size-cells = <1>; 391 cell-index = <0>; 392 device_type = "network"; 393 model = "eTSEC"; 394 compatible = "gianfar"; 395 reg = <0x24000 0x1000>; 396 ranges = <0x0 0x24000 0x1000>; 397 local-mac-address = [ 00 00 00 00 00 00 ]; 398 interrupts = <29 2 30 2 34 2>; 399 interrupt-parent = <&mpic>; 400 tbi-handle = <&tbi0>; 401 phy-handle = <&phy0>; 402 ptimer-handle = < &ptp_timer >; 403 phy-connection-type = "rgmii-id"; 404 405 mdio@520 { 406 #address-cells = <1>; 407 #size-cells = <0>; 408 compatible = "fsl,gianfar-mdio"; 409 reg = <0x520 0x20>; 410 411 phy0: ethernet-phy@0 { 412 interrupt-parent = <&mpic>; 413 interrupts = <10 1>; 414 reg = <0x0>; 415 }; 416 phy1: ethernet-phy@1 { 417 interrupt-parent = <&mpic>; 418 interrupts = <10 1>; 419 reg = <0x1>; 420 }; 421 phy2: ethernet-phy@2 { 422 interrupt-parent = <&mpic>; 423 interrupts = <10 1>; 424 reg = <0x2>; 425 }; 426 phy3: ethernet-phy@3 { 427 interrupt-parent = <&mpic>; 428 interrupts = <10 1>; 429 reg = <0x3>; 430 }; 431 432 tbi0: tbi-phy@11 { 433 reg = <0x11>; 434 device_type = "tbi-phy"; 435 }; 436 }; 437 }; 438 439 enet1: ethernet@25000 { 440 #address-cells = <1>; 441 #size-cells = <1>; 442 cell-index = <1>; 443 device_type = "network"; 444 model = "eTSEC"; 445 compatible = "gianfar"; 446 reg = <0x25000 0x1000>; 447 ranges = <0x0 0x25000 0x1000>; 448 local-mac-address = [ 00 00 00 00 00 00 ]; 449 interrupts = <35 2 36 2 40 2>; 450 interrupt-parent = <&mpic>; 451 tbi-handle = <&tbi1>; 452 phy-handle = <&phy1>; 453 ptimer-handle = < &ptp_timer >; 454 phy-connection-type = "rgmii-id"; 455 456 mdio@520 { 457 #address-cells = <1>; 458 #size-cells = <0>; 459 compatible = "fsl,gianfar-tbi"; 460 reg = <0x520 0x20>; 461 462 tbi1: tbi-phy@11 { 463 reg = <0x11>; 464 device_type = "tbi-phy"; 465 }; 466 }; 467 }; 468 469 enet2: ethernet@26000 { 470 #address-cells = <1>; 471 #size-cells = <1>; 472 cell-index = <2>; 473 device_type = "network"; 474 model = "eTSEC"; 475 compatible = "gianfar"; 476 reg = <0x26000 0x1000>; 477 ranges = <0x0 0x26000 0x1000>; 478 local-mac-address = [ 00 00 00 00 00 00 ]; 479 interrupts = <31 2 32 2 33 2>; 480 interrupt-parent = <&mpic>; 481 tbi-handle = <&tbi2>; 482 phy-handle = <&phy2>; 483 ptimer-handle = < &ptp_timer >; 484 phy-connection-type = "rgmii-id"; 485 486 mdio@520 { 487 #address-cells = <1>; 488 #size-cells = <0>; 489 compatible = "fsl,gianfar-tbi"; 490 reg = <0x520 0x20>; 491 492 tbi2: tbi-phy@11 { 493 reg = <0x11>; 494 device_type = "tbi-phy"; 495 }; 496 }; 497 }; 498 499 enet3: ethernet@27000 { 500 #address-cells = <1>; 501 #size-cells = <1>; 502 cell-index = <3>; 503 device_type = "network"; 504 model = "eTSEC"; 505 compatible = "gianfar"; 506 reg = <0x27000 0x1000>; 507 ranges = <0x0 0x27000 0x1000>; 508 local-mac-address = [ 00 00 00 00 00 00 ]; 509 interrupts = <37 2 38 2 39 2>; 510 interrupt-parent = <&mpic>; 511 tbi-handle = <&tbi3>; 512 phy-handle = <&phy3>; 513 phy-connection-type = "rgmii-id"; 514 515 mdio@520 { 516 #address-cells = <1>; 517 #size-cells = <0>; 518 compatible = "fsl,gianfar-tbi"; 519 reg = <0x520 0x20>; 520 521 tbi3: tbi-phy@11 { 522 reg = <0x11>; 523 device_type = "tbi-phy"; 524 }; 525 }; 526 }; 527 528 serial0: serial@4500 { 529 cell-index = <0>; 530 device_type = "serial"; 531 compatible = "ns16550"; 532 reg = <0x4500 0x100>; 533 clock-frequency = <0>; 534 interrupts = <42 2>; 535 interrupt-parent = <&mpic>; 536 }; 537 538 serial1: serial@4600 { 539 cell-index = <1>; 540 device_type = "serial"; 541 compatible = "ns16550"; 542 reg = <0x4600 0x100>; 543 clock-frequency = <0>; 544 interrupts = <42 2>; 545 interrupt-parent = <&mpic>; 546 }; 547 548 global-utilities@e0000 { //global utilities block 549 compatible = "fsl,mpc8572-guts"; 550 reg = <0xe0000 0x1000>; 551 fsl,has-rstcr; 552 }; 553 554 power@e0070{ 555 compatible = "fsl,mpc8548-pmc"; 556 reg = <0xe0070 0x14>; 557 }; 558 559 timer@41100 { 560 compatible = "fsl,mpic-global-timer"; 561 reg = <0x41100 0x204>; 562 interrupts = <0xf7 0x2>; 563 interrupt-parent = <&mpic>; 564 }; 565 566 msi@41600 { 567 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; 568 reg = <0x41600 0x80>; 569 msi-available-ranges = <0 0x100>; 570 interrupts = < 571 0xe0 0 572 0xe1 0 573 0xe2 0 574 0xe3 0 575 0xe4 0 576 0xe5 0 577 0xe6 0 578 0xe7 0>; 579 interrupt-parent = <&mpic>; 580 }; 581 582 crypto@30000 { 583 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 584 "fsl,sec2.1", "fsl,sec2.0"; 585 reg = <0x30000 0x10000>; 586 interrupts = <45 2 58 2>; 587 interrupt-parent = <&mpic>; 588 fsl,num-channels = <4>; 589 fsl,channel-fifo-len = <24>; 590 fsl,exec-units-mask = <0x9fe>; 591 fsl,descriptor-types-mask = <0x3ab0ebf>; 592 }; 593 594 /* PME (pattern-matcher) */ 595 pme@10000 { 596 device_type = "pme"; 597 compatible = "pme8572"; 598 reg = <0x10000 0x5000>; 599 interrupts = <0x39 0x2 0x40 0x2 0x41 0x2 0x42 0x2 0x43 0x2>; 600 interrupt-parent = <&mpic>; 601 }; 602 603 mpic: pic@40000 { 604 interrupt-controller; 605 #address-cells = <0>; 606 #interrupt-cells = <2>; 607 reg = <0x40000 0x40000>; 608 compatible = "chrp,open-pic"; 609 device_type = "open-pic"; 610 }; 611 }; 612 613 pci0: pcie@ffe08000 { 614 compatible = "fsl,mpc8548-pcie"; 615 device_type = "pci"; 616 #interrupt-cells = <1>; 617 #size-cells = <2>; 618 #address-cells = <3>; 619 reg = <0 0xffe08000 0 0x1000>; 620 bus-range = <0 255>; 621 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000 622 0x1000000 0x0 0x00000000 0 0xfee20000 0x0 0x00010000>; 623 clock-frequency = <33333333>; 624 interrupt-parent = <&mpic>; 625 interrupts = <24 2>; 626 interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 627 interrupt-map = < 628 /* IDSEL 0x11 func 0 - PCI slot 1 */ 629 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 630 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 631 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 632 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 633 634 /* IDSEL 0x11 func 1 - PCI slot 1 */ 635 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 636 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 637 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 638 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 639 640 /* IDSEL 0x11 func 2 - PCI slot 1 */ 641 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 642 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 643 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 644 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 645 646 /* IDSEL 0x11 func 3 - PCI slot 1 */ 647 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1 648 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 649 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 650 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 651 652 /* IDSEL 0x11 func 4 - PCI slot 1 */ 653 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1 654 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 655 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 656 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1 657 658 /* IDSEL 0x11 func 5 - PCI slot 1 */ 659 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1 660 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1 661 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1 662 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1 663 664 /* IDSEL 0x11 func 6 - PCI slot 1 */ 665 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1 666 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1 667 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1 668 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1 669 670 /* IDSEL 0x11 func 7 - PCI slot 1 */ 671 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1 672 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1 673 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1 674 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1 675 676 /* IDSEL 0x12 func 0 - PCI slot 2 */ 677 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 678 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 679 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1 680 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1 681 682 /* IDSEL 0x12 func 1 - PCI slot 2 */ 683 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1 684 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1 685 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1 686 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1 687 688 /* IDSEL 0x12 func 2 - PCI slot 2 */ 689 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1 690 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1 691 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1 692 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1 693 694 /* IDSEL 0x12 func 3 - PCI slot 2 */ 695 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1 696 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1 697 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1 698 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1 699 700 /* IDSEL 0x12 func 4 - PCI slot 2 */ 701 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1 702 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1 703 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1 704 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1 705 706 /* IDSEL 0x12 func 5 - PCI slot 2 */ 707 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1 708 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1 709 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1 710 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1 711 712 /* IDSEL 0x12 func 6 - PCI slot 2 */ 713 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1 714 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1 715 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1 716 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1 717 718 /* IDSEL 0x12 func 7 - PCI slot 2 */ 719 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1 720 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1 721 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1 722 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1 723 724 // IDSEL 0x1c USB 725 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2 726 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2 727 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2 728 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2 729 730 // IDSEL 0x1d Audio 731 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2 732 733 // IDSEL 0x1e Legacy 734 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2 735 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2 736 737 // IDSEL 0x1f IDE/SATA 738 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2 739 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2 740 741 >; 742 743 pcie@0 { 744 reg = <0x0 0x0 0x0 0x0 0x0>; 745 #size-cells = <2>; 746 #address-cells = <3>; 747 device_type = "pci"; 748 ranges = <0x2000000 0x0 0xa0000000 749 0x2000000 0x0 0xa0000000 750 0x0 0x10000000 751 752 0x1000000 0x0 0x0 753 0x1000000 0x0 0x0 754 0x0 0x10000>; 755 uli1575@0 { 756 reg = <0x0 0x0 0x0 0x0 0x0>; 757 #size-cells = <2>; 758 #address-cells = <3>; 759 ranges = <0x2000000 0x0 0xa0000000 760 0x2000000 0x0 0xa0000000 761 0x0 0x10000000 762 763 0x1000000 0x0 0x0 764 0x1000000 0x0 0x0 765 0x0 0x10000>; 766 isa@1e { 767 device_type = "isa"; 768 #interrupt-cells = <2>; 769 #size-cells = <1>; 770 #address-cells = <2>; 771 reg = <0xf000 0x0 0x0 0x0 0x0>; 772 ranges = <0x1 0x0 0x1000000 0x0 0x0 773 0x1000>; 774 interrupt-parent = <&i8259>; 775 776 i8259: interrupt-controller@20 { 777 reg = <0x1 0x20 0x2 778 0x1 0xa0 0x2 779 0x1 0x4d0 0x2>; 780 interrupt-controller; 781 device_type = "interrupt-controller"; 782 #address-cells = <0>; 783 #interrupt-cells = <2>; 784 compatible = "chrp,iic"; 785 interrupts = <9 2>; 786 interrupt-parent = <&mpic>; 787 }; 788 789 i8042@60 { 790 #size-cells = <0>; 791 #address-cells = <1>; 792 reg = <0x1 0x60 0x1 0x1 0x64 0x1>; 793 interrupts = <1 3 12 3>; 794 interrupt-parent = 795 <&i8259>; 796 797 keyboard@0 { 798 reg = <0x0>; 799 compatible = "pnpPNP,303"; 800 }; 801 802 mouse@1 { 803 reg = <0x1>; 804 compatible = "pnpPNP,f03"; 805 }; 806 }; 807 808 rtc@70 { 809 compatible = "pnpPNP,b00"; 810 reg = <0x1 0x70 0x2>; 811 }; 812 813 gpio@400 { 814 reg = <0x1 0x400 0x80>; 815 }; 816 }; 817 }; 818 }; 819 820 }; 821 822 pci1: pcie@ffe09000 { 823 compatible = "fsl,mpc8548-pcie"; 824 device_type = "pci"; 825 #interrupt-cells = <1>; 826 #size-cells = <2>; 827 #address-cells = <3>; 828 reg = <0 0xffe09000 0 0x1000>; 829 bus-range = <0 255>; 830 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000 831 0x1000000 0x0 0x00000000 0 0xfee10000 0x0 0x00010000>; 832 clock-frequency = <33333333>; 833 interrupt-parent = <&mpic>; 834 interrupts = <25 2>; 835 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 836 interrupt-map = < 837 /* IDSEL 0x0 */ 838 0000 0x0 0x0 0x1 &mpic 0x4 0x1 839 0000 0x0 0x0 0x2 &mpic 0x5 0x1 840 0000 0x0 0x0 0x3 &mpic 0x6 0x1 841 0000 0x0 0x0 0x4 &mpic 0x7 0x1 842 >; 843 pcie@0 { 844 reg = <0x0 0x0 0x0 0x0 0x0>; 845 #size-cells = <2>; 846 #address-cells = <3>; 847 device_type = "pci"; 848 ranges = <0x2000000 0x0 0x90000000 849 0x2000000 0x0 0x90000000 850 0x0 0x10000000 851 852 0x1000000 0x0 0x0 853 0x1000000 0x0 0x0 854 0x0 0x10000>; 855 }; 856 }; 857 858 pci2: pcie@ffe0a000 { 859 compatible = "fsl,mpc8548-pcie"; 860 device_type = "pci"; 861 #interrupt-cells = <1>; 862 #size-cells = <2>; 863 #address-cells = <3>; 864 reg = <0 0xffe0a000 0 0x1000>; 865 bus-range = <0 255>; 866 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000 867 0x1000000 0x0 0x00000000 0 0xfee00000 0x0 0x00010000>; 868 clock-frequency = <33333333>; 869 interrupt-parent = <&mpic>; 870 interrupts = <26 2>; 871 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 872 interrupt-map = < 873 /* IDSEL 0x0 */ 874 0000 0x0 0x0 0x1 &mpic 0x0 0x1 875 0000 0x0 0x0 0x2 &mpic 0x1 0x1 876 0000 0x0 0x0 0x3 &mpic 0x2 0x1 877 0000 0x0 0x0 0x4 &mpic 0x3 0x1 878 >; 879 pcie@0 { 880 reg = <0x0 0x0 0x0 0x0 0x0>; 881 #size-cells = <2>; 882 #address-cells = <3>; 883 device_type = "pci"; 884 ranges = <0x2000000 0x0 0x80000000 885 0x2000000 0x0 0x80000000 886 0x0 0x10000000 887 888 0x1000000 0x0 0x0 889 0x1000000 0x0 0x0 890 0x0 0x10000>; 891 }; 892 }; 893}; 894