1 2* Multi purpose pin (MPP) configuration. 3 4Required properties: 5 6- pin-map : array of pin configurations. Each pin is defined by 2 cells, 7 respectively: <pin> <function>. Pins not specified in the pin-map property 8 are assumed to have default value of <function> = 0, which means GPIO. 9 10 - pin : pin number. 11 12 - function : function ID of the pin according to the assignment tables in 13 User Manual. Each pin can have many possible functions depending on the 14 MPP unit incarnation. 15 16- pin-count: number of the physical MPP connections on the SOC (depending on 17 the model it can be 24-50, or possibly else in future devices). 18 19Example: 20 21 mpp@10000 { 22 #pin-cells = <2>; 23 compatible = "mrvl,mpp"; 24 reg = <0x10000 0x34>; 25 pin-count= <50>; 26 pin-map = < 27 0 1 /* MPP[0]: NF_IO[2] */ 28 1 1 /* MPP[1]: NF_IO[3] */ 29 2 1 /* MPP[2]: NF_IO[4] */ 30 3 1 /* MPP[3]: NF_IO[5] */ 31 4 1 /* MPP[4]: NF_IO[6] */ 32 5 1 /* MPP[5]: NF_IO[7] */ 33 6 1 /* MPP[6]: SYSRST_OUTn */ 34 7 2 /* MPP[7]: SPI_SCn */ 35 8 1 /* MPP[8]: TW_SDA */ 36 9 1 /* MPP[9]: TW_SCK */ 37 10 3 /* MPP[10]: UA0_TXD */ 38 11 3 /* MPP[11]: UA0_RXD */ 39 12 1 /* MPP[12]: SD_CLK */ 40 13 1 /* MPP[13]: SD_CMD */ 41 14 1 /* MPP[14]: SD_D[0] */ 42 15 1 /* MPP[15]: SD_D[1] */ 43 16 1 /* MPP[16]: SD_D[2] */ 44 17 1 /* MPP[17]: SD_D[3] */ 45 18 1 /* MPP[18]: NF_IO[0] */ 46 19 1 /* MPP[19]: NF_IO[1] */ 47 20 5 /* MPP[20]: SATA1_AC */ 48 21 5 >; /* MPP[21]: SATA0_AC */ 49 }; 50