1/*- 2 * Copyright (c) 2016 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28/ { 29 compatible = "xlnx,zynq-7000"; 30 #address-cells = <1>; 31 #size-cells = <1>; 32 interrupt-parent = <&GIC>; 33 34 // Reserve first half megabyte because it is not accessible to all 35 // bus masters. 36 memreserve = <0x00000000 0x00080000>; 37 38 // Zynq PS System registers. 39 // 40 ps7sys@f8000000 { 41 device_type = "soc"; 42 compatible = "simple-bus"; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x0 0xf8000000 0xf10000>; 46 47 // SLCR block 48 slcr: slcr@7000 { 49 compatible = "xlnx,zy7_slcr"; 50 reg = <0x0 0x1000>; 51 }; 52 53 // Interrupt controller 54 GIC: gic { 55 compatible = "arm,gic"; 56 interrupt-controller; 57 #address-cells = <0>; 58 #interrupt-cells = <3>; 59 reg = <0xf01000 0x1000>, // distributer registers 60 <0xf00100 0x0100>; // CPU if registers 61 }; 62 63 // L2 cache controller 64 pl310@f02000 { 65 compatible = "arm,pl310"; 66 reg = <0xf02000 0x1000>; 67 interrupts = <0 2 4>; 68 interrupt-parent = <&GIC>; 69 }; 70 71 // Device Config 72 devcfg: devcfg@7000 { 73 compatible = "xlnx,zy7_devcfg"; 74 reg = <0x7000 0x1000>; 75 interrupts = <0 8 4>; 76 interrupt-parent = <&GIC>; 77 }; 78 79 // triple timer counters0,1 80 ttc0: ttc@1000 { 81 compatible = "xlnx,ttc"; 82 reg = <0x1000 0x1000>; 83 }; 84 85 ttc1: ttc@2000 { 86 compatible = "xlnx,ttc"; 87 reg = <0x2000 0x1000>; 88 }; 89 90 // ARM Cortex A9 TWD Timer 91 global_timer: timer@f00600 { 92 compatible = "arm,mpcore-timers"; 93 #address-cells = <1>; 94 #size-cells = <0>; 95 reg = <0xf00200 0x100>, // Global Timer Regs 96 <0xf00600 0x20>; // Private Timer Regs 97 interrupts = <1 11 1>, <1 13 1>; 98 interrupt-parent = <&GIC>; 99 }; 100 101 // system watch-dog timer 102 swdt@5000 { 103 device_type = "watchdog"; 104 compatible = "xlnx,zy7_wdt"; 105 reg = <0x5000 0x1000>; 106 interrupts = <0 9 1>; 107 interrupt-parent = <&GIC>; 108 }; 109 110 scuwdt@f00620 { 111 device_type = "watchdog"; 112 compatible = "arm,mpcore_wdt"; 113 reg = <0xf00620 0x20>; 114 interrupts = <1 14 1>; 115 interrupt-parent = <&GIC>; 116 reset = <1>; 117 }; 118 119 }; // pssys@f8000000 120 121 // Zynq PS I/O Peripheral registers. 122 // 123 ps7io@e0000000 { 124 device_type = "soc"; 125 compatible = "simple-bus"; 126 #address-cells = <1>; 127 #size-cells = <1>; 128 ranges = <0x0 0xe0000000 0x300000>; 129 130 // UART controllers 131 uart0: uart@0000 { 132 device_type = "serial"; 133 compatible = "cadence,uart"; 134 status = "disabled"; 135 reg = <0x0000 0x1000>; 136 interrupts = <0 27 4>; 137 interrupt-parent = <&GIC>; 138 clock-frequency = <50000000>; 139 }; 140 141 uart1: uart@1000 { 142 device_type = "serial"; 143 compatible = "cadence,uart"; 144 status = "disabled"; 145 reg = <0x1000 0x1000>; 146 interrupts = <0 50 4>; 147 interrupt-parent = <&GIC>; 148 clock-frequency = <50000000>; 149 }; 150 151 // USB controllers 152 ehci0: ehci@2000 { 153 compatible = "xlnx,zy7_ehci"; 154 status = "disabled"; 155 reg = <0x2000 0x1000>; 156 interrupts = <0 21 4>; 157 interrupt-parent = <&GIC>; 158 }; 159 160 ehci1: ehci@3000 { 161 compatible = "xlnx,zy7_ehci"; 162 status = "disabled"; 163 reg = <0x3000 0x1000>; 164 interrupts = <0 44 4>; 165 interrupt-parent = <&GIC>; 166 }; 167 168 // GPIO controller 169 gpio: gpio@a000 { 170 compatible = "xlnx,zy7_gpio"; 171 reg = <0xa000 0x1000>; 172 interrupts = <0 20 4>; 173 interrupt-parent = <&GIC>; 174 }; 175 176 // Gigabit Ethernet controllers 177 eth0: eth@b000 { 178 device_type = "network"; 179 compatible = "cdns,zynq-gem", "cadence,gem"; 180 status = "disabled"; 181 reg = <0xb000 0x1000>; 182 interrupts = <0 22 4>; 183 interrupt-parent = <&GIC>; 184 ref-clock-num = <0>; 185 }; 186 187 eth1: eth@c000 { 188 device_type = "network"; 189 compatible = "cdns,zynq-gem", "cadence,gem"; 190 status = "disabled"; 191 reg = <0xc000 0x1000>; 192 interrupts = <0 45 4>; 193 interrupt-parent = <&GIC>; 194 ref-clock-num = <1>; 195 }; 196 197 // Quad-SPI controller 198 qspi0: qspi@d000 { 199 compatible = "xlnx,zy7_qspi"; 200 status = "disabled"; 201 reg = <0xd000 0x1000>; 202 interrupts = <0 19 4>; 203 interrupt-parent = <&GIC>; 204 ref-clock = <200000000>; // 200 Mhz 205 spi-clock = <50000000>; // 50 Mhz 206 }; 207 208 // SPI controllers 209 spi0: spi0@6000 { 210 compatible = "xlnx,zy7_spi"; 211 status = "disabled"; 212 reg = <0x6000 0x100>; 213 interrupts = <0 26 4>; 214 interrupt-parent = <&GIC>; 215 }; 216 217 spi1: spi0@7000 { 218 compatible = "xlnx,zy7_spi"; 219 status = "disabled"; 220 reg = <0x7000 0x100>; 221 interrupts = <0 49 4>; 222 interrupt-parent = <&GIC>; 223 }; 224 225 // SDIO controllers 226 sdhci0: sdhci@100000 { 227 compatible = "xlnx,zy7_sdhci"; 228 status = "disabled"; 229 reg = <0x100000 0x1000>; 230 interrupts = <0 24 4>; 231 interrupt-parent = <&GIC>; 232 max-frequency = <50000000>; 233 }; 234 235 sdhci1: sdhci@101000 { 236 compatible = "xlnx,zy7_sdhci"; 237 status = "disabled"; 238 reg = <0x101000 0x1000>; 239 interrupts = <0 47 4>; 240 interrupt-parent = <&GIC>; 241 max-frequency = <50000000>; 242 }; 243 244 }; // ps7io@e0000000 245}; 246 247