1/*- 2 * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29/ { 30 model = "Freescale Vybrid Family"; 31 compatible = "freescale,vybrid", "fsl,mvf"; 32 #address-cells = <1>; 33 #size-cells = <1>; 34 35 interrupt-parent = <&GIC>; 36 37 aliases { 38 soc = &SOC; 39 serial0 = &serial0; 40 serial1 = &serial1; 41 sai0 = &sai0; 42 sai1 = &sai1; 43 sai2 = &sai2; 44 sai3 = &sai3; 45 esai = &esai; 46 adc0 = &adc0; 47 adc1 = &adc1; 48 edma0 = &edma0; 49 edma1 = &edma1; 50 src = &SRC; 51 }; 52 53 SOC: vybrid { 54 #address-cells = <1>; 55 #size-cells = <1>; 56 compatible = "simple-bus"; 57 ranges; 58 bus-frequency = <0>; 59 60 SRC: src@4006E000 { 61 compatible = "fsl,mvf600-src"; 62 reg = <0x4006E000 0x100>; 63 }; 64 65 mscm@40001000 { 66 compatible = "fsl,mvf600-mscm"; 67 reg = <0x40001000 0x1000>; 68 }; 69 70 GIC: interrupt-controller@01c81000 { 71 compatible = "arm,gic"; 72 reg = <0x40003000 0x1000>, /* Distributor Registers */ 73 <0x40002100 0x100>; /* CPU Interface Registers */ 74 interrupt-controller; 75 #interrupt-cells = <1>; 76 }; 77 78 anadig@40050000 { 79 compatible = "fsl,mvf600-anadig"; 80 reg = <0x40050000 0x300>; 81 }; 82 83 ccm@4006b000 { 84 compatible = "fsl,mvf600-ccm"; 85 reg = <0x4006b000 0x1000>; 86 clock_names = "pll4"; 87 }; 88 89 mp_tmr@40002100 { 90 compatible = "arm,mpcore-timers"; 91 clock-frequency = <133000000>; 92 #address-cells = <1>; 93 #size-cells = <0>; 94 reg = < 0x40002200 0x100 >, /* Global Timer Registers */ 95 < 0x40002600 0x100 >; /* Private Timer Registers */ 96 interrupts = < 27 29 >; 97 interrupt-parent = < &GIC >; 98 }; 99 100 dmamux@40024000 { 101 compatible = "fsl,mvf600-dmamux"; 102 reg = <0x40024000 0x100>, 103 <0x40025000 0x100>, 104 <0x400A1000 0x100>, 105 <0x400A2000 0x100>; 106 }; 107 108 edma0: edma@40018000 { 109 compatible = "fsl,mvf600-edma"; 110 reg = <0x40018000 0x1000>, 111 <0x40019000 0x1000>; /* TCD */ 112 interrupts = < 40 41 >; 113 interrupt-parent = <&GIC>; 114 device-id = < 0 >; 115 status = "disabled"; 116 }; 117 118 edma1: edma@40098000 { 119 compatible = "fsl,mvf600-edma"; 120 reg = <0x40098000 0x1000>, 121 <0x40099000 0x1000>; /* TCD */ 122 interrupts = < 42 43 >; 123 interrupt-parent = <&GIC>; 124 device-id = < 1 >; 125 status = "disabled"; 126 }; 127 128 pit@40037000 { 129 compatible = "fsl,mvf600-pit"; 130 reg = <0x40037000 0x1000>; 131 interrupts = < 71 >; 132 interrupt-parent = <&GIC>; 133 clock-frequency = < 24000000 >; 134 }; 135 136 lptmr@40040000 { 137 compatible = "fsl,mvf600-lptmr"; 138 reg = <0x40040000 0x1000>; 139 interrupts = < 72 >; 140 interrupt-parent = <&GIC>; 141 clock-frequency = < 24000000 >; 142 }; 143 144 iomuxc@40048000 { 145 compatible = "fsl,mvf600-iomuxc"; 146 reg = <0x40048000 0x1000>; 147 }; 148 149 port@40049000 { 150 compatible = "fsl,mvf600-port"; 151 reg = <0x40049000 0x5000>; 152 interrupts = < 139 140 141 142 143 >; 153 interrupt-parent = <&GIC>; 154 }; 155 156 gpio@400FF000 { 157 compatible = "fsl,mvf600-gpio"; 158 reg = <0x400FF000 0x200>; 159 #gpio-cells = <3>; 160 gpio-controller; 161 }; 162 163 nand@400E0000 { 164 #address-cells = <1>; 165 #size-cells = <1>; 166 compatible = "fsl,mvf600-nand"; 167 reg = <0x400E0000 0x10000>; 168 interrupts = < 115 >; 169 interrupt-parent = <&GIC>; 170 clock_names = "nand"; 171 status = "disabled"; 172 173 partition@40000 { 174 reg = <0x40000 0x200000>; /* 2MB */ 175 label = "u-boot"; 176 read-only; 177 }; 178 179 partition@240000 { 180 reg = <0x240000 0x200000>; /* 2MB */ 181 label = "test"; 182 }; 183 184 partition@440000 { 185 reg = <0x440000 0xa00000>; /* 10MB */ 186 label = "kernel"; 187 }; 188 189 partition@e40000 { 190 reg = <0xe40000 0x1e000000>; /* 480MB */ 191 label = "root"; 192 }; 193 }; 194 195 sdhci0: sdhci@400B1000 { 196 compatible = "fsl,mvf600-sdhci"; 197 reg = <0x400B1000 0x1000>; 198 interrupts = < 59 >; 199 interrupt-parent = <&GIC>; 200 clock-frequency = <50000000>; 201 status = "disabled"; 202 clock_names = "esdhc0"; 203 }; 204 205 sdhci1: sdhci@400B2000 { 206 compatible = "fsl,mvf600-sdhci"; 207 reg = <0x400B2000 0x1000>; 208 interrupts = < 60 >; 209 interrupt-parent = <&GIC>; 210 clock-frequency = <50000000>; 211 status = "disabled"; 212 clock_names = "esdhc1"; 213 iomux_config = < 14 0x500060 214 15 0x500060 215 16 0x500060 216 17 0x500060 217 18 0x500060 218 19 0x500060 >; 219 }; 220 221 serial0: serial@40027000 { 222 compatible = "fsl,mvf600-uart"; 223 reg = <0x40027000 0x1000>; 224 interrupts = <93>; 225 interrupt-parent = <&GIC>; 226 current-speed = <115200>; 227 clock-frequency = < 24000000 >; 228 status = "disabled"; 229 }; 230 231 serial1: serial@40028000 { 232 compatible = "fsl,mvf600-uart"; 233 reg = <0x40028000 0x1000>; 234 interrupts = <94>; 235 interrupt-parent = <&GIC>; 236 current-speed = <115200>; 237 clock-frequency = < 24000000 >; 238 status = "disabled"; 239 }; 240 241 usb@40034000 { 242 compatible = "fsl,mvf600-usb-ehci", "usb-ehci"; 243 reg = < 0x40034000 0x1000 >, /* ehci */ 244 < 0x40035000 0x1000 >, /* usbc */ 245 < 0x40050800 0x100 >; /* phy */ 246 interrupts = < 107 >; 247 interrupt-parent = <&GIC>; 248 iomux_config = < 134 0x0001be 249 7 0x200060 >; 250 }; 251 252 usb@400b4000 { 253 compatible = "fsl,mvf600-usb-ehci", "usb-ehci"; 254 reg = < 0x400b4000 0x1000 >, /* ehci */ 255 < 0x400b5000 0x1000 >, /* usbc */ 256 < 0x40050C00 0x100 >; /* phy */ 257 interrupts = < 108 >; 258 interrupt-parent = <&GIC>; 259 iomux_config = < 134 0x0001be 260 7 0x200060 >; 261 }; 262 263 fec0: ethernet@400D0000 { 264 compatible = "fsl,mvf600-fec"; 265 reg = <0x400D0000 0x1000>; 266 interrupts = < 110 >; 267 interrupt-parent = <&GIC>; 268 phy-mode = "rmii"; 269 phy-disable-preamble; 270 status = "disabled"; 271 clock_names = "enet"; 272 iomux_config = < 45 0x100061 273 46 0x100061 274 47 0x100061 275 48 0x100060 276 49 0x100060 277 50 0x100060 278 51 0x100060 279 52 0x100060 280 53 0x100060 >; 281 }; 282 283 fec1: ethernet@400D1000 { 284 compatible = "fsl,mvf600-fec"; 285 reg = <0x400D1000 0x1000>; 286 interrupts = < 111 >; 287 interrupt-parent = <&GIC>; 288 phy-mode = "rmii"; 289 phy-disable-preamble; 290 status = "disabled"; 291 clock_names = "enet"; 292 iomux_config = < 54 0x103192 293 55 0x103193 294 56 0x103191 295 57 0x103191 296 58 0x103191 297 59 0x103191 298 60 0x103192 299 61 0x103192 300 62 0x103192 >; 301 }; 302 303 sai0: sai@4002F000 { 304 compatible = "fsl,mvf600-sai"; 305 reg = <0x4002F000 0x1000>; 306 interrupts = < 116 >; 307 interrupt-parent = <&GIC>; 308 status = "disabled"; 309 }; 310 311 sai1: sai@40030000 { 312 compatible = "fsl,mvf600-sai"; 313 reg = <0x40030000 0x1000>; 314 interrupts = < 117 >; 315 interrupt-parent = <&GIC>; 316 status = "disabled"; 317 }; 318 319 sai2: sai@40031000 { 320 compatible = "fsl,mvf600-sai"; 321 reg = <0x40031000 0x1000>; 322 interrupts = < 118 >; 323 interrupt-parent = <&GIC>; 324 status = "disabled"; 325 }; 326 327 sai3: sai@40032000 { 328 compatible = "fsl,mvf600-sai"; 329 reg = <0x40032000 0x1000>; 330 interrupts = < 119 >; 331 interrupt-parent = <&GIC>; 332 status = "disabled"; 333 edma-controller = <&edma1>; 334 edma-src-receive = < 8 >; 335 edma-src-transmit = < 9 >; 336 edma-mux-group = < 1 >; 337 clock_names = "sai3", "cko1"; 338 iomux_config = < 16 0x200060 339 19 0x200060 340 21 0x200060 341 40 0x400061 >; /* CKO1 */ 342 }; 343 344 esai: esai@40062000 { 345 compatible = "fsl,mvf600-esai"; 346 reg = <0x40062000 0x1000>; 347 interrupts = < 120 >; 348 interrupt-parent = <&GIC>; 349 status = "disabled"; 350 clock_names = "esai"; 351 iomux_config = < 45 0x400061 352 46 0x400061 353 47 0x400061 354 48 0x400060 355 49 0x400060 356 50 0x400060 357 51 0x400060 358 52 0x400060 359 78 0x3038df 360 40 0x400061 >; 361 }; 362 363 spi0: spi@4002C000 { 364 compatible = "fsl,mvf600-spi"; 365 reg = <0x4002C000 0x1000>; 366 interrupts = < 99 >; 367 interrupt-parent = <&GIC>; 368 status = "disabled"; 369 iomux_config = < 40 0x100061 370 41 0x100061 371 42 0x100060 372 43 0x100060 373 44 0x100061 >; 374 }; 375 376 spi1: spi@4002D000 { 377 compatible = "fsl,mvf600-spi"; 378 reg = <0x4002D000 0x1000>; 379 interrupts = < 100 >; 380 interrupt-parent = <&GIC>; 381 status = "disabled"; 382 }; 383 384 spi2: spi@400AC000 { 385 compatible = "fsl,mvf600-spi"; 386 reg = <0x400AC000 0x1000>; 387 interrupts = < 101 >; 388 interrupt-parent = <&GIC>; 389 status = "disabled"; 390 }; 391 392 spi3: spi@400AD000 { 393 compatible = "fsl,mvf600-spi"; 394 reg = <0x400AD000 0x1000>; 395 interrupts = < 102 >; 396 interrupt-parent = <&GIC>; 397 status = "disabled"; 398 }; 399 400 i2c0: i2c@40066000 { 401 compatible = "fsl,mvf600-i2c"; 402 reg = <0x40066000 0x1000>; 403 interrupts = < 103 >; 404 interrupt-parent = <&GIC>; 405 status = "disabled"; 406 clock_names = "ipg"; 407 iomux_config = < 36 0x2034d3 408 37 0x2034d3 409 207 0x1 410 208 0x1 >; 411 }; 412 413 i2c1: i2c@40067000 { 414 compatible = "fsl,mvf600-i2c"; 415 reg = <0x40067000 0x1000>; 416 interrupts = < 104 >; 417 interrupt-parent = <&GIC>; 418 status = "disabled"; 419 }; 420 421 i2c2: i2c@400E6000 { 422 compatible = "fsl,mvf600-i2c"; 423 reg = <0x400E6000 0x1000>; 424 interrupts = < 105 >; 425 interrupt-parent = <&GIC>; 426 status = "disabled"; 427 }; 428 429 i2c3: i2c@400E7000 { 430 compatible = "fsl,mvf600-i2c"; 431 reg = <0x400E7000 0x1000>; 432 interrupts = < 106 >; 433 interrupt-parent = <&GIC>; 434 status = "disabled"; 435 }; 436 437 adc0: adc@4003B000 { 438 compatible = "fsl,mvf600-adc"; 439 reg = <0x4003B000 0x1000>; 440 interrupts = < 85 >; 441 interrupt-parent = <&GIC>; 442 status = "disabled"; 443 }; 444 445 adc1: adc@400BB000 { 446 compatible = "fsl,mvf600-adc"; 447 reg = <0x400BB000 0x1000>; 448 interrupts = < 86 >; 449 interrupt-parent = <&GIC>; 450 status = "disabled"; 451 }; 452 453 tcon0: tcon@4003D000 { 454 compatible = "fsl,mvf600-tcon"; 455 reg = <0x4003D000 0x1000>; 456 status = "disabled"; 457 }; 458 459 dcu0: dcu4@40058000 { 460 compatible = "fsl,mvf600-dcu4"; 461 reg = <0x40058000 0x7000>; 462 interrupts = < 62 >; 463 interrupt-parent = <&GIC>; 464 status = "disabled"; 465 clock_names = "dcu0"; 466 iomux_config = < 105 0x100044 467 106 0x100044 468 107 0x100060 469 108 0x100060 470 109 0x100060 471 110 0x100060 472 111 0x100060 473 112 0x100060 474 113 0x100060 475 114 0x100060 476 115 0x100060 477 116 0x100060 478 117 0x100060 479 118 0x100060 480 119 0x100060 481 120 0x100060 482 121 0x100060 483 122 0x100060 484 123 0x100060 485 124 0x100060 486 125 0x100060 487 126 0x100060 488 127 0x100060 489 128 0x100060 490 129 0x100060 491 130 0x100060 492 131 0x100060 493 132 0x100060 494 133 0x100060 >; 495 }; 496 }; 497}; 498