1/* 2 */ 3/dts-v1/; 4 5/ { 6 model = "ARM Versatile PB"; 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "arm,versatile-pb"; 10 11 amba { 12 compatible = "simple-bus"; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges; 16 17 intc: interrupt-controller { 18 compatible = "arm,versatile-vic"; 19 reg = <0x10140000 0x1000>; 20 21 interrupt-controller; 22 #interrupt-cells = <1>; 23 }; 24 25 sic: secondary-interrupt-controller { 26 compatible = "arm,versatile-sic"; 27 reg = <0x10003000 0x28>; 28 29 interrupt-controller; 30 #interrupt-cells = <1>; 31 }; 32 33 uart0: uart0 { 34 compatible = "arm,pl011", "arm,primecell"; 35 reg = <0x101f1000 0x1000>; 36 interrupts = <12>; 37 interrupt-parent = <&intc>; 38 clock-frequency = <3000000>; 39 reg-shift = <2>; 40 }; 41 42 uart1: uart1 { 43 compatible = "arm,pl011", "arm,primecell"; 44 reg = <0x101f2000 0x1000>; 45 interrupts = <13>; 46 interrupt-parent = <&intc>; 47 clock-frequency = <3000000>; 48 reg-shift = <2>; 49 }; 50 51 uart2: uart2 { 52 compatible = "arm,pl011", "arm,primecell"; 53 reg = <0x101f3000 0x1000>; 54 interrupts = <14>; 55 interrupt-parent = <&intc>; 56 clock-frequency = <3000000>; 57 reg-shift = <2>; 58 }; 59 60 timer0 { 61 compatible = "arm,sp804", "arm,primecell"; 62 reg = <0x101e2000 0x40>; 63 interrupts = <4>; 64 interrupt-parent = <&intc>; 65 }; 66 67 pci0 { 68 69 compatible = "versatile,pci"; 70 reg = <0x10000044 0x4 71 0x10001000 0x1000 72 0x41000000 0x01000000 73 0x42000000 0x02000000>; 74 }; 75 76 net { 77 compatible = "smsc,lan91c111"; 78 reg = <0x10010000 0x10000>; 79 interrupts = <25>; 80 interrupt-parent = <&intc>; 81 }; 82 83 display { 84 compatible = "arm,pl110", "arm,primecell"; 85 reg = <0x10000050 4 86 0x10120000 0x1000>; 87 interrupts = <16>; 88 interrupt-parent = <&intc>; 89 }; 90 91 /* 92 * Cut corner here: we do not have proper interrupt 93 * controllers cascading so just hardwire SIC IRQ 3 94 * to VIC IRQ31 95 */ 96 kmi { 97 compatible = "arm,pl050", "arm,primecell"; 98 reg = <0x10006000 0x1000>; 99 interrupt-parent = <&intc>; 100 interrupts = <31>; 101 }; 102 }; 103 104 memory { 105 device_type = "memory"; 106 reg = <0 0x08000000>; /* 128MB */ 107 }; 108 109 aliases { 110 uart0 = &uart0; 111 }; 112 113 chosen { 114 stdin = "uart0"; 115 stdout = "uart0"; 116 }; 117}; 118