1/*- 2 * Copyright (c) 2011 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Developed by Damjan Marion <damjan.marion@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31/dts-v1/; 32 33/ { 34 model = "CompuLab TrimSlice"; 35 compatible = "compulab,trimslice", "nvidia,tegra20"; 36 #address-cells = <1>; 37 #size-cells = <1>; 38 39 interrupt-parent = <&GIC>; 40 41 aliases { 42 serial0 = &serial0; 43 soc = &SOC; 44 }; 45 46 memory { 47 device_type = "memory"; 48 reg = < 0x00000000 0x40000000 >; /* 1GB RAM at 0x0 */ 49 }; 50 51 52 SOC: tegra20@0 { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 compatible = "simple-bus"; 56 ranges; 57 bus-frequency = <0>; 58 59 GIC: interrupt-controller@50041000 { 60 compatible = "arm,gic"; 61 interrupt-controller; 62 #address-cells = <0>; 63 #interrupt-cells = <1>; 64 reg = < 0x50041000 0x1000 >, /* Distributor Registers */ 65 < 0x50040100 0x0100 >; /* CPU Interface Registers */ 66 }; 67 mp_tmr@50040200 { 68 compatible = "arm,mpcore-timers"; 69 clock-frequency = < 50040200 >; 70 #address-cells = <1>; 71 #size-cells = <0>; 72 reg = < 0x50040200 0x100 >, /* Global Timer Registers */ 73 < 0x50040600 0x100 >; /* Private Timer Registers */ 74 interrupts = < 27 29 >; 75 interrupt-parent = < &GIC >; 76 }; 77 78 tmr1@60005000 { 79 compatible = "nvidia,tegra2-timer"; 80 reg = <0x60005000 0x8>; 81 interrupts = < 32 >; 82 interrupt-parent = <&GIC>; 83 }; 84 85 tmr2@60005008 { 86 compatible = "nvidia,tegra2-timer"; 87 reg = <0x60005008 0x8>; 88 interrupts = < 33 >; 89 interrupt-parent = <&GIC>; 90 }; 91 92 tmrus@60005010 { 93 compatible = "nvidia,tegra2-timestamp"; 94 reg = <0x60005010 0x8>; 95 }; 96 97 tmr3@60005050 { 98 compatible = "nvidia,tegra2-timer"; 99 reg = <0x60005050 0x8>; 100 interrupts = < 73 >; 101 interrupt-parent = <&GIC>; 102 }; 103 104 tmr4@60005058 { 105 compatible = "nvidia,tegra2-timer"; 106 reg = <0x60005058 0x8>; 107 interrupts = < 74 >; 108 interrupt-parent = <&GIC>; 109 }; 110 111 serial0: serial@70006000 { 112 compatible = "ns16550"; 113 reg = <0x70006000 0x40>; 114 reg-shift = <2>; 115 interrupts = < 68 >; 116 interrupt-parent = <&GIC>; 117 clock-frequency = < 215654400 >; 118 }; 119 120 serial1: serial@70006040 { 121 compatible = "ns16550"; 122 reg = <0x70006040 0x40>; 123 reg-shift = <2>; 124 interrupts = < 69 >; 125 interrupt-parent = <&GIC>; 126 clock-frequency = < 215654400 >; 127 }; 128 129 serial2: serial@70006200 { 130 compatible = "ns16550"; 131 reg = <0x70006200 0x100>; 132 reg-shift = <2>; 133 interrupts = < 78 >; 134 interrupt-parent = <&GIC>; 135 clock-frequency = < 215654400 >; 136 }; 137 }; 138 139 chosen { 140 stdin = "serial0"; 141 stdout = "serial0"; 142 }; 143}; 144