1/*- 2 * Copyright (c) 2011 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Developed by Damjan Marion <damjan.marion@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30/dts-v1/; 31 32/ { 33 model = "CompuLab TrimSlice"; 34 compatible = "compulab,trimslice", "nvidia,tegra20"; 35 #address-cells = <1>; 36 #size-cells = <1>; 37 38 interrupt-parent = <&GIC>; 39 40 aliases { 41 serial0 = &serial0; 42 soc = &SOC; 43 }; 44 45 memory { 46 device_type = "memory"; 47 reg = < 0x00000000 0x40000000 >; /* 1GB RAM at 0x0 */ 48 }; 49 50 51 SOC: tegra20@0 { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 compatible = "simple-bus"; 55 ranges; 56 bus-frequency = <0>; 57 58 GIC: interrupt-controller@50041000 { 59 compatible = "arm,gic"; 60 interrupt-controller; 61 #address-cells = <0>; 62 #interrupt-cells = <1>; 63 reg = < 0x50041000 0x1000 >, /* Distributor Registers */ 64 < 0x50040100 0x0100 >; /* CPU Interface Registers */ 65 }; 66 mp_tmr@50040200 { 67 compatible = "arm,mpcore-timers"; 68 clock-frequency = < 50040200 >; 69 #address-cells = <1>; 70 #size-cells = <0>; 71 reg = < 0x50040200 0x100 >, /* Global Timer Registers */ 72 < 0x50040600 0x100 >; /* Private Timer Registers */ 73 interrupts = < 27 29 >; 74 interrupt-parent = < &GIC >; 75 }; 76 77 tmr1@60005000 { 78 compatible = "nvidia,tegra2-timer"; 79 reg = <0x60005000 0x8>; 80 interrupts = < 32 >; 81 interrupt-parent = <&GIC>; 82 }; 83 84 tmr2@60005008 { 85 compatible = "nvidia,tegra2-timer"; 86 reg = <0x60005008 0x8>; 87 interrupts = < 33 >; 88 interrupt-parent = <&GIC>; 89 }; 90 91 tmrus@60005010 { 92 compatible = "nvidia,tegra2-timestamp"; 93 reg = <0x60005010 0x8>; 94 }; 95 96 tmr3@60005050 { 97 compatible = "nvidia,tegra2-timer"; 98 reg = <0x60005050 0x8>; 99 interrupts = < 73 >; 100 interrupt-parent = <&GIC>; 101 }; 102 103 tmr4@60005058 { 104 compatible = "nvidia,tegra2-timer"; 105 reg = <0x60005058 0x8>; 106 interrupts = < 74 >; 107 interrupt-parent = <&GIC>; 108 }; 109 110 serial0: serial@70006000 { 111 compatible = "ns16550"; 112 reg = <0x70006000 0x40>; 113 reg-shift = <2>; 114 interrupts = < 68 >; 115 interrupt-parent = <&GIC>; 116 clock-frequency = < 215654400 >; 117 }; 118 119 serial1: serial@70006040 { 120 compatible = "ns16550"; 121 reg = <0x70006040 0x40>; 122 reg-shift = <2>; 123 interrupts = < 69 >; 124 interrupt-parent = <&GIC>; 125 clock-frequency = < 215654400 >; 126 }; 127 128 serial2: serial@70006200 { 129 compatible = "ns16550"; 130 reg = <0x70006200 0x100>; 131 reg-shift = <2>; 132 interrupts = < 78 >; 133 interrupt-parent = <&GIC>; 134 clock-frequency = < 215654400 >; 135 }; 136 }; 137 138 chosen { 139 stdin = "serial0"; 140 stdout = "serial0"; 141 }; 142}; 143