1/*- 2 * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31/* /dts-v1/; */ 32#include "socfpga_cyclone5_sockit.dts" 33 34/ { 35 model = "Terasic SoCkit"; 36 compatible = "altr,socfpga-cyclone5", "altr,socfpga"; 37 38 /* Reserve first page for secondary CPU trampoline code */ 39 memreserve = < 0x00000000 0x1000 >; 40 41 soc { 42 /* Local timer */ 43 timer@fffec600 { 44 clock-frequency = <200000000>; 45 }; 46 47 /* Global timer */ 48 global_timer: timer@fffec200 { 49 compatible = "arm,cortex-a9-global-timer"; 50 reg = <0xfffec200 0x20>; 51 interrupts = <1 11 0xf04>; 52 clock-frequency = <200000000>; 53 }; 54 }; 55 56 chosen { 57 stdin = "serial0"; 58 stdout = "serial0"; 59 }; 60}; 61 62&mmc0 { 63 bus-frequency = <25000000>; 64}; 65 66&uart0 { 67 clock-frequency = <100000000>; 68}; 69 70&uart1 { 71 status = "disabled"; 72}; 73