xref: /freebsd/sys/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts (revision 4f52dfbb8d6c4d446500c5b097e3806ec219fbd4) 
1/*-
2 * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD$
31 */
32
33/* /dts-v1/; */
34#include "socfpga_cyclone5_sockit.dts"
35
36/ {
37	model = "Terasic SoCkit";
38	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
39
40	/* Reserve first page for secondary CPU trampoline code */
41	memreserve = < 0x00000000 0x1000 >;
42
43	soc {
44		/* Local timer */
45		timer@fffec600 {
46			clock-frequency = <200000000>;
47		};
48
49		/* Global timer */
50		global_timer: timer@fffec200 {
51			compatible = "arm,cortex-a9-global-timer";
52			reg = <0xfffec200 0x20>;
53			interrupts = <1 11 0xf04>;
54			clock-frequency = <200000000>;
55		};
56	};
57
58	chosen {
59		stdin = "serial0";
60		stdout = "serial0";
61	};
62};
63
64&mmc0 {
65	bus-frequency = <25000000>;
66};
67
68&uart0 {
69	clock-frequency = <100000000>;
70};
71
72&uart1 {
73	status = "disabled";
74};
75