1/*- 2 * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31/dts-v1/; 32#include "socfpga_arria10_socdk.dtsi" 33 34/ { 35 model = "Altera SOCFPGA Arria 10"; 36 compatible = "altr,socfpga-arria10", "altr,socfpga"; 37 38 /* Reserve first page for secondary CPU trampoline code */ 39 memreserve = < 0x00000000 0x1000 >; 40 41 soc { 42 /* Local timer */ 43 timer@ffffc600 { 44 clock-frequency = <200000000>; 45 }; 46 47 /* Global timer */ 48 global_timer: timer@ffffc200 { 49 compatible = "arm,cortex-a9-global-timer"; 50 reg = <0xffffc200 0x20>; 51 interrupts = <1 11 0x301>; 52 clock-frequency = <200000000>; 53 }; 54 }; 55 56 chosen { 57 stdin = "serial1"; 58 stdout = "serial1"; 59 }; 60}; 61 62&uart1 { 63 clock-frequency = < 50000000 >; 64}; 65 66&mmc { 67 status = "okay"; 68 num-slots = <1>; 69 cap-sd-highspeed; 70 broken-cd; 71 bus-width = <4>; 72 bus-frequency = <200000000>; 73}; 74 75&i2c1 { 76 lcd@28 { 77 compatible = "newhaven,nhd-0216k3z-nsw-bbw"; 78 reg = <0x28>; 79 }; 80}; 81 82&usb0 { 83 dr_mode = "host"; 84}; 85 86&qspi { 87 status = "okay"; 88 89 dmas = <&pdma 24>, <&pdma 25>; 90 dma-names = "tx", "rx"; 91 92 flash0: n25q00@0 { 93 #address-cells = <1>; 94 #size-cells = <1>; 95 compatible = "n25q00aa"; 96 reg = <0>; 97 spi-max-frequency = <100000000>; 98 99 m25p,fast-read; 100 cdns,page-size = <256>; 101 cdns,block-size = <16>; 102 cdns,read-delay = <4>; 103 cdns,tshsl-ns = <50>; 104 cdns,tsd2d-ns = <50>; 105 cdns,tchsh-ns = <4>; 106 cdns,tslch-ns = <4>; 107 108 partition@qspi-boot { 109 label = "boot"; 110 reg = <0x0 0x2720000>; 111 }; 112 113 partition@qspi-rootfs { 114 label = "rootfs"; 115 reg = <0x2720000 0x58E0000>; 116 }; 117 }; 118}; 119