1/* 2 * Copyright (c) 2012 The FreeBSD Foundation 3 * Copyright (c) 2013 Rui Paulo 4 * All rights reserved. 5 * 6 * This software was developed by Semihalf under sponsorship from 7 * the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * Freescale i.MX535 Device Tree Source. 31 */ 32 33/ { 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 aliases { 38 soc = &SOC; 39 }; 40 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "ARM,MCIMX535"; 49 reg = <0x0>; 50 d-cache-line-size = <32>; 51 i-cache-line-size = <32>; 52 d-cache-size = <0x8000>; 53 i-cache-size = <0x8000>; 54 l2-cache-line-size = <32>; 55 l2-cache-line = <0x40000>; 56 timebase-frequency = <0>; 57 bus-frequency = <0>; 58 clock-frequency = <0>; 59 }; 60 }; 61 62 localbus@0fffc000 { 63 compatible = "simple-bus"; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 67 /* This reflects CPU decode windows setup. */ 68 ranges; 69 70 tzic: tz-interrupt-controller@0fffc000 { 71 compatible = "fsl,imx53-tzic", "fsl,tzic"; 72 interrupt-controller; 73 #interrupt-cells = <1>; 74 reg = <0x0fffc000 0x00004000>; 75 }; 76 /* 77 * 40000000 40000FFF 4K Debug ROM 78 * 40001000 40001FFF 4K ETB 79 * 40002000 40002FFF 4K ETM 80 * 40003000 40003FFF 4K TPIU 81 * 40004000 40004FFF 4K CTI0 82 * 40005000 40005FFF 4K CTI1 83 * 40006000 40006FFF 4K CTI2 84 * 40007000 40007FFF 4K CTI3 85 * 40008000 40008FFF 4K ARM Debug Unit 86 * 87 * 0FFFC000 0FFFCFFF 0x4000 TZIC 88 */ 89 }; 90 91 SOC: soc@50000000 { 92 compatible = "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 interrupt-parent = <&tzic>; 96 ranges; 97 98 aips@50000000 { /* AIPS1 */ 99 compatible = "fsl,aips-bus", "simple-bus"; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 interrupt-parent = <&tzic>; 103 ranges; 104 105 /* Required by many devices, so better to stay first */ 106 /* 53FD4000 0x4000 CCM */ 107 clock@53fd4000 { 108 compatible = "fsl,imx53-ccm"; 109 /* 63F80000 0x4000 DPLLIP1 */ 110 /* 63F84000 0x4000 DPLLIP2 */ 111 /* 63F88000 0x4000 DPLLIP3 */ 112 reg = <0x53fd4000 0x4000 113 0x63F80000 0x4000 114 0x63F84000 0x4000 115 0x63F88000 0x4000>; 116 interrupt-parent = <&tzic>; 117 interrupts = <71 72>; 118 status = "disabled"; 119 }; 120 121 /* 122 * GPIO modules moved up - to have it attached for 123 * drivers which rely on GPIO 124 */ 125 /* 53F84000 0x4000 GPIO1 */ 126 gpio1: gpio@53f84000 { 127 compatible = "fsl,imx53-gpio"; 128 reg = <0x53f84000 0x4000>; 129 interrupt-parent = <&tzic>; 130 interrupts = <50 51 42 43 44 45 46 47 48 49>; 131 /* TODO: use <> also */ 132 gpio-controller; 133 #gpio-cells = <2>; 134 interrupt-controller; 135 #interrupt-cells = <1>; 136 }; 137 138 /* 53F88000 0x4000 GPIO2 */ 139 gpio2: gpio@53f88000 { 140 compatible = "fsl,imx53-gpio"; 141 reg = <0x53f88000 0x4000>; 142 interrupt-parent = <&tzic>; 143 interrupts = <52 53>; 144 gpio-controller; 145 #gpio-cells = <2>; 146 interrupt-controller; 147 #interrupt-cells = <1>; 148 }; 149 150 /* 53F8C000 0x4000 GPIO3 */ 151 gpio3: gpio@53f8c000 { 152 compatible = "fsl,imx53-gpio"; 153 reg = <0x53f8c000 0x4000>; 154 interrupt-parent = <&tzic>; 155 interrupts = <54 55>; 156 gpio-controller; 157 #gpio-cells = <2>; 158 interrupt-controller; 159 #interrupt-cells = <1>; 160 }; 161 162 /* 53F90000 0x4000 GPIO4 */ 163 gpio4: gpio@53f90000 { 164 compatible = "fsl,imx53-gpio"; 165 reg = <0x53f90000 0x4000>; 166 interrupt-parent = <&tzic>; 167 interrupts = <56 57>; 168 gpio-controller; 169 #gpio-cells = <2>; 170 interrupt-controller; 171 #interrupt-cells = <1>; 172 }; 173 174 /* 53FDC000 0x4000 GPIO5 */ 175 gpio5: gpio@53fdc000 { 176 compatible = "fsl,imx53-gpio"; 177 reg = <0x53fdc000 0x4000>; 178 interrupt-parent = <&tzic>; 179 interrupts = <103 104>; 180 gpio-controller; 181 #gpio-cells = <2>; 182 interrupt-controller; 183 #interrupt-cells = <1>; 184 }; 185 186 /* 53FE0000 0x4000 GPIO6 */ 187 gpio6: gpio@53fe0000 { 188 compatible = "fsl,imx53-gpio"; 189 reg = <0x53fe0000 0x4000>; 190 interrupt-parent = <&tzic>; 191 interrupts = <105 106>; 192 gpio-controller; 193 #gpio-cells = <2>; 194 interrupt-controller; 195 #interrupt-cells = <1>; 196 }; 197 198 /* 53FE4000 0x4000 GPIO5 */ 199 gpio7: gpio@53fe4000 { 200 compatible = "fsl,imx53-gpio"; 201 reg = <0x53fe4000 0x4000>; 202 interrupt-parent = <&tzic>; 203 interrupts = <107 108>; 204 gpio-controller; 205 #gpio-cells = <2>; 206 interrupt-controller; 207 #interrupt-cells = <1>; 208 }; 209 210 spba@50000000 { 211 compatible = "fsl,spba-bus", "simple-bus"; 212 #address-cells = <1>; 213 #size-cells = <1>; 214 interrupt-parent = <&tzic>; 215 ranges; 216 217 /* 50004000 0x4000 ESDHC 1 */ 218 esdhc@50004000 { 219 compatible = "fsl,imx53-esdhc"; 220 reg = <0x50004000 0x4000>; 221 interrupt-parent = <&tzic>; interrupts = <1>; 222 status = "disabled"; 223 }; 224 225 /* 50008000 0x4000 ESDHC 2 */ 226 esdhc@50008000 { 227 compatible = "fsl,imx53-esdhc"; 228 reg = <0x50008000 0x4000>; 229 interrupt-parent = <&tzic>; interrupts = <2>; 230 status = "disabled"; 231 }; 232 233 /* 5000C000 0x4000 UART 3 */ 234 uart3: serial@5000c000 { 235 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 236 reg = <0x5000c000 0x4000>; 237 interrupt-parent = <&tzic>; 238 interrupts = <33>; 239 status = "disabled"; 240 }; 241 242 /* 50010000 0x4000 eCSPI1 */ 243 ecspi@50010000 { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 compatible = "fsl,imx53-ecspi"; 247 reg = <0x50010000 0x4000>; 248 interrupt-parent = <&tzic>; 249 interrupts = <36>; 250 status = "disabled"; 251 }; 252 253 /* 50014000 0x4000 SSI2 irq30 */ 254 SSI2: ssi@50014000 { 255 compatible = "fsl,imx53-ssi"; 256 reg = <0x50014000 0x4000>; 257 interrupt-parent = <&tzic>; 258 interrupts = <30>; 259 status = "disabled"; 260 }; 261 262 /* 50020000 0x4000 ESDHC 3 */ 263 esdhc@50020000 { 264 compatible = "fsl,imx53-esdhc"; 265 reg = <0x50020000 0x4000>; 266 interrupt-parent = <&tzic>; 267 interrupts = <3>; 268 status = "disabled"; 269 }; 270 271 /* 50024000 0x4000 ESDHC 4 */ 272 esdhc@50024000 { 273 compatible = "fsl,imx53-esdhc"; 274 reg = <0x50024000 0x4000>; 275 interrupt-parent = <&tzic>; 276 interrupts = <4>; 277 status = "disabled"; 278 }; 279 280 /* 50028000 0x4000 SPDIF */ 281 /* 91 SPDIF */ 282 283 pata@50030000 { 284 compatible = "fsl,imx53-ata"; 285 reg = <0x50030000 0x4000>; 286 interrupt-parent = <&tzic>; 287 interrupts = <70>; 288 status = "disabled"; 289 }; 290 291 /* 50034000 0x4000 SLM */ 292 /* 50038000 0x4000 HSI2C */ 293 /* 64 HS-I2C */ 294 /* 5003C000 0x4000 SPBA */ 295 }; 296 297 usbphy0: usbphy@0 { 298 compatible = "usb-nop-xceiv"; 299 status = "okay"; 300 }; 301 302 usbphy1: usbphy@1 { 303 compatible = "usb-nop-xceiv"; 304 status = "okay"; 305 }; 306 307 usbotg: usb@53f80000 { 308 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 309 reg = <0x53f80000 0x0200>; 310 interrupts = <18>; 311 fsl,usbphy = <&usbphy0>; 312 status = "disabled"; 313 }; 314 315 usbh1: usb@53f80200 { 316 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 317 reg = <0x53f80200 0x0200>; 318 interrupts = <14>; 319 fsl,usbphy = <&usbphy1>; 320 status = "disabled"; 321 }; 322 323 usbh2: usb@53f80400 { 324 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 325 reg = <0x53f80400 0x0200>; 326 interrupts = <16>; 327 status = "disabled"; 328 }; 329 330 usbh3: usb@53f80600 { 331 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 332 reg = <0x53f80600 0x0200>; 333 interrupts = <17>; 334 status = "disabled"; 335 }; 336 337 usbmisc: usbmisc@53f80800 { 338 #index-cells = <1>; 339 compatible = "fsl,imx53-usbmisc"; 340 reg = <0x53f80800 0x200>; 341 }; 342 343 /* 53F98000 0x4000 WDOG1 */ 344 wdog@53f98000 { 345 compatible = "fsl,imx53-wdt"; 346 reg = <0x53f98000 0x4000>; 347 interrupt-parent = <&tzic>; 348 interrupts = <58>; 349 status = "disabled"; 350 }; 351 352 /* 53F9C000 0x4000 WDOG2 (TZ) */ 353 wdog@53f9c000 { 354 compatible = "fsl,imx53-wdt"; 355 reg = <0x53f9c000 0x4000>; 356 interrupt-parent = <&tzic>; 357 interrupts = <59>; 358 status = "disabled"; 359 }; 360 361 /* 53F94000 0x4000 KPP */ 362 keyboard@53f94000 { 363 compatible = "fsl,imx53-kpp"; 364 reg = <0x53f94000 0x4000>; 365 interrupt-parent = <&tzic>; 366 interrupts = <60>; 367 status = "disabled"; 368 }; 369 370 /* 53FA0000 0x4000 GPT */ 371 timer@53fa0000 { 372 compatible = "fsl,imx53-gpt"; 373 reg = <0x53fa0000 0x4000>; 374 interrupt-parent = <&tzic>; 375 interrupts = <39>; 376 status = "disabled"; 377 }; 378 379 /* 53FA4000 0x4000 SRTC */ 380 381 rtc@53fa4000 { 382 compatible = "fsl,imx53-srtc"; 383 reg = <0x53fa4000 0x4000>; 384 interrupt-parent = <&tzic>; 385 interrupts = <24 25>; 386 status = "disabled"; 387 }; 388 389 /* 53FA8000 0x4000 IOMUXC */ 390 iomux@53fa8000 { 391 compatible = "fsl,imx53-iomux"; 392 reg = <0x53fa8000 0x4000>; 393 interrupt-parent = <&tzic>; 394 interrupts = <7>; 395 }; 396 397 /* 53FAC000 0x4000 EPIT1 */ 398 epit1: timer@53fac000 { 399 compatible = "fsl,imx53-epit"; 400 reg = <0x53fac000 0x4000>; 401 interrupt-parent = <&tzic>; 402 interrupts = <40>; 403 status = "disabled"; 404 }; 405 406 /* 53FB0000 0x4000 EPIT2 */ 407 epit2: timer@53fb0000 { 408 compatible = "fsl,imx53-epit"; 409 reg = <0x53fb0000 0x4000>; 410 interrupt-parent = <&tzic>; 411 interrupts = <41>; 412 status = "disabled"; 413 }; 414 415 /* 53FB4000 0x4000 PWM1 */ 416 pwm@53fb4000 { 417 compatible = "fsl,imx53-pwm"; 418 reg = <0x53fb4000 0x4000>; 419 interrupt-parent = <&tzic>; 420 interrupts = <61>; 421 status = "disabled"; 422 }; 423 424 /* 53FB8000 0x4000 PWM2 */ 425 pwm@53fb8000 { 426 compatible = "fsl,imx53-pwm"; 427 reg = <0x53fb8000 0x4000>; 428 interrupt-parent = <&tzic>; 429 interrupts = <94>; 430 status = "disabled"; 431 }; 432 433 /* 53FBC000 0x4000 UART 1 */ 434 uart1: serial@53fbc000 { 435 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 436 reg = <0x53fbc000 0x4000>; 437 interrupt-parent = <&tzic>; 438 interrupts = <31>; 439 status = "disabled"; 440 }; 441 442 /* 53FC0000 0x4000 UART 2 */ 443 uart2: serial@53fc0000 { 444 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 445 reg = <0x53fc0000 0x4000>; 446 interrupt-parent = <&tzic>; 447 interrupts = <32>; 448 status = "disabled"; 449 }; 450 451 /* 53FF0000 0x4000 UART 4 */ 452 uart4: serial@53ff0000 { 453 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 454 reg = <0x53ff0000 0x4000>; 455 interrupt-parent = <&tzic>; 456 interrupts = <13>; 457 status = "disabled"; 458 }; 459 460 /* 53FD0000 0x4000 SRC */ 461 reset@53fd0000 { 462 compatible = "fsl,imx53-src"; 463 reg = <0x53fd0000 0x4000>; 464 interrupt-parent = <&tzic>; 465 interrupts = <75>; 466 status = "disabled"; 467 }; 468 /* 53FD8000 0x4000 GPC */ 469 power@53fd8000 { 470 compatible = "fsl,imx53-gpc"; 471 reg = <0x53fd8000 0x4000>; 472 interrupt-parent = <&tzic>; 473 interrupts = <73 74>; 474 status = "disabled"; 475 }; 476 i2c@53fec000 { 477 #address-cells = <1>; 478 #size-cells = <0>; 479 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", 480 "fsl,imx-i2c"; 481 reg = <0x53fec000 0x4000>; 482 interrupt-parent = <&tzic>; 483 interrupts = <64>; 484 status = "disabled"; 485 }; 486 }; 487 488 aips@60000000 { /* AIPS2 */ 489 compatible = "fsl,aips-bus", "simple-bus"; 490 #address-cells = <1>; 491 #size-cells = <1>; 492 interrupt-parent = <&tzic>; 493 ranges; 494 495 /* 63F90000 0x4000 UART 5 */ 496 uart5: serial@63f90000 { 497 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 498 reg = <0x63f90000 0x4000>; 499 interrupt-parent = <&tzic>; 500 interrupts = <32>; 501 status = "disabled"; 502 }; 503 504 /* 63F94000 0x4000 AHBMAX */ 505 /* 63F98000 0x4000 IIM */ 506 /* 507 * 69 IIM Interrupt request to the processor. 508 * Indicates to the processor that program or 509 * explicit. 510 */ 511 /* 63F9C000 0x4000 CSU */ 512 /* 513 * 27 CSU Interrupt Request 1. Indicates to the 514 * processor that one or more alarm inputs were. 515 */ 516 517 /* 63FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */ 518 /* irq76 Neon Monitor Interrupt */ 519 /* irq77 Performance Unit Interrupt */ 520 /* irq78 CTI IRQ */ 521 /* irq79 Debug Interrupt, Cross-Trigger Interface 1 */ 522 /* irq80 Debug Interrupt, Cross-Trigger Interface 1 */ 523 /* irq89 Debug Interrupt, Cross-Trigger Interface 2 */ 524 /* irq98 Debug Interrupt, Cross-Trigger Interface 3 */ 525 526 /* 63FA4000 0x4000 OWIRE irq88 */ 527 /* 63FA8000 0x4000 FIRI irq93 */ 528 /* 63FAC000 0x4000 eCSPI2 */ 529 ecspi@63fac000 { 530 #address-cells = <1>; 531 #size-cells = <0>; 532 compatible = "fsl,imx53-ecspi"; 533 reg = <0x63fac000 0x4000>; 534 interrupt-parent = <&tzic>; 535 interrupts = <37>; 536 status = "disabled"; 537 }; 538 539 /* 63FB0000 0x4000 SDMA */ 540 sdma@63fb0000 { 541 compatible = "fsl,imx53-sdma"; 542 reg = <0x63fb0000 0x4000>; 543 interrupt-parent = <&tzic>; 544 interrupts = <6>; 545 }; 546 547 /* 63FB4000 0x4000 SCC */ 548 /* 21 SCC Security Monitor High Priority Interrupt. */ 549 /* 22 SCC Secure (TrustZone) Interrupt. */ 550 /* 23 SCC Regular (Non-Secure) Interrupt. */ 551 552 /* 63FB8000 0x4000 ROMCP */ 553 /* 63FBC000 0x4000 RTIC */ 554 /* 555 * 26 RTIC RTIC (Trust Zone) Interrupt Request. 556 * Indicates that the RTIC has completed hashing the 557 */ 558 559 /* 63FC0000 0x4000 CSPI */ 560 cspi@63fc0000 { 561 #address-cells = <1>; 562 #size-cells = <0>; 563 compatible = "fsl,imx53-cspi"; 564 reg = <0x63fc0000 0x4000>; 565 interrupt-parent = <&tzic>; 566 interrupts = <38>; 567 status = "disabled"; 568 }; 569 570 /* 63FC4000 0x4000 I2C2 */ 571 i2c@63fc4000 { 572 #address-cells = <1>; 573 #size-cells = <0>; 574 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c"; 575 reg = <0x63fc4000 0x4000>; 576 interrupt-parent = <&tzic>; 577 interrupts = <63>; 578 status = "disabled"; 579 }; 580 581 /* 63FC8000 0x4000 I2C1 */ 582 i2c@63fc8000 { 583 #address-cells = <1>; 584 #size-cells = <0>; 585 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c"; 586 reg = <0x63fc8000 0x4000>; 587 interrupt-parent = <&tzic>; 588 interrupts = <62>; 589 status = "disabled"; 590 }; 591 592 /* 63FCC000 0x4000 SSI1 */ 593 /* 29 SSI1 SSI-1 Interrupt Request */ 594 SSI1: ssi@63fcc000 { 595 compatible = "fsl,imx53-ssi"; 596 reg = <0x63fcc000 0x4000>; 597 interrupt-parent = <&tzic>; 598 interrupts = <29>; 599 status = "disabled"; 600 }; 601 602 /* 63FD0000 0x4000 AUDMUX */ 603 audmux@63fd4000 { 604 compatible = "fsl,imx53-audmux"; 605 reg = <0x63fd4000 0x4000>; 606 status = "disabled"; 607 }; 608 609 /* 63FD8000 0x4000 EXTMC */ 610 /* 8 EXTMC (NFC) */ 611 /* 15 EXTMC */ 612 /* 97 EXTMC Boot sequence completed interrupt */ 613 /* 614 * 101 EMI Indicates all pages have been transferred 615 * to NFC during an auto program operation. 616 */ 617 618 /* 83FE4000 0x4000 SIM */ 619 /* 67 SIM intr composed of oef, xte, sdi1, and sdi0 */ 620 /* 68 SIM intr composed of tc, etc, tfe, and rdrf */ 621 622 /* 63FD_C000 0x4000 apb2ip_pl301_2x2 */ 623 /* 63FE_0000 0x4000 apb2ip_pl301_4x1 */ 624 /* 63FE4000 0x4000 MLB */ 625 /* 63FE8000 0x4000 SSI3 */ 626 /* 96 SSI3 SSI-3 Interrupt Request */ 627 SSI3: ssi@63fe8000 { 628 compatible = "fsl,imx51-ssi"; 629 reg = <0x63fe8000 0x4000>; 630 interrupt-parent = <&tzic>; 631 interrupts = <96>; 632 status = "disabled"; 633 }; 634 635 /* 63FEC000 0x4000 FEC */ 636 ethernet@63fec000 { 637 compatible = "fsl,imx53-fec"; 638 reg = <0x63fec000 0x4000>; 639 interrupt-parent = <&tzic>; 640 interrupts = <87>; 641 status = "disabled"; 642 }; 643 644 /* 63FF0000 0x4000 TVE */ 645 /* 92 TVE */ 646 /* 63FF4000 0x4000 VPU */ 647 /* 9 VPU */ 648 /* 100 VPU Idle interrupt from VPU */ 649 650 /* 63FF8000 0x4000 SAHARA */ 651 /* 19 SAHARA SAHARA host 0 (TrustZone) Intr */ 652 /* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr */ 653 }; 654 }; 655 656 localbus@10000000 { 657 compatible = "simple-bus"; 658 #address-cells = <1>; 659 #size-cells = <1>; 660 ranges; 661 662 sata@10000000 { 663 compatible = "fsl,imx53-ata"; 664 reg = <0x10000000 0x4000>; 665 interrupt-parent = <&tzic>; 666 interrupts = <28>; 667 status = "disabled"; 668 }; 669 670 vga: ipu3@1E000000 { 671 compatible = "fsl,ipu3"; 672 reg = < 673 0x1E000000 0x08000 /* CM */ 674 0x1E008000 0x08000 /* IDMAC */ 675 0x1E018000 0x08000 /* DP */ 676 0x1E020000 0x08000 /* IC */ 677 0x1E028000 0x08000 /* IRT */ 678 0x1E030000 0x08000 /* CSI0 */ 679 0x1E038000 0x08000 /* CSI1 */ 680 0x1E040000 0x08000 /* DI0 */ 681 0x1E048000 0x08000 /* DI1 */ 682 0x1E050000 0x08000 /* SMFC */ 683 0x1E058000 0x08000 /* DC */ 684 0x1E060000 0x08000 /* DMFC */ 685 0x1E068000 0x08000 /* VDI */ 686 0x1F000000 0x20000 /* CPMEM */ 687 0x1F020000 0x20000 /* LUT */ 688 0x1F040000 0x20000 /* SRM */ 689 0x1F060000 0x20000 /* TPM */ 690 0x1F080000 0x20000 /* DCTMPL */ 691 >; 692 interrupt-parent = <&tzic>; 693 interrupts = < 694 10 /* IPUEX Error */ 695 11 /* IPUEX Sync */ 696 >; 697 status = "disabled"; 698 }; 699 }; 700}; 701 702/* 703 704TODO: Not mapped interrupts 705 7065 DAP 70784 GPU2D (OpenVG) general interrupt 70885 GPU2D (OpenVG) busy signal (for S/W power gating feasibility) 70912 GPU3D 710102 GPU3D Idle interrupt from GPU3D (for S/W power gating) 71190 SJC 712*/ 713