1/* 2 * Copyright (c) 2012 The FreeBSD Foundation 3 * Copyright (c) 2013 Rui Paulo 4 * All rights reserved. 5 * 6 * This software was developed by Semihalf under sponsorship from 7 * the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * Freescale i.MX535 Device Tree Source. 31 * 32 * $FreeBSD$ 33 */ 34 35/ { 36 #address-cells = <1>; 37 #size-cells = <1>; 38 39 aliases { 40 soc = &SOC; 41 }; 42 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu@0 { 49 device_type = "cpu"; 50 compatible = "ARM,MCIMX535"; 51 reg = <0x0>; 52 d-cache-line-size = <32>; 53 i-cache-line-size = <32>; 54 d-cache-size = <0x8000>; 55 i-cache-size = <0x8000>; 56 l2-cache-line-size = <32>; 57 l2-cache-line = <0x40000>; 58 timebase-frequency = <0>; 59 bus-frequency = <0>; 60 clock-frequency = <0>; 61 }; 62 }; 63 64 localbus@0fffc000 { 65 compatible = "simple-bus"; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 69 /* This reflects CPU decode windows setup. */ 70 ranges; 71 72 tzic: tz-interrupt-controller@0fffc000 { 73 compatible = "fsl,imx53-tzic", "fsl,tzic"; 74 interrupt-controller; 75 #interrupt-cells = <1>; 76 reg = <0x0fffc000 0x00004000>; 77 }; 78 /* 79 * 40000000 40000FFF 4K Debug ROM 80 * 40001000 40001FFF 4K ETB 81 * 40002000 40002FFF 4K ETM 82 * 40003000 40003FFF 4K TPIU 83 * 40004000 40004FFF 4K CTI0 84 * 40005000 40005FFF 4K CTI1 85 * 40006000 40006FFF 4K CTI2 86 * 40007000 40007FFF 4K CTI3 87 * 40008000 40008FFF 4K ARM Debug Unit 88 * 89 * 0FFFC000 0FFFCFFF 0x4000 TZIC 90 */ 91 }; 92 93 SOC: soc@50000000 { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 interrupt-parent = <&tzic>; 98 ranges; 99 100 aips@50000000 { /* AIPS1 */ 101 compatible = "fsl,aips-bus", "simple-bus"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 interrupt-parent = <&tzic>; 105 ranges; 106 107 /* Required by many devices, so better to stay first */ 108 /* 53FD4000 0x4000 CCM */ 109 clock@53fd4000 { 110 compatible = "fsl,imx53-ccm"; 111 /* 63F80000 0x4000 DPLLIP1 */ 112 /* 63F84000 0x4000 DPLLIP2 */ 113 /* 63F88000 0x4000 DPLLIP3 */ 114 reg = <0x53fd4000 0x4000 115 0x63F80000 0x4000 116 0x63F84000 0x4000 117 0x63F88000 0x4000>; 118 interrupt-parent = <&tzic>; 119 interrupts = <71 72>; 120 status = "disabled"; 121 }; 122 123 /* 124 * GPIO modules moved up - to have it attached for 125 * drivers which rely on GPIO 126 */ 127 /* 53F84000 0x4000 GPIO1 */ 128 gpio1: gpio@53f84000 { 129 compatible = "fsl,imx53-gpio"; 130 reg = <0x53f84000 0x4000>; 131 interrupt-parent = <&tzic>; 132 interrupts = <50 51 42 43 44 45 46 47 48 49>; 133 /* TODO: use <> also */ 134 gpio-controller; 135 #gpio-cells = <2>; 136 interrupt-controller; 137 #interrupt-cells = <1>; 138 }; 139 140 /* 53F88000 0x4000 GPIO2 */ 141 gpio2: gpio@53f88000 { 142 compatible = "fsl,imx53-gpio"; 143 reg = <0x53f88000 0x4000>; 144 interrupt-parent = <&tzic>; 145 interrupts = <52 53>; 146 gpio-controller; 147 #gpio-cells = <2>; 148 interrupt-controller; 149 #interrupt-cells = <1>; 150 }; 151 152 /* 53F8C000 0x4000 GPIO3 */ 153 gpio3: gpio@53f8c000 { 154 compatible = "fsl,imx53-gpio"; 155 reg = <0x53f8c000 0x4000>; 156 interrupt-parent = <&tzic>; 157 interrupts = <54 55>; 158 gpio-controller; 159 #gpio-cells = <2>; 160 interrupt-controller; 161 #interrupt-cells = <1>; 162 }; 163 164 /* 53F90000 0x4000 GPIO4 */ 165 gpio4: gpio@53f90000 { 166 compatible = "fsl,imx53-gpio"; 167 reg = <0x53f90000 0x4000>; 168 interrupt-parent = <&tzic>; 169 interrupts = <56 57>; 170 gpio-controller; 171 #gpio-cells = <2>; 172 interrupt-controller; 173 #interrupt-cells = <1>; 174 }; 175 176 /* 53FDC000 0x4000 GPIO5 */ 177 gpio5: gpio@53fdc000 { 178 compatible = "fsl,imx53-gpio"; 179 reg = <0x53fdc000 0x4000>; 180 interrupt-parent = <&tzic>; 181 interrupts = <103 104>; 182 gpio-controller; 183 #gpio-cells = <2>; 184 interrupt-controller; 185 #interrupt-cells = <1>; 186 }; 187 188 /* 53FE0000 0x4000 GPIO6 */ 189 gpio6: gpio@53fe0000 { 190 compatible = "fsl,imx53-gpio"; 191 reg = <0x53fe0000 0x4000>; 192 interrupt-parent = <&tzic>; 193 interrupts = <105 106>; 194 gpio-controller; 195 #gpio-cells = <2>; 196 interrupt-controller; 197 #interrupt-cells = <1>; 198 }; 199 200 /* 53FE4000 0x4000 GPIO5 */ 201 gpio7: gpio@53fe4000 { 202 compatible = "fsl,imx53-gpio"; 203 reg = <0x53fe4000 0x4000>; 204 interrupt-parent = <&tzic>; 205 interrupts = <107 108>; 206 gpio-controller; 207 #gpio-cells = <2>; 208 interrupt-controller; 209 #interrupt-cells = <1>; 210 }; 211 212 spba@50000000 { 213 compatible = "fsl,spba-bus", "simple-bus"; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 interrupt-parent = <&tzic>; 217 ranges; 218 219 /* 50004000 0x4000 ESDHC 1 */ 220 esdhc@50004000 { 221 compatible = "fsl,imx53-esdhc"; 222 reg = <0x50004000 0x4000>; 223 interrupt-parent = <&tzic>; interrupts = <1>; 224 status = "disabled"; 225 }; 226 227 /* 50008000 0x4000 ESDHC 2 */ 228 esdhc@50008000 { 229 compatible = "fsl,imx53-esdhc"; 230 reg = <0x50008000 0x4000>; 231 interrupt-parent = <&tzic>; interrupts = <2>; 232 status = "disabled"; 233 }; 234 235 /* 5000C000 0x4000 UART 3 */ 236 uart3: serial@5000c000 { 237 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 238 reg = <0x5000c000 0x4000>; 239 interrupt-parent = <&tzic>; 240 interrupts = <33>; 241 status = "disabled"; 242 }; 243 244 /* 50010000 0x4000 eCSPI1 */ 245 ecspi@50010000 { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 compatible = "fsl,imx53-ecspi"; 249 reg = <0x50010000 0x4000>; 250 interrupt-parent = <&tzic>; 251 interrupts = <36>; 252 status = "disabled"; 253 }; 254 255 /* 50014000 0x4000 SSI2 irq30 */ 256 SSI2: ssi@50014000 { 257 compatible = "fsl,imx53-ssi"; 258 reg = <0x50014000 0x4000>; 259 interrupt-parent = <&tzic>; 260 interrupts = <30>; 261 status = "disabled"; 262 }; 263 264 /* 50020000 0x4000 ESDHC 3 */ 265 esdhc@50020000 { 266 compatible = "fsl,imx53-esdhc"; 267 reg = <0x50020000 0x4000>; 268 interrupt-parent = <&tzic>; 269 interrupts = <3>; 270 status = "disabled"; 271 }; 272 273 /* 50024000 0x4000 ESDHC 4 */ 274 esdhc@50024000 { 275 compatible = "fsl,imx53-esdhc"; 276 reg = <0x50024000 0x4000>; 277 interrupt-parent = <&tzic>; 278 interrupts = <4>; 279 status = "disabled"; 280 }; 281 282 /* 50028000 0x4000 SPDIF */ 283 /* 91 SPDIF */ 284 285 pata@50030000 { 286 compatible = "fsl,imx53-ata"; 287 reg = <0x50030000 0x4000>; 288 interrupt-parent = <&tzic>; 289 interrupts = <70>; 290 status = "disabled"; 291 }; 292 293 /* 50034000 0x4000 SLM */ 294 /* 50038000 0x4000 HSI2C */ 295 /* 64 HS-I2C */ 296 /* 5003C000 0x4000 SPBA */ 297 }; 298 299 usbphy0: usbphy@0 { 300 compatible = "usb-nop-xceiv"; 301 status = "okay"; 302 }; 303 304 usbphy1: usbphy@1 { 305 compatible = "usb-nop-xceiv"; 306 status = "okay"; 307 }; 308 309 usbotg: usb@53f80000 { 310 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 311 reg = <0x53f80000 0x0200>; 312 interrupts = <18>; 313 fsl,usbphy = <&usbphy0>; 314 status = "disabled"; 315 }; 316 317 usbh1: usb@53f80200 { 318 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 319 reg = <0x53f80200 0x0200>; 320 interrupts = <14>; 321 fsl,usbphy = <&usbphy1>; 322 status = "disabled"; 323 }; 324 325 usbh2: usb@53f80400 { 326 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 327 reg = <0x53f80400 0x0200>; 328 interrupts = <16>; 329 status = "disabled"; 330 }; 331 332 usbh3: usb@53f80600 { 333 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 334 reg = <0x53f80600 0x0200>; 335 interrupts = <17>; 336 status = "disabled"; 337 }; 338 339 usbmisc: usbmisc@53f80800 { 340 #index-cells = <1>; 341 compatible = "fsl,imx53-usbmisc"; 342 reg = <0x53f80800 0x200>; 343 }; 344 345 /* 53F98000 0x4000 WDOG1 */ 346 wdog@53f98000 { 347 compatible = "fsl,imx53-wdt"; 348 reg = <0x53f98000 0x4000>; 349 interrupt-parent = <&tzic>; 350 interrupts = <58>; 351 status = "disabled"; 352 }; 353 354 /* 53F9C000 0x4000 WDOG2 (TZ) */ 355 wdog@53f9c000 { 356 compatible = "fsl,imx53-wdt"; 357 reg = <0x53f9c000 0x4000>; 358 interrupt-parent = <&tzic>; 359 interrupts = <59>; 360 status = "disabled"; 361 }; 362 363 /* 53F94000 0x4000 KPP */ 364 keyboard@53f94000 { 365 compatible = "fsl,imx53-kpp"; 366 reg = <0x53f94000 0x4000>; 367 interrupt-parent = <&tzic>; 368 interrupts = <60>; 369 status = "disabled"; 370 }; 371 372 /* 53FA0000 0x4000 GPT */ 373 timer@53fa0000 { 374 compatible = "fsl,imx53-gpt"; 375 reg = <0x53fa0000 0x4000>; 376 interrupt-parent = <&tzic>; 377 interrupts = <39>; 378 status = "disabled"; 379 }; 380 381 /* 53FA4000 0x4000 SRTC */ 382 383 rtc@53fa4000 { 384 compatible = "fsl,imx53-srtc"; 385 reg = <0x53fa4000 0x4000>; 386 interrupt-parent = <&tzic>; 387 interrupts = <24 25>; 388 status = "disabled"; 389 }; 390 391 /* 53FA8000 0x4000 IOMUXC */ 392 iomux@53fa8000 { 393 compatible = "fsl,imx53-iomux"; 394 reg = <0x53fa8000 0x4000>; 395 interrupt-parent = <&tzic>; 396 interrupts = <7>; 397 }; 398 399 /* 53FAC000 0x4000 EPIT1 */ 400 epit1: timer@53fac000 { 401 compatible = "fsl,imx53-epit"; 402 reg = <0x53fac000 0x4000>; 403 interrupt-parent = <&tzic>; 404 interrupts = <40>; 405 status = "disabled"; 406 }; 407 408 /* 53FB0000 0x4000 EPIT2 */ 409 epit2: timer@53fb0000 { 410 compatible = "fsl,imx53-epit"; 411 reg = <0x53fb0000 0x4000>; 412 interrupt-parent = <&tzic>; 413 interrupts = <41>; 414 status = "disabled"; 415 }; 416 417 /* 53FB4000 0x4000 PWM1 */ 418 pwm@53fb4000 { 419 compatible = "fsl,imx53-pwm"; 420 reg = <0x53fb4000 0x4000>; 421 interrupt-parent = <&tzic>; 422 interrupts = <61>; 423 status = "disabled"; 424 }; 425 426 /* 53FB8000 0x4000 PWM2 */ 427 pwm@53fb8000 { 428 compatible = "fsl,imx53-pwm"; 429 reg = <0x53fb8000 0x4000>; 430 interrupt-parent = <&tzic>; 431 interrupts = <94>; 432 status = "disabled"; 433 }; 434 435 /* 53FBC000 0x4000 UART 1 */ 436 uart1: serial@53fbc000 { 437 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 438 reg = <0x53fbc000 0x4000>; 439 interrupt-parent = <&tzic>; 440 interrupts = <31>; 441 status = "disabled"; 442 }; 443 444 /* 53FC0000 0x4000 UART 2 */ 445 uart2: serial@53fc0000 { 446 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 447 reg = <0x53fc0000 0x4000>; 448 interrupt-parent = <&tzic>; 449 interrupts = <32>; 450 status = "disabled"; 451 }; 452 453 /* 53FF0000 0x4000 UART 4 */ 454 uart4: serial@53ff0000 { 455 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 456 reg = <0x53ff0000 0x4000>; 457 interrupt-parent = <&tzic>; 458 interrupts = <13>; 459 status = "disabled"; 460 }; 461 462 /* 53FD0000 0x4000 SRC */ 463 reset@53fd0000 { 464 compatible = "fsl,imx53-src"; 465 reg = <0x53fd0000 0x4000>; 466 interrupt-parent = <&tzic>; 467 interrupts = <75>; 468 status = "disabled"; 469 }; 470 /* 53FD8000 0x4000 GPC */ 471 power@53fd8000 { 472 compatible = "fsl,imx53-gpc"; 473 reg = <0x53fd8000 0x4000>; 474 interrupt-parent = <&tzic>; 475 interrupts = <73 74>; 476 status = "disabled"; 477 }; 478 i2c@53fec000 { 479 #address-cells = <1>; 480 #size-cells = <0>; 481 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", 482 "fsl,imx-i2c"; 483 reg = <0x53fec000 0x4000>; 484 interrupt-parent = <&tzic>; 485 interrupts = <64>; 486 status = "disabled"; 487 }; 488 }; 489 490 aips@60000000 { /* AIPS2 */ 491 compatible = "fsl,aips-bus", "simple-bus"; 492 #address-cells = <1>; 493 #size-cells = <1>; 494 interrupt-parent = <&tzic>; 495 ranges; 496 497 /* 63F90000 0x4000 UART 5 */ 498 uart5: serial@63f90000 { 499 compatible = "fsl,imx53-uart", "fsl,imx-uart"; 500 reg = <0x63f90000 0x4000>; 501 interrupt-parent = <&tzic>; 502 interrupts = <32>; 503 status = "disabled"; 504 }; 505 506 /* 63F94000 0x4000 AHBMAX */ 507 /* 63F98000 0x4000 IIM */ 508 /* 509 * 69 IIM Interrupt request to the processor. 510 * Indicates to the processor that program or 511 * explicit. 512 */ 513 /* 63F9C000 0x4000 CSU */ 514 /* 515 * 27 CSU Interrupt Request 1. Indicates to the 516 * processor that one or more alarm inputs were. 517 */ 518 519 /* 63FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */ 520 /* irq76 Neon Monitor Interrupt */ 521 /* irq77 Performance Unit Interrupt */ 522 /* irq78 CTI IRQ */ 523 /* irq79 Debug Interrupt, Cross-Trigger Interface 1 */ 524 /* irq80 Debug Interrupt, Cross-Trigger Interface 1 */ 525 /* irq89 Debug Interrupt, Cross-Trigger Interface 2 */ 526 /* irq98 Debug Interrupt, Cross-Trigger Interface 3 */ 527 528 /* 63FA4000 0x4000 OWIRE irq88 */ 529 /* 63FA8000 0x4000 FIRI irq93 */ 530 /* 63FAC000 0x4000 eCSPI2 */ 531 ecspi@63fac000 { 532 #address-cells = <1>; 533 #size-cells = <0>; 534 compatible = "fsl,imx53-ecspi"; 535 reg = <0x63fac000 0x4000>; 536 interrupt-parent = <&tzic>; 537 interrupts = <37>; 538 status = "disabled"; 539 }; 540 541 /* 63FB0000 0x4000 SDMA */ 542 sdma@63fb0000 { 543 compatible = "fsl,imx53-sdma"; 544 reg = <0x63fb0000 0x4000>; 545 interrupt-parent = <&tzic>; 546 interrupts = <6>; 547 }; 548 549 /* 63FB4000 0x4000 SCC */ 550 /* 21 SCC Security Monitor High Priority Interrupt. */ 551 /* 22 SCC Secure (TrustZone) Interrupt. */ 552 /* 23 SCC Regular (Non-Secure) Interrupt. */ 553 554 /* 63FB8000 0x4000 ROMCP */ 555 /* 63FBC000 0x4000 RTIC */ 556 /* 557 * 26 RTIC RTIC (Trust Zone) Interrupt Request. 558 * Indicates that the RTIC has completed hashing the 559 */ 560 561 /* 63FC0000 0x4000 CSPI */ 562 cspi@63fc0000 { 563 #address-cells = <1>; 564 #size-cells = <0>; 565 compatible = "fsl,imx53-cspi"; 566 reg = <0x63fc0000 0x4000>; 567 interrupt-parent = <&tzic>; 568 interrupts = <38>; 569 status = "disabled"; 570 }; 571 572 /* 63FC4000 0x4000 I2C2 */ 573 i2c@63fc4000 { 574 #address-cells = <1>; 575 #size-cells = <0>; 576 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c"; 577 reg = <0x63fc4000 0x4000>; 578 interrupt-parent = <&tzic>; 579 interrupts = <63>; 580 status = "disabled"; 581 }; 582 583 /* 63FC8000 0x4000 I2C1 */ 584 i2c@63fc8000 { 585 #address-cells = <1>; 586 #size-cells = <0>; 587 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c"; 588 reg = <0x63fc8000 0x4000>; 589 interrupt-parent = <&tzic>; 590 interrupts = <62>; 591 status = "disabled"; 592 }; 593 594 /* 63FCC000 0x4000 SSI1 */ 595 /* 29 SSI1 SSI-1 Interrupt Request */ 596 SSI1: ssi@63fcc000 { 597 compatible = "fsl,imx53-ssi"; 598 reg = <0x63fcc000 0x4000>; 599 interrupt-parent = <&tzic>; 600 interrupts = <29>; 601 status = "disabled"; 602 }; 603 604 /* 63FD0000 0x4000 AUDMUX */ 605 audmux@63fd4000 { 606 compatible = "fsl,imx53-audmux"; 607 reg = <0x63fd4000 0x4000>; 608 status = "disabled"; 609 }; 610 611 /* 63FD8000 0x4000 EXTMC */ 612 /* 8 EXTMC (NFC) */ 613 /* 15 EXTMC */ 614 /* 97 EXTMC Boot sequence completed interrupt */ 615 /* 616 * 101 EMI Indicates all pages have been transferred 617 * to NFC during an auto program operation. 618 */ 619 620 /* 83FE4000 0x4000 SIM */ 621 /* 67 SIM intr composed of oef, xte, sdi1, and sdi0 */ 622 /* 68 SIM intr composed of tc, etc, tfe, and rdrf */ 623 624 /* 63FD_C000 0x4000 apb2ip_pl301_2x2 */ 625 /* 63FE_0000 0x4000 apb2ip_pl301_4x1 */ 626 /* 63FE4000 0x4000 MLB */ 627 /* 63FE8000 0x4000 SSI3 */ 628 /* 96 SSI3 SSI-3 Interrupt Request */ 629 SSI3: ssi@63fe8000 { 630 compatible = "fsl,imx51-ssi"; 631 reg = <0x63fe8000 0x4000>; 632 interrupt-parent = <&tzic>; 633 interrupts = <96>; 634 status = "disabled"; 635 }; 636 637 /* 63FEC000 0x4000 FEC */ 638 ethernet@63fec000 { 639 compatible = "fsl,imx53-fec"; 640 reg = <0x63fec000 0x4000>; 641 interrupt-parent = <&tzic>; 642 interrupts = <87>; 643 status = "disabled"; 644 }; 645 646 /* 63FF0000 0x4000 TVE */ 647 /* 92 TVE */ 648 /* 63FF4000 0x4000 VPU */ 649 /* 9 VPU */ 650 /* 100 VPU Idle interrupt from VPU */ 651 652 /* 63FF8000 0x4000 SAHARA */ 653 /* 19 SAHARA SAHARA host 0 (TrustZone) Intr */ 654 /* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr */ 655 }; 656 }; 657 658 localbus@10000000 { 659 compatible = "simple-bus"; 660 #address-cells = <1>; 661 #size-cells = <1>; 662 ranges; 663 664 sata@10000000 { 665 compatible = "fsl,imx53-ata"; 666 reg = <0x10000000 0x4000>; 667 interrupt-parent = <&tzic>; 668 interrupts = <28>; 669 status = "disabled"; 670 }; 671 672 vga: ipu3@1E000000 { 673 compatible = "fsl,ipu3"; 674 reg = < 675 0x1E000000 0x08000 /* CM */ 676 0x1E008000 0x08000 /* IDMAC */ 677 0x1E018000 0x08000 /* DP */ 678 0x1E020000 0x08000 /* IC */ 679 0x1E028000 0x08000 /* IRT */ 680 0x1E030000 0x08000 /* CSI0 */ 681 0x1E038000 0x08000 /* CSI1 */ 682 0x1E040000 0x08000 /* DI0 */ 683 0x1E048000 0x08000 /* DI1 */ 684 0x1E050000 0x08000 /* SMFC */ 685 0x1E058000 0x08000 /* DC */ 686 0x1E060000 0x08000 /* DMFC */ 687 0x1E068000 0x08000 /* VDI */ 688 0x1F000000 0x20000 /* CPMEM */ 689 0x1F020000 0x20000 /* LUT */ 690 0x1F040000 0x20000 /* SRM */ 691 0x1F060000 0x20000 /* TPM */ 692 0x1F080000 0x20000 /* DCTMPL */ 693 >; 694 interrupt-parent = <&tzic>; 695 interrupts = < 696 10 /* IPUEX Error */ 697 11 /* IPUEX Sync */ 698 >; 699 status = "disabled"; 700 }; 701 }; 702}; 703 704/* 705 706TODO: Not mapped interrupts 707 7085 DAP 70984 GPU2D (OpenVG) general interrupt 71085 GPU2D (OpenVG) busy signal (for S/W power gating feasibility) 71112 GPU3D 712102 GPU3D Idle interrupt from GPU3D (for S/W power gating) 71390 SJC 714*/ 715