1/* 2 * Copyright (c) 2012 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Semihalf under sponsorship from 6 * the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Freescale i.MX515 Device Tree Source. 30 * 31 * $FreeBSD$ 32 */ 33 34/ { 35 #address-cells = <1>; 36 #size-cells = <1>; 37 38 aliases { 39 soc = &SOC; 40 }; 41 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 cpu@0 { 48 device_type = "cpu"; 49 compatible = "ARM,MCIMX515"; 50 reg = <0x0>; 51 d-cache-line-size = <32>; 52 i-cache-line-size = <32>; 53 d-cache-size = <0x8000>; 54 i-cache-size = <0x8000>; 55 /* TODO: describe L2 cache also */ 56 timebase-frequency = <0>; 57 bus-frequency = <0>; 58 clock-frequency = <0>; 59 }; 60 }; 61 62 localbus@e0000000 { 63 compatible = "simple-bus"; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 67 /* This reflects CPU decode windows setup. */ 68 ranges; 69 70 tzic: tz-interrupt-controller@e0000000 { 71 compatible = "fsl,imx51-tzic", "fsl,tzic"; 72 interrupt-controller; 73 #interrupt-cells = <1>; 74 reg = <0xe0000000 0x00004000>; 75 }; 76 /* 77 * 60000000 60000FFF 4K Debug ROM 78 * 60001000 60001FFF 4K ETB 79 * 60002000 60002FFF 4K ETM 80 * 60003000 60003FFF 4K TPIU 81 * 60004000 60004FFF 4K CTI0 82 * 60005000 60005FFF 4K CTI1 83 * 60006000 60006FFF 4K CTI2 84 * 60007000 60007FFF 4K CTI3 85 * 60008000 60008FFF 4K Cortex Debug Unit 86 * 87 * E0000000 E0003FFF 0x4000 TZIC 88 */ 89 }; 90 91 SOC: soc@70000000 { 92 compatible = "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 interrupt-parent = <&tzic>; 96 ranges = <0x70000000 0x70000000 0x14000000>; 97 98 aips@70000000 { /* AIPS1 */ 99 compatible = "fsl,aips-bus", "simple-bus"; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 interrupt-parent = <&tzic>; 103 ranges; 104 105 /* Required by many devices, so better to stay first */ 106 /* 73FD4000 0x4000 CCM */ 107 clock@73fd4000 { 108 compatible = "fsl,imx51-ccm"; 109 /* 83F80000 0x4000 DPLLIP1 */ 110 /* 83F84000 0x4000 DPLLIP2 */ 111 /* 83F88000 0x4000 DPLLIP3 */ 112 reg = <0x73fd4000 0x4000 113 0x83F80000 0x4000 114 0x83F84000 0x4000 115 0x83F88000 0x4000>; 116 interrupt-parent = <&tzic>; 117 interrupts = <71 72>; 118 status = "disabled"; 119 }; 120 121 /* 122 * GPIO modules moved up - to have it attached for 123 * drivers which rely on GPIO 124 */ 125 /* 73F84000 0x4000 GPIO1 */ 126 gpio1: gpio@73f84000 { 127 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 128 reg = <0x73f84000 0x4000>; 129 interrupt-parent = <&tzic>; 130 interrupts = <50 51 42 43 44 45 46 47 48 49>; 131 /* TODO: use <> also */ 132 gpio-controller; 133 #gpio-cells = <2>; 134 interrupt-controller; 135 #interrupt-cells = <1>; 136 }; 137 138 /* 73F88000 0x4000 GPIO2 */ 139 gpio2: gpio@73f88000 { 140 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 141 reg = <0x73f88000 0x4000>; 142 interrupt-parent = <&tzic>; 143 interrupts = <52 53>; 144 gpio-controller; 145 #gpio-cells = <2>; 146 interrupt-controller; 147 #interrupt-cells = <1>; 148 }; 149 150 /* 73F8C000 0x4000 GPIO3 */ 151 gpio3: gpio@73f8c000 { 152 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 153 reg = <0x73f8c000 0x4000>; 154 interrupt-parent = <&tzic>; 155 interrupts = <54 55>; 156 gpio-controller; 157 #gpio-cells = <2>; 158 interrupt-controller; 159 #interrupt-cells = <1>; 160 }; 161 162 /* 73F90000 0x4000 GPIO4 */ 163 gpio4: gpio@73f90000 { 164 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 165 reg = <0x73f90000 0x4000>; 166 interrupt-parent = <&tzic>; 167 interrupts = <56 57>; 168 gpio-controller; 169 #gpio-cells = <2>; 170 interrupt-controller; 171 #interrupt-cells = <1>; 172 }; 173 174 spba@70000000 { 175 compatible = "fsl,spba-bus", "simple-bus"; 176 #address-cells = <1>; 177 #size-cells = <1>; 178 interrupt-parent = <&tzic>; 179 ranges; 180 181 /* 70004000 0x4000 ESDHC 1 */ 182 esdhc@70004000 { 183 compatible = "fsl,imx51-esdhc"; 184 reg = <0x70004000 0x4000>; 185 interrupt-parent = <&tzic>; interrupts = <1>; 186 status = "disabled"; 187 }; 188 189 /* 70008000 0x4000 ESDHC 2 */ 190 esdhc@70008000 { 191 compatible = "fsl,imx51-esdhc"; 192 reg = <0x70008000 0x4000>; 193 interrupt-parent = <&tzic>; interrupts = <2>; 194 status = "disabled"; 195 }; 196 197 /* 7000C000 0x4000 UART 3 */ 198 uart3: serial@7000c000 { 199 compatible = "fsl,imx51-uart", "fsl,imx-uart"; 200 reg = <0x7000c000 0x4000>; 201 interrupt-parent = <&tzic>; interrupts = <33>; 202 status = "disabled"; 203 }; 204 205 /* 70010000 0x4000 eCSPI1 */ 206 ecspi@70010000 { 207 #address-cells = <1>; 208 #size-cells = <0>; 209 compatible = "fsl,imx51-ecspi"; 210 reg = <0x70010000 0x4000>; 211 interrupt-parent = <&tzic>; interrupts = <36>; 212 status = "disabled"; 213 }; 214 215 /* 70014000 0x4000 SSI2 irq30 */ 216 SSI2: ssi@70014000 { 217 compatible = "fsl,imx51-ssi"; 218 reg = <0x70014000 0x4000>; 219 interrupt-parent = <&tzic>; interrupts = <30>; 220 status = "disabled"; 221 }; 222 223 /* 70020000 0x4000 ESDHC 3 */ 224 esdhc@70020000 { 225 compatible = "fsl,imx51-esdhc"; 226 reg = <0x70020000 0x4000>; 227 interrupt-parent = <&tzic>; interrupts = <3>; 228 status = "disabled"; 229 }; 230 231 /* 70024000 0x4000 ESDHC 4 */ 232 esdhc@70024000 { 233 compatible = "fsl,imx51-esdhc"; 234 reg = <0x70024000 0x4000>; 235 interrupt-parent = <&tzic>; interrupts = <4>; 236 status = "disabled"; 237 }; 238 239 /* 70028000 0x4000 SPDIF */ 240 /* 91 SPDIF */ 241 242 /* 70030000 0x4000 PATA (PORT UDMA) irq70 */ 243 244 /* 70034000 0x4000 SLM */ 245 /* 70038000 0x4000 HSI2C */ /* 64 HS-I2C */ 246 /* 7003C000 0x4000 SPBA */ 247 }; 248 249 usbphy0: usbphy@0 { 250 compatible = "usb-nop-xceiv"; 251 status = "okay"; 252 }; 253 254 usbotg: usb@73f80000 { 255 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 256 reg = <0x73f80000 0x0200>; 257 interrupts = <18>; 258 fsl,usbmisc = <&usbmisc 0>; 259 fsl,usbphy = <&usbphy0>; 260 status = "disabled"; 261 }; 262 263 usbh1: usb@73f80200 { 264 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 265 reg = <0x73f80200 0x0200>; 266 interrupts = <14>; 267 fsl,usbmisc = <&usbmisc 1>; 268 status = "disabled"; 269 }; 270 271 usbh2: usb@73f80400 { 272 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 273 reg = <0x73f80400 0x0200>; 274 interrupts = <16>; 275 fsl,usbmisc = <&usbmisc 2>; 276 status = "disabled"; 277 }; 278 279 usbh3: usb@73f80600 { 280 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 281 reg = <0x73f80600 0x0200>; 282 interrupts = <17>; 283 fsl,usbmisc = <&usbmisc 3>; 284 status = "disabled"; 285 }; 286 287 usbmisc: usbmisc@73f80800 { 288 #index-cells = <1>; 289 compatible = "fsl,imx51-usbmisc"; 290 reg = <0x73f80800 0x200>; 291 }; 292 293 /* 73F98000 0x4000 WDOG1 */ 294 wdog@73f98000 { 295 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 296 reg = <0x73f98000 0x4000>; 297 interrupt-parent = <&tzic>; interrupts = <58>; 298 status = "disabled"; 299 }; 300 301 /* 73F9C000 0x4000 WDOG2 (TZ) */ 302 wdog@73f9c000 { 303 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 304 reg = <0x73f9c000 0x4000>; 305 interrupt-parent = <&tzic>; interrupts = <59>; 306 status = "disabled"; 307 }; 308 309 /* 73F94000 0x4000 KPP */ 310 keyboard@73f94000 { 311 compatible = "fsl,imx51-kpp"; 312 reg = <0x73f94000 0x4000>; 313 interrupt-parent = <&tzic>; interrupts = <60>; 314 status = "disabled"; 315 }; 316 317 /* 73FA0000 0x4000 GPT */ 318 timer@73fa0000 { 319 compatible = "fsl,imx51-gpt"; 320 reg = <0x73fa0000 0x4000>; 321 interrupt-parent = <&tzic>; interrupts = <39>; 322 status = "disabled"; 323 }; 324 325 /* 73FA4000 0x4000 SRTC */ 326 327 rtc@73fa4000 { 328 compatible = "fsl,imx51-srtc"; 329 reg = <0x73fa4000 0x4000>; 330 interrupt-parent = <&tzic>; interrupts = <24 25>; 331 status = "disabled"; 332 }; 333 334 /* 73FA8000 0x4000 IOMUXC */ 335 iomux@73fa8000 { 336 compatible = "fsl,imx51-iomux"; 337 reg = <0x73fa8000 0x4000>; 338 interrupt-parent = <&tzic>; interrupts = <7>; 339 }; 340 341 /* 73FAC000 0x4000 EPIT1 */ 342 epit1: timer@73fac000 { 343 compatible = "fsl,imx51-epit"; 344 reg = <0x73fac000 0x4000>; 345 interrupt-parent = <&tzic>; interrupts = <40>; 346 status = "disabled"; 347 }; 348 349 /* 73FB0000 0x4000 EPIT2 */ 350 epit2: timer@73fb0000 { 351 compatible = "fsl,imx51-epit"; 352 reg = <0x73fb0000 0x4000>; 353 interrupt-parent = <&tzic>; interrupts = <41>; 354 status = "disabled"; 355 }; 356 357 /* 73FB4000 0x4000 PWM1 */ 358 pwm@73fb4000 { 359 compatible = "fsl,imx51-pwm"; 360 reg = <0x73fb4000 0x4000>; 361 interrupt-parent = <&tzic>; interrupts = <61>; 362 status = "disabled"; 363 }; 364 365 /* 73FB8000 0x4000 PWM2 */ 366 pwm@73fb8000 { 367 compatible = "fsl,imx51-pwm"; 368 reg = <0x73fb8000 0x4000>; 369 interrupt-parent = <&tzic>; interrupts = <94>; 370 status = "disabled"; 371 }; 372 373 /* 73FBC000 0x4000 UART 1 */ 374 uart1: serial@73fbc000 { 375 compatible = "fsl,imx51-uart", "fsl,imx-uart"; 376 reg = <0x73fbc000 0x4000>; 377 interrupt-parent = <&tzic>; interrupts = <31>; 378 status = "disabled"; 379 }; 380 381 /* 73FC0000 0x4000 UART 2 */ 382 uart2: serial@73fc0000 { 383 compatible = "fsl,imx51-uart", "fsl,imx-uart"; 384 reg = <0x73fc0000 0x4000>; 385 interrupt-parent = <&tzic>; interrupts = <32>; 386 status = "disabled"; 387 }; 388 389 /* 73FC4000 0x4000 USBOH3 */ 390 /* NOTYET 391 usb@73fc4000 { 392 compatible = "fsl,imx51-otg"; 393 reg = <0x73fc4000 0x4000>; 394 interrupt-parent = <&tzic>; interrupts = <>; 395 status = "disabled"; 396 }; 397 */ 398 /* 73FD0000 0x4000 SRC */ 399 reset@73fd0000 { 400 compatible = "fsl,imx51-src"; 401 reg = <0x73fd0000 0x4000>; 402 interrupt-parent = <&tzic>; interrupts = <75>; 403 status = "disabled"; 404 }; 405 /* 73FD8000 0x4000 GPC */ 406 power@73fd8000 { 407 compatible = "fsl,imx51-gpc"; 408 reg = <0x73fd8000 0x4000>; 409 interrupt-parent = <&tzic>; interrupts = <73 74>; 410 status = "disabled"; 411 }; 412 413 }; 414 415 aips@80000000 { /* AIPS2 */ 416 compatible = "fsl,aips-bus", "simple-bus"; 417 #address-cells = <1>; 418 #size-cells = <1>; 419 interrupt-parent = <&tzic>; 420 ranges; 421 422 /* 83F94000 0x4000 AHBMAX */ 423 /* 83F98000 0x4000 IIM */ 424 /* 425 * 69 IIM Interrupt request to the processor. 426 * Indicates to the processor that program or 427 * explicit. 428 */ 429 /* 83F9C000 0x4000 CSU */ 430 /* 431 * 27 CSU Interrupt Request 1. Indicates to the 432 * processor that one or more alarm inputs were. 433 */ 434 435 /* 83FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */ 436 /* irq76 Neon Monitor Interrupt */ 437 /* irq77 Performance Unit Interrupt */ 438 /* irq78 CTI IRQ */ 439 /* irq79 Debug Interrupt, Cross-Trigger Interface 1 */ 440 /* irq80 Debug Interrupt, Cross-Trigger Interface 1 */ 441 /* irq89 Debug Interrupt, Cross-Trigger Interface 2 */ 442 /* irq98 Debug Interrupt, Cross-Trigger Interface 3 */ 443 444 /* 83FA4000 0x4000 OWIRE irq88 */ 445 /* 83FA8000 0x4000 FIRI irq93 */ 446 /* 83FAC000 0x4000 eCSPI2 */ 447 ecspi@83fac000 { 448 #address-cells = <1>; 449 #size-cells = <0>; 450 compatible = "fsl,imx51-ecspi"; 451 reg = <0x83fac000 0x4000>; 452 interrupt-parent = <&tzic>; interrupts = <37>; 453 status = "disabled"; 454 }; 455 456 /* 83FB0000 0x4000 SDMA */ 457 sdma@83fb0000 { 458 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 459 reg = <0x83fb0000 0x4000>; 460 interrupt-parent = <&tzic>; interrupts = <6>; 461 }; 462 463 /* 83FB4000 0x4000 SCC */ 464 /* 21 SCC Security Monitor High Priority Interrupt. */ 465 /* 22 SCC Secure (TrustZone) Interrupt. */ 466 /* 23 SCC Regular (Non-Secure) Interrupt. */ 467 468 /* 83FB8000 0x4000 ROMCP */ 469 /* 83FBC000 0x4000 RTIC */ 470 /* 471 * 26 RTIC RTIC (Trust Zone) Interrupt Request. 472 * Indicates that the RTIC has completed hashing the 473 */ 474 475 /* 83FC0000 0x4000 CSPI */ 476 cspi@83fc0000 { 477 #address-cells = <1>; 478 #size-cells = <0>; 479 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 480 reg = <0x83fc0000 0x4000>; 481 interrupt-parent = <&tzic>; interrupts = <38>; 482 status = "disabled"; 483 }; 484 485 /* 83FC4000 0x4000 I2C2 */ 486 i2c@83fc4000 { 487 #address-cells = <1>; 488 #size-cells = <0>; 489 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c", "fsl,imx-i2c"; 490 reg = <0x83fc4000 0x4000>; 491 interrupt-parent = <&tzic>; interrupts = <63>; 492 status = "disabled"; 493 }; 494 495 /* 83FC8000 0x4000 I2C1 */ 496 i2c@83fc8000 { 497 #address-cells = <1>; 498 #size-cells = <0>; 499 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c", "fsl,imx-i2c"; 500 reg = <0x83fc8000 0x4000>; 501 interrupt-parent = <&tzic>; interrupts = <62>; 502 status = "disabled"; 503 }; 504 505 /* 83FCC000 0x4000 SSI1 */ 506 /* 29 SSI1 SSI-1 Interrupt Request */ 507 SSI1: ssi@83fcc000 { 508 compatible = "fsl,imx51-ssi"; 509 reg = <0x83fcc000 0x4000>; 510 interrupt-parent = <&tzic>; interrupts = <29>; 511 status = "disabled"; 512 }; 513 514 /* 83FD0000 0x4000 AUDMUX */ 515 audmux@83fd4000 { 516 compatible = "fsl,imx51-audmux"; 517 reg = <0x83fd4000 0x4000>; 518 status = "disabled"; 519 }; 520 521 /* 83FD8000 0x4000 EMI1 */ 522 /* 8 EMI (NFC) */ 523 /* 15 EMI */ 524 /* 97 EMI Boot sequence completed interrupt */ 525 /* 526 * 101 EMI Indicates all pages have been transferred 527 * to NFC during an auto program operation. 528 */ 529 530 /* 83FE0000 0x4000 PATA (PORT PIO) */ 531 /* 70 PATA Parallel ATA host controller interrupt */ 532 ide@83fe0000 { 533 compatible = "fsl,imx51-ata"; 534 reg = <0x83fe0000 0x4000>; 535 interrupt-parent = <&tzic>; 536 interrupts = <70>; 537 status = "disabled"; 538 }; 539 540 /* 83FE4000 0x4000 SIM */ 541 /* 67 SIM intr composed of oef, xte, sdi1, and sdi0 */ 542 /* 68 SIM intr composed of tc, etc, tfe, and rdrf */ 543 544 /* 83FE8000 0x4000 SSI3 */ 545 /* 96 SSI3 SSI-3 Interrupt Request */ 546 SSI3: ssi@83fe8000 { 547 compatible = "fsl,imx51-ssi"; 548 reg = <0x83fe8000 0x4000>; 549 interrupt-parent = <&tzic>; interrupts = <96>; 550 status = "disabled"; 551 }; 552 553 /* 83FEC000 0x4000 FEC */ 554 ethernet@83fec000 { 555 compatible = "fsl,imx51-fec"; 556 reg = <0x83fec000 0x4000>; 557 interrupt-parent = <&tzic>; interrupts = <87>; 558 status = "disabled"; 559 }; 560 561 /* 83FF0000 0x4000 TVE */ 562 /* 92 TVE */ 563 /* 83FF4000 0x4000 VPU */ 564 /* 9 VPU */ 565 /* 100 VPU Idle interrupt from VPU */ 566 567 /* 83FF8000 0x4000 SAHARA Lite */ 568 /* 19 SAHARA SAHARA host 0 (TrustZone) Intr Lite */ 569 /* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr Lite */ 570 }; 571 }; 572 573 localbus@5e000000 { 574 compatible = "simple-bus"; 575 #address-cells = <1>; 576 #size-cells = <1>; 577 578 ranges; 579 580 vga: ipu3@5e000000 { 581 compatible = "fsl,ipu3"; 582 reg = < 583 0x5e000000 0x08000 /* CM */ 584 0x5e008000 0x08000 /* IDMAC */ 585 0x5e018000 0x08000 /* DP */ 586 0x5e020000 0x08000 /* IC */ 587 0x5e028000 0x08000 /* IRT */ 588 0x5e030000 0x08000 /* CSI0 */ 589 0x5e038000 0x08000 /* CSI1 */ 590 0x5e040000 0x08000 /* DI0 */ 591 0x5e048000 0x08000 /* DI1 */ 592 0x5e050000 0x08000 /* SMFC */ 593 0x5e058000 0x08000 /* DC */ 594 0x5e060000 0x08000 /* DMFC */ 595 0x5e068000 0x08000 /* VDI */ 596 0x5f000000 0x20000 /* CPMEM */ 597 0x5f020000 0x20000 /* LUT */ 598 0x5f040000 0x20000 /* SRM */ 599 0x5f060000 0x20000 /* TPM */ 600 0x5f080000 0x20000 /* DCTMPL */ 601 >; 602 interrupt-parent = <&tzic>; 603 interrupts = < 604 10 /* IPUEX Error */ 605 11 /* IPUEX Sync */ 606 >; 607 status = "disabled"; 608 }; 609 }; 610}; 611 612/* 613 614TODO: Not mapped interrupts 615 6165 DAP 61784 GPU2D (OpenVG) general interrupt 61885 GPU2D (OpenVG) busy signal (for S/W power gating feasibility) 61912 GPU3D 620102 GPU3D Idle interrupt from GPU3D (for S/W power gating) 62190 SJC 622*/ 623