1/* 2 * Copyright (c) 2012 The FreeBSD Foundation 3 * 4 * This software was developed by Semihalf under sponsorship from 5 * the FreeBSD Foundation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Freescale i.MX515 Device Tree Source. 29 */ 30 31/ { 32 #address-cells = <1>; 33 #size-cells = <1>; 34 35 aliases { 36 soc = &SOC; 37 }; 38 39 40 cpus { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 44 cpu@0 { 45 device_type = "cpu"; 46 compatible = "ARM,MCIMX515"; 47 reg = <0x0>; 48 d-cache-line-size = <32>; 49 i-cache-line-size = <32>; 50 d-cache-size = <0x8000>; 51 i-cache-size = <0x8000>; 52 /* TODO: describe L2 cache also */ 53 timebase-frequency = <0>; 54 bus-frequency = <0>; 55 clock-frequency = <0>; 56 }; 57 }; 58 59 localbus@e0000000 { 60 compatible = "simple-bus"; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 64 /* This reflects CPU decode windows setup. */ 65 ranges; 66 67 tzic: tz-interrupt-controller@e0000000 { 68 compatible = "fsl,imx51-tzic", "fsl,tzic"; 69 interrupt-controller; 70 #interrupt-cells = <1>; 71 reg = <0xe0000000 0x00004000>; 72 }; 73 /* 74 * 60000000 60000FFF 4K Debug ROM 75 * 60001000 60001FFF 4K ETB 76 * 60002000 60002FFF 4K ETM 77 * 60003000 60003FFF 4K TPIU 78 * 60004000 60004FFF 4K CTI0 79 * 60005000 60005FFF 4K CTI1 80 * 60006000 60006FFF 4K CTI2 81 * 60007000 60007FFF 4K CTI3 82 * 60008000 60008FFF 4K Cortex Debug Unit 83 * 84 * E0000000 E0003FFF 0x4000 TZIC 85 */ 86 }; 87 88 SOC: soc@70000000 { 89 compatible = "simple-bus"; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 interrupt-parent = <&tzic>; 93 ranges = <0x70000000 0x70000000 0x14000000>; 94 95 aips@70000000 { /* AIPS1 */ 96 compatible = "fsl,aips-bus", "simple-bus"; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 interrupt-parent = <&tzic>; 100 ranges; 101 102 /* Required by many devices, so better to stay first */ 103 /* 73FD4000 0x4000 CCM */ 104 clock@73fd4000 { 105 compatible = "fsl,imx51-ccm"; 106 /* 83F80000 0x4000 DPLLIP1 */ 107 /* 83F84000 0x4000 DPLLIP2 */ 108 /* 83F88000 0x4000 DPLLIP3 */ 109 reg = <0x73fd4000 0x4000 110 0x83F80000 0x4000 111 0x83F84000 0x4000 112 0x83F88000 0x4000>; 113 interrupt-parent = <&tzic>; 114 interrupts = <71 72>; 115 status = "disabled"; 116 }; 117 118 /* 119 * GPIO modules moved up - to have it attached for 120 * drivers which rely on GPIO 121 */ 122 /* 73F84000 0x4000 GPIO1 */ 123 gpio1: gpio@73f84000 { 124 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 125 reg = <0x73f84000 0x4000>; 126 interrupt-parent = <&tzic>; 127 interrupts = <50 51 42 43 44 45 46 47 48 49>; 128 /* TODO: use <> also */ 129 gpio-controller; 130 #gpio-cells = <2>; 131 interrupt-controller; 132 #interrupt-cells = <1>; 133 }; 134 135 /* 73F88000 0x4000 GPIO2 */ 136 gpio2: gpio@73f88000 { 137 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 138 reg = <0x73f88000 0x4000>; 139 interrupt-parent = <&tzic>; 140 interrupts = <52 53>; 141 gpio-controller; 142 #gpio-cells = <2>; 143 interrupt-controller; 144 #interrupt-cells = <1>; 145 }; 146 147 /* 73F8C000 0x4000 GPIO3 */ 148 gpio3: gpio@73f8c000 { 149 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 150 reg = <0x73f8c000 0x4000>; 151 interrupt-parent = <&tzic>; 152 interrupts = <54 55>; 153 gpio-controller; 154 #gpio-cells = <2>; 155 interrupt-controller; 156 #interrupt-cells = <1>; 157 }; 158 159 /* 73F90000 0x4000 GPIO4 */ 160 gpio4: gpio@73f90000 { 161 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 162 reg = <0x73f90000 0x4000>; 163 interrupt-parent = <&tzic>; 164 interrupts = <56 57>; 165 gpio-controller; 166 #gpio-cells = <2>; 167 interrupt-controller; 168 #interrupt-cells = <1>; 169 }; 170 171 spba@70000000 { 172 compatible = "fsl,spba-bus", "simple-bus"; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 interrupt-parent = <&tzic>; 176 ranges; 177 178 /* 70004000 0x4000 ESDHC 1 */ 179 esdhc@70004000 { 180 compatible = "fsl,imx51-esdhc"; 181 reg = <0x70004000 0x4000>; 182 interrupt-parent = <&tzic>; interrupts = <1>; 183 status = "disabled"; 184 }; 185 186 /* 70008000 0x4000 ESDHC 2 */ 187 esdhc@70008000 { 188 compatible = "fsl,imx51-esdhc"; 189 reg = <0x70008000 0x4000>; 190 interrupt-parent = <&tzic>; interrupts = <2>; 191 status = "disabled"; 192 }; 193 194 /* 7000C000 0x4000 UART 3 */ 195 uart3: serial@7000c000 { 196 compatible = "fsl,imx51-uart", "fsl,imx-uart"; 197 reg = <0x7000c000 0x4000>; 198 interrupt-parent = <&tzic>; interrupts = <33>; 199 status = "disabled"; 200 }; 201 202 /* 70010000 0x4000 eCSPI1 */ 203 ecspi@70010000 { 204 #address-cells = <1>; 205 #size-cells = <0>; 206 compatible = "fsl,imx51-ecspi"; 207 reg = <0x70010000 0x4000>; 208 interrupt-parent = <&tzic>; interrupts = <36>; 209 status = "disabled"; 210 }; 211 212 /* 70014000 0x4000 SSI2 irq30 */ 213 SSI2: ssi@70014000 { 214 compatible = "fsl,imx51-ssi"; 215 reg = <0x70014000 0x4000>; 216 interrupt-parent = <&tzic>; interrupts = <30>; 217 status = "disabled"; 218 }; 219 220 /* 70020000 0x4000 ESDHC 3 */ 221 esdhc@70020000 { 222 compatible = "fsl,imx51-esdhc"; 223 reg = <0x70020000 0x4000>; 224 interrupt-parent = <&tzic>; interrupts = <3>; 225 status = "disabled"; 226 }; 227 228 /* 70024000 0x4000 ESDHC 4 */ 229 esdhc@70024000 { 230 compatible = "fsl,imx51-esdhc"; 231 reg = <0x70024000 0x4000>; 232 interrupt-parent = <&tzic>; interrupts = <4>; 233 status = "disabled"; 234 }; 235 236 /* 70028000 0x4000 SPDIF */ 237 /* 91 SPDIF */ 238 239 /* 70030000 0x4000 PATA (PORT UDMA) irq70 */ 240 241 /* 70034000 0x4000 SLM */ 242 /* 70038000 0x4000 HSI2C */ /* 64 HS-I2C */ 243 /* 7003C000 0x4000 SPBA */ 244 }; 245 246 usbphy0: usbphy@0 { 247 compatible = "usb-nop-xceiv"; 248 status = "okay"; 249 }; 250 251 usbotg: usb@73f80000 { 252 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 253 reg = <0x73f80000 0x0200>; 254 interrupts = <18>; 255 fsl,usbmisc = <&usbmisc 0>; 256 fsl,usbphy = <&usbphy0>; 257 status = "disabled"; 258 }; 259 260 usbh1: usb@73f80200 { 261 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 262 reg = <0x73f80200 0x0200>; 263 interrupts = <14>; 264 fsl,usbmisc = <&usbmisc 1>; 265 status = "disabled"; 266 }; 267 268 usbh2: usb@73f80400 { 269 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 270 reg = <0x73f80400 0x0200>; 271 interrupts = <16>; 272 fsl,usbmisc = <&usbmisc 2>; 273 status = "disabled"; 274 }; 275 276 usbh3: usb@73f80600 { 277 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 278 reg = <0x73f80600 0x0200>; 279 interrupts = <17>; 280 fsl,usbmisc = <&usbmisc 3>; 281 status = "disabled"; 282 }; 283 284 usbmisc: usbmisc@73f80800 { 285 #index-cells = <1>; 286 compatible = "fsl,imx51-usbmisc"; 287 reg = <0x73f80800 0x200>; 288 }; 289 290 /* 73F98000 0x4000 WDOG1 */ 291 wdog@73f98000 { 292 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 293 reg = <0x73f98000 0x4000>; 294 interrupt-parent = <&tzic>; interrupts = <58>; 295 status = "disabled"; 296 }; 297 298 /* 73F9C000 0x4000 WDOG2 (TZ) */ 299 wdog@73f9c000 { 300 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 301 reg = <0x73f9c000 0x4000>; 302 interrupt-parent = <&tzic>; interrupts = <59>; 303 status = "disabled"; 304 }; 305 306 /* 73F94000 0x4000 KPP */ 307 keyboard@73f94000 { 308 compatible = "fsl,imx51-kpp"; 309 reg = <0x73f94000 0x4000>; 310 interrupt-parent = <&tzic>; interrupts = <60>; 311 status = "disabled"; 312 }; 313 314 /* 73FA0000 0x4000 GPT */ 315 timer@73fa0000 { 316 compatible = "fsl,imx51-gpt"; 317 reg = <0x73fa0000 0x4000>; 318 interrupt-parent = <&tzic>; interrupts = <39>; 319 status = "disabled"; 320 }; 321 322 /* 73FA4000 0x4000 SRTC */ 323 324 rtc@73fa4000 { 325 compatible = "fsl,imx51-srtc"; 326 reg = <0x73fa4000 0x4000>; 327 interrupt-parent = <&tzic>; interrupts = <24 25>; 328 status = "disabled"; 329 }; 330 331 /* 73FA8000 0x4000 IOMUXC */ 332 iomux@73fa8000 { 333 compatible = "fsl,imx51-iomux"; 334 reg = <0x73fa8000 0x4000>; 335 interrupt-parent = <&tzic>; interrupts = <7>; 336 }; 337 338 /* 73FAC000 0x4000 EPIT1 */ 339 epit1: timer@73fac000 { 340 compatible = "fsl,imx51-epit"; 341 reg = <0x73fac000 0x4000>; 342 interrupt-parent = <&tzic>; interrupts = <40>; 343 status = "disabled"; 344 }; 345 346 /* 73FB0000 0x4000 EPIT2 */ 347 epit2: timer@73fb0000 { 348 compatible = "fsl,imx51-epit"; 349 reg = <0x73fb0000 0x4000>; 350 interrupt-parent = <&tzic>; interrupts = <41>; 351 status = "disabled"; 352 }; 353 354 /* 73FB4000 0x4000 PWM1 */ 355 pwm@73fb4000 { 356 compatible = "fsl,imx51-pwm"; 357 reg = <0x73fb4000 0x4000>; 358 interrupt-parent = <&tzic>; interrupts = <61>; 359 status = "disabled"; 360 }; 361 362 /* 73FB8000 0x4000 PWM2 */ 363 pwm@73fb8000 { 364 compatible = "fsl,imx51-pwm"; 365 reg = <0x73fb8000 0x4000>; 366 interrupt-parent = <&tzic>; interrupts = <94>; 367 status = "disabled"; 368 }; 369 370 /* 73FBC000 0x4000 UART 1 */ 371 uart1: serial@73fbc000 { 372 compatible = "fsl,imx51-uart", "fsl,imx-uart"; 373 reg = <0x73fbc000 0x4000>; 374 interrupt-parent = <&tzic>; interrupts = <31>; 375 status = "disabled"; 376 }; 377 378 /* 73FC0000 0x4000 UART 2 */ 379 uart2: serial@73fc0000 { 380 compatible = "fsl,imx51-uart", "fsl,imx-uart"; 381 reg = <0x73fc0000 0x4000>; 382 interrupt-parent = <&tzic>; interrupts = <32>; 383 status = "disabled"; 384 }; 385 386 /* 73FC4000 0x4000 USBOH3 */ 387 /* NOTYET 388 usb@73fc4000 { 389 compatible = "fsl,imx51-otg"; 390 reg = <0x73fc4000 0x4000>; 391 interrupt-parent = <&tzic>; interrupts = <>; 392 status = "disabled"; 393 }; 394 */ 395 /* 73FD0000 0x4000 SRC */ 396 reset@73fd0000 { 397 compatible = "fsl,imx51-src"; 398 reg = <0x73fd0000 0x4000>; 399 interrupt-parent = <&tzic>; interrupts = <75>; 400 status = "disabled"; 401 }; 402 /* 73FD8000 0x4000 GPC */ 403 power@73fd8000 { 404 compatible = "fsl,imx51-gpc"; 405 reg = <0x73fd8000 0x4000>; 406 interrupt-parent = <&tzic>; interrupts = <73 74>; 407 status = "disabled"; 408 }; 409 410 }; 411 412 aips@80000000 { /* AIPS2 */ 413 compatible = "fsl,aips-bus", "simple-bus"; 414 #address-cells = <1>; 415 #size-cells = <1>; 416 interrupt-parent = <&tzic>; 417 ranges; 418 419 /* 83F94000 0x4000 AHBMAX */ 420 /* 83F98000 0x4000 IIM */ 421 /* 422 * 69 IIM Interrupt request to the processor. 423 * Indicates to the processor that program or 424 * explicit. 425 */ 426 /* 83F9C000 0x4000 CSU */ 427 /* 428 * 27 CSU Interrupt Request 1. Indicates to the 429 * processor that one or more alarm inputs were. 430 */ 431 432 /* 83FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */ 433 /* irq76 Neon Monitor Interrupt */ 434 /* irq77 Performance Unit Interrupt */ 435 /* irq78 CTI IRQ */ 436 /* irq79 Debug Interrupt, Cross-Trigger Interface 1 */ 437 /* irq80 Debug Interrupt, Cross-Trigger Interface 1 */ 438 /* irq89 Debug Interrupt, Cross-Trigger Interface 2 */ 439 /* irq98 Debug Interrupt, Cross-Trigger Interface 3 */ 440 441 /* 83FA4000 0x4000 OWIRE irq88 */ 442 /* 83FA8000 0x4000 FIRI irq93 */ 443 /* 83FAC000 0x4000 eCSPI2 */ 444 ecspi@83fac000 { 445 #address-cells = <1>; 446 #size-cells = <0>; 447 compatible = "fsl,imx51-ecspi"; 448 reg = <0x83fac000 0x4000>; 449 interrupt-parent = <&tzic>; interrupts = <37>; 450 status = "disabled"; 451 }; 452 453 /* 83FB0000 0x4000 SDMA */ 454 sdma@83fb0000 { 455 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 456 reg = <0x83fb0000 0x4000>; 457 interrupt-parent = <&tzic>; interrupts = <6>; 458 }; 459 460 /* 83FB4000 0x4000 SCC */ 461 /* 21 SCC Security Monitor High Priority Interrupt. */ 462 /* 22 SCC Secure (TrustZone) Interrupt. */ 463 /* 23 SCC Regular (Non-Secure) Interrupt. */ 464 465 /* 83FB8000 0x4000 ROMCP */ 466 /* 83FBC000 0x4000 RTIC */ 467 /* 468 * 26 RTIC RTIC (Trust Zone) Interrupt Request. 469 * Indicates that the RTIC has completed hashing the 470 */ 471 472 /* 83FC0000 0x4000 CSPI */ 473 cspi@83fc0000 { 474 #address-cells = <1>; 475 #size-cells = <0>; 476 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 477 reg = <0x83fc0000 0x4000>; 478 interrupt-parent = <&tzic>; interrupts = <38>; 479 status = "disabled"; 480 }; 481 482 /* 83FC4000 0x4000 I2C2 */ 483 i2c@83fc4000 { 484 #address-cells = <1>; 485 #size-cells = <0>; 486 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c", "fsl,imx-i2c"; 487 reg = <0x83fc4000 0x4000>; 488 interrupt-parent = <&tzic>; interrupts = <63>; 489 status = "disabled"; 490 }; 491 492 /* 83FC8000 0x4000 I2C1 */ 493 i2c@83fc8000 { 494 #address-cells = <1>; 495 #size-cells = <0>; 496 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c", "fsl,imx-i2c"; 497 reg = <0x83fc8000 0x4000>; 498 interrupt-parent = <&tzic>; interrupts = <62>; 499 status = "disabled"; 500 }; 501 502 /* 83FCC000 0x4000 SSI1 */ 503 /* 29 SSI1 SSI-1 Interrupt Request */ 504 SSI1: ssi@83fcc000 { 505 compatible = "fsl,imx51-ssi"; 506 reg = <0x83fcc000 0x4000>; 507 interrupt-parent = <&tzic>; interrupts = <29>; 508 status = "disabled"; 509 }; 510 511 /* 83FD0000 0x4000 AUDMUX */ 512 audmux@83fd4000 { 513 compatible = "fsl,imx51-audmux"; 514 reg = <0x83fd4000 0x4000>; 515 status = "disabled"; 516 }; 517 518 /* 83FD8000 0x4000 EMI1 */ 519 /* 8 EMI (NFC) */ 520 /* 15 EMI */ 521 /* 97 EMI Boot sequence completed interrupt */ 522 /* 523 * 101 EMI Indicates all pages have been transferred 524 * to NFC during an auto program operation. 525 */ 526 527 /* 83FE0000 0x4000 PATA (PORT PIO) */ 528 /* 70 PATA Parallel ATA host controller interrupt */ 529 ide@83fe0000 { 530 compatible = "fsl,imx51-ata"; 531 reg = <0x83fe0000 0x4000>; 532 interrupt-parent = <&tzic>; 533 interrupts = <70>; 534 status = "disabled"; 535 }; 536 537 /* 83FE4000 0x4000 SIM */ 538 /* 67 SIM intr composed of oef, xte, sdi1, and sdi0 */ 539 /* 68 SIM intr composed of tc, etc, tfe, and rdrf */ 540 541 /* 83FE8000 0x4000 SSI3 */ 542 /* 96 SSI3 SSI-3 Interrupt Request */ 543 SSI3: ssi@83fe8000 { 544 compatible = "fsl,imx51-ssi"; 545 reg = <0x83fe8000 0x4000>; 546 interrupt-parent = <&tzic>; interrupts = <96>; 547 status = "disabled"; 548 }; 549 550 /* 83FEC000 0x4000 FEC */ 551 ethernet@83fec000 { 552 compatible = "fsl,imx51-fec"; 553 reg = <0x83fec000 0x4000>; 554 interrupt-parent = <&tzic>; interrupts = <87>; 555 status = "disabled"; 556 }; 557 558 /* 83FF0000 0x4000 TVE */ 559 /* 92 TVE */ 560 /* 83FF4000 0x4000 VPU */ 561 /* 9 VPU */ 562 /* 100 VPU Idle interrupt from VPU */ 563 564 /* 83FF8000 0x4000 SAHARA Lite */ 565 /* 19 SAHARA SAHARA host 0 (TrustZone) Intr Lite */ 566 /* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr Lite */ 567 }; 568 }; 569 570 localbus@5e000000 { 571 compatible = "simple-bus"; 572 #address-cells = <1>; 573 #size-cells = <1>; 574 575 ranges; 576 577 vga: ipu3@5e000000 { 578 compatible = "fsl,ipu3"; 579 reg = < 580 0x5e000000 0x08000 /* CM */ 581 0x5e008000 0x08000 /* IDMAC */ 582 0x5e018000 0x08000 /* DP */ 583 0x5e020000 0x08000 /* IC */ 584 0x5e028000 0x08000 /* IRT */ 585 0x5e030000 0x08000 /* CSI0 */ 586 0x5e038000 0x08000 /* CSI1 */ 587 0x5e040000 0x08000 /* DI0 */ 588 0x5e048000 0x08000 /* DI1 */ 589 0x5e050000 0x08000 /* SMFC */ 590 0x5e058000 0x08000 /* DC */ 591 0x5e060000 0x08000 /* DMFC */ 592 0x5e068000 0x08000 /* VDI */ 593 0x5f000000 0x20000 /* CPMEM */ 594 0x5f020000 0x20000 /* LUT */ 595 0x5f040000 0x20000 /* SRM */ 596 0x5f060000 0x20000 /* TPM */ 597 0x5f080000 0x20000 /* DCTMPL */ 598 >; 599 interrupt-parent = <&tzic>; 600 interrupts = < 601 10 /* IPUEX Error */ 602 11 /* IPUEX Sync */ 603 >; 604 status = "disabled"; 605 }; 606 }; 607}; 608 609/* 610 611TODO: Not mapped interrupts 612 6135 DAP 61484 GPU2D (OpenVG) general interrupt 61585 GPU2D (OpenVG) busy signal (for S/W power gating feasibility) 61612 GPU3D 617102 GPU3D Idle interrupt from GPU3D (for S/W power gating) 61890 SJC 619*/ 620