1/*- 2 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2015 Semihalf 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/dts-v1/; 29 30/ { 31 model = "annapurna,alpine"; 32 #address-cells = <1>; 33 #size-cells = <1>; 34 35 aliases { 36 serial0 = &serial0; 37 }; 38 39 cpus { 40 #address-cells = <1>; 41 #size-cells = <0>; 42 43 cpu@0 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a15"; 46 reg = <0x0>; 47 d-cache-line-size = <64>; // 64 bytes 48 i-cache-line-size = <64>; // 64 bytes 49 d-cache-size = <0x8000>; // L1, 32K 50 i-cache-size = <0x8000>; // L1, 32K 51 timebase-frequency = <0>; 52 bus-frequency = <375000000>; 53 clock-frequency = <0>; 54 }; 55 56 cpu@1 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a15"; 59 reg = <0x0>; 60 d-cache-line-size = <64>; // 64 bytes 61 i-cache-line-size = <64>; // 64 bytes 62 d-cache-size = <0x8000>; // L1, 32K 63 i-cache-size = <0x8000>; // L1, 32K 64 timebase-frequency = <0>; 65 bus-frequency = <375000000>; 66 clock-frequency = <0>; 67 }; 68 69 cpu@2 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a15"; 72 reg = <0x0>; 73 d-cache-line-size = <64>; // 64 bytes 74 i-cache-line-size = <64>; // 64 bytes 75 d-cache-size = <0x8000>; // L1, 32K 76 i-cache-size = <0x8000>; // L1, 32K 77 timebase-frequency = <0>; 78 bus-frequency = <375000000>; 79 clock-frequency = <0>; 80 }; 81 82 cpu@3 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a15"; 85 reg = <0x0>; 86 d-cache-line-size = <64>; // 64 bytes 87 i-cache-line-size = <64>; // 64 bytes 88 d-cache-size = <0x8000>; // L1, 32K 89 i-cache-size = <0x8000>; // L1, 32K 90 timebase-frequency = <0>; 91 bus-frequency = <375000000>; 92 clock-frequency = <0>; 93 }; 94 }; 95 96 memory { 97 device_type = "memory"; 98 reg = <0x00100000 0x7ff00000>; // 2047MB at 1MB 99 }; 100 101 soc { 102 #address-cells = <1>; 103 #size-cells = <1>; 104 compatible = "simple-bus"; 105 ranges = <0x0 0xfb000000 0x03000000>; 106 bus-frequency = <0>; 107 108 MPIC: interrupt-controller { 109 compatible = "arm,gic"; 110 reg = < 0x1000 0x1000 >, /* Distributor Registers */ 111 < 0x2000 0x2000 >; /* CPU Interface Registers */ 112 interrupt-controller; 113 #address-cells = <0>; 114 #interrupt-cells = <3>; 115 116 // In intr[2], bits[3:0] are trigger type and level flags. 117 // 1 = low-to-high edge triggered 118 // 2 = high-to-low edge triggered 119 // 4 = active high level-sensitive 120 // 8 = active low level-sensitive 121 // The hardware only supports active-high-level or rising-edge. 122 123 }; 124 125 generic_timer { 126 compatible = "arm,sp804"; 127 reg = <0x02890000 0x1000>; 128 interrupts = <0 9 4>; 129 interrupt-parent = <&MPIC>; 130 clock-frequency = <375000000>; 131 }; 132 133 cpu_resume { 134 compatible = "annapurna-labs,al-cpu-resume"; 135 reg = <0x00ff5ec0 0x30>; 136 }; 137 138 ccu { 139 compatible = "annapurna-labs,al-ccu"; 140 reg = <0x00090000 0x10000>; 141 io_coherency = <1>; 142 }; 143 144 nb_service { 145 compatible = "annapurna-labs,al-nb-service"; 146 reg = <0x00070000 0x10000>; 147 interrupts = <0 32 4>, 148 <0 33 4>, 149 <0 34 4>, 150 <0 35 4>; 151 interrupt-parent = <&MPIC>; 152 }; 153 154 wdt0 { 155 compatible = "arm,sp805", "arm,primecell"; 156 reg = <0x288c000 0x1000>; 157 interrupt-parent = <&MPIC>; 158 }; 159 160 /* SerDes */ 161 serdes { 162 compatible = "annapurna-labs,al-serdes"; 163 reg = <0x28c0000 0x1000>; 164 }; 165 166 serial0: serial@2883000 { 167 compatible = "ns16550"; 168 reg = <0x2883000 0x20>; 169 reg-shift = <2>; 170 current-speed = <115200>; 171 clock-frequency = <375000000>; 172 interrupts = <0 17 4>; 173 interrupt-parent = <&MPIC>; 174 }; 175 }; 176 177 /* MSIX Configuration */ 178 msix: msix { 179 compatible = "annapurna-labs,al-msix"; 180 #address-cells = <2>; 181 #size-cells = <1>; 182 reg = <0xfbe00000 0x100000>; 183 interrupts = <0 96 1 0 159 1>; 184 interrupt-parent = <&MPIC>; 185 }; 186 187 pcie-internal { 188 compatible = "annapurna-labs,al-internal-pcie"; 189 device_type = "pci"; 190 #size-cells = <2>; 191 #address-cells = <3>; 192 reg = <0xfbc00000 0x100000>; 193 interrupt-parent = <&MPIC>; 194 interrupt-map-mask = <0xf800 0 0 7>; 195 interrupt-map = <0x3000 0 0 1 &MPIC 0 32 4>, // USB adapter 196 <0x3800 0 0 1 &MPIC 0 36 4>, 197 <0x4000 0 0 1 &MPIC 0 43 4>, // SATA 0 (PCIe expander) 198 <0x4800 0 0 1 &MPIC 0 44 1>; // SATA 1 (onboard) 199 msi-parent = <&msix>; 200 201 // ranges: 202 // - ECAM - non prefetchable config space 203 // - 32 bit non prefetchable memory space 204 ranges = <0x00000000 0x0 0xfbc00000 0xfbc00000 0x0 0x100000 205 0x02000000 0x0 0xfe000000 0xfe000000 0x0 0x1000000>; 206 207 bus-range = <0x00 0x00>; 208 }; 209 210// WORKAROUND: enabling PCIe controller when no card is plugged in 211// leads to kernel panic because u-boot disables PCIe controller if no link 212// is detected. Just be kind and compatible with Linux 213/* // External PCIe Controller 0 214 pcie-external0 { 215 compatible = "annapurna-labs,al-external-pcie"; 216 reg = <0xfd800000 0x00020000>; 217 device_type = "pci"; 218 #size-cells = <2>; 219 #address-cells = <3>; 220 interrupt-parent = <&MPIC>; 221 interrupt-map-mask = <0x00 0 0 7>; 222 interrupt-map = <0x0000 0 0 1 &MPIC 0 40 4>; 223 224 // ranges: 225 // Controller 0: 226 // - ECAM - non prefetchable config space: 2MB 227 // - IO - IO port space 64KB, reserve 64KB from target memory windows 228 // real IO address on the pci bus starts at 0x10000 229 // - 32 bit non prefetchable memory space: 128MB - 64KB 230 231 ranges = <0x00000000 0x0 0xfb600000 0xfb600000 0x0 0x00200000 232 0x01000000 0x0 0x00010000 0xe0000000 0x0 0x00010000 233 0x02000000 0x0 0xe1000000 0xe1000000 0x0 0x06f00000>; 234 235 bus-range = <0x00 0xff>; 236 }; 237 238 // External PCIe Controllers 1 239 pcie-external1 { 240 compatible = "annapurna-labs,al-external-pcie"; 241 reg = <0xfd820000 0x00020000>; 242 device_type = "pci"; 243 #size-cells = <2>; 244 #address-cells = <3>; 245 interrupt-parent = <&MPIC>; 246 interrupt-map-mask = <0x0 0 0 7>; 247 interrupt-map = <0x0000 0 0 1 &MPIC 0 41 4>; 248 249 // ranges: 250 // - ECAM - non prefetchable config space: 2MB 251 // - IO - IO port space 64KB, reserve 64KB from target memory windows 252 // real IO address on the pci bus starts at 0x20000 253 // - 32 bit non prefetchable memory space: 64MB - 64KB 254 ranges = <0x00000000 0x0 0xfb800000 0xfb800000 0x0 0x00200000 255 0x01000000 0x0 0x00020000 0xe8000000 0x0 0x00010000 256 0x02000000 0x0 0xe8100000 0xe8100000 0x0 0x02ff0000>; 257 258 bus-range = <0x00 0xff>; 259 }; */ 260 261 chosen { 262 stdin = "serial0"; 263 stdout = "serial0"; 264 stddbg = "serial0"; 265 }; 266}; 267