1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * 3Com 3c90x Etherlink XL PCI NIC driver 40 * 41 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 42 * bus-master chips (3c90x cards and embedded controllers) including 43 * the following: 44 * 45 * 3Com 3c900-TPO 10Mbps/RJ-45 46 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 47 * 3Com 3c905-TX 10/100Mbps/RJ-45 48 * 3Com 3c905-T4 10/100Mbps/RJ-45 49 * 3Com 3c900B-TPO 10Mbps/RJ-45 50 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 51 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 52 * 3Com 3c900B-FL 10Mbps/Fiber-optic 53 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 54 * 3Com 3c905B-TX 10/100Mbps/RJ-45 55 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 56 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 57 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 58 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 59 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 60 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 61 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 62 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 63 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 64 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 68 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 69 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 70 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 71 * Dell on-board 3c920 10/100Mbps/RJ-45 72 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 73 * Dell Latitude laptop docking station embedded 3c905-TX 74 * 75 * Written by Bill Paul <wpaul@ctr.columbia.edu> 76 * Electrical Engineering Department 77 * Columbia University, New York City 78 */ 79 /* 80 * The 3c90x series chips use a bus-master DMA interface for transferring 81 * packets to and from the controller chip. Some of the "vortex" cards 82 * (3c59x) also supported a bus master mode, however for those chips 83 * you could only DMA packets to/from a contiguous memory buffer. For 84 * transmission this would mean copying the contents of the queued mbuf 85 * chain into an mbuf cluster and then DMAing the cluster. This extra 86 * copy would sort of defeat the purpose of the bus master support for 87 * any packet that doesn't fit into a single mbuf. 88 * 89 * By contrast, the 3c90x cards support a fragment-based bus master 90 * mode where mbuf chains can be encapsulated using TX descriptors. 91 * This is similar to other PCI chips such as the Texas Instruments 92 * ThunderLAN and the Intel 82557/82558. 93 * 94 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 95 * bus master chips because they maintain the old PIO interface for 96 * backwards compatibility, but starting with the 3c905B and the 97 * "cyclone" chips, the compatibility interface has been dropped. 98 * Since using bus master DMA is a big win, we use this driver to 99 * support the PCI "boomerang" chips even though they work with the 100 * "vortex" driver in order to obtain better performance. 101 */ 102 103 #ifdef HAVE_KERNEL_OPTION_HEADERS 104 #include "opt_device_polling.h" 105 #endif 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/sockio.h> 110 #include <sys/endian.h> 111 #include <sys/kernel.h> 112 #include <sys/malloc.h> 113 #include <sys/mbuf.h> 114 #include <sys/module.h> 115 #include <sys/socket.h> 116 #include <sys/taskqueue.h> 117 118 #include <net/if.h> 119 #include <net/if_var.h> 120 #include <net/if_arp.h> 121 #include <net/ethernet.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/if_types.h> 125 126 #include <net/bpf.h> 127 128 #include <machine/bus.h> 129 #include <machine/resource.h> 130 #include <sys/bus.h> 131 #include <sys/rman.h> 132 133 #include <dev/mii/mii.h> 134 #include <dev/mii/mii_bitbang.h> 135 #include <dev/mii/miivar.h> 136 137 #include <dev/pci/pcireg.h> 138 #include <dev/pci/pcivar.h> 139 140 MODULE_DEPEND(xl, pci, 1, 1, 1); 141 MODULE_DEPEND(xl, ether, 1, 1, 1); 142 MODULE_DEPEND(xl, miibus, 1, 1, 1); 143 144 /* "device miibus" required. See GENERIC if you get errors here. */ 145 #include "miibus_if.h" 146 147 #include <dev/xl/if_xlreg.h> 148 149 /* 150 * TX Checksumming is disabled by default for two reasons: 151 * - TX Checksumming will occasionally produce corrupt packets 152 * - TX Checksumming seems to reduce performance 153 * 154 * Only 905B/C cards were reported to have this problem, it is possible 155 * that later chips _may_ be immune. 156 */ 157 #define XL905B_TXCSUM_BROKEN 1 158 159 #ifdef XL905B_TXCSUM_BROKEN 160 #define XL905B_CSUM_FEATURES 0 161 #else 162 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 #endif 164 165 /* 166 * Various supported device vendors/types and their names. 167 */ 168 static const struct xl_type xl_devs[] = { 169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 170 "3Com 3c900-TPO Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 172 "3Com 3c900-COMBO Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 174 "3Com 3c905-TX Fast Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 176 "3Com 3c905-T4 Fast Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 178 "3Com 3c900B-TPO Etherlink XL" }, 179 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 180 "3Com 3c900B-COMBO Etherlink XL" }, 181 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 182 "3Com 3c900B-TPC Etherlink XL" }, 183 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 184 "3Com 3c900B-FL Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 186 "3Com 3c905B-TX Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 188 "3Com 3c905B-T4 Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 190 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 192 "3Com 3c905B-COMBO Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 194 "3Com 3c905C-TX Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 196 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 197 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 198 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 199 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 200 "3Com 3c980 Fast Etherlink XL" }, 201 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 202 "3Com 3c980C Fast Etherlink XL" }, 203 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 204 "3Com 3cSOHO100-TX OfficeConnect" }, 205 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 206 "3Com 3c450-TX HomeConnect" }, 207 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 208 "3Com 3c555 Fast Etherlink XL" }, 209 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 210 "3Com 3c556 Fast Etherlink XL" }, 211 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 212 "3Com 3c556B Fast Etherlink XL" }, 213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 214 "3Com 3c575TX Fast Etherlink XL" }, 215 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 216 "3Com 3c575B Fast Etherlink XL" }, 217 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 218 "3Com 3c575C Fast Etherlink XL" }, 219 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 220 "3Com 3c656 Fast Etherlink XL" }, 221 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 222 "3Com 3c656B Fast Etherlink XL" }, 223 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 224 "3Com 3c656C Fast Etherlink XL" }, 225 { 0, 0, NULL } 226 }; 227 228 static int xl_probe(device_t); 229 static int xl_attach(device_t); 230 static int xl_detach(device_t); 231 232 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 233 static void xl_tick(void *); 234 static void xl_stats_update(struct xl_softc *); 235 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); 236 static int xl_rxeof(struct xl_softc *); 237 static void xl_rxeof_task(void *, int); 238 static int xl_rx_resync(struct xl_softc *); 239 static void xl_txeof(struct xl_softc *); 240 static void xl_txeof_90xB(struct xl_softc *); 241 static void xl_txeoc(struct xl_softc *); 242 static void xl_intr(void *); 243 static void xl_start(struct ifnet *); 244 static void xl_start_locked(struct ifnet *); 245 static void xl_start_90xB_locked(struct ifnet *); 246 static int xl_ioctl(struct ifnet *, u_long, caddr_t); 247 static void xl_init(void *); 248 static void xl_init_locked(struct xl_softc *); 249 static void xl_stop(struct xl_softc *); 250 static int xl_watchdog(struct xl_softc *); 251 static int xl_shutdown(device_t); 252 static int xl_suspend(device_t); 253 static int xl_resume(device_t); 254 static void xl_setwol(struct xl_softc *); 255 256 #ifdef DEVICE_POLLING 257 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 258 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 259 #endif 260 261 static int xl_ifmedia_upd(struct ifnet *); 262 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 263 264 static int xl_eeprom_wait(struct xl_softc *); 265 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 266 267 static void xl_rxfilter(struct xl_softc *); 268 static void xl_rxfilter_90x(struct xl_softc *); 269 static void xl_rxfilter_90xB(struct xl_softc *); 270 static void xl_setcfg(struct xl_softc *); 271 static void xl_setmode(struct xl_softc *, int); 272 static void xl_reset(struct xl_softc *); 273 static int xl_list_rx_init(struct xl_softc *); 274 static int xl_list_tx_init(struct xl_softc *); 275 static int xl_list_tx_init_90xB(struct xl_softc *); 276 static void xl_wait(struct xl_softc *); 277 static void xl_mediacheck(struct xl_softc *); 278 static void xl_choose_media(struct xl_softc *sc, int *media); 279 static void xl_choose_xcvr(struct xl_softc *, int); 280 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 281 #ifdef notdef 282 static void xl_testpacket(struct xl_softc *); 283 #endif 284 285 static int xl_miibus_readreg(device_t, int, int); 286 static int xl_miibus_writereg(device_t, int, int, int); 287 static void xl_miibus_statchg(device_t); 288 static void xl_miibus_mediainit(device_t); 289 290 /* 291 * MII bit-bang glue 292 */ 293 static uint32_t xl_mii_bitbang_read(device_t); 294 static void xl_mii_bitbang_write(device_t, uint32_t); 295 296 static const struct mii_bitbang_ops xl_mii_bitbang_ops = { 297 xl_mii_bitbang_read, 298 xl_mii_bitbang_write, 299 { 300 XL_MII_DATA, /* MII_BIT_MDO */ 301 XL_MII_DATA, /* MII_BIT_MDI */ 302 XL_MII_CLK, /* MII_BIT_MDC */ 303 XL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 304 0, /* MII_BIT_DIR_PHY_HOST */ 305 } 306 }; 307 308 static device_method_t xl_methods[] = { 309 /* Device interface */ 310 DEVMETHOD(device_probe, xl_probe), 311 DEVMETHOD(device_attach, xl_attach), 312 DEVMETHOD(device_detach, xl_detach), 313 DEVMETHOD(device_shutdown, xl_shutdown), 314 DEVMETHOD(device_suspend, xl_suspend), 315 DEVMETHOD(device_resume, xl_resume), 316 317 /* MII interface */ 318 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 319 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 320 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 321 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 322 323 DEVMETHOD_END 324 }; 325 326 static driver_t xl_driver = { 327 "xl", 328 xl_methods, 329 sizeof(struct xl_softc) 330 }; 331 332 static devclass_t xl_devclass; 333 334 DRIVER_MODULE_ORDERED(xl, pci, xl_driver, xl_devclass, NULL, NULL, 335 SI_ORDER_ANY); 336 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, NULL, NULL); 337 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, xl, xl_devs, sizeof(xl_devs[0]), 338 nitems(xl_devs) - 1); 339 340 static void 341 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 342 { 343 u_int32_t *paddr; 344 345 paddr = arg; 346 *paddr = segs->ds_addr; 347 } 348 349 /* 350 * Murphy's law says that it's possible the chip can wedge and 351 * the 'command in progress' bit may never clear. Hence, we wait 352 * only a finite amount of time to avoid getting caught in an 353 * infinite loop. Normally this delay routine would be a macro, 354 * but it isn't called during normal operation so we can afford 355 * to make it a function. Suppress warning when card gone. 356 */ 357 static void 358 xl_wait(struct xl_softc *sc) 359 { 360 int i; 361 362 for (i = 0; i < XL_TIMEOUT; i++) { 363 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 364 break; 365 } 366 367 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev)) 368 device_printf(sc->xl_dev, "command never completed!\n"); 369 } 370 371 /* 372 * MII access routines are provided for adapters with external 373 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 374 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 375 * Note: if you don't perform the MDIO operations just right, 376 * it's possible to end up with code that works correctly with 377 * some chips/CPUs/processor speeds/bus speeds/etc but not 378 * with others. 379 */ 380 381 /* 382 * Read the MII serial port for the MII bit-bang module. 383 */ 384 static uint32_t 385 xl_mii_bitbang_read(device_t dev) 386 { 387 struct xl_softc *sc; 388 uint32_t val; 389 390 sc = device_get_softc(dev); 391 392 /* We're already in window 4. */ 393 val = CSR_READ_2(sc, XL_W4_PHY_MGMT); 394 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 395 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 396 397 return (val); 398 } 399 400 /* 401 * Write the MII serial port for the MII bit-bang module. 402 */ 403 static void 404 xl_mii_bitbang_write(device_t dev, uint32_t val) 405 { 406 struct xl_softc *sc; 407 408 sc = device_get_softc(dev); 409 410 /* We're already in window 4. */ 411 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val); 412 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 413 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 414 } 415 416 static int 417 xl_miibus_readreg(device_t dev, int phy, int reg) 418 { 419 struct xl_softc *sc; 420 421 sc = device_get_softc(dev); 422 423 /* Select the window 4. */ 424 XL_SEL_WIN(4); 425 426 return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg)); 427 } 428 429 static int 430 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 431 { 432 struct xl_softc *sc; 433 434 sc = device_get_softc(dev); 435 436 /* Select the window 4. */ 437 XL_SEL_WIN(4); 438 439 mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data); 440 441 return (0); 442 } 443 444 static void 445 xl_miibus_statchg(device_t dev) 446 { 447 struct xl_softc *sc; 448 struct mii_data *mii; 449 uint8_t macctl; 450 451 sc = device_get_softc(dev); 452 mii = device_get_softc(sc->xl_miibus); 453 454 xl_setcfg(sc); 455 456 /* Set ASIC's duplex mode to match the PHY. */ 457 XL_SEL_WIN(3); 458 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 459 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 460 macctl |= XL_MACCTRL_DUPLEX; 461 if (sc->xl_type == XL_TYPE_905B) { 462 if ((IFM_OPTIONS(mii->mii_media_active) & 463 IFM_ETH_RXPAUSE) != 0) 464 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB; 465 else 466 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 467 } 468 } else { 469 macctl &= ~XL_MACCTRL_DUPLEX; 470 if (sc->xl_type == XL_TYPE_905B) 471 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 472 } 473 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 474 } 475 476 /* 477 * Special support for the 3c905B-COMBO. This card has 10/100 support 478 * plus BNC and AUI ports. This means we will have both an miibus attached 479 * plus some non-MII media settings. In order to allow this, we have to 480 * add the extra media to the miibus's ifmedia struct, but we can't do 481 * that during xl_attach() because the miibus hasn't been attached yet. 482 * So instead, we wait until the miibus probe/attach is done, at which 483 * point we will get a callback telling is that it's safe to add our 484 * extra media. 485 */ 486 static void 487 xl_miibus_mediainit(device_t dev) 488 { 489 struct xl_softc *sc; 490 struct mii_data *mii; 491 struct ifmedia *ifm; 492 493 sc = device_get_softc(dev); 494 mii = device_get_softc(sc->xl_miibus); 495 ifm = &mii->mii_media; 496 497 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 498 /* 499 * Check for a 10baseFL board in disguise. 500 */ 501 if (sc->xl_type == XL_TYPE_905B && 502 sc->xl_media == XL_MEDIAOPT_10FL) { 503 if (bootverbose) 504 device_printf(sc->xl_dev, "found 10baseFL\n"); 505 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 506 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 507 NULL); 508 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 509 ifmedia_add(ifm, 510 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 511 } else { 512 if (bootverbose) 513 device_printf(sc->xl_dev, "found AUI\n"); 514 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 515 } 516 } 517 518 if (sc->xl_media & XL_MEDIAOPT_BNC) { 519 if (bootverbose) 520 device_printf(sc->xl_dev, "found BNC\n"); 521 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 522 } 523 } 524 525 /* 526 * The EEPROM is slow: give it time to come ready after issuing 527 * it a command. 528 */ 529 static int 530 xl_eeprom_wait(struct xl_softc *sc) 531 { 532 int i; 533 534 for (i = 0; i < 100; i++) { 535 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 536 DELAY(162); 537 else 538 break; 539 } 540 541 if (i == 100) { 542 device_printf(sc->xl_dev, "eeprom failed to come ready\n"); 543 return (1); 544 } 545 546 return (0); 547 } 548 549 /* 550 * Read a sequence of words from the EEPROM. Note that ethernet address 551 * data is stored in the EEPROM in network byte order. 552 */ 553 static int 554 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 555 { 556 int err = 0, i; 557 u_int16_t word = 0, *ptr; 558 559 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 560 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 561 /* 562 * XXX: WARNING! DANGER! 563 * It's easy to accidentally overwrite the rom content! 564 * Note: the 3c575 uses 8bit EEPROM offsets. 565 */ 566 XL_SEL_WIN(0); 567 568 if (xl_eeprom_wait(sc)) 569 return (1); 570 571 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 572 off += 0x30; 573 574 for (i = 0; i < cnt; i++) { 575 if (sc->xl_flags & XL_FLAG_8BITROM) 576 CSR_WRITE_2(sc, XL_W0_EE_CMD, 577 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 578 else 579 CSR_WRITE_2(sc, XL_W0_EE_CMD, 580 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 581 err = xl_eeprom_wait(sc); 582 if (err) 583 break; 584 word = CSR_READ_2(sc, XL_W0_EE_DATA); 585 ptr = (u_int16_t *)(dest + (i * 2)); 586 if (swap) 587 *ptr = ntohs(word); 588 else 589 *ptr = word; 590 } 591 592 return (err ? 1 : 0); 593 } 594 595 static void 596 xl_rxfilter(struct xl_softc *sc) 597 { 598 599 if (sc->xl_type == XL_TYPE_905B) 600 xl_rxfilter_90xB(sc); 601 else 602 xl_rxfilter_90x(sc); 603 } 604 605 /* 606 * NICs older than the 3c905B have only one multicast option, which 607 * is to enable reception of all multicast frames. 608 */ 609 static void 610 xl_rxfilter_90x(struct xl_softc *sc) 611 { 612 struct ifnet *ifp; 613 struct ifmultiaddr *ifma; 614 u_int8_t rxfilt; 615 616 XL_LOCK_ASSERT(sc); 617 618 ifp = sc->xl_ifp; 619 620 XL_SEL_WIN(5); 621 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 622 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 623 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL); 624 625 /* Set the individual bit to receive frames for this host only. */ 626 rxfilt |= XL_RXFILTER_INDIVIDUAL; 627 /* Set capture broadcast bit to capture broadcast frames. */ 628 if (ifp->if_flags & IFF_BROADCAST) 629 rxfilt |= XL_RXFILTER_BROADCAST; 630 631 /* If we want promiscuous mode, set the allframes bit. */ 632 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 633 if (ifp->if_flags & IFF_PROMISC) 634 rxfilt |= XL_RXFILTER_ALLFRAMES; 635 if (ifp->if_flags & IFF_ALLMULTI) 636 rxfilt |= XL_RXFILTER_ALLMULTI; 637 } else { 638 if_maddr_rlock(ifp); 639 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 640 if (ifma->ifma_addr->sa_family != AF_LINK) 641 continue; 642 rxfilt |= XL_RXFILTER_ALLMULTI; 643 break; 644 } 645 if_maddr_runlock(ifp); 646 } 647 648 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 649 XL_SEL_WIN(7); 650 } 651 652 /* 653 * 3c905B adapters have a hash filter that we can program. 654 */ 655 static void 656 xl_rxfilter_90xB(struct xl_softc *sc) 657 { 658 struct ifnet *ifp; 659 struct ifmultiaddr *ifma; 660 int i, mcnt; 661 u_int16_t h; 662 u_int8_t rxfilt; 663 664 XL_LOCK_ASSERT(sc); 665 666 ifp = sc->xl_ifp; 667 668 XL_SEL_WIN(5); 669 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 670 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 671 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL | 672 XL_RXFILTER_MULTIHASH); 673 674 /* Set the individual bit to receive frames for this host only. */ 675 rxfilt |= XL_RXFILTER_INDIVIDUAL; 676 /* Set capture broadcast bit to capture broadcast frames. */ 677 if (ifp->if_flags & IFF_BROADCAST) 678 rxfilt |= XL_RXFILTER_BROADCAST; 679 680 /* If we want promiscuous mode, set the allframes bit. */ 681 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 682 if (ifp->if_flags & IFF_PROMISC) 683 rxfilt |= XL_RXFILTER_ALLFRAMES; 684 if (ifp->if_flags & IFF_ALLMULTI) 685 rxfilt |= XL_RXFILTER_ALLMULTI; 686 } else { 687 /* First, zot all the existing hash bits. */ 688 for (i = 0; i < XL_HASHFILT_SIZE; i++) 689 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i); 690 691 /* Now program new ones. */ 692 mcnt = 0; 693 if_maddr_rlock(ifp); 694 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 695 if (ifma->ifma_addr->sa_family != AF_LINK) 696 continue; 697 /* 698 * Note: the 3c905B currently only supports a 64-bit 699 * hash table, which means we really only need 6 bits, 700 * but the manual indicates that future chip revisions 701 * will have a 256-bit hash table, hence the routine 702 * is set up to calculate 8 bits of position info in 703 * case we need it some day. 704 * Note II, The Sequel: _CURRENT_ versions of the 705 * 3c905B have a 256 bit hash table. This means we have 706 * to use all 8 bits regardless. On older cards, the 707 * upper 2 bits will be ignored. Grrrr.... 708 */ 709 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 710 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 711 CSR_WRITE_2(sc, XL_COMMAND, 712 h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 713 mcnt++; 714 } 715 if_maddr_runlock(ifp); 716 if (mcnt > 0) 717 rxfilt |= XL_RXFILTER_MULTIHASH; 718 } 719 720 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 721 XL_SEL_WIN(7); 722 } 723 724 static void 725 xl_setcfg(struct xl_softc *sc) 726 { 727 u_int32_t icfg; 728 729 /*XL_LOCK_ASSERT(sc);*/ 730 731 XL_SEL_WIN(3); 732 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 733 icfg &= ~XL_ICFG_CONNECTOR_MASK; 734 if (sc->xl_media & XL_MEDIAOPT_MII || 735 sc->xl_media & XL_MEDIAOPT_BT4) 736 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 737 if (sc->xl_media & XL_MEDIAOPT_BTX) 738 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 739 740 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 741 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 742 } 743 744 static void 745 xl_setmode(struct xl_softc *sc, int media) 746 { 747 u_int32_t icfg; 748 u_int16_t mediastat; 749 char *pmsg = "", *dmsg = ""; 750 751 XL_LOCK_ASSERT(sc); 752 753 XL_SEL_WIN(4); 754 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 755 XL_SEL_WIN(3); 756 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 757 758 if (sc->xl_media & XL_MEDIAOPT_BT) { 759 if (IFM_SUBTYPE(media) == IFM_10_T) { 760 pmsg = "10baseT transceiver"; 761 sc->xl_xcvr = XL_XCVR_10BT; 762 icfg &= ~XL_ICFG_CONNECTOR_MASK; 763 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 764 mediastat |= XL_MEDIASTAT_LINKBEAT | 765 XL_MEDIASTAT_JABGUARD; 766 mediastat &= ~XL_MEDIASTAT_SQEENB; 767 } 768 } 769 770 if (sc->xl_media & XL_MEDIAOPT_BFX) { 771 if (IFM_SUBTYPE(media) == IFM_100_FX) { 772 pmsg = "100baseFX port"; 773 sc->xl_xcvr = XL_XCVR_100BFX; 774 icfg &= ~XL_ICFG_CONNECTOR_MASK; 775 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 776 mediastat |= XL_MEDIASTAT_LINKBEAT; 777 mediastat &= ~XL_MEDIASTAT_SQEENB; 778 } 779 } 780 781 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 782 if (IFM_SUBTYPE(media) == IFM_10_5) { 783 pmsg = "AUI port"; 784 sc->xl_xcvr = XL_XCVR_AUI; 785 icfg &= ~XL_ICFG_CONNECTOR_MASK; 786 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 787 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 788 XL_MEDIASTAT_JABGUARD); 789 mediastat |= ~XL_MEDIASTAT_SQEENB; 790 } 791 if (IFM_SUBTYPE(media) == IFM_10_FL) { 792 pmsg = "10baseFL transceiver"; 793 sc->xl_xcvr = XL_XCVR_AUI; 794 icfg &= ~XL_ICFG_CONNECTOR_MASK; 795 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 796 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 797 XL_MEDIASTAT_JABGUARD); 798 mediastat |= ~XL_MEDIASTAT_SQEENB; 799 } 800 } 801 802 if (sc->xl_media & XL_MEDIAOPT_BNC) { 803 if (IFM_SUBTYPE(media) == IFM_10_2) { 804 pmsg = "AUI port"; 805 sc->xl_xcvr = XL_XCVR_COAX; 806 icfg &= ~XL_ICFG_CONNECTOR_MASK; 807 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 808 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 809 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 810 } 811 } 812 813 if ((media & IFM_GMASK) == IFM_FDX || 814 IFM_SUBTYPE(media) == IFM_100_FX) { 815 dmsg = "full"; 816 XL_SEL_WIN(3); 817 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 818 } else { 819 dmsg = "half"; 820 XL_SEL_WIN(3); 821 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 822 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 823 } 824 825 if (IFM_SUBTYPE(media) == IFM_10_2) 826 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 827 else 828 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 829 830 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 831 XL_SEL_WIN(4); 832 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 833 834 DELAY(800); 835 XL_SEL_WIN(7); 836 837 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg); 838 } 839 840 static void 841 xl_reset(struct xl_softc *sc) 842 { 843 int i; 844 845 XL_LOCK_ASSERT(sc); 846 847 XL_SEL_WIN(0); 848 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 849 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 850 XL_RESETOPT_DISADVFD:0)); 851 852 /* 853 * If we're using memory mapped register mode, pause briefly 854 * after issuing the reset command before trying to access any 855 * other registers. With my 3c575C CardBus card, failing to do 856 * this results in the system locking up while trying to poll 857 * the command busy bit in the status register. 858 */ 859 if (sc->xl_flags & XL_FLAG_USE_MMIO) 860 DELAY(100000); 861 862 for (i = 0; i < XL_TIMEOUT; i++) { 863 DELAY(10); 864 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 865 break; 866 } 867 868 if (i == XL_TIMEOUT) 869 device_printf(sc->xl_dev, "reset didn't complete\n"); 870 871 /* Reset TX and RX. */ 872 /* Note: the RX reset takes an absurd amount of time 873 * on newer versions of the Tornado chips such as those 874 * on the 3c905CX and newer 3c908C cards. We wait an 875 * extra amount of time so that xl_wait() doesn't complain 876 * and annoy the users. 877 */ 878 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 879 DELAY(100000); 880 xl_wait(sc); 881 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 882 xl_wait(sc); 883 884 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 885 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 886 XL_SEL_WIN(2); 887 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 888 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 889 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 890 XL_RESETOPT_INVERT_LED : 0) | 891 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 892 XL_RESETOPT_INVERT_MII : 0)); 893 } 894 895 /* Wait a little while for the chip to get its brains in order. */ 896 DELAY(100000); 897 } 898 899 /* 900 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 901 * IDs against our list and return a device name if we find a match. 902 */ 903 static int 904 xl_probe(device_t dev) 905 { 906 const struct xl_type *t; 907 908 t = xl_devs; 909 910 while (t->xl_name != NULL) { 911 if ((pci_get_vendor(dev) == t->xl_vid) && 912 (pci_get_device(dev) == t->xl_did)) { 913 device_set_desc(dev, t->xl_name); 914 return (BUS_PROBE_DEFAULT); 915 } 916 t++; 917 } 918 919 return (ENXIO); 920 } 921 922 /* 923 * This routine is a kludge to work around possible hardware faults 924 * or manufacturing defects that can cause the media options register 925 * (or reset options register, as it's called for the first generation 926 * 3c90x adapters) to return an incorrect result. I have encountered 927 * one Dell Latitude laptop docking station with an integrated 3c905-TX 928 * which doesn't have any of the 'mediaopt' bits set. This screws up 929 * the attach routine pretty badly because it doesn't know what media 930 * to look for. If we find ourselves in this predicament, this routine 931 * will try to guess the media options values and warn the user of a 932 * possible manufacturing defect with his adapter/system/whatever. 933 */ 934 static void 935 xl_mediacheck(struct xl_softc *sc) 936 { 937 938 /* 939 * If some of the media options bits are set, assume they are 940 * correct. If not, try to figure it out down below. 941 * XXX I should check for 10baseFL, but I don't have an adapter 942 * to test with. 943 */ 944 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 945 /* 946 * Check the XCVR value. If it's not in the normal range 947 * of values, we need to fake it up here. 948 */ 949 if (sc->xl_xcvr <= XL_XCVR_AUTO) 950 return; 951 else { 952 device_printf(sc->xl_dev, 953 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 954 device_printf(sc->xl_dev, 955 "choosing new default based on card type\n"); 956 } 957 } else { 958 if (sc->xl_type == XL_TYPE_905B && 959 sc->xl_media & XL_MEDIAOPT_10FL) 960 return; 961 device_printf(sc->xl_dev, 962 "WARNING: no media options bits set in the media options register!!\n"); 963 device_printf(sc->xl_dev, 964 "this could be a manufacturing defect in your adapter or system\n"); 965 device_printf(sc->xl_dev, 966 "attempting to guess media type; you should probably consult your vendor\n"); 967 } 968 969 xl_choose_xcvr(sc, 1); 970 } 971 972 static void 973 xl_choose_xcvr(struct xl_softc *sc, int verbose) 974 { 975 u_int16_t devid; 976 977 /* 978 * Read the device ID from the EEPROM. 979 * This is what's loaded into the PCI device ID register, so it has 980 * to be correct otherwise we wouldn't have gotten this far. 981 */ 982 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 983 984 switch (devid) { 985 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 986 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 987 sc->xl_media = XL_MEDIAOPT_BT; 988 sc->xl_xcvr = XL_XCVR_10BT; 989 if (verbose) 990 device_printf(sc->xl_dev, 991 "guessing 10BaseT transceiver\n"); 992 break; 993 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 994 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 995 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 996 sc->xl_xcvr = XL_XCVR_10BT; 997 if (verbose) 998 device_printf(sc->xl_dev, 999 "guessing COMBO (AUI/BNC/TP)\n"); 1000 break; 1001 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1002 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1003 sc->xl_xcvr = XL_XCVR_10BT; 1004 if (verbose) 1005 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n"); 1006 break; 1007 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1008 sc->xl_media = XL_MEDIAOPT_10FL; 1009 sc->xl_xcvr = XL_XCVR_AUI; 1010 if (verbose) 1011 device_printf(sc->xl_dev, "guessing 10baseFL\n"); 1012 break; 1013 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1014 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1015 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1016 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1017 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1018 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1019 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1020 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1021 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1022 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1023 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1024 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1025 sc->xl_media = XL_MEDIAOPT_MII; 1026 sc->xl_xcvr = XL_XCVR_MII; 1027 if (verbose) 1028 device_printf(sc->xl_dev, "guessing MII\n"); 1029 break; 1030 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1031 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1032 sc->xl_media = XL_MEDIAOPT_BT4; 1033 sc->xl_xcvr = XL_XCVR_MII; 1034 if (verbose) 1035 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n"); 1036 break; 1037 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1038 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1039 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1040 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1041 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1042 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1043 sc->xl_media = XL_MEDIAOPT_BTX; 1044 sc->xl_xcvr = XL_XCVR_AUTO; 1045 if (verbose) 1046 device_printf(sc->xl_dev, "guessing 10/100 internal\n"); 1047 break; 1048 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1049 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1050 sc->xl_xcvr = XL_XCVR_AUTO; 1051 if (verbose) 1052 device_printf(sc->xl_dev, 1053 "guessing 10/100 plus BNC/AUI\n"); 1054 break; 1055 default: 1056 device_printf(sc->xl_dev, 1057 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1058 sc->xl_media = XL_MEDIAOPT_BT; 1059 break; 1060 } 1061 } 1062 1063 /* 1064 * Attach the interface. Allocate softc structures, do ifmedia 1065 * setup and ethernet/BPF attach. 1066 */ 1067 static int 1068 xl_attach(device_t dev) 1069 { 1070 u_char eaddr[ETHER_ADDR_LEN]; 1071 u_int16_t sinfo2, xcvr[2]; 1072 struct xl_softc *sc; 1073 struct ifnet *ifp; 1074 int media, pmcap; 1075 int error = 0, phy, rid, res, unit; 1076 uint16_t did; 1077 1078 sc = device_get_softc(dev); 1079 sc->xl_dev = dev; 1080 1081 unit = device_get_unit(dev); 1082 1083 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1084 MTX_DEF); 1085 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1086 1087 did = pci_get_device(dev); 1088 1089 sc->xl_flags = 0; 1090 if (did == TC_DEVICEID_HURRICANE_555) 1091 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1092 if (did == TC_DEVICEID_HURRICANE_556 || 1093 did == TC_DEVICEID_HURRICANE_556B) 1094 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1095 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1096 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1097 if (did == TC_DEVICEID_HURRICANE_555 || 1098 did == TC_DEVICEID_HURRICANE_556) 1099 sc->xl_flags |= XL_FLAG_8BITROM; 1100 if (did == TC_DEVICEID_HURRICANE_556B) 1101 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1102 1103 if (did == TC_DEVICEID_HURRICANE_575B || 1104 did == TC_DEVICEID_HURRICANE_575C || 1105 did == TC_DEVICEID_HURRICANE_656B || 1106 did == TC_DEVICEID_TORNADO_656C) 1107 sc->xl_flags |= XL_FLAG_FUNCREG; 1108 if (did == TC_DEVICEID_HURRICANE_575A || 1109 did == TC_DEVICEID_HURRICANE_575B || 1110 did == TC_DEVICEID_HURRICANE_575C || 1111 did == TC_DEVICEID_HURRICANE_656B || 1112 did == TC_DEVICEID_TORNADO_656C) 1113 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1114 XL_FLAG_8BITROM; 1115 if (did == TC_DEVICEID_HURRICANE_656) 1116 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1117 if (did == TC_DEVICEID_HURRICANE_575B) 1118 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1119 if (did == TC_DEVICEID_HURRICANE_575C) 1120 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1121 if (did == TC_DEVICEID_TORNADO_656C) 1122 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1123 if (did == TC_DEVICEID_HURRICANE_656 || 1124 did == TC_DEVICEID_HURRICANE_656B) 1125 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1126 XL_FLAG_INVERT_LED_PWR; 1127 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1128 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1129 sc->xl_flags |= XL_FLAG_PHYOK; 1130 1131 switch (did) { 1132 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1133 case TC_DEVICEID_HURRICANE_575A: 1134 case TC_DEVICEID_HURRICANE_575B: 1135 case TC_DEVICEID_HURRICANE_575C: 1136 sc->xl_flags |= XL_FLAG_NO_MMIO; 1137 break; 1138 default: 1139 break; 1140 } 1141 1142 /* 1143 * Map control/status registers. 1144 */ 1145 pci_enable_busmaster(dev); 1146 1147 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1148 rid = XL_PCI_LOMEM; 1149 res = SYS_RES_MEMORY; 1150 1151 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1152 } 1153 1154 if (sc->xl_res != NULL) { 1155 sc->xl_flags |= XL_FLAG_USE_MMIO; 1156 if (bootverbose) 1157 device_printf(dev, "using memory mapped I/O\n"); 1158 } else { 1159 rid = XL_PCI_LOIO; 1160 res = SYS_RES_IOPORT; 1161 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1162 if (sc->xl_res == NULL) { 1163 device_printf(dev, "couldn't map ports/memory\n"); 1164 error = ENXIO; 1165 goto fail; 1166 } 1167 if (bootverbose) 1168 device_printf(dev, "using port I/O\n"); 1169 } 1170 1171 sc->xl_btag = rman_get_bustag(sc->xl_res); 1172 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1173 1174 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1175 rid = XL_PCI_FUNCMEM; 1176 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1177 RF_ACTIVE); 1178 1179 if (sc->xl_fres == NULL) { 1180 device_printf(dev, "couldn't map funcreg memory\n"); 1181 error = ENXIO; 1182 goto fail; 1183 } 1184 1185 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1186 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1187 } 1188 1189 /* Allocate interrupt */ 1190 rid = 0; 1191 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1192 RF_SHAREABLE | RF_ACTIVE); 1193 if (sc->xl_irq == NULL) { 1194 device_printf(dev, "couldn't map interrupt\n"); 1195 error = ENXIO; 1196 goto fail; 1197 } 1198 1199 /* Initialize interface name. */ 1200 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1201 if (ifp == NULL) { 1202 device_printf(dev, "can not if_alloc()\n"); 1203 error = ENOSPC; 1204 goto fail; 1205 } 1206 ifp->if_softc = sc; 1207 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1208 1209 /* Reset the adapter. */ 1210 XL_LOCK(sc); 1211 xl_reset(sc); 1212 XL_UNLOCK(sc); 1213 1214 /* 1215 * Get station address from the EEPROM. 1216 */ 1217 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1218 device_printf(dev, "failed to read station address\n"); 1219 error = ENXIO; 1220 goto fail; 1221 } 1222 1223 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0); 1224 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1225 1226 /* 1227 * Now allocate a tag for the DMA descriptor lists and a chunk 1228 * of DMA-able memory based on the tag. Also obtain the DMA 1229 * addresses of the RX and TX ring, which we'll need later. 1230 * All of our lists are allocated as a contiguous block 1231 * of memory. 1232 */ 1233 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1234 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1235 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1236 &sc->xl_ldata.xl_rx_tag); 1237 if (error) { 1238 device_printf(dev, "failed to allocate rx dma tag\n"); 1239 goto fail; 1240 } 1241 1242 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1243 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | 1244 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap); 1245 if (error) { 1246 device_printf(dev, "no memory for rx list buffers!\n"); 1247 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1248 sc->xl_ldata.xl_rx_tag = NULL; 1249 goto fail; 1250 } 1251 1252 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1253 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1254 XL_RX_LIST_SZ, xl_dma_map_addr, 1255 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1256 if (error) { 1257 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1258 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1259 sc->xl_ldata.xl_rx_dmamap); 1260 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1261 sc->xl_ldata.xl_rx_tag = NULL; 1262 goto fail; 1263 } 1264 1265 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1266 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1267 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1268 &sc->xl_ldata.xl_tx_tag); 1269 if (error) { 1270 device_printf(dev, "failed to allocate tx dma tag\n"); 1271 goto fail; 1272 } 1273 1274 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1275 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | 1276 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap); 1277 if (error) { 1278 device_printf(dev, "no memory for list buffers!\n"); 1279 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1280 sc->xl_ldata.xl_tx_tag = NULL; 1281 goto fail; 1282 } 1283 1284 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1285 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1286 XL_TX_LIST_SZ, xl_dma_map_addr, 1287 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1288 if (error) { 1289 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1290 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1291 sc->xl_ldata.xl_tx_dmamap); 1292 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1293 sc->xl_ldata.xl_tx_tag = NULL; 1294 goto fail; 1295 } 1296 1297 /* 1298 * Allocate a DMA tag for the mapping of mbufs. 1299 */ 1300 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1301 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1302 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1303 NULL, &sc->xl_mtag); 1304 if (error) { 1305 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1306 goto fail; 1307 } 1308 1309 /* We need a spare DMA map for the RX ring. */ 1310 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1311 if (error) 1312 goto fail; 1313 1314 /* 1315 * Figure out the card type. 3c905B adapters have the 1316 * 'supportsNoTxLength' bit set in the capabilities 1317 * word in the EEPROM. 1318 * Note: my 3c575C CardBus card lies. It returns a value 1319 * of 0x1578 for its capabilities word, which is somewhat 1320 * nonsensical. Another way to distinguish a 3c90x chip 1321 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1322 * bit. This will only be set for 3c90x boomerage chips. 1323 */ 1324 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1325 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1326 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1327 sc->xl_type = XL_TYPE_905B; 1328 else 1329 sc->xl_type = XL_TYPE_90X; 1330 1331 /* Check availability of WOL. */ 1332 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 && 1333 pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) { 1334 sc->xl_pmcap = pmcap; 1335 sc->xl_flags |= XL_FLAG_WOL; 1336 sinfo2 = 0; 1337 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0); 1338 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose) 1339 device_printf(dev, 1340 "No auxiliary remote wakeup connector!\n"); 1341 } 1342 1343 /* Set the TX start threshold for best performance. */ 1344 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1345 1346 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1347 ifp->if_ioctl = xl_ioctl; 1348 ifp->if_capabilities = IFCAP_VLAN_MTU; 1349 if (sc->xl_type == XL_TYPE_905B) { 1350 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1351 #ifdef XL905B_TXCSUM_BROKEN 1352 ifp->if_capabilities |= IFCAP_RXCSUM; 1353 #else 1354 ifp->if_capabilities |= IFCAP_HWCSUM; 1355 #endif 1356 } 1357 if ((sc->xl_flags & XL_FLAG_WOL) != 0) 1358 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1359 ifp->if_capenable = ifp->if_capabilities; 1360 #ifdef DEVICE_POLLING 1361 ifp->if_capabilities |= IFCAP_POLLING; 1362 #endif 1363 ifp->if_start = xl_start; 1364 ifp->if_init = xl_init; 1365 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1366 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1; 1367 IFQ_SET_READY(&ifp->if_snd); 1368 1369 /* 1370 * Now we have to see what sort of media we have. 1371 * This includes probing for an MII interace and a 1372 * possible PHY. 1373 */ 1374 XL_SEL_WIN(3); 1375 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1376 if (bootverbose) 1377 device_printf(dev, "media options word: %x\n", sc->xl_media); 1378 1379 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1380 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1381 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1382 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1383 1384 xl_mediacheck(sc); 1385 1386 if (sc->xl_media & XL_MEDIAOPT_MII || 1387 sc->xl_media & XL_MEDIAOPT_BTX || 1388 sc->xl_media & XL_MEDIAOPT_BT4) { 1389 if (bootverbose) 1390 device_printf(dev, "found MII/AUTO\n"); 1391 xl_setcfg(sc); 1392 /* 1393 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK. 1394 * This is to guard against problems with certain 3Com ASIC 1395 * revisions that incorrectly map the internal transceiver 1396 * control registers at all MII addresses. 1397 */ 1398 phy = MII_PHY_ANY; 1399 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0) 1400 phy = 24; 1401 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd, 1402 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 1403 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0); 1404 if (error != 0) { 1405 device_printf(dev, "attaching PHYs failed\n"); 1406 goto fail; 1407 } 1408 goto done; 1409 } 1410 1411 /* 1412 * Sanity check. If the user has selected "auto" and this isn't 1413 * a 10/100 card of some kind, we need to force the transceiver 1414 * type to something sane. 1415 */ 1416 if (sc->xl_xcvr == XL_XCVR_AUTO) 1417 xl_choose_xcvr(sc, bootverbose); 1418 1419 /* 1420 * Do ifmedia setup. 1421 */ 1422 if (sc->xl_media & XL_MEDIAOPT_BT) { 1423 if (bootverbose) 1424 device_printf(dev, "found 10baseT\n"); 1425 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1426 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1427 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1428 ifmedia_add(&sc->ifmedia, 1429 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1430 } 1431 1432 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1433 /* 1434 * Check for a 10baseFL board in disguise. 1435 */ 1436 if (sc->xl_type == XL_TYPE_905B && 1437 sc->xl_media == XL_MEDIAOPT_10FL) { 1438 if (bootverbose) 1439 device_printf(dev, "found 10baseFL\n"); 1440 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1441 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1442 0, NULL); 1443 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1444 ifmedia_add(&sc->ifmedia, 1445 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1446 } else { 1447 if (bootverbose) 1448 device_printf(dev, "found AUI\n"); 1449 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1450 } 1451 } 1452 1453 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1454 if (bootverbose) 1455 device_printf(dev, "found BNC\n"); 1456 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1457 } 1458 1459 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1460 if (bootverbose) 1461 device_printf(dev, "found 100baseFX\n"); 1462 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1463 } 1464 1465 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1466 xl_choose_media(sc, &media); 1467 1468 if (sc->xl_miibus == NULL) 1469 ifmedia_set(&sc->ifmedia, media); 1470 1471 done: 1472 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1473 XL_SEL_WIN(0); 1474 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1475 } 1476 1477 /* 1478 * Call MI attach routine. 1479 */ 1480 ether_ifattach(ifp, eaddr); 1481 1482 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1483 NULL, xl_intr, sc, &sc->xl_intrhand); 1484 if (error) { 1485 device_printf(dev, "couldn't set up irq\n"); 1486 ether_ifdetach(ifp); 1487 goto fail; 1488 } 1489 1490 fail: 1491 if (error) 1492 xl_detach(dev); 1493 1494 return (error); 1495 } 1496 1497 /* 1498 * Choose a default media. 1499 * XXX This is a leaf function only called by xl_attach() and 1500 * acquires/releases the non-recursible driver mutex to 1501 * satisfy lock assertions. 1502 */ 1503 static void 1504 xl_choose_media(struct xl_softc *sc, int *media) 1505 { 1506 1507 XL_LOCK(sc); 1508 1509 switch (sc->xl_xcvr) { 1510 case XL_XCVR_10BT: 1511 *media = IFM_ETHER|IFM_10_T; 1512 xl_setmode(sc, *media); 1513 break; 1514 case XL_XCVR_AUI: 1515 if (sc->xl_type == XL_TYPE_905B && 1516 sc->xl_media == XL_MEDIAOPT_10FL) { 1517 *media = IFM_ETHER|IFM_10_FL; 1518 xl_setmode(sc, *media); 1519 } else { 1520 *media = IFM_ETHER|IFM_10_5; 1521 xl_setmode(sc, *media); 1522 } 1523 break; 1524 case XL_XCVR_COAX: 1525 *media = IFM_ETHER|IFM_10_2; 1526 xl_setmode(sc, *media); 1527 break; 1528 case XL_XCVR_AUTO: 1529 case XL_XCVR_100BTX: 1530 case XL_XCVR_MII: 1531 /* Chosen by miibus */ 1532 break; 1533 case XL_XCVR_100BFX: 1534 *media = IFM_ETHER|IFM_100_FX; 1535 break; 1536 default: 1537 device_printf(sc->xl_dev, "unknown XCVR type: %d\n", 1538 sc->xl_xcvr); 1539 /* 1540 * This will probably be wrong, but it prevents 1541 * the ifmedia code from panicking. 1542 */ 1543 *media = IFM_ETHER|IFM_10_T; 1544 break; 1545 } 1546 1547 XL_UNLOCK(sc); 1548 } 1549 1550 /* 1551 * Shutdown hardware and free up resources. This can be called any 1552 * time after the mutex has been initialized. It is called in both 1553 * the error case in attach and the normal detach case so it needs 1554 * to be careful about only freeing resources that have actually been 1555 * allocated. 1556 */ 1557 static int 1558 xl_detach(device_t dev) 1559 { 1560 struct xl_softc *sc; 1561 struct ifnet *ifp; 1562 int rid, res; 1563 1564 sc = device_get_softc(dev); 1565 ifp = sc->xl_ifp; 1566 1567 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1568 1569 #ifdef DEVICE_POLLING 1570 if (ifp && ifp->if_capenable & IFCAP_POLLING) 1571 ether_poll_deregister(ifp); 1572 #endif 1573 1574 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1575 rid = XL_PCI_LOMEM; 1576 res = SYS_RES_MEMORY; 1577 } else { 1578 rid = XL_PCI_LOIO; 1579 res = SYS_RES_IOPORT; 1580 } 1581 1582 /* These should only be active if attach succeeded */ 1583 if (device_is_attached(dev)) { 1584 XL_LOCK(sc); 1585 xl_stop(sc); 1586 XL_UNLOCK(sc); 1587 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1588 callout_drain(&sc->xl_tick_callout); 1589 ether_ifdetach(ifp); 1590 } 1591 if (sc->xl_miibus) 1592 device_delete_child(dev, sc->xl_miibus); 1593 bus_generic_detach(dev); 1594 ifmedia_removeall(&sc->ifmedia); 1595 1596 if (sc->xl_intrhand) 1597 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1598 if (sc->xl_irq) 1599 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1600 if (sc->xl_fres != NULL) 1601 bus_release_resource(dev, SYS_RES_MEMORY, 1602 XL_PCI_FUNCMEM, sc->xl_fres); 1603 if (sc->xl_res) 1604 bus_release_resource(dev, res, rid, sc->xl_res); 1605 1606 if (ifp) 1607 if_free(ifp); 1608 1609 if (sc->xl_mtag) { 1610 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1611 bus_dma_tag_destroy(sc->xl_mtag); 1612 } 1613 if (sc->xl_ldata.xl_rx_tag) { 1614 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1615 sc->xl_ldata.xl_rx_dmamap); 1616 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1617 sc->xl_ldata.xl_rx_dmamap); 1618 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1619 } 1620 if (sc->xl_ldata.xl_tx_tag) { 1621 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1622 sc->xl_ldata.xl_tx_dmamap); 1623 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1624 sc->xl_ldata.xl_tx_dmamap); 1625 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1626 } 1627 1628 mtx_destroy(&sc->xl_mtx); 1629 1630 return (0); 1631 } 1632 1633 /* 1634 * Initialize the transmit descriptors. 1635 */ 1636 static int 1637 xl_list_tx_init(struct xl_softc *sc) 1638 { 1639 struct xl_chain_data *cd; 1640 struct xl_list_data *ld; 1641 int error, i; 1642 1643 XL_LOCK_ASSERT(sc); 1644 1645 cd = &sc->xl_cdata; 1646 ld = &sc->xl_ldata; 1647 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1648 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1649 error = bus_dmamap_create(sc->xl_mtag, 0, 1650 &cd->xl_tx_chain[i].xl_map); 1651 if (error) 1652 return (error); 1653 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1654 i * sizeof(struct xl_list); 1655 if (i == (XL_TX_LIST_CNT - 1)) 1656 cd->xl_tx_chain[i].xl_next = NULL; 1657 else 1658 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1659 } 1660 1661 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1662 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1663 1664 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1665 return (0); 1666 } 1667 1668 /* 1669 * Initialize the transmit descriptors. 1670 */ 1671 static int 1672 xl_list_tx_init_90xB(struct xl_softc *sc) 1673 { 1674 struct xl_chain_data *cd; 1675 struct xl_list_data *ld; 1676 int error, i; 1677 1678 XL_LOCK_ASSERT(sc); 1679 1680 cd = &sc->xl_cdata; 1681 ld = &sc->xl_ldata; 1682 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1683 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1684 error = bus_dmamap_create(sc->xl_mtag, 0, 1685 &cd->xl_tx_chain[i].xl_map); 1686 if (error) 1687 return (error); 1688 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1689 i * sizeof(struct xl_list); 1690 if (i == (XL_TX_LIST_CNT - 1)) 1691 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1692 else 1693 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1694 if (i == 0) 1695 cd->xl_tx_chain[i].xl_prev = 1696 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1697 else 1698 cd->xl_tx_chain[i].xl_prev = 1699 &cd->xl_tx_chain[i - 1]; 1700 } 1701 1702 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1703 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1704 1705 cd->xl_tx_prod = 1; 1706 cd->xl_tx_cons = 1; 1707 cd->xl_tx_cnt = 0; 1708 1709 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1710 return (0); 1711 } 1712 1713 /* 1714 * Initialize the RX descriptors and allocate mbufs for them. Note that 1715 * we arrange the descriptors in a closed ring, so that the last descriptor 1716 * points back to the first. 1717 */ 1718 static int 1719 xl_list_rx_init(struct xl_softc *sc) 1720 { 1721 struct xl_chain_data *cd; 1722 struct xl_list_data *ld; 1723 int error, i, next; 1724 u_int32_t nextptr; 1725 1726 XL_LOCK_ASSERT(sc); 1727 1728 cd = &sc->xl_cdata; 1729 ld = &sc->xl_ldata; 1730 1731 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1732 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1733 error = bus_dmamap_create(sc->xl_mtag, 0, 1734 &cd->xl_rx_chain[i].xl_map); 1735 if (error) 1736 return (error); 1737 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1738 if (error) 1739 return (error); 1740 if (i == (XL_RX_LIST_CNT - 1)) 1741 next = 0; 1742 else 1743 next = i + 1; 1744 nextptr = ld->xl_rx_dmaaddr + 1745 next * sizeof(struct xl_list_onefrag); 1746 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1747 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1748 } 1749 1750 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1751 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1752 1753 return (0); 1754 } 1755 1756 /* 1757 * Initialize an RX descriptor and attach an MBUF cluster. 1758 * If we fail to do so, we need to leave the old mbuf and 1759 * the old DMA map untouched so that it can be reused. 1760 */ 1761 static int 1762 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1763 { 1764 struct mbuf *m_new = NULL; 1765 bus_dmamap_t map; 1766 bus_dma_segment_t segs[1]; 1767 int error, nseg; 1768 1769 XL_LOCK_ASSERT(sc); 1770 1771 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1772 if (m_new == NULL) 1773 return (ENOBUFS); 1774 1775 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1776 1777 /* Force longword alignment for packet payload. */ 1778 m_adj(m_new, ETHER_ALIGN); 1779 1780 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, 1781 segs, &nseg, BUS_DMA_NOWAIT); 1782 if (error) { 1783 m_freem(m_new); 1784 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", 1785 error); 1786 return (error); 1787 } 1788 KASSERT(nseg == 1, 1789 ("%s: too many DMA segments (%d)", __func__, nseg)); 1790 1791 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1792 map = c->xl_map; 1793 c->xl_map = sc->xl_tmpmap; 1794 sc->xl_tmpmap = map; 1795 c->xl_mbuf = m_new; 1796 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1797 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); 1798 c->xl_ptr->xl_status = 0; 1799 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1800 return (0); 1801 } 1802 1803 static int 1804 xl_rx_resync(struct xl_softc *sc) 1805 { 1806 struct xl_chain_onefrag *pos; 1807 int i; 1808 1809 XL_LOCK_ASSERT(sc); 1810 1811 pos = sc->xl_cdata.xl_rx_head; 1812 1813 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1814 if (pos->xl_ptr->xl_status) 1815 break; 1816 pos = pos->xl_next; 1817 } 1818 1819 if (i == XL_RX_LIST_CNT) 1820 return (0); 1821 1822 sc->xl_cdata.xl_rx_head = pos; 1823 1824 return (EAGAIN); 1825 } 1826 1827 /* 1828 * A frame has been uploaded: pass the resulting mbuf chain up to 1829 * the higher level protocols. 1830 */ 1831 static int 1832 xl_rxeof(struct xl_softc *sc) 1833 { 1834 struct mbuf *m; 1835 struct ifnet *ifp = sc->xl_ifp; 1836 struct xl_chain_onefrag *cur_rx; 1837 int total_len; 1838 int rx_npkts = 0; 1839 u_int32_t rxstat; 1840 1841 XL_LOCK_ASSERT(sc); 1842 again: 1843 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1844 BUS_DMASYNC_POSTREAD); 1845 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1846 #ifdef DEVICE_POLLING 1847 if (ifp->if_capenable & IFCAP_POLLING) { 1848 if (sc->rxcycles <= 0) 1849 break; 1850 sc->rxcycles--; 1851 } 1852 #endif 1853 cur_rx = sc->xl_cdata.xl_rx_head; 1854 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1855 total_len = rxstat & XL_RXSTAT_LENMASK; 1856 rx_npkts++; 1857 1858 /* 1859 * Since we have told the chip to allow large frames, 1860 * we need to trap giant frame errors in software. We allow 1861 * a little more than the normal frame size to account for 1862 * frames with VLAN tags. 1863 */ 1864 if (total_len > XL_MAX_FRAMELEN) 1865 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1866 1867 /* 1868 * If an error occurs, update stats, clear the 1869 * status word and leave the mbuf cluster in place: 1870 * it should simply get re-used next time this descriptor 1871 * comes up in the ring. 1872 */ 1873 if (rxstat & XL_RXSTAT_UP_ERROR) { 1874 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1875 cur_rx->xl_ptr->xl_status = 0; 1876 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1877 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1878 continue; 1879 } 1880 1881 /* 1882 * If the error bit was not set, the upload complete 1883 * bit should be set which means we have a valid packet. 1884 * If not, something truly strange has happened. 1885 */ 1886 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1887 device_printf(sc->xl_dev, 1888 "bad receive status -- packet dropped\n"); 1889 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1890 cur_rx->xl_ptr->xl_status = 0; 1891 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1892 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1893 continue; 1894 } 1895 1896 /* No errors; receive the packet. */ 1897 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 1898 BUS_DMASYNC_POSTREAD); 1899 m = cur_rx->xl_mbuf; 1900 1901 /* 1902 * Try to conjure up a new mbuf cluster. If that 1903 * fails, it means we have an out of memory condition and 1904 * should leave the buffer in place and continue. This will 1905 * result in a lost packet, but there's little else we 1906 * can do in this situation. 1907 */ 1908 if (xl_newbuf(sc, cur_rx)) { 1909 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1910 cur_rx->xl_ptr->xl_status = 0; 1911 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1912 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1913 continue; 1914 } 1915 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1916 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1917 1918 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1919 m->m_pkthdr.rcvif = ifp; 1920 m->m_pkthdr.len = m->m_len = total_len; 1921 1922 if (ifp->if_capenable & IFCAP_RXCSUM) { 1923 /* Do IP checksum checking. */ 1924 if (rxstat & XL_RXSTAT_IPCKOK) 1925 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1926 if (!(rxstat & XL_RXSTAT_IPCKERR)) 1927 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1928 if ((rxstat & XL_RXSTAT_TCPCOK && 1929 !(rxstat & XL_RXSTAT_TCPCKERR)) || 1930 (rxstat & XL_RXSTAT_UDPCKOK && 1931 !(rxstat & XL_RXSTAT_UDPCKERR))) { 1932 m->m_pkthdr.csum_flags |= 1933 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1934 m->m_pkthdr.csum_data = 0xffff; 1935 } 1936 } 1937 1938 XL_UNLOCK(sc); 1939 (*ifp->if_input)(ifp, m); 1940 XL_LOCK(sc); 1941 1942 /* 1943 * If we are running from the taskqueue, the interface 1944 * might have been stopped while we were passing the last 1945 * packet up the network stack. 1946 */ 1947 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1948 return (rx_npkts); 1949 } 1950 1951 /* 1952 * Handle the 'end of channel' condition. When the upload 1953 * engine hits the end of the RX ring, it will stall. This 1954 * is our cue to flush the RX ring, reload the uplist pointer 1955 * register and unstall the engine. 1956 * XXX This is actually a little goofy. With the ThunderLAN 1957 * chip, you get an interrupt when the receiver hits the end 1958 * of the receive ring, which tells you exactly when you 1959 * you need to reload the ring pointer. Here we have to 1960 * fake it. I'm mad at myself for not being clever enough 1961 * to avoid the use of a goto here. 1962 */ 1963 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 1964 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 1965 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 1966 xl_wait(sc); 1967 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 1968 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 1969 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 1970 goto again; 1971 } 1972 return (rx_npkts); 1973 } 1974 1975 /* 1976 * Taskqueue wrapper for xl_rxeof(). 1977 */ 1978 static void 1979 xl_rxeof_task(void *arg, int pending) 1980 { 1981 struct xl_softc *sc = (struct xl_softc *)arg; 1982 1983 XL_LOCK(sc); 1984 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING) 1985 xl_rxeof(sc); 1986 XL_UNLOCK(sc); 1987 } 1988 1989 /* 1990 * A frame was downloaded to the chip. It's safe for us to clean up 1991 * the list buffers. 1992 */ 1993 static void 1994 xl_txeof(struct xl_softc *sc) 1995 { 1996 struct xl_chain *cur_tx; 1997 struct ifnet *ifp = sc->xl_ifp; 1998 1999 XL_LOCK_ASSERT(sc); 2000 2001 /* 2002 * Go through our tx list and free mbufs for those 2003 * frames that have been uploaded. Note: the 3c905B 2004 * sets a special bit in the status word to let us 2005 * know that a frame has been downloaded, but the 2006 * original 3c900/3c905 adapters don't do that. 2007 * Consequently, we have to use a different test if 2008 * xl_type != XL_TYPE_905B. 2009 */ 2010 while (sc->xl_cdata.xl_tx_head != NULL) { 2011 cur_tx = sc->xl_cdata.xl_tx_head; 2012 2013 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2014 break; 2015 2016 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2017 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2018 BUS_DMASYNC_POSTWRITE); 2019 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2020 m_freem(cur_tx->xl_mbuf); 2021 cur_tx->xl_mbuf = NULL; 2022 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2023 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2024 2025 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2026 sc->xl_cdata.xl_tx_free = cur_tx; 2027 } 2028 2029 if (sc->xl_cdata.xl_tx_head == NULL) { 2030 sc->xl_wdog_timer = 0; 2031 sc->xl_cdata.xl_tx_tail = NULL; 2032 } else { 2033 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2034 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2035 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2036 sc->xl_cdata.xl_tx_head->xl_phys); 2037 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2038 } 2039 } 2040 } 2041 2042 static void 2043 xl_txeof_90xB(struct xl_softc *sc) 2044 { 2045 struct xl_chain *cur_tx = NULL; 2046 struct ifnet *ifp = sc->xl_ifp; 2047 int idx; 2048 2049 XL_LOCK_ASSERT(sc); 2050 2051 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2052 BUS_DMASYNC_POSTREAD); 2053 idx = sc->xl_cdata.xl_tx_cons; 2054 while (idx != sc->xl_cdata.xl_tx_prod) { 2055 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2056 2057 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2058 XL_TXSTAT_DL_COMPLETE)) 2059 break; 2060 2061 if (cur_tx->xl_mbuf != NULL) { 2062 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2063 BUS_DMASYNC_POSTWRITE); 2064 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2065 m_freem(cur_tx->xl_mbuf); 2066 cur_tx->xl_mbuf = NULL; 2067 } 2068 2069 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2070 2071 sc->xl_cdata.xl_tx_cnt--; 2072 XL_INC(idx, XL_TX_LIST_CNT); 2073 } 2074 2075 if (sc->xl_cdata.xl_tx_cnt == 0) 2076 sc->xl_wdog_timer = 0; 2077 sc->xl_cdata.xl_tx_cons = idx; 2078 2079 if (cur_tx != NULL) 2080 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2081 } 2082 2083 /* 2084 * TX 'end of channel' interrupt handler. Actually, we should 2085 * only get a 'TX complete' interrupt if there's a transmit error, 2086 * so this is really TX error handler. 2087 */ 2088 static void 2089 xl_txeoc(struct xl_softc *sc) 2090 { 2091 u_int8_t txstat; 2092 2093 XL_LOCK_ASSERT(sc); 2094 2095 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2096 if (txstat & XL_TXSTATUS_UNDERRUN || 2097 txstat & XL_TXSTATUS_JABBER || 2098 txstat & XL_TXSTATUS_RECLAIM) { 2099 device_printf(sc->xl_dev, 2100 "transmission error: 0x%02x\n", txstat); 2101 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2102 xl_wait(sc); 2103 if (sc->xl_type == XL_TYPE_905B) { 2104 if (sc->xl_cdata.xl_tx_cnt) { 2105 int i; 2106 struct xl_chain *c; 2107 2108 i = sc->xl_cdata.xl_tx_cons; 2109 c = &sc->xl_cdata.xl_tx_chain[i]; 2110 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2111 c->xl_phys); 2112 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2113 sc->xl_wdog_timer = 5; 2114 } 2115 } else { 2116 if (sc->xl_cdata.xl_tx_head != NULL) { 2117 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2118 sc->xl_cdata.xl_tx_head->xl_phys); 2119 sc->xl_wdog_timer = 5; 2120 } 2121 } 2122 /* 2123 * Remember to set this for the 2124 * first generation 3c90X chips. 2125 */ 2126 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2127 if (txstat & XL_TXSTATUS_UNDERRUN && 2128 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2129 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2130 device_printf(sc->xl_dev, 2131 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2132 } 2133 CSR_WRITE_2(sc, XL_COMMAND, 2134 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2135 if (sc->xl_type == XL_TYPE_905B) { 2136 CSR_WRITE_2(sc, XL_COMMAND, 2137 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2138 } 2139 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2140 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2141 } else { 2142 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2143 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2144 } 2145 /* 2146 * Write an arbitrary byte to the TX_STATUS register 2147 * to clear this interrupt/error and advance to the next. 2148 */ 2149 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2150 } 2151 } 2152 2153 static void 2154 xl_intr(void *arg) 2155 { 2156 struct xl_softc *sc = arg; 2157 struct ifnet *ifp = sc->xl_ifp; 2158 u_int16_t status; 2159 2160 XL_LOCK(sc); 2161 2162 #ifdef DEVICE_POLLING 2163 if (ifp->if_capenable & IFCAP_POLLING) { 2164 XL_UNLOCK(sc); 2165 return; 2166 } 2167 #endif 2168 2169 for (;;) { 2170 status = CSR_READ_2(sc, XL_STATUS); 2171 if ((status & XL_INTRS) == 0 || status == 0xFFFF) 2172 break; 2173 CSR_WRITE_2(sc, XL_COMMAND, 2174 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2175 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2176 break; 2177 2178 if (status & XL_STAT_UP_COMPLETE) { 2179 if (xl_rxeof(sc) == 0) { 2180 while (xl_rx_resync(sc)) 2181 xl_rxeof(sc); 2182 } 2183 } 2184 2185 if (status & XL_STAT_DOWN_COMPLETE) { 2186 if (sc->xl_type == XL_TYPE_905B) 2187 xl_txeof_90xB(sc); 2188 else 2189 xl_txeof(sc); 2190 } 2191 2192 if (status & XL_STAT_TX_COMPLETE) { 2193 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2194 xl_txeoc(sc); 2195 } 2196 2197 if (status & XL_STAT_ADFAIL) { 2198 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2199 xl_init_locked(sc); 2200 break; 2201 } 2202 2203 if (status & XL_STAT_STATSOFLOW) 2204 xl_stats_update(sc); 2205 } 2206 2207 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2208 ifp->if_drv_flags & IFF_DRV_RUNNING) { 2209 if (sc->xl_type == XL_TYPE_905B) 2210 xl_start_90xB_locked(ifp); 2211 else 2212 xl_start_locked(ifp); 2213 } 2214 2215 XL_UNLOCK(sc); 2216 } 2217 2218 #ifdef DEVICE_POLLING 2219 static int 2220 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2221 { 2222 struct xl_softc *sc = ifp->if_softc; 2223 int rx_npkts = 0; 2224 2225 XL_LOCK(sc); 2226 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2227 rx_npkts = xl_poll_locked(ifp, cmd, count); 2228 XL_UNLOCK(sc); 2229 return (rx_npkts); 2230 } 2231 2232 static int 2233 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2234 { 2235 struct xl_softc *sc = ifp->if_softc; 2236 int rx_npkts; 2237 2238 XL_LOCK_ASSERT(sc); 2239 2240 sc->rxcycles = count; 2241 rx_npkts = xl_rxeof(sc); 2242 if (sc->xl_type == XL_TYPE_905B) 2243 xl_txeof_90xB(sc); 2244 else 2245 xl_txeof(sc); 2246 2247 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2248 if (sc->xl_type == XL_TYPE_905B) 2249 xl_start_90xB_locked(ifp); 2250 else 2251 xl_start_locked(ifp); 2252 } 2253 2254 if (cmd == POLL_AND_CHECK_STATUS) { 2255 u_int16_t status; 2256 2257 status = CSR_READ_2(sc, XL_STATUS); 2258 if (status & XL_INTRS && status != 0xFFFF) { 2259 CSR_WRITE_2(sc, XL_COMMAND, 2260 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2261 2262 if (status & XL_STAT_TX_COMPLETE) { 2263 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2264 xl_txeoc(sc); 2265 } 2266 2267 if (status & XL_STAT_ADFAIL) { 2268 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2269 xl_init_locked(sc); 2270 } 2271 2272 if (status & XL_STAT_STATSOFLOW) 2273 xl_stats_update(sc); 2274 } 2275 } 2276 return (rx_npkts); 2277 } 2278 #endif /* DEVICE_POLLING */ 2279 2280 static void 2281 xl_tick(void *xsc) 2282 { 2283 struct xl_softc *sc = xsc; 2284 struct mii_data *mii; 2285 2286 XL_LOCK_ASSERT(sc); 2287 2288 if (sc->xl_miibus != NULL) { 2289 mii = device_get_softc(sc->xl_miibus); 2290 mii_tick(mii); 2291 } 2292 2293 xl_stats_update(sc); 2294 if (xl_watchdog(sc) == EJUSTRETURN) 2295 return; 2296 2297 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc); 2298 } 2299 2300 static void 2301 xl_stats_update(struct xl_softc *sc) 2302 { 2303 struct ifnet *ifp = sc->xl_ifp; 2304 struct xl_stats xl_stats; 2305 u_int8_t *p; 2306 int i; 2307 2308 XL_LOCK_ASSERT(sc); 2309 2310 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2311 2312 p = (u_int8_t *)&xl_stats; 2313 2314 /* Read all the stats registers. */ 2315 XL_SEL_WIN(6); 2316 2317 for (i = 0; i < 16; i++) 2318 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2319 2320 if_inc_counter(ifp, IFCOUNTER_IERRORS, xl_stats.xl_rx_overrun); 2321 2322 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2323 xl_stats.xl_tx_multi_collision + 2324 xl_stats.xl_tx_single_collision + 2325 xl_stats.xl_tx_late_collision); 2326 2327 /* 2328 * Boomerang and cyclone chips have an extra stats counter 2329 * in window 4 (BadSSD). We have to read this too in order 2330 * to clear out all the stats registers and avoid a statsoflow 2331 * interrupt. 2332 */ 2333 XL_SEL_WIN(4); 2334 CSR_READ_1(sc, XL_W4_BADSSD); 2335 XL_SEL_WIN(7); 2336 } 2337 2338 /* 2339 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2340 * pointers to the fragment pointers. 2341 */ 2342 static int 2343 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) 2344 { 2345 struct mbuf *m_new; 2346 struct ifnet *ifp = sc->xl_ifp; 2347 int error, i, nseg, total_len; 2348 u_int32_t status; 2349 2350 XL_LOCK_ASSERT(sc); 2351 2352 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, 2353 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2354 2355 if (error && error != EFBIG) { 2356 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2357 return (error); 2358 } 2359 2360 /* 2361 * Handle special case: we used up all 63 fragments, 2362 * but we have more mbufs left in the chain. Copy the 2363 * data into an mbuf cluster. Note that we don't 2364 * bother clearing the values in the other fragment 2365 * pointers/counters; it wouldn't gain us anything, 2366 * and would waste cycles. 2367 */ 2368 if (error) { 2369 m_new = m_collapse(*m_head, M_NOWAIT, XL_MAXFRAGS); 2370 if (m_new == NULL) { 2371 m_freem(*m_head); 2372 *m_head = NULL; 2373 return (ENOBUFS); 2374 } 2375 *m_head = m_new; 2376 2377 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, 2378 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2379 if (error) { 2380 m_freem(*m_head); 2381 *m_head = NULL; 2382 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2383 return (error); 2384 } 2385 } 2386 2387 KASSERT(nseg <= XL_MAXFRAGS, 2388 ("%s: too many DMA segments (%d)", __func__, nseg)); 2389 if (nseg == 0) { 2390 m_freem(*m_head); 2391 *m_head = NULL; 2392 return (EIO); 2393 } 2394 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2395 2396 total_len = 0; 2397 for (i = 0; i < nseg; i++) { 2398 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, 2399 ("segment size too large")); 2400 c->xl_ptr->xl_frag[i].xl_addr = 2401 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); 2402 c->xl_ptr->xl_frag[i].xl_len = 2403 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); 2404 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; 2405 } 2406 c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG); 2407 2408 if (sc->xl_type == XL_TYPE_905B) { 2409 status = XL_TXSTAT_RND_DEFEAT; 2410 2411 #ifndef XL905B_TXCSUM_BROKEN 2412 if ((*m_head)->m_pkthdr.csum_flags) { 2413 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2414 status |= XL_TXSTAT_IPCKSUM; 2415 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2416 status |= XL_TXSTAT_TCPCKSUM; 2417 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2418 status |= XL_TXSTAT_UDPCKSUM; 2419 } 2420 #endif 2421 } else 2422 status = total_len; 2423 c->xl_ptr->xl_status = htole32(status); 2424 c->xl_ptr->xl_next = 0; 2425 2426 c->xl_mbuf = *m_head; 2427 return (0); 2428 } 2429 2430 /* 2431 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2432 * to the mbuf data regions directly in the transmit lists. We also save a 2433 * copy of the pointers since the transmit list fragment pointers are 2434 * physical addresses. 2435 */ 2436 2437 static void 2438 xl_start(struct ifnet *ifp) 2439 { 2440 struct xl_softc *sc = ifp->if_softc; 2441 2442 XL_LOCK(sc); 2443 2444 if (sc->xl_type == XL_TYPE_905B) 2445 xl_start_90xB_locked(ifp); 2446 else 2447 xl_start_locked(ifp); 2448 2449 XL_UNLOCK(sc); 2450 } 2451 2452 static void 2453 xl_start_locked(struct ifnet *ifp) 2454 { 2455 struct xl_softc *sc = ifp->if_softc; 2456 struct mbuf *m_head; 2457 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2458 struct xl_chain *prev_tx; 2459 int error; 2460 2461 XL_LOCK_ASSERT(sc); 2462 2463 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2464 IFF_DRV_RUNNING) 2465 return; 2466 /* 2467 * Check for an available queue slot. If there are none, 2468 * punt. 2469 */ 2470 if (sc->xl_cdata.xl_tx_free == NULL) { 2471 xl_txeoc(sc); 2472 xl_txeof(sc); 2473 if (sc->xl_cdata.xl_tx_free == NULL) { 2474 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2475 return; 2476 } 2477 } 2478 2479 start_tx = sc->xl_cdata.xl_tx_free; 2480 2481 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2482 sc->xl_cdata.xl_tx_free != NULL;) { 2483 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2484 if (m_head == NULL) 2485 break; 2486 2487 /* Pick a descriptor off the free list. */ 2488 prev_tx = cur_tx; 2489 cur_tx = sc->xl_cdata.xl_tx_free; 2490 2491 /* Pack the data into the descriptor. */ 2492 error = xl_encap(sc, cur_tx, &m_head); 2493 if (error) { 2494 cur_tx = prev_tx; 2495 if (m_head == NULL) 2496 break; 2497 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2498 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2499 break; 2500 } 2501 2502 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2503 cur_tx->xl_next = NULL; 2504 2505 /* Chain it together. */ 2506 if (prev != NULL) { 2507 prev->xl_next = cur_tx; 2508 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2509 } 2510 prev = cur_tx; 2511 2512 /* 2513 * If there's a BPF listener, bounce a copy of this frame 2514 * to him. 2515 */ 2516 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2517 } 2518 2519 /* 2520 * If there are no packets queued, bail. 2521 */ 2522 if (cur_tx == NULL) 2523 return; 2524 2525 /* 2526 * Place the request for the upload interrupt 2527 * in the last descriptor in the chain. This way, if 2528 * we're chaining several packets at once, we'll only 2529 * get an interrupt once for the whole chain rather than 2530 * once for each packet. 2531 */ 2532 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2533 2534 /* 2535 * Queue the packets. If the TX channel is clear, update 2536 * the downlist pointer register. 2537 */ 2538 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2539 xl_wait(sc); 2540 2541 if (sc->xl_cdata.xl_tx_head != NULL) { 2542 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2543 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2544 htole32(start_tx->xl_phys); 2545 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &= 2546 htole32(~XL_TXSTAT_DL_INTR); 2547 sc->xl_cdata.xl_tx_tail = cur_tx; 2548 } else { 2549 sc->xl_cdata.xl_tx_head = start_tx; 2550 sc->xl_cdata.xl_tx_tail = cur_tx; 2551 } 2552 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2553 BUS_DMASYNC_PREWRITE); 2554 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2555 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2556 2557 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2558 2559 XL_SEL_WIN(7); 2560 2561 /* 2562 * Set a timeout in case the chip goes out to lunch. 2563 */ 2564 sc->xl_wdog_timer = 5; 2565 2566 /* 2567 * XXX Under certain conditions, usually on slower machines 2568 * where interrupts may be dropped, it's possible for the 2569 * adapter to chew up all the buffers in the receive ring 2570 * and stall, without us being able to do anything about it. 2571 * To guard against this, we need to make a pass over the 2572 * RX queue to make sure there aren't any packets pending. 2573 * Doing it here means we can flush the receive ring at the 2574 * same time the chip is DMAing the transmit descriptors we 2575 * just gave it. 2576 * 2577 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2578 * nature of their chips in all their marketing literature; 2579 * we may as well take advantage of it. :) 2580 */ 2581 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2582 } 2583 2584 static void 2585 xl_start_90xB_locked(struct ifnet *ifp) 2586 { 2587 struct xl_softc *sc = ifp->if_softc; 2588 struct mbuf *m_head; 2589 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2590 struct xl_chain *prev_tx; 2591 int error, idx; 2592 2593 XL_LOCK_ASSERT(sc); 2594 2595 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2596 IFF_DRV_RUNNING) 2597 return; 2598 2599 idx = sc->xl_cdata.xl_tx_prod; 2600 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2601 2602 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2603 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { 2604 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2605 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2606 break; 2607 } 2608 2609 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2610 if (m_head == NULL) 2611 break; 2612 2613 prev_tx = cur_tx; 2614 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2615 2616 /* Pack the data into the descriptor. */ 2617 error = xl_encap(sc, cur_tx, &m_head); 2618 if (error) { 2619 cur_tx = prev_tx; 2620 if (m_head == NULL) 2621 break; 2622 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2623 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2624 break; 2625 } 2626 2627 /* Chain it together. */ 2628 if (prev != NULL) 2629 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2630 prev = cur_tx; 2631 2632 /* 2633 * If there's a BPF listener, bounce a copy of this frame 2634 * to him. 2635 */ 2636 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2637 2638 XL_INC(idx, XL_TX_LIST_CNT); 2639 sc->xl_cdata.xl_tx_cnt++; 2640 } 2641 2642 /* 2643 * If there are no packets queued, bail. 2644 */ 2645 if (cur_tx == NULL) 2646 return; 2647 2648 /* 2649 * Place the request for the upload interrupt 2650 * in the last descriptor in the chain. This way, if 2651 * we're chaining several packets at once, we'll only 2652 * get an interrupt once for the whole chain rather than 2653 * once for each packet. 2654 */ 2655 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2656 2657 /* Start transmission */ 2658 sc->xl_cdata.xl_tx_prod = idx; 2659 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2660 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2661 BUS_DMASYNC_PREWRITE); 2662 2663 /* 2664 * Set a timeout in case the chip goes out to lunch. 2665 */ 2666 sc->xl_wdog_timer = 5; 2667 } 2668 2669 static void 2670 xl_init(void *xsc) 2671 { 2672 struct xl_softc *sc = xsc; 2673 2674 XL_LOCK(sc); 2675 xl_init_locked(sc); 2676 XL_UNLOCK(sc); 2677 } 2678 2679 static void 2680 xl_init_locked(struct xl_softc *sc) 2681 { 2682 struct ifnet *ifp = sc->xl_ifp; 2683 int error, i; 2684 struct mii_data *mii = NULL; 2685 2686 XL_LOCK_ASSERT(sc); 2687 2688 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2689 return; 2690 /* 2691 * Cancel pending I/O and free all RX/TX buffers. 2692 */ 2693 xl_stop(sc); 2694 2695 /* Reset the chip to a known state. */ 2696 xl_reset(sc); 2697 2698 if (sc->xl_miibus == NULL) { 2699 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2700 xl_wait(sc); 2701 } 2702 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2703 xl_wait(sc); 2704 DELAY(10000); 2705 2706 if (sc->xl_miibus != NULL) 2707 mii = device_get_softc(sc->xl_miibus); 2708 2709 /* 2710 * Clear WOL status and disable all WOL feature as WOL 2711 * would interfere Rx operation under normal environments. 2712 */ 2713 if ((sc->xl_flags & XL_FLAG_WOL) != 0) { 2714 XL_SEL_WIN(7); 2715 CSR_READ_2(sc, XL_W7_BM_PME); 2716 CSR_WRITE_2(sc, XL_W7_BM_PME, 0); 2717 } 2718 /* Init our MAC address */ 2719 XL_SEL_WIN(2); 2720 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2721 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2722 IF_LLADDR(sc->xl_ifp)[i]); 2723 } 2724 2725 /* Clear the station mask. */ 2726 for (i = 0; i < 3; i++) 2727 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2728 #ifdef notdef 2729 /* Reset TX and RX. */ 2730 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2731 xl_wait(sc); 2732 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2733 xl_wait(sc); 2734 #endif 2735 /* Init circular RX list. */ 2736 error = xl_list_rx_init(sc); 2737 if (error) { 2738 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n", 2739 error); 2740 xl_stop(sc); 2741 return; 2742 } 2743 2744 /* Init TX descriptors. */ 2745 if (sc->xl_type == XL_TYPE_905B) 2746 error = xl_list_tx_init_90xB(sc); 2747 else 2748 error = xl_list_tx_init(sc); 2749 if (error) { 2750 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n", 2751 error); 2752 xl_stop(sc); 2753 return; 2754 } 2755 2756 /* 2757 * Set the TX freethresh value. 2758 * Note that this has no effect on 3c905B "cyclone" 2759 * cards but is required for 3c900/3c905 "boomerang" 2760 * cards in order to enable the download engine. 2761 */ 2762 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2763 2764 /* Set the TX start threshold for best performance. */ 2765 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2766 2767 /* 2768 * If this is a 3c905B, also set the tx reclaim threshold. 2769 * This helps cut down on the number of tx reclaim errors 2770 * that could happen on a busy network. The chip multiplies 2771 * the register value by 16 to obtain the actual threshold 2772 * in bytes, so we divide by 16 when setting the value here. 2773 * The existing threshold value can be examined by reading 2774 * the register at offset 9 in window 5. 2775 */ 2776 if (sc->xl_type == XL_TYPE_905B) { 2777 CSR_WRITE_2(sc, XL_COMMAND, 2778 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2779 } 2780 2781 /* Set RX filter bits. */ 2782 xl_rxfilter(sc); 2783 2784 /* 2785 * Load the address of the RX list. We have to 2786 * stall the upload engine before we can manipulate 2787 * the uplist pointer register, then unstall it when 2788 * we're finished. We also have to wait for the 2789 * stall command to complete before proceeding. 2790 * Note that we have to do this after any RX resets 2791 * have completed since the uplist register is cleared 2792 * by a reset. 2793 */ 2794 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2795 xl_wait(sc); 2796 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2797 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2798 xl_wait(sc); 2799 2800 if (sc->xl_type == XL_TYPE_905B) { 2801 /* Set polling interval */ 2802 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2803 /* Load the address of the TX list */ 2804 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2805 xl_wait(sc); 2806 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2807 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2808 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2809 xl_wait(sc); 2810 } 2811 2812 /* 2813 * If the coax transceiver is on, make sure to enable 2814 * the DC-DC converter. 2815 */ 2816 XL_SEL_WIN(3); 2817 if (sc->xl_xcvr == XL_XCVR_COAX) 2818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2819 else 2820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2821 2822 /* 2823 * increase packet size to allow reception of 802.1q or ISL packets. 2824 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2825 * control register. For 3c90xB/C chips, use the RX packet size 2826 * register. 2827 */ 2828 2829 if (sc->xl_type == XL_TYPE_905B) 2830 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2831 else { 2832 u_int8_t macctl; 2833 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2834 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2835 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2836 } 2837 2838 /* Clear out the stats counters. */ 2839 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2840 xl_stats_update(sc); 2841 XL_SEL_WIN(4); 2842 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2843 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2844 2845 /* 2846 * Enable interrupts. 2847 */ 2848 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2849 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2850 #ifdef DEVICE_POLLING 2851 /* Disable interrupts if we are polling. */ 2852 if (ifp->if_capenable & IFCAP_POLLING) 2853 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2854 else 2855 #endif 2856 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2857 if (sc->xl_flags & XL_FLAG_FUNCREG) 2858 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2859 2860 /* Set the RX early threshold */ 2861 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2862 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2863 2864 /* Enable receiver and transmitter. */ 2865 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2866 xl_wait(sc); 2867 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2868 xl_wait(sc); 2869 2870 /* XXX Downcall to miibus. */ 2871 if (mii != NULL) 2872 mii_mediachg(mii); 2873 2874 /* Select window 7 for normal operations. */ 2875 XL_SEL_WIN(7); 2876 2877 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2878 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2879 2880 sc->xl_wdog_timer = 0; 2881 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc); 2882 } 2883 2884 /* 2885 * Set media options. 2886 */ 2887 static int 2888 xl_ifmedia_upd(struct ifnet *ifp) 2889 { 2890 struct xl_softc *sc = ifp->if_softc; 2891 struct ifmedia *ifm = NULL; 2892 struct mii_data *mii = NULL; 2893 2894 XL_LOCK(sc); 2895 2896 if (sc->xl_miibus != NULL) 2897 mii = device_get_softc(sc->xl_miibus); 2898 if (mii == NULL) 2899 ifm = &sc->ifmedia; 2900 else 2901 ifm = &mii->mii_media; 2902 2903 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2904 case IFM_100_FX: 2905 case IFM_10_FL: 2906 case IFM_10_2: 2907 case IFM_10_5: 2908 xl_setmode(sc, ifm->ifm_media); 2909 XL_UNLOCK(sc); 2910 return (0); 2911 } 2912 2913 if (sc->xl_media & XL_MEDIAOPT_MII || 2914 sc->xl_media & XL_MEDIAOPT_BTX || 2915 sc->xl_media & XL_MEDIAOPT_BT4) { 2916 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2917 xl_init_locked(sc); 2918 } else { 2919 xl_setmode(sc, ifm->ifm_media); 2920 } 2921 2922 XL_UNLOCK(sc); 2923 2924 return (0); 2925 } 2926 2927 /* 2928 * Report current media status. 2929 */ 2930 static void 2931 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2932 { 2933 struct xl_softc *sc = ifp->if_softc; 2934 u_int32_t icfg; 2935 u_int16_t status = 0; 2936 struct mii_data *mii = NULL; 2937 2938 XL_LOCK(sc); 2939 2940 if (sc->xl_miibus != NULL) 2941 mii = device_get_softc(sc->xl_miibus); 2942 2943 XL_SEL_WIN(4); 2944 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 2945 2946 XL_SEL_WIN(3); 2947 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2948 icfg >>= XL_ICFG_CONNECTOR_BITS; 2949 2950 ifmr->ifm_active = IFM_ETHER; 2951 ifmr->ifm_status = IFM_AVALID; 2952 2953 if ((status & XL_MEDIASTAT_CARRIER) == 0) 2954 ifmr->ifm_status |= IFM_ACTIVE; 2955 2956 switch (icfg) { 2957 case XL_XCVR_10BT: 2958 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2959 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2960 ifmr->ifm_active |= IFM_FDX; 2961 else 2962 ifmr->ifm_active |= IFM_HDX; 2963 break; 2964 case XL_XCVR_AUI: 2965 if (sc->xl_type == XL_TYPE_905B && 2966 sc->xl_media == XL_MEDIAOPT_10FL) { 2967 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 2968 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2969 ifmr->ifm_active |= IFM_FDX; 2970 else 2971 ifmr->ifm_active |= IFM_HDX; 2972 } else 2973 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2974 break; 2975 case XL_XCVR_COAX: 2976 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 2977 break; 2978 /* 2979 * XXX MII and BTX/AUTO should be separate cases. 2980 */ 2981 2982 case XL_XCVR_100BTX: 2983 case XL_XCVR_AUTO: 2984 case XL_XCVR_MII: 2985 if (mii != NULL) { 2986 mii_pollstat(mii); 2987 ifmr->ifm_active = mii->mii_media_active; 2988 ifmr->ifm_status = mii->mii_media_status; 2989 } 2990 break; 2991 case XL_XCVR_100BFX: 2992 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 2993 break; 2994 default: 2995 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 2996 break; 2997 } 2998 2999 XL_UNLOCK(sc); 3000 } 3001 3002 static int 3003 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3004 { 3005 struct xl_softc *sc = ifp->if_softc; 3006 struct ifreq *ifr = (struct ifreq *) data; 3007 int error = 0, mask; 3008 struct mii_data *mii = NULL; 3009 3010 switch (command) { 3011 case SIOCSIFFLAGS: 3012 XL_LOCK(sc); 3013 if (ifp->if_flags & IFF_UP) { 3014 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3015 (ifp->if_flags ^ sc->xl_if_flags) & 3016 (IFF_PROMISC | IFF_ALLMULTI)) 3017 xl_rxfilter(sc); 3018 else 3019 xl_init_locked(sc); 3020 } else { 3021 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3022 xl_stop(sc); 3023 } 3024 sc->xl_if_flags = ifp->if_flags; 3025 XL_UNLOCK(sc); 3026 break; 3027 case SIOCADDMULTI: 3028 case SIOCDELMULTI: 3029 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3030 XL_LOCK(sc); 3031 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3032 xl_rxfilter(sc); 3033 XL_UNLOCK(sc); 3034 break; 3035 case SIOCGIFMEDIA: 3036 case SIOCSIFMEDIA: 3037 if (sc->xl_miibus != NULL) 3038 mii = device_get_softc(sc->xl_miibus); 3039 if (mii == NULL) 3040 error = ifmedia_ioctl(ifp, ifr, 3041 &sc->ifmedia, command); 3042 else 3043 error = ifmedia_ioctl(ifp, ifr, 3044 &mii->mii_media, command); 3045 break; 3046 case SIOCSIFCAP: 3047 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3048 #ifdef DEVICE_POLLING 3049 if ((mask & IFCAP_POLLING) != 0 && 3050 (ifp->if_capabilities & IFCAP_POLLING) != 0) { 3051 ifp->if_capenable ^= IFCAP_POLLING; 3052 if ((ifp->if_capenable & IFCAP_POLLING) != 0) { 3053 error = ether_poll_register(xl_poll, ifp); 3054 if (error) 3055 break; 3056 XL_LOCK(sc); 3057 /* Disable interrupts */ 3058 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3059 ifp->if_capenable |= IFCAP_POLLING; 3060 XL_UNLOCK(sc); 3061 } else { 3062 error = ether_poll_deregister(ifp); 3063 /* Enable interrupts. */ 3064 XL_LOCK(sc); 3065 CSR_WRITE_2(sc, XL_COMMAND, 3066 XL_CMD_INTR_ACK | 0xFF); 3067 CSR_WRITE_2(sc, XL_COMMAND, 3068 XL_CMD_INTR_ENB | XL_INTRS); 3069 if (sc->xl_flags & XL_FLAG_FUNCREG) 3070 bus_space_write_4(sc->xl_ftag, 3071 sc->xl_fhandle, 4, 0x8000); 3072 XL_UNLOCK(sc); 3073 } 3074 } 3075 #endif /* DEVICE_POLLING */ 3076 XL_LOCK(sc); 3077 if ((mask & IFCAP_TXCSUM) != 0 && 3078 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3079 ifp->if_capenable ^= IFCAP_TXCSUM; 3080 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3081 ifp->if_hwassist |= XL905B_CSUM_FEATURES; 3082 else 3083 ifp->if_hwassist &= ~XL905B_CSUM_FEATURES; 3084 } 3085 if ((mask & IFCAP_RXCSUM) != 0 && 3086 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3087 ifp->if_capenable ^= IFCAP_RXCSUM; 3088 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3089 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3090 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3091 XL_UNLOCK(sc); 3092 break; 3093 default: 3094 error = ether_ioctl(ifp, command, data); 3095 break; 3096 } 3097 3098 return (error); 3099 } 3100 3101 static int 3102 xl_watchdog(struct xl_softc *sc) 3103 { 3104 struct ifnet *ifp = sc->xl_ifp; 3105 u_int16_t status = 0; 3106 int misintr; 3107 3108 XL_LOCK_ASSERT(sc); 3109 3110 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) 3111 return (0); 3112 3113 xl_rxeof(sc); 3114 xl_txeoc(sc); 3115 misintr = 0; 3116 if (sc->xl_type == XL_TYPE_905B) { 3117 xl_txeof_90xB(sc); 3118 if (sc->xl_cdata.xl_tx_cnt == 0) 3119 misintr++; 3120 } else { 3121 xl_txeof(sc); 3122 if (sc->xl_cdata.xl_tx_head == NULL) 3123 misintr++; 3124 } 3125 if (misintr != 0) { 3126 device_printf(sc->xl_dev, 3127 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 3128 return (0); 3129 } 3130 3131 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3132 XL_SEL_WIN(4); 3133 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3134 device_printf(sc->xl_dev, "watchdog timeout\n"); 3135 3136 if (status & XL_MEDIASTAT_CARRIER) 3137 device_printf(sc->xl_dev, 3138 "no carrier - transceiver cable problem?\n"); 3139 3140 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3141 xl_init_locked(sc); 3142 3143 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 3144 if (sc->xl_type == XL_TYPE_905B) 3145 xl_start_90xB_locked(ifp); 3146 else 3147 xl_start_locked(ifp); 3148 } 3149 3150 return (EJUSTRETURN); 3151 } 3152 3153 /* 3154 * Stop the adapter and free any mbufs allocated to the 3155 * RX and TX lists. 3156 */ 3157 static void 3158 xl_stop(struct xl_softc *sc) 3159 { 3160 int i; 3161 struct ifnet *ifp = sc->xl_ifp; 3162 3163 XL_LOCK_ASSERT(sc); 3164 3165 sc->xl_wdog_timer = 0; 3166 3167 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3168 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3169 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3170 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3171 xl_wait(sc); 3172 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3173 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3174 DELAY(800); 3175 3176 #ifdef foo 3177 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3178 xl_wait(sc); 3179 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3180 xl_wait(sc); 3181 #endif 3182 3183 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3184 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3185 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3186 if (sc->xl_flags & XL_FLAG_FUNCREG) 3187 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3188 3189 /* Stop the stats updater. */ 3190 callout_stop(&sc->xl_tick_callout); 3191 3192 /* 3193 * Free data in the RX lists. 3194 */ 3195 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3196 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3197 bus_dmamap_unload(sc->xl_mtag, 3198 sc->xl_cdata.xl_rx_chain[i].xl_map); 3199 bus_dmamap_destroy(sc->xl_mtag, 3200 sc->xl_cdata.xl_rx_chain[i].xl_map); 3201 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3202 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3203 } 3204 } 3205 if (sc->xl_ldata.xl_rx_list != NULL) 3206 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3207 /* 3208 * Free the TX list buffers. 3209 */ 3210 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3211 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3212 bus_dmamap_unload(sc->xl_mtag, 3213 sc->xl_cdata.xl_tx_chain[i].xl_map); 3214 bus_dmamap_destroy(sc->xl_mtag, 3215 sc->xl_cdata.xl_tx_chain[i].xl_map); 3216 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3217 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3218 } 3219 } 3220 if (sc->xl_ldata.xl_tx_list != NULL) 3221 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3222 3223 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3224 } 3225 3226 /* 3227 * Stop all chip I/O so that the kernel's probe routines don't 3228 * get confused by errant DMAs when rebooting. 3229 */ 3230 static int 3231 xl_shutdown(device_t dev) 3232 { 3233 3234 return (xl_suspend(dev)); 3235 } 3236 3237 static int 3238 xl_suspend(device_t dev) 3239 { 3240 struct xl_softc *sc; 3241 3242 sc = device_get_softc(dev); 3243 3244 XL_LOCK(sc); 3245 xl_stop(sc); 3246 xl_setwol(sc); 3247 XL_UNLOCK(sc); 3248 3249 return (0); 3250 } 3251 3252 static int 3253 xl_resume(device_t dev) 3254 { 3255 struct xl_softc *sc; 3256 struct ifnet *ifp; 3257 3258 sc = device_get_softc(dev); 3259 ifp = sc->xl_ifp; 3260 3261 XL_LOCK(sc); 3262 3263 if (ifp->if_flags & IFF_UP) { 3264 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3265 xl_init_locked(sc); 3266 } 3267 3268 XL_UNLOCK(sc); 3269 3270 return (0); 3271 } 3272 3273 static void 3274 xl_setwol(struct xl_softc *sc) 3275 { 3276 struct ifnet *ifp; 3277 u_int16_t cfg, pmstat; 3278 3279 if ((sc->xl_flags & XL_FLAG_WOL) == 0) 3280 return; 3281 3282 ifp = sc->xl_ifp; 3283 XL_SEL_WIN(7); 3284 /* Clear any pending PME events. */ 3285 CSR_READ_2(sc, XL_W7_BM_PME); 3286 cfg = 0; 3287 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3288 cfg |= XL_BM_PME_MAGIC; 3289 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg); 3290 /* Enable RX. */ 3291 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3292 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 3293 /* Request PME. */ 3294 pmstat = pci_read_config(sc->xl_dev, 3295 sc->xl_pmcap + PCIR_POWER_STATUS, 2); 3296 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3297 pmstat |= PCIM_PSTAT_PMEENABLE; 3298 else 3299 pmstat &= ~PCIM_PSTAT_PMEENABLE; 3300 pci_write_config(sc->xl_dev, 3301 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2); 3302 } 3303