1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 /* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 */ 100 101 #ifdef HAVE_KERNEL_OPTION_HEADERS 102 #include "opt_device_polling.h" 103 #endif 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/sockio.h> 108 #include <sys/endian.h> 109 #include <sys/mbuf.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/taskqueue.h> 114 115 #include <net/if.h> 116 #include <net/if_var.h> 117 #include <net/if_arp.h> 118 #include <net/ethernet.h> 119 #include <net/if_dl.h> 120 #include <net/if_media.h> 121 #include <net/if_types.h> 122 123 #include <net/bpf.h> 124 125 #include <machine/bus.h> 126 #include <machine/resource.h> 127 #include <sys/bus.h> 128 #include <sys/rman.h> 129 130 #include <dev/mii/mii.h> 131 #include <dev/mii/mii_bitbang.h> 132 #include <dev/mii/miivar.h> 133 134 #include <dev/pci/pcireg.h> 135 #include <dev/pci/pcivar.h> 136 137 MODULE_DEPEND(xl, pci, 1, 1, 1); 138 MODULE_DEPEND(xl, ether, 1, 1, 1); 139 MODULE_DEPEND(xl, miibus, 1, 1, 1); 140 141 /* "device miibus" required. See GENERIC if you get errors here. */ 142 #include "miibus_if.h" 143 144 #include <dev/xl/if_xlreg.h> 145 146 /* 147 * TX Checksumming is disabled by default for two reasons: 148 * - TX Checksumming will occasionally produce corrupt packets 149 * - TX Checksumming seems to reduce performance 150 * 151 * Only 905B/C cards were reported to have this problem, it is possible 152 * that later chips _may_ be immune. 153 */ 154 #define XL905B_TXCSUM_BROKEN 1 155 156 #ifdef XL905B_TXCSUM_BROKEN 157 #define XL905B_CSUM_FEATURES 0 158 #else 159 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 160 #endif 161 162 /* 163 * Various supported device vendors/types and their names. 164 */ 165 static const struct xl_type xl_devs[] = { 166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 167 "3Com 3c900-TPO Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 169 "3Com 3c900-COMBO Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 171 "3Com 3c905-TX Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 173 "3Com 3c905-T4 Fast Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 175 "3Com 3c900B-TPO Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 177 "3Com 3c900B-COMBO Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 179 "3Com 3c900B-TPC Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 181 "3Com 3c900B-FL Etherlink XL" }, 182 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 183 "3Com 3c905B-TX Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 185 "3Com 3c905B-T4 Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 187 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 189 "3Com 3c905B-COMBO Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 191 "3Com 3c905C-TX Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 193 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 195 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 197 "3Com 3c980 Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 199 "3Com 3c980C Fast Etherlink XL" }, 200 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 201 "3Com 3cSOHO100-TX OfficeConnect" }, 202 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 203 "3Com 3c450-TX HomeConnect" }, 204 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 205 "3Com 3c555 Fast Etherlink XL" }, 206 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 207 "3Com 3c556 Fast Etherlink XL" }, 208 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 209 "3Com 3c556B Fast Etherlink XL" }, 210 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 211 "3Com 3c575TX Fast Etherlink XL" }, 212 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 213 "3Com 3c575B Fast Etherlink XL" }, 214 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 215 "3Com 3c575C Fast Etherlink XL" }, 216 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 217 "3Com 3c656 Fast Etherlink XL" }, 218 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 219 "3Com 3c656B Fast Etherlink XL" }, 220 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 221 "3Com 3c656C Fast Etherlink XL" }, 222 { 0, 0, NULL } 223 }; 224 225 static int xl_probe(device_t); 226 static int xl_attach(device_t); 227 static int xl_detach(device_t); 228 229 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 230 static void xl_tick(void *); 231 static void xl_stats_update(struct xl_softc *); 232 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); 233 static int xl_rxeof(struct xl_softc *); 234 static void xl_rxeof_task(void *, int); 235 static int xl_rx_resync(struct xl_softc *); 236 static void xl_txeof(struct xl_softc *); 237 static void xl_txeof_90xB(struct xl_softc *); 238 static void xl_txeoc(struct xl_softc *); 239 static void xl_intr(void *); 240 static void xl_start(struct ifnet *); 241 static void xl_start_locked(struct ifnet *); 242 static void xl_start_90xB_locked(struct ifnet *); 243 static int xl_ioctl(struct ifnet *, u_long, caddr_t); 244 static void xl_init(void *); 245 static void xl_init_locked(struct xl_softc *); 246 static void xl_stop(struct xl_softc *); 247 static int xl_watchdog(struct xl_softc *); 248 static int xl_shutdown(device_t); 249 static int xl_suspend(device_t); 250 static int xl_resume(device_t); 251 static void xl_setwol(struct xl_softc *); 252 253 #ifdef DEVICE_POLLING 254 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 255 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 256 #endif 257 258 static int xl_ifmedia_upd(struct ifnet *); 259 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 260 261 static int xl_eeprom_wait(struct xl_softc *); 262 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 263 264 static void xl_rxfilter(struct xl_softc *); 265 static void xl_rxfilter_90x(struct xl_softc *); 266 static void xl_rxfilter_90xB(struct xl_softc *); 267 static void xl_setcfg(struct xl_softc *); 268 static void xl_setmode(struct xl_softc *, int); 269 static void xl_reset(struct xl_softc *); 270 static int xl_list_rx_init(struct xl_softc *); 271 static int xl_list_tx_init(struct xl_softc *); 272 static int xl_list_tx_init_90xB(struct xl_softc *); 273 static void xl_wait(struct xl_softc *); 274 static void xl_mediacheck(struct xl_softc *); 275 static void xl_choose_media(struct xl_softc *sc, int *media); 276 static void xl_choose_xcvr(struct xl_softc *, int); 277 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 278 #ifdef notdef 279 static void xl_testpacket(struct xl_softc *); 280 #endif 281 282 static int xl_miibus_readreg(device_t, int, int); 283 static int xl_miibus_writereg(device_t, int, int, int); 284 static void xl_miibus_statchg(device_t); 285 static void xl_miibus_mediainit(device_t); 286 287 /* 288 * MII bit-bang glue 289 */ 290 static uint32_t xl_mii_bitbang_read(device_t); 291 static void xl_mii_bitbang_write(device_t, uint32_t); 292 293 static const struct mii_bitbang_ops xl_mii_bitbang_ops = { 294 xl_mii_bitbang_read, 295 xl_mii_bitbang_write, 296 { 297 XL_MII_DATA, /* MII_BIT_MDO */ 298 XL_MII_DATA, /* MII_BIT_MDI */ 299 XL_MII_CLK, /* MII_BIT_MDC */ 300 XL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 301 0, /* MII_BIT_DIR_PHY_HOST */ 302 } 303 }; 304 305 static device_method_t xl_methods[] = { 306 /* Device interface */ 307 DEVMETHOD(device_probe, xl_probe), 308 DEVMETHOD(device_attach, xl_attach), 309 DEVMETHOD(device_detach, xl_detach), 310 DEVMETHOD(device_shutdown, xl_shutdown), 311 DEVMETHOD(device_suspend, xl_suspend), 312 DEVMETHOD(device_resume, xl_resume), 313 314 /* MII interface */ 315 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 316 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 317 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 318 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 319 320 DEVMETHOD_END 321 }; 322 323 static driver_t xl_driver = { 324 "xl", 325 xl_methods, 326 sizeof(struct xl_softc) 327 }; 328 329 static devclass_t xl_devclass; 330 331 DRIVER_MODULE_ORDERED(xl, pci, xl_driver, xl_devclass, NULL, NULL, 332 SI_ORDER_ANY); 333 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, NULL, NULL); 334 335 static void 336 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 337 { 338 u_int32_t *paddr; 339 340 paddr = arg; 341 *paddr = segs->ds_addr; 342 } 343 344 /* 345 * Murphy's law says that it's possible the chip can wedge and 346 * the 'command in progress' bit may never clear. Hence, we wait 347 * only a finite amount of time to avoid getting caught in an 348 * infinite loop. Normally this delay routine would be a macro, 349 * but it isn't called during normal operation so we can afford 350 * to make it a function. Suppress warning when card gone. 351 */ 352 static void 353 xl_wait(struct xl_softc *sc) 354 { 355 register int i; 356 357 for (i = 0; i < XL_TIMEOUT; i++) { 358 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 359 break; 360 } 361 362 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev)) 363 device_printf(sc->xl_dev, "command never completed!\n"); 364 } 365 366 /* 367 * MII access routines are provided for adapters with external 368 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 369 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 370 * Note: if you don't perform the MDIO operations just right, 371 * it's possible to end up with code that works correctly with 372 * some chips/CPUs/processor speeds/bus speeds/etc but not 373 * with others. 374 */ 375 376 /* 377 * Read the MII serial port for the MII bit-bang module. 378 */ 379 static uint32_t 380 xl_mii_bitbang_read(device_t dev) 381 { 382 struct xl_softc *sc; 383 uint32_t val; 384 385 sc = device_get_softc(dev); 386 387 /* We're already in window 4. */ 388 val = CSR_READ_2(sc, XL_W4_PHY_MGMT); 389 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 390 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 391 392 return (val); 393 } 394 395 /* 396 * Write the MII serial port for the MII bit-bang module. 397 */ 398 static void 399 xl_mii_bitbang_write(device_t dev, uint32_t val) 400 { 401 struct xl_softc *sc; 402 403 sc = device_get_softc(dev); 404 405 /* We're already in window 4. */ 406 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val); 407 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 408 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 409 } 410 411 static int 412 xl_miibus_readreg(device_t dev, int phy, int reg) 413 { 414 struct xl_softc *sc; 415 416 sc = device_get_softc(dev); 417 418 /* Select the window 4. */ 419 XL_SEL_WIN(4); 420 421 return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg)); 422 } 423 424 static int 425 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 426 { 427 struct xl_softc *sc; 428 429 sc = device_get_softc(dev); 430 431 /* Select the window 4. */ 432 XL_SEL_WIN(4); 433 434 mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data); 435 436 return (0); 437 } 438 439 static void 440 xl_miibus_statchg(device_t dev) 441 { 442 struct xl_softc *sc; 443 struct mii_data *mii; 444 uint8_t macctl; 445 446 sc = device_get_softc(dev); 447 mii = device_get_softc(sc->xl_miibus); 448 449 xl_setcfg(sc); 450 451 /* Set ASIC's duplex mode to match the PHY. */ 452 XL_SEL_WIN(3); 453 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 454 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 455 macctl |= XL_MACCTRL_DUPLEX; 456 if (sc->xl_type == XL_TYPE_905B) { 457 if ((IFM_OPTIONS(mii->mii_media_active) & 458 IFM_ETH_RXPAUSE) != 0) 459 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB; 460 else 461 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 462 } 463 } else { 464 macctl &= ~XL_MACCTRL_DUPLEX; 465 if (sc->xl_type == XL_TYPE_905B) 466 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 467 } 468 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 469 } 470 471 /* 472 * Special support for the 3c905B-COMBO. This card has 10/100 support 473 * plus BNC and AUI ports. This means we will have both an miibus attached 474 * plus some non-MII media settings. In order to allow this, we have to 475 * add the extra media to the miibus's ifmedia struct, but we can't do 476 * that during xl_attach() because the miibus hasn't been attached yet. 477 * So instead, we wait until the miibus probe/attach is done, at which 478 * point we will get a callback telling is that it's safe to add our 479 * extra media. 480 */ 481 static void 482 xl_miibus_mediainit(device_t dev) 483 { 484 struct xl_softc *sc; 485 struct mii_data *mii; 486 struct ifmedia *ifm; 487 488 sc = device_get_softc(dev); 489 mii = device_get_softc(sc->xl_miibus); 490 ifm = &mii->mii_media; 491 492 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 493 /* 494 * Check for a 10baseFL board in disguise. 495 */ 496 if (sc->xl_type == XL_TYPE_905B && 497 sc->xl_media == XL_MEDIAOPT_10FL) { 498 if (bootverbose) 499 device_printf(sc->xl_dev, "found 10baseFL\n"); 500 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 501 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 502 NULL); 503 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 504 ifmedia_add(ifm, 505 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 506 } else { 507 if (bootverbose) 508 device_printf(sc->xl_dev, "found AUI\n"); 509 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 510 } 511 } 512 513 if (sc->xl_media & XL_MEDIAOPT_BNC) { 514 if (bootverbose) 515 device_printf(sc->xl_dev, "found BNC\n"); 516 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 517 } 518 } 519 520 /* 521 * The EEPROM is slow: give it time to come ready after issuing 522 * it a command. 523 */ 524 static int 525 xl_eeprom_wait(struct xl_softc *sc) 526 { 527 int i; 528 529 for (i = 0; i < 100; i++) { 530 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 531 DELAY(162); 532 else 533 break; 534 } 535 536 if (i == 100) { 537 device_printf(sc->xl_dev, "eeprom failed to come ready\n"); 538 return (1); 539 } 540 541 return (0); 542 } 543 544 /* 545 * Read a sequence of words from the EEPROM. Note that ethernet address 546 * data is stored in the EEPROM in network byte order. 547 */ 548 static int 549 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 550 { 551 int err = 0, i; 552 u_int16_t word = 0, *ptr; 553 554 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 555 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 556 /* 557 * XXX: WARNING! DANGER! 558 * It's easy to accidentally overwrite the rom content! 559 * Note: the 3c575 uses 8bit EEPROM offsets. 560 */ 561 XL_SEL_WIN(0); 562 563 if (xl_eeprom_wait(sc)) 564 return (1); 565 566 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 567 off += 0x30; 568 569 for (i = 0; i < cnt; i++) { 570 if (sc->xl_flags & XL_FLAG_8BITROM) 571 CSR_WRITE_2(sc, XL_W0_EE_CMD, 572 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 573 else 574 CSR_WRITE_2(sc, XL_W0_EE_CMD, 575 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 576 err = xl_eeprom_wait(sc); 577 if (err) 578 break; 579 word = CSR_READ_2(sc, XL_W0_EE_DATA); 580 ptr = (u_int16_t *)(dest + (i * 2)); 581 if (swap) 582 *ptr = ntohs(word); 583 else 584 *ptr = word; 585 } 586 587 return (err ? 1 : 0); 588 } 589 590 static void 591 xl_rxfilter(struct xl_softc *sc) 592 { 593 594 if (sc->xl_type == XL_TYPE_905B) 595 xl_rxfilter_90xB(sc); 596 else 597 xl_rxfilter_90x(sc); 598 } 599 600 /* 601 * NICs older than the 3c905B have only one multicast option, which 602 * is to enable reception of all multicast frames. 603 */ 604 static void 605 xl_rxfilter_90x(struct xl_softc *sc) 606 { 607 struct ifnet *ifp; 608 struct ifmultiaddr *ifma; 609 u_int8_t rxfilt; 610 611 XL_LOCK_ASSERT(sc); 612 613 ifp = sc->xl_ifp; 614 615 XL_SEL_WIN(5); 616 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 617 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 618 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL); 619 620 /* Set the individual bit to receive frames for this host only. */ 621 rxfilt |= XL_RXFILTER_INDIVIDUAL; 622 /* Set capture broadcast bit to capture broadcast frames. */ 623 if (ifp->if_flags & IFF_BROADCAST) 624 rxfilt |= XL_RXFILTER_BROADCAST; 625 626 /* If we want promiscuous mode, set the allframes bit. */ 627 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 628 if (ifp->if_flags & IFF_PROMISC) 629 rxfilt |= XL_RXFILTER_ALLFRAMES; 630 if (ifp->if_flags & IFF_ALLMULTI) 631 rxfilt |= XL_RXFILTER_ALLMULTI; 632 } else { 633 if_maddr_rlock(ifp); 634 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 635 if (ifma->ifma_addr->sa_family != AF_LINK) 636 continue; 637 rxfilt |= XL_RXFILTER_ALLMULTI; 638 break; 639 } 640 if_maddr_runlock(ifp); 641 } 642 643 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 644 XL_SEL_WIN(7); 645 } 646 647 /* 648 * 3c905B adapters have a hash filter that we can program. 649 */ 650 static void 651 xl_rxfilter_90xB(struct xl_softc *sc) 652 { 653 struct ifnet *ifp; 654 struct ifmultiaddr *ifma; 655 int i, mcnt; 656 u_int16_t h; 657 u_int8_t rxfilt; 658 659 XL_LOCK_ASSERT(sc); 660 661 ifp = sc->xl_ifp; 662 663 XL_SEL_WIN(5); 664 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 665 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 666 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL | 667 XL_RXFILTER_MULTIHASH); 668 669 /* Set the individual bit to receive frames for this host only. */ 670 rxfilt |= XL_RXFILTER_INDIVIDUAL; 671 /* Set capture broadcast bit to capture broadcast frames. */ 672 if (ifp->if_flags & IFF_BROADCAST) 673 rxfilt |= XL_RXFILTER_BROADCAST; 674 675 /* If we want promiscuous mode, set the allframes bit. */ 676 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 677 if (ifp->if_flags & IFF_PROMISC) 678 rxfilt |= XL_RXFILTER_ALLFRAMES; 679 if (ifp->if_flags & IFF_ALLMULTI) 680 rxfilt |= XL_RXFILTER_ALLMULTI; 681 } else { 682 /* First, zot all the existing hash bits. */ 683 for (i = 0; i < XL_HASHFILT_SIZE; i++) 684 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i); 685 686 /* Now program new ones. */ 687 mcnt = 0; 688 if_maddr_rlock(ifp); 689 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 690 if (ifma->ifma_addr->sa_family != AF_LINK) 691 continue; 692 /* 693 * Note: the 3c905B currently only supports a 64-bit 694 * hash table, which means we really only need 6 bits, 695 * but the manual indicates that future chip revisions 696 * will have a 256-bit hash table, hence the routine 697 * is set up to calculate 8 bits of position info in 698 * case we need it some day. 699 * Note II, The Sequel: _CURRENT_ versions of the 700 * 3c905B have a 256 bit hash table. This means we have 701 * to use all 8 bits regardless. On older cards, the 702 * upper 2 bits will be ignored. Grrrr.... 703 */ 704 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 705 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 706 CSR_WRITE_2(sc, XL_COMMAND, 707 h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 708 mcnt++; 709 } 710 if_maddr_runlock(ifp); 711 if (mcnt > 0) 712 rxfilt |= XL_RXFILTER_MULTIHASH; 713 } 714 715 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 716 XL_SEL_WIN(7); 717 } 718 719 static void 720 xl_setcfg(struct xl_softc *sc) 721 { 722 u_int32_t icfg; 723 724 /*XL_LOCK_ASSERT(sc);*/ 725 726 XL_SEL_WIN(3); 727 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 728 icfg &= ~XL_ICFG_CONNECTOR_MASK; 729 if (sc->xl_media & XL_MEDIAOPT_MII || 730 sc->xl_media & XL_MEDIAOPT_BT4) 731 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 732 if (sc->xl_media & XL_MEDIAOPT_BTX) 733 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 734 735 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 736 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 737 } 738 739 static void 740 xl_setmode(struct xl_softc *sc, int media) 741 { 742 u_int32_t icfg; 743 u_int16_t mediastat; 744 char *pmsg = "", *dmsg = ""; 745 746 XL_LOCK_ASSERT(sc); 747 748 XL_SEL_WIN(4); 749 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 750 XL_SEL_WIN(3); 751 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 752 753 if (sc->xl_media & XL_MEDIAOPT_BT) { 754 if (IFM_SUBTYPE(media) == IFM_10_T) { 755 pmsg = "10baseT transceiver"; 756 sc->xl_xcvr = XL_XCVR_10BT; 757 icfg &= ~XL_ICFG_CONNECTOR_MASK; 758 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 759 mediastat |= XL_MEDIASTAT_LINKBEAT | 760 XL_MEDIASTAT_JABGUARD; 761 mediastat &= ~XL_MEDIASTAT_SQEENB; 762 } 763 } 764 765 if (sc->xl_media & XL_MEDIAOPT_BFX) { 766 if (IFM_SUBTYPE(media) == IFM_100_FX) { 767 pmsg = "100baseFX port"; 768 sc->xl_xcvr = XL_XCVR_100BFX; 769 icfg &= ~XL_ICFG_CONNECTOR_MASK; 770 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 771 mediastat |= XL_MEDIASTAT_LINKBEAT; 772 mediastat &= ~XL_MEDIASTAT_SQEENB; 773 } 774 } 775 776 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 777 if (IFM_SUBTYPE(media) == IFM_10_5) { 778 pmsg = "AUI port"; 779 sc->xl_xcvr = XL_XCVR_AUI; 780 icfg &= ~XL_ICFG_CONNECTOR_MASK; 781 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 782 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 783 XL_MEDIASTAT_JABGUARD); 784 mediastat |= ~XL_MEDIASTAT_SQEENB; 785 } 786 if (IFM_SUBTYPE(media) == IFM_10_FL) { 787 pmsg = "10baseFL transceiver"; 788 sc->xl_xcvr = XL_XCVR_AUI; 789 icfg &= ~XL_ICFG_CONNECTOR_MASK; 790 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 791 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 792 XL_MEDIASTAT_JABGUARD); 793 mediastat |= ~XL_MEDIASTAT_SQEENB; 794 } 795 } 796 797 if (sc->xl_media & XL_MEDIAOPT_BNC) { 798 if (IFM_SUBTYPE(media) == IFM_10_2) { 799 pmsg = "AUI port"; 800 sc->xl_xcvr = XL_XCVR_COAX; 801 icfg &= ~XL_ICFG_CONNECTOR_MASK; 802 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 803 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 804 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 805 } 806 } 807 808 if ((media & IFM_GMASK) == IFM_FDX || 809 IFM_SUBTYPE(media) == IFM_100_FX) { 810 dmsg = "full"; 811 XL_SEL_WIN(3); 812 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 813 } else { 814 dmsg = "half"; 815 XL_SEL_WIN(3); 816 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 817 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 818 } 819 820 if (IFM_SUBTYPE(media) == IFM_10_2) 821 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 822 else 823 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 824 825 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 826 XL_SEL_WIN(4); 827 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 828 829 DELAY(800); 830 XL_SEL_WIN(7); 831 832 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg); 833 } 834 835 static void 836 xl_reset(struct xl_softc *sc) 837 { 838 register int i; 839 840 XL_LOCK_ASSERT(sc); 841 842 XL_SEL_WIN(0); 843 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 844 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 845 XL_RESETOPT_DISADVFD:0)); 846 847 /* 848 * If we're using memory mapped register mode, pause briefly 849 * after issuing the reset command before trying to access any 850 * other registers. With my 3c575C CardBus card, failing to do 851 * this results in the system locking up while trying to poll 852 * the command busy bit in the status register. 853 */ 854 if (sc->xl_flags & XL_FLAG_USE_MMIO) 855 DELAY(100000); 856 857 for (i = 0; i < XL_TIMEOUT; i++) { 858 DELAY(10); 859 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 860 break; 861 } 862 863 if (i == XL_TIMEOUT) 864 device_printf(sc->xl_dev, "reset didn't complete\n"); 865 866 /* Reset TX and RX. */ 867 /* Note: the RX reset takes an absurd amount of time 868 * on newer versions of the Tornado chips such as those 869 * on the 3c905CX and newer 3c908C cards. We wait an 870 * extra amount of time so that xl_wait() doesn't complain 871 * and annoy the users. 872 */ 873 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 874 DELAY(100000); 875 xl_wait(sc); 876 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 877 xl_wait(sc); 878 879 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 880 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 881 XL_SEL_WIN(2); 882 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 883 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 884 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 885 XL_RESETOPT_INVERT_LED : 0) | 886 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 887 XL_RESETOPT_INVERT_MII : 0)); 888 } 889 890 /* Wait a little while for the chip to get its brains in order. */ 891 DELAY(100000); 892 } 893 894 /* 895 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 896 * IDs against our list and return a device name if we find a match. 897 */ 898 static int 899 xl_probe(device_t dev) 900 { 901 const struct xl_type *t; 902 903 t = xl_devs; 904 905 while (t->xl_name != NULL) { 906 if ((pci_get_vendor(dev) == t->xl_vid) && 907 (pci_get_device(dev) == t->xl_did)) { 908 device_set_desc(dev, t->xl_name); 909 return (BUS_PROBE_DEFAULT); 910 } 911 t++; 912 } 913 914 return (ENXIO); 915 } 916 917 /* 918 * This routine is a kludge to work around possible hardware faults 919 * or manufacturing defects that can cause the media options register 920 * (or reset options register, as it's called for the first generation 921 * 3c90x adapters) to return an incorrect result. I have encountered 922 * one Dell Latitude laptop docking station with an integrated 3c905-TX 923 * which doesn't have any of the 'mediaopt' bits set. This screws up 924 * the attach routine pretty badly because it doesn't know what media 925 * to look for. If we find ourselves in this predicament, this routine 926 * will try to guess the media options values and warn the user of a 927 * possible manufacturing defect with his adapter/system/whatever. 928 */ 929 static void 930 xl_mediacheck(struct xl_softc *sc) 931 { 932 933 /* 934 * If some of the media options bits are set, assume they are 935 * correct. If not, try to figure it out down below. 936 * XXX I should check for 10baseFL, but I don't have an adapter 937 * to test with. 938 */ 939 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 940 /* 941 * Check the XCVR value. If it's not in the normal range 942 * of values, we need to fake it up here. 943 */ 944 if (sc->xl_xcvr <= XL_XCVR_AUTO) 945 return; 946 else { 947 device_printf(sc->xl_dev, 948 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 949 device_printf(sc->xl_dev, 950 "choosing new default based on card type\n"); 951 } 952 } else { 953 if (sc->xl_type == XL_TYPE_905B && 954 sc->xl_media & XL_MEDIAOPT_10FL) 955 return; 956 device_printf(sc->xl_dev, 957 "WARNING: no media options bits set in the media options register!!\n"); 958 device_printf(sc->xl_dev, 959 "this could be a manufacturing defect in your adapter or system\n"); 960 device_printf(sc->xl_dev, 961 "attempting to guess media type; you should probably consult your vendor\n"); 962 } 963 964 xl_choose_xcvr(sc, 1); 965 } 966 967 static void 968 xl_choose_xcvr(struct xl_softc *sc, int verbose) 969 { 970 u_int16_t devid; 971 972 /* 973 * Read the device ID from the EEPROM. 974 * This is what's loaded into the PCI device ID register, so it has 975 * to be correct otherwise we wouldn't have gotten this far. 976 */ 977 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 978 979 switch (devid) { 980 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 981 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 982 sc->xl_media = XL_MEDIAOPT_BT; 983 sc->xl_xcvr = XL_XCVR_10BT; 984 if (verbose) 985 device_printf(sc->xl_dev, 986 "guessing 10BaseT transceiver\n"); 987 break; 988 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 989 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 990 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 991 sc->xl_xcvr = XL_XCVR_10BT; 992 if (verbose) 993 device_printf(sc->xl_dev, 994 "guessing COMBO (AUI/BNC/TP)\n"); 995 break; 996 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 997 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 998 sc->xl_xcvr = XL_XCVR_10BT; 999 if (verbose) 1000 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n"); 1001 break; 1002 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1003 sc->xl_media = XL_MEDIAOPT_10FL; 1004 sc->xl_xcvr = XL_XCVR_AUI; 1005 if (verbose) 1006 device_printf(sc->xl_dev, "guessing 10baseFL\n"); 1007 break; 1008 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1009 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1010 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1011 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1012 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1013 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1014 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1015 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1016 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1017 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1018 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1019 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1020 sc->xl_media = XL_MEDIAOPT_MII; 1021 sc->xl_xcvr = XL_XCVR_MII; 1022 if (verbose) 1023 device_printf(sc->xl_dev, "guessing MII\n"); 1024 break; 1025 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1026 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1027 sc->xl_media = XL_MEDIAOPT_BT4; 1028 sc->xl_xcvr = XL_XCVR_MII; 1029 if (verbose) 1030 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n"); 1031 break; 1032 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1033 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1034 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1035 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1036 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1037 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1038 sc->xl_media = XL_MEDIAOPT_BTX; 1039 sc->xl_xcvr = XL_XCVR_AUTO; 1040 if (verbose) 1041 device_printf(sc->xl_dev, "guessing 10/100 internal\n"); 1042 break; 1043 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1044 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1045 sc->xl_xcvr = XL_XCVR_AUTO; 1046 if (verbose) 1047 device_printf(sc->xl_dev, 1048 "guessing 10/100 plus BNC/AUI\n"); 1049 break; 1050 default: 1051 device_printf(sc->xl_dev, 1052 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1053 sc->xl_media = XL_MEDIAOPT_BT; 1054 break; 1055 } 1056 } 1057 1058 /* 1059 * Attach the interface. Allocate softc structures, do ifmedia 1060 * setup and ethernet/BPF attach. 1061 */ 1062 static int 1063 xl_attach(device_t dev) 1064 { 1065 u_char eaddr[ETHER_ADDR_LEN]; 1066 u_int16_t sinfo2, xcvr[2]; 1067 struct xl_softc *sc; 1068 struct ifnet *ifp; 1069 int media, pmcap; 1070 int error = 0, phy, rid, res, unit; 1071 uint16_t did; 1072 1073 sc = device_get_softc(dev); 1074 sc->xl_dev = dev; 1075 1076 unit = device_get_unit(dev); 1077 1078 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1079 MTX_DEF); 1080 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1081 1082 did = pci_get_device(dev); 1083 1084 sc->xl_flags = 0; 1085 if (did == TC_DEVICEID_HURRICANE_555) 1086 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1087 if (did == TC_DEVICEID_HURRICANE_556 || 1088 did == TC_DEVICEID_HURRICANE_556B) 1089 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1090 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1091 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1092 if (did == TC_DEVICEID_HURRICANE_555 || 1093 did == TC_DEVICEID_HURRICANE_556) 1094 sc->xl_flags |= XL_FLAG_8BITROM; 1095 if (did == TC_DEVICEID_HURRICANE_556B) 1096 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1097 1098 if (did == TC_DEVICEID_HURRICANE_575B || 1099 did == TC_DEVICEID_HURRICANE_575C || 1100 did == TC_DEVICEID_HURRICANE_656B || 1101 did == TC_DEVICEID_TORNADO_656C) 1102 sc->xl_flags |= XL_FLAG_FUNCREG; 1103 if (did == TC_DEVICEID_HURRICANE_575A || 1104 did == TC_DEVICEID_HURRICANE_575B || 1105 did == TC_DEVICEID_HURRICANE_575C || 1106 did == TC_DEVICEID_HURRICANE_656B || 1107 did == TC_DEVICEID_TORNADO_656C) 1108 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1109 XL_FLAG_8BITROM; 1110 if (did == TC_DEVICEID_HURRICANE_656) 1111 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1112 if (did == TC_DEVICEID_HURRICANE_575B) 1113 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1114 if (did == TC_DEVICEID_HURRICANE_575C) 1115 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1116 if (did == TC_DEVICEID_TORNADO_656C) 1117 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1118 if (did == TC_DEVICEID_HURRICANE_656 || 1119 did == TC_DEVICEID_HURRICANE_656B) 1120 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1121 XL_FLAG_INVERT_LED_PWR; 1122 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1123 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1124 sc->xl_flags |= XL_FLAG_PHYOK; 1125 1126 switch (did) { 1127 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1128 case TC_DEVICEID_HURRICANE_575A: 1129 case TC_DEVICEID_HURRICANE_575B: 1130 case TC_DEVICEID_HURRICANE_575C: 1131 sc->xl_flags |= XL_FLAG_NO_MMIO; 1132 break; 1133 default: 1134 break; 1135 } 1136 1137 /* 1138 * Map control/status registers. 1139 */ 1140 pci_enable_busmaster(dev); 1141 1142 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1143 rid = XL_PCI_LOMEM; 1144 res = SYS_RES_MEMORY; 1145 1146 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1147 } 1148 1149 if (sc->xl_res != NULL) { 1150 sc->xl_flags |= XL_FLAG_USE_MMIO; 1151 if (bootverbose) 1152 device_printf(dev, "using memory mapped I/O\n"); 1153 } else { 1154 rid = XL_PCI_LOIO; 1155 res = SYS_RES_IOPORT; 1156 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1157 if (sc->xl_res == NULL) { 1158 device_printf(dev, "couldn't map ports/memory\n"); 1159 error = ENXIO; 1160 goto fail; 1161 } 1162 if (bootverbose) 1163 device_printf(dev, "using port I/O\n"); 1164 } 1165 1166 sc->xl_btag = rman_get_bustag(sc->xl_res); 1167 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1168 1169 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1170 rid = XL_PCI_FUNCMEM; 1171 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1172 RF_ACTIVE); 1173 1174 if (sc->xl_fres == NULL) { 1175 device_printf(dev, "couldn't map funcreg memory\n"); 1176 error = ENXIO; 1177 goto fail; 1178 } 1179 1180 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1181 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1182 } 1183 1184 /* Allocate interrupt */ 1185 rid = 0; 1186 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1187 RF_SHAREABLE | RF_ACTIVE); 1188 if (sc->xl_irq == NULL) { 1189 device_printf(dev, "couldn't map interrupt\n"); 1190 error = ENXIO; 1191 goto fail; 1192 } 1193 1194 /* Initialize interface name. */ 1195 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1196 if (ifp == NULL) { 1197 device_printf(dev, "can not if_alloc()\n"); 1198 error = ENOSPC; 1199 goto fail; 1200 } 1201 ifp->if_softc = sc; 1202 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1203 1204 /* Reset the adapter. */ 1205 XL_LOCK(sc); 1206 xl_reset(sc); 1207 XL_UNLOCK(sc); 1208 1209 /* 1210 * Get station address from the EEPROM. 1211 */ 1212 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1213 device_printf(dev, "failed to read station address\n"); 1214 error = ENXIO; 1215 goto fail; 1216 } 1217 1218 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0); 1219 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1220 1221 /* 1222 * Now allocate a tag for the DMA descriptor lists and a chunk 1223 * of DMA-able memory based on the tag. Also obtain the DMA 1224 * addresses of the RX and TX ring, which we'll need later. 1225 * All of our lists are allocated as a contiguous block 1226 * of memory. 1227 */ 1228 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1229 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1230 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1231 &sc->xl_ldata.xl_rx_tag); 1232 if (error) { 1233 device_printf(dev, "failed to allocate rx dma tag\n"); 1234 goto fail; 1235 } 1236 1237 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1238 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | 1239 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap); 1240 if (error) { 1241 device_printf(dev, "no memory for rx list buffers!\n"); 1242 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1243 sc->xl_ldata.xl_rx_tag = NULL; 1244 goto fail; 1245 } 1246 1247 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1248 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1249 XL_RX_LIST_SZ, xl_dma_map_addr, 1250 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1251 if (error) { 1252 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1253 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1254 sc->xl_ldata.xl_rx_dmamap); 1255 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1256 sc->xl_ldata.xl_rx_tag = NULL; 1257 goto fail; 1258 } 1259 1260 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1261 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1262 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1263 &sc->xl_ldata.xl_tx_tag); 1264 if (error) { 1265 device_printf(dev, "failed to allocate tx dma tag\n"); 1266 goto fail; 1267 } 1268 1269 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1270 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | 1271 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap); 1272 if (error) { 1273 device_printf(dev, "no memory for list buffers!\n"); 1274 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1275 sc->xl_ldata.xl_tx_tag = NULL; 1276 goto fail; 1277 } 1278 1279 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1280 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1281 XL_TX_LIST_SZ, xl_dma_map_addr, 1282 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1283 if (error) { 1284 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1285 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1286 sc->xl_ldata.xl_tx_dmamap); 1287 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1288 sc->xl_ldata.xl_tx_tag = NULL; 1289 goto fail; 1290 } 1291 1292 /* 1293 * Allocate a DMA tag for the mapping of mbufs. 1294 */ 1295 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1296 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1297 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1298 NULL, &sc->xl_mtag); 1299 if (error) { 1300 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1301 goto fail; 1302 } 1303 1304 /* We need a spare DMA map for the RX ring. */ 1305 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1306 if (error) 1307 goto fail; 1308 1309 /* 1310 * Figure out the card type. 3c905B adapters have the 1311 * 'supportsNoTxLength' bit set in the capabilities 1312 * word in the EEPROM. 1313 * Note: my 3c575C CardBus card lies. It returns a value 1314 * of 0x1578 for its capabilities word, which is somewhat 1315 * nonsensical. Another way to distinguish a 3c90x chip 1316 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1317 * bit. This will only be set for 3c90x boomerage chips. 1318 */ 1319 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1320 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1321 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1322 sc->xl_type = XL_TYPE_905B; 1323 else 1324 sc->xl_type = XL_TYPE_90X; 1325 1326 /* Check availability of WOL. */ 1327 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 && 1328 pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) { 1329 sc->xl_pmcap = pmcap; 1330 sc->xl_flags |= XL_FLAG_WOL; 1331 sinfo2 = 0; 1332 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0); 1333 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose) 1334 device_printf(dev, 1335 "No auxiliary remote wakeup connector!\n"); 1336 } 1337 1338 /* Set the TX start threshold for best performance. */ 1339 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1340 1341 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1342 ifp->if_ioctl = xl_ioctl; 1343 ifp->if_capabilities = IFCAP_VLAN_MTU; 1344 if (sc->xl_type == XL_TYPE_905B) { 1345 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1346 #ifdef XL905B_TXCSUM_BROKEN 1347 ifp->if_capabilities |= IFCAP_RXCSUM; 1348 #else 1349 ifp->if_capabilities |= IFCAP_HWCSUM; 1350 #endif 1351 } 1352 if ((sc->xl_flags & XL_FLAG_WOL) != 0) 1353 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1354 ifp->if_capenable = ifp->if_capabilities; 1355 #ifdef DEVICE_POLLING 1356 ifp->if_capabilities |= IFCAP_POLLING; 1357 #endif 1358 ifp->if_start = xl_start; 1359 ifp->if_init = xl_init; 1360 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1361 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1; 1362 IFQ_SET_READY(&ifp->if_snd); 1363 1364 /* 1365 * Now we have to see what sort of media we have. 1366 * This includes probing for an MII interace and a 1367 * possible PHY. 1368 */ 1369 XL_SEL_WIN(3); 1370 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1371 if (bootverbose) 1372 device_printf(dev, "media options word: %x\n", sc->xl_media); 1373 1374 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1375 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1376 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1377 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1378 1379 xl_mediacheck(sc); 1380 1381 if (sc->xl_media & XL_MEDIAOPT_MII || 1382 sc->xl_media & XL_MEDIAOPT_BTX || 1383 sc->xl_media & XL_MEDIAOPT_BT4) { 1384 if (bootverbose) 1385 device_printf(dev, "found MII/AUTO\n"); 1386 xl_setcfg(sc); 1387 /* 1388 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK. 1389 * This is to guard against problems with certain 3Com ASIC 1390 * revisions that incorrectly map the internal transceiver 1391 * control registers at all MII addresses. 1392 */ 1393 phy = MII_PHY_ANY; 1394 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0) 1395 phy = 24; 1396 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd, 1397 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 1398 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0); 1399 if (error != 0) { 1400 device_printf(dev, "attaching PHYs failed\n"); 1401 goto fail; 1402 } 1403 goto done; 1404 } 1405 1406 /* 1407 * Sanity check. If the user has selected "auto" and this isn't 1408 * a 10/100 card of some kind, we need to force the transceiver 1409 * type to something sane. 1410 */ 1411 if (sc->xl_xcvr == XL_XCVR_AUTO) 1412 xl_choose_xcvr(sc, bootverbose); 1413 1414 /* 1415 * Do ifmedia setup. 1416 */ 1417 if (sc->xl_media & XL_MEDIAOPT_BT) { 1418 if (bootverbose) 1419 device_printf(dev, "found 10baseT\n"); 1420 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1421 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1422 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1423 ifmedia_add(&sc->ifmedia, 1424 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1425 } 1426 1427 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1428 /* 1429 * Check for a 10baseFL board in disguise. 1430 */ 1431 if (sc->xl_type == XL_TYPE_905B && 1432 sc->xl_media == XL_MEDIAOPT_10FL) { 1433 if (bootverbose) 1434 device_printf(dev, "found 10baseFL\n"); 1435 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1436 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1437 0, NULL); 1438 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1439 ifmedia_add(&sc->ifmedia, 1440 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1441 } else { 1442 if (bootverbose) 1443 device_printf(dev, "found AUI\n"); 1444 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1445 } 1446 } 1447 1448 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1449 if (bootverbose) 1450 device_printf(dev, "found BNC\n"); 1451 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1452 } 1453 1454 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1455 if (bootverbose) 1456 device_printf(dev, "found 100baseFX\n"); 1457 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1458 } 1459 1460 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1461 xl_choose_media(sc, &media); 1462 1463 if (sc->xl_miibus == NULL) 1464 ifmedia_set(&sc->ifmedia, media); 1465 1466 done: 1467 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1468 XL_SEL_WIN(0); 1469 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1470 } 1471 1472 /* 1473 * Call MI attach routine. 1474 */ 1475 ether_ifattach(ifp, eaddr); 1476 1477 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1478 NULL, xl_intr, sc, &sc->xl_intrhand); 1479 if (error) { 1480 device_printf(dev, "couldn't set up irq\n"); 1481 ether_ifdetach(ifp); 1482 goto fail; 1483 } 1484 1485 fail: 1486 if (error) 1487 xl_detach(dev); 1488 1489 return (error); 1490 } 1491 1492 /* 1493 * Choose a default media. 1494 * XXX This is a leaf function only called by xl_attach() and 1495 * acquires/releases the non-recursible driver mutex to 1496 * satisfy lock assertions. 1497 */ 1498 static void 1499 xl_choose_media(struct xl_softc *sc, int *media) 1500 { 1501 1502 XL_LOCK(sc); 1503 1504 switch (sc->xl_xcvr) { 1505 case XL_XCVR_10BT: 1506 *media = IFM_ETHER|IFM_10_T; 1507 xl_setmode(sc, *media); 1508 break; 1509 case XL_XCVR_AUI: 1510 if (sc->xl_type == XL_TYPE_905B && 1511 sc->xl_media == XL_MEDIAOPT_10FL) { 1512 *media = IFM_ETHER|IFM_10_FL; 1513 xl_setmode(sc, *media); 1514 } else { 1515 *media = IFM_ETHER|IFM_10_5; 1516 xl_setmode(sc, *media); 1517 } 1518 break; 1519 case XL_XCVR_COAX: 1520 *media = IFM_ETHER|IFM_10_2; 1521 xl_setmode(sc, *media); 1522 break; 1523 case XL_XCVR_AUTO: 1524 case XL_XCVR_100BTX: 1525 case XL_XCVR_MII: 1526 /* Chosen by miibus */ 1527 break; 1528 case XL_XCVR_100BFX: 1529 *media = IFM_ETHER|IFM_100_FX; 1530 break; 1531 default: 1532 device_printf(sc->xl_dev, "unknown XCVR type: %d\n", 1533 sc->xl_xcvr); 1534 /* 1535 * This will probably be wrong, but it prevents 1536 * the ifmedia code from panicking. 1537 */ 1538 *media = IFM_ETHER|IFM_10_T; 1539 break; 1540 } 1541 1542 XL_UNLOCK(sc); 1543 } 1544 1545 /* 1546 * Shutdown hardware and free up resources. This can be called any 1547 * time after the mutex has been initialized. It is called in both 1548 * the error case in attach and the normal detach case so it needs 1549 * to be careful about only freeing resources that have actually been 1550 * allocated. 1551 */ 1552 static int 1553 xl_detach(device_t dev) 1554 { 1555 struct xl_softc *sc; 1556 struct ifnet *ifp; 1557 int rid, res; 1558 1559 sc = device_get_softc(dev); 1560 ifp = sc->xl_ifp; 1561 1562 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1563 1564 #ifdef DEVICE_POLLING 1565 if (ifp && ifp->if_capenable & IFCAP_POLLING) 1566 ether_poll_deregister(ifp); 1567 #endif 1568 1569 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1570 rid = XL_PCI_LOMEM; 1571 res = SYS_RES_MEMORY; 1572 } else { 1573 rid = XL_PCI_LOIO; 1574 res = SYS_RES_IOPORT; 1575 } 1576 1577 /* These should only be active if attach succeeded */ 1578 if (device_is_attached(dev)) { 1579 XL_LOCK(sc); 1580 xl_stop(sc); 1581 XL_UNLOCK(sc); 1582 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1583 callout_drain(&sc->xl_tick_callout); 1584 ether_ifdetach(ifp); 1585 } 1586 if (sc->xl_miibus) 1587 device_delete_child(dev, sc->xl_miibus); 1588 bus_generic_detach(dev); 1589 ifmedia_removeall(&sc->ifmedia); 1590 1591 if (sc->xl_intrhand) 1592 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1593 if (sc->xl_irq) 1594 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1595 if (sc->xl_fres != NULL) 1596 bus_release_resource(dev, SYS_RES_MEMORY, 1597 XL_PCI_FUNCMEM, sc->xl_fres); 1598 if (sc->xl_res) 1599 bus_release_resource(dev, res, rid, sc->xl_res); 1600 1601 if (ifp) 1602 if_free(ifp); 1603 1604 if (sc->xl_mtag) { 1605 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1606 bus_dma_tag_destroy(sc->xl_mtag); 1607 } 1608 if (sc->xl_ldata.xl_rx_tag) { 1609 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1610 sc->xl_ldata.xl_rx_dmamap); 1611 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1612 sc->xl_ldata.xl_rx_dmamap); 1613 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1614 } 1615 if (sc->xl_ldata.xl_tx_tag) { 1616 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1617 sc->xl_ldata.xl_tx_dmamap); 1618 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1619 sc->xl_ldata.xl_tx_dmamap); 1620 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1621 } 1622 1623 mtx_destroy(&sc->xl_mtx); 1624 1625 return (0); 1626 } 1627 1628 /* 1629 * Initialize the transmit descriptors. 1630 */ 1631 static int 1632 xl_list_tx_init(struct xl_softc *sc) 1633 { 1634 struct xl_chain_data *cd; 1635 struct xl_list_data *ld; 1636 int error, i; 1637 1638 XL_LOCK_ASSERT(sc); 1639 1640 cd = &sc->xl_cdata; 1641 ld = &sc->xl_ldata; 1642 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1643 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1644 error = bus_dmamap_create(sc->xl_mtag, 0, 1645 &cd->xl_tx_chain[i].xl_map); 1646 if (error) 1647 return (error); 1648 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1649 i * sizeof(struct xl_list); 1650 if (i == (XL_TX_LIST_CNT - 1)) 1651 cd->xl_tx_chain[i].xl_next = NULL; 1652 else 1653 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1654 } 1655 1656 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1657 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1658 1659 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1660 return (0); 1661 } 1662 1663 /* 1664 * Initialize the transmit descriptors. 1665 */ 1666 static int 1667 xl_list_tx_init_90xB(struct xl_softc *sc) 1668 { 1669 struct xl_chain_data *cd; 1670 struct xl_list_data *ld; 1671 int error, i; 1672 1673 XL_LOCK_ASSERT(sc); 1674 1675 cd = &sc->xl_cdata; 1676 ld = &sc->xl_ldata; 1677 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1678 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1679 error = bus_dmamap_create(sc->xl_mtag, 0, 1680 &cd->xl_tx_chain[i].xl_map); 1681 if (error) 1682 return (error); 1683 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1684 i * sizeof(struct xl_list); 1685 if (i == (XL_TX_LIST_CNT - 1)) 1686 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1687 else 1688 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1689 if (i == 0) 1690 cd->xl_tx_chain[i].xl_prev = 1691 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1692 else 1693 cd->xl_tx_chain[i].xl_prev = 1694 &cd->xl_tx_chain[i - 1]; 1695 } 1696 1697 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1698 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1699 1700 cd->xl_tx_prod = 1; 1701 cd->xl_tx_cons = 1; 1702 cd->xl_tx_cnt = 0; 1703 1704 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1705 return (0); 1706 } 1707 1708 /* 1709 * Initialize the RX descriptors and allocate mbufs for them. Note that 1710 * we arrange the descriptors in a closed ring, so that the last descriptor 1711 * points back to the first. 1712 */ 1713 static int 1714 xl_list_rx_init(struct xl_softc *sc) 1715 { 1716 struct xl_chain_data *cd; 1717 struct xl_list_data *ld; 1718 int error, i, next; 1719 u_int32_t nextptr; 1720 1721 XL_LOCK_ASSERT(sc); 1722 1723 cd = &sc->xl_cdata; 1724 ld = &sc->xl_ldata; 1725 1726 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1727 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1728 error = bus_dmamap_create(sc->xl_mtag, 0, 1729 &cd->xl_rx_chain[i].xl_map); 1730 if (error) 1731 return (error); 1732 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1733 if (error) 1734 return (error); 1735 if (i == (XL_RX_LIST_CNT - 1)) 1736 next = 0; 1737 else 1738 next = i + 1; 1739 nextptr = ld->xl_rx_dmaaddr + 1740 next * sizeof(struct xl_list_onefrag); 1741 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1742 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1743 } 1744 1745 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1746 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1747 1748 return (0); 1749 } 1750 1751 /* 1752 * Initialize an RX descriptor and attach an MBUF cluster. 1753 * If we fail to do so, we need to leave the old mbuf and 1754 * the old DMA map untouched so that it can be reused. 1755 */ 1756 static int 1757 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1758 { 1759 struct mbuf *m_new = NULL; 1760 bus_dmamap_t map; 1761 bus_dma_segment_t segs[1]; 1762 int error, nseg; 1763 1764 XL_LOCK_ASSERT(sc); 1765 1766 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1767 if (m_new == NULL) 1768 return (ENOBUFS); 1769 1770 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1771 1772 /* Force longword alignment for packet payload. */ 1773 m_adj(m_new, ETHER_ALIGN); 1774 1775 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, 1776 segs, &nseg, BUS_DMA_NOWAIT); 1777 if (error) { 1778 m_freem(m_new); 1779 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", 1780 error); 1781 return (error); 1782 } 1783 KASSERT(nseg == 1, 1784 ("%s: too many DMA segments (%d)", __func__, nseg)); 1785 1786 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1787 map = c->xl_map; 1788 c->xl_map = sc->xl_tmpmap; 1789 sc->xl_tmpmap = map; 1790 c->xl_mbuf = m_new; 1791 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1792 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); 1793 c->xl_ptr->xl_status = 0; 1794 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1795 return (0); 1796 } 1797 1798 static int 1799 xl_rx_resync(struct xl_softc *sc) 1800 { 1801 struct xl_chain_onefrag *pos; 1802 int i; 1803 1804 XL_LOCK_ASSERT(sc); 1805 1806 pos = sc->xl_cdata.xl_rx_head; 1807 1808 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1809 if (pos->xl_ptr->xl_status) 1810 break; 1811 pos = pos->xl_next; 1812 } 1813 1814 if (i == XL_RX_LIST_CNT) 1815 return (0); 1816 1817 sc->xl_cdata.xl_rx_head = pos; 1818 1819 return (EAGAIN); 1820 } 1821 1822 /* 1823 * A frame has been uploaded: pass the resulting mbuf chain up to 1824 * the higher level protocols. 1825 */ 1826 static int 1827 xl_rxeof(struct xl_softc *sc) 1828 { 1829 struct mbuf *m; 1830 struct ifnet *ifp = sc->xl_ifp; 1831 struct xl_chain_onefrag *cur_rx; 1832 int total_len; 1833 int rx_npkts = 0; 1834 u_int32_t rxstat; 1835 1836 XL_LOCK_ASSERT(sc); 1837 again: 1838 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1839 BUS_DMASYNC_POSTREAD); 1840 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1841 #ifdef DEVICE_POLLING 1842 if (ifp->if_capenable & IFCAP_POLLING) { 1843 if (sc->rxcycles <= 0) 1844 break; 1845 sc->rxcycles--; 1846 } 1847 #endif 1848 cur_rx = sc->xl_cdata.xl_rx_head; 1849 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1850 total_len = rxstat & XL_RXSTAT_LENMASK; 1851 rx_npkts++; 1852 1853 /* 1854 * Since we have told the chip to allow large frames, 1855 * we need to trap giant frame errors in software. We allow 1856 * a little more than the normal frame size to account for 1857 * frames with VLAN tags. 1858 */ 1859 if (total_len > XL_MAX_FRAMELEN) 1860 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1861 1862 /* 1863 * If an error occurs, update stats, clear the 1864 * status word and leave the mbuf cluster in place: 1865 * it should simply get re-used next time this descriptor 1866 * comes up in the ring. 1867 */ 1868 if (rxstat & XL_RXSTAT_UP_ERROR) { 1869 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1870 cur_rx->xl_ptr->xl_status = 0; 1871 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1872 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1873 continue; 1874 } 1875 1876 /* 1877 * If the error bit was not set, the upload complete 1878 * bit should be set which means we have a valid packet. 1879 * If not, something truly strange has happened. 1880 */ 1881 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1882 device_printf(sc->xl_dev, 1883 "bad receive status -- packet dropped\n"); 1884 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1885 cur_rx->xl_ptr->xl_status = 0; 1886 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1887 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1888 continue; 1889 } 1890 1891 /* No errors; receive the packet. */ 1892 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 1893 BUS_DMASYNC_POSTREAD); 1894 m = cur_rx->xl_mbuf; 1895 1896 /* 1897 * Try to conjure up a new mbuf cluster. If that 1898 * fails, it means we have an out of memory condition and 1899 * should leave the buffer in place and continue. This will 1900 * result in a lost packet, but there's little else we 1901 * can do in this situation. 1902 */ 1903 if (xl_newbuf(sc, cur_rx)) { 1904 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1905 cur_rx->xl_ptr->xl_status = 0; 1906 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1907 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1908 continue; 1909 } 1910 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1911 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1912 1913 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1914 m->m_pkthdr.rcvif = ifp; 1915 m->m_pkthdr.len = m->m_len = total_len; 1916 1917 if (ifp->if_capenable & IFCAP_RXCSUM) { 1918 /* Do IP checksum checking. */ 1919 if (rxstat & XL_RXSTAT_IPCKOK) 1920 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1921 if (!(rxstat & XL_RXSTAT_IPCKERR)) 1922 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1923 if ((rxstat & XL_RXSTAT_TCPCOK && 1924 !(rxstat & XL_RXSTAT_TCPCKERR)) || 1925 (rxstat & XL_RXSTAT_UDPCKOK && 1926 !(rxstat & XL_RXSTAT_UDPCKERR))) { 1927 m->m_pkthdr.csum_flags |= 1928 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1929 m->m_pkthdr.csum_data = 0xffff; 1930 } 1931 } 1932 1933 XL_UNLOCK(sc); 1934 (*ifp->if_input)(ifp, m); 1935 XL_LOCK(sc); 1936 1937 /* 1938 * If we are running from the taskqueue, the interface 1939 * might have been stopped while we were passing the last 1940 * packet up the network stack. 1941 */ 1942 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1943 return (rx_npkts); 1944 } 1945 1946 /* 1947 * Handle the 'end of channel' condition. When the upload 1948 * engine hits the end of the RX ring, it will stall. This 1949 * is our cue to flush the RX ring, reload the uplist pointer 1950 * register and unstall the engine. 1951 * XXX This is actually a little goofy. With the ThunderLAN 1952 * chip, you get an interrupt when the receiver hits the end 1953 * of the receive ring, which tells you exactly when you 1954 * you need to reload the ring pointer. Here we have to 1955 * fake it. I'm mad at myself for not being clever enough 1956 * to avoid the use of a goto here. 1957 */ 1958 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 1959 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 1960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 1961 xl_wait(sc); 1962 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 1963 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 1964 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 1965 goto again; 1966 } 1967 return (rx_npkts); 1968 } 1969 1970 /* 1971 * Taskqueue wrapper for xl_rxeof(). 1972 */ 1973 static void 1974 xl_rxeof_task(void *arg, int pending) 1975 { 1976 struct xl_softc *sc = (struct xl_softc *)arg; 1977 1978 XL_LOCK(sc); 1979 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING) 1980 xl_rxeof(sc); 1981 XL_UNLOCK(sc); 1982 } 1983 1984 /* 1985 * A frame was downloaded to the chip. It's safe for us to clean up 1986 * the list buffers. 1987 */ 1988 static void 1989 xl_txeof(struct xl_softc *sc) 1990 { 1991 struct xl_chain *cur_tx; 1992 struct ifnet *ifp = sc->xl_ifp; 1993 1994 XL_LOCK_ASSERT(sc); 1995 1996 /* 1997 * Go through our tx list and free mbufs for those 1998 * frames that have been uploaded. Note: the 3c905B 1999 * sets a special bit in the status word to let us 2000 * know that a frame has been downloaded, but the 2001 * original 3c900/3c905 adapters don't do that. 2002 * Consequently, we have to use a different test if 2003 * xl_type != XL_TYPE_905B. 2004 */ 2005 while (sc->xl_cdata.xl_tx_head != NULL) { 2006 cur_tx = sc->xl_cdata.xl_tx_head; 2007 2008 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2009 break; 2010 2011 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2012 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2013 BUS_DMASYNC_POSTWRITE); 2014 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2015 m_freem(cur_tx->xl_mbuf); 2016 cur_tx->xl_mbuf = NULL; 2017 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2018 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2019 2020 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2021 sc->xl_cdata.xl_tx_free = cur_tx; 2022 } 2023 2024 if (sc->xl_cdata.xl_tx_head == NULL) { 2025 sc->xl_wdog_timer = 0; 2026 sc->xl_cdata.xl_tx_tail = NULL; 2027 } else { 2028 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2029 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2030 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2031 sc->xl_cdata.xl_tx_head->xl_phys); 2032 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2033 } 2034 } 2035 } 2036 2037 static void 2038 xl_txeof_90xB(struct xl_softc *sc) 2039 { 2040 struct xl_chain *cur_tx = NULL; 2041 struct ifnet *ifp = sc->xl_ifp; 2042 int idx; 2043 2044 XL_LOCK_ASSERT(sc); 2045 2046 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2047 BUS_DMASYNC_POSTREAD); 2048 idx = sc->xl_cdata.xl_tx_cons; 2049 while (idx != sc->xl_cdata.xl_tx_prod) { 2050 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2051 2052 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2053 XL_TXSTAT_DL_COMPLETE)) 2054 break; 2055 2056 if (cur_tx->xl_mbuf != NULL) { 2057 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2058 BUS_DMASYNC_POSTWRITE); 2059 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2060 m_freem(cur_tx->xl_mbuf); 2061 cur_tx->xl_mbuf = NULL; 2062 } 2063 2064 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2065 2066 sc->xl_cdata.xl_tx_cnt--; 2067 XL_INC(idx, XL_TX_LIST_CNT); 2068 } 2069 2070 if (sc->xl_cdata.xl_tx_cnt == 0) 2071 sc->xl_wdog_timer = 0; 2072 sc->xl_cdata.xl_tx_cons = idx; 2073 2074 if (cur_tx != NULL) 2075 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2076 } 2077 2078 /* 2079 * TX 'end of channel' interrupt handler. Actually, we should 2080 * only get a 'TX complete' interrupt if there's a transmit error, 2081 * so this is really TX error handler. 2082 */ 2083 static void 2084 xl_txeoc(struct xl_softc *sc) 2085 { 2086 u_int8_t txstat; 2087 2088 XL_LOCK_ASSERT(sc); 2089 2090 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2091 if (txstat & XL_TXSTATUS_UNDERRUN || 2092 txstat & XL_TXSTATUS_JABBER || 2093 txstat & XL_TXSTATUS_RECLAIM) { 2094 device_printf(sc->xl_dev, 2095 "transmission error: 0x%02x\n", txstat); 2096 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2097 xl_wait(sc); 2098 if (sc->xl_type == XL_TYPE_905B) { 2099 if (sc->xl_cdata.xl_tx_cnt) { 2100 int i; 2101 struct xl_chain *c; 2102 2103 i = sc->xl_cdata.xl_tx_cons; 2104 c = &sc->xl_cdata.xl_tx_chain[i]; 2105 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2106 c->xl_phys); 2107 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2108 sc->xl_wdog_timer = 5; 2109 } 2110 } else { 2111 if (sc->xl_cdata.xl_tx_head != NULL) { 2112 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2113 sc->xl_cdata.xl_tx_head->xl_phys); 2114 sc->xl_wdog_timer = 5; 2115 } 2116 } 2117 /* 2118 * Remember to set this for the 2119 * first generation 3c90X chips. 2120 */ 2121 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2122 if (txstat & XL_TXSTATUS_UNDERRUN && 2123 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2124 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2125 device_printf(sc->xl_dev, 2126 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2127 } 2128 CSR_WRITE_2(sc, XL_COMMAND, 2129 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2130 if (sc->xl_type == XL_TYPE_905B) { 2131 CSR_WRITE_2(sc, XL_COMMAND, 2132 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2133 } 2134 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2135 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2136 } else { 2137 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2138 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2139 } 2140 /* 2141 * Write an arbitrary byte to the TX_STATUS register 2142 * to clear this interrupt/error and advance to the next. 2143 */ 2144 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2145 } 2146 } 2147 2148 static void 2149 xl_intr(void *arg) 2150 { 2151 struct xl_softc *sc = arg; 2152 struct ifnet *ifp = sc->xl_ifp; 2153 u_int16_t status; 2154 2155 XL_LOCK(sc); 2156 2157 #ifdef DEVICE_POLLING 2158 if (ifp->if_capenable & IFCAP_POLLING) { 2159 XL_UNLOCK(sc); 2160 return; 2161 } 2162 #endif 2163 2164 for (;;) { 2165 status = CSR_READ_2(sc, XL_STATUS); 2166 if ((status & XL_INTRS) == 0 || status == 0xFFFF) 2167 break; 2168 CSR_WRITE_2(sc, XL_COMMAND, 2169 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2170 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2171 break; 2172 2173 if (status & XL_STAT_UP_COMPLETE) { 2174 if (xl_rxeof(sc) == 0) { 2175 while (xl_rx_resync(sc)) 2176 xl_rxeof(sc); 2177 } 2178 } 2179 2180 if (status & XL_STAT_DOWN_COMPLETE) { 2181 if (sc->xl_type == XL_TYPE_905B) 2182 xl_txeof_90xB(sc); 2183 else 2184 xl_txeof(sc); 2185 } 2186 2187 if (status & XL_STAT_TX_COMPLETE) { 2188 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2189 xl_txeoc(sc); 2190 } 2191 2192 if (status & XL_STAT_ADFAIL) { 2193 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2194 xl_init_locked(sc); 2195 break; 2196 } 2197 2198 if (status & XL_STAT_STATSOFLOW) 2199 xl_stats_update(sc); 2200 } 2201 2202 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2203 ifp->if_drv_flags & IFF_DRV_RUNNING) { 2204 if (sc->xl_type == XL_TYPE_905B) 2205 xl_start_90xB_locked(ifp); 2206 else 2207 xl_start_locked(ifp); 2208 } 2209 2210 XL_UNLOCK(sc); 2211 } 2212 2213 #ifdef DEVICE_POLLING 2214 static int 2215 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2216 { 2217 struct xl_softc *sc = ifp->if_softc; 2218 int rx_npkts = 0; 2219 2220 XL_LOCK(sc); 2221 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2222 rx_npkts = xl_poll_locked(ifp, cmd, count); 2223 XL_UNLOCK(sc); 2224 return (rx_npkts); 2225 } 2226 2227 static int 2228 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2229 { 2230 struct xl_softc *sc = ifp->if_softc; 2231 int rx_npkts; 2232 2233 XL_LOCK_ASSERT(sc); 2234 2235 sc->rxcycles = count; 2236 rx_npkts = xl_rxeof(sc); 2237 if (sc->xl_type == XL_TYPE_905B) 2238 xl_txeof_90xB(sc); 2239 else 2240 xl_txeof(sc); 2241 2242 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2243 if (sc->xl_type == XL_TYPE_905B) 2244 xl_start_90xB_locked(ifp); 2245 else 2246 xl_start_locked(ifp); 2247 } 2248 2249 if (cmd == POLL_AND_CHECK_STATUS) { 2250 u_int16_t status; 2251 2252 status = CSR_READ_2(sc, XL_STATUS); 2253 if (status & XL_INTRS && status != 0xFFFF) { 2254 CSR_WRITE_2(sc, XL_COMMAND, 2255 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2256 2257 if (status & XL_STAT_TX_COMPLETE) { 2258 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2259 xl_txeoc(sc); 2260 } 2261 2262 if (status & XL_STAT_ADFAIL) { 2263 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2264 xl_init_locked(sc); 2265 } 2266 2267 if (status & XL_STAT_STATSOFLOW) 2268 xl_stats_update(sc); 2269 } 2270 } 2271 return (rx_npkts); 2272 } 2273 #endif /* DEVICE_POLLING */ 2274 2275 static void 2276 xl_tick(void *xsc) 2277 { 2278 struct xl_softc *sc = xsc; 2279 struct mii_data *mii; 2280 2281 XL_LOCK_ASSERT(sc); 2282 2283 if (sc->xl_miibus != NULL) { 2284 mii = device_get_softc(sc->xl_miibus); 2285 mii_tick(mii); 2286 } 2287 2288 xl_stats_update(sc); 2289 if (xl_watchdog(sc) == EJUSTRETURN) 2290 return; 2291 2292 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc); 2293 } 2294 2295 static void 2296 xl_stats_update(struct xl_softc *sc) 2297 { 2298 struct ifnet *ifp = sc->xl_ifp; 2299 struct xl_stats xl_stats; 2300 u_int8_t *p; 2301 int i; 2302 2303 XL_LOCK_ASSERT(sc); 2304 2305 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2306 2307 p = (u_int8_t *)&xl_stats; 2308 2309 /* Read all the stats registers. */ 2310 XL_SEL_WIN(6); 2311 2312 for (i = 0; i < 16; i++) 2313 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2314 2315 if_inc_counter(ifp, IFCOUNTER_IERRORS, xl_stats.xl_rx_overrun); 2316 2317 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2318 xl_stats.xl_tx_multi_collision + 2319 xl_stats.xl_tx_single_collision + 2320 xl_stats.xl_tx_late_collision); 2321 2322 /* 2323 * Boomerang and cyclone chips have an extra stats counter 2324 * in window 4 (BadSSD). We have to read this too in order 2325 * to clear out all the stats registers and avoid a statsoflow 2326 * interrupt. 2327 */ 2328 XL_SEL_WIN(4); 2329 CSR_READ_1(sc, XL_W4_BADSSD); 2330 XL_SEL_WIN(7); 2331 } 2332 2333 /* 2334 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2335 * pointers to the fragment pointers. 2336 */ 2337 static int 2338 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) 2339 { 2340 struct mbuf *m_new; 2341 struct ifnet *ifp = sc->xl_ifp; 2342 int error, i, nseg, total_len; 2343 u_int32_t status; 2344 2345 XL_LOCK_ASSERT(sc); 2346 2347 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, 2348 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2349 2350 if (error && error != EFBIG) { 2351 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2352 return (error); 2353 } 2354 2355 /* 2356 * Handle special case: we used up all 63 fragments, 2357 * but we have more mbufs left in the chain. Copy the 2358 * data into an mbuf cluster. Note that we don't 2359 * bother clearing the values in the other fragment 2360 * pointers/counters; it wouldn't gain us anything, 2361 * and would waste cycles. 2362 */ 2363 if (error) { 2364 m_new = m_collapse(*m_head, M_NOWAIT, XL_MAXFRAGS); 2365 if (m_new == NULL) { 2366 m_freem(*m_head); 2367 *m_head = NULL; 2368 return (ENOBUFS); 2369 } 2370 *m_head = m_new; 2371 2372 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, 2373 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2374 if (error) { 2375 m_freem(*m_head); 2376 *m_head = NULL; 2377 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2378 return (error); 2379 } 2380 } 2381 2382 KASSERT(nseg <= XL_MAXFRAGS, 2383 ("%s: too many DMA segments (%d)", __func__, nseg)); 2384 if (nseg == 0) { 2385 m_freem(*m_head); 2386 *m_head = NULL; 2387 return (EIO); 2388 } 2389 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2390 2391 total_len = 0; 2392 for (i = 0; i < nseg; i++) { 2393 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, 2394 ("segment size too large")); 2395 c->xl_ptr->xl_frag[i].xl_addr = 2396 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); 2397 c->xl_ptr->xl_frag[i].xl_len = 2398 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); 2399 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; 2400 } 2401 c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG); 2402 2403 if (sc->xl_type == XL_TYPE_905B) { 2404 status = XL_TXSTAT_RND_DEFEAT; 2405 2406 #ifndef XL905B_TXCSUM_BROKEN 2407 if ((*m_head)->m_pkthdr.csum_flags) { 2408 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2409 status |= XL_TXSTAT_IPCKSUM; 2410 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2411 status |= XL_TXSTAT_TCPCKSUM; 2412 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2413 status |= XL_TXSTAT_UDPCKSUM; 2414 } 2415 #endif 2416 } else 2417 status = total_len; 2418 c->xl_ptr->xl_status = htole32(status); 2419 c->xl_ptr->xl_next = 0; 2420 2421 c->xl_mbuf = *m_head; 2422 return (0); 2423 } 2424 2425 /* 2426 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2427 * to the mbuf data regions directly in the transmit lists. We also save a 2428 * copy of the pointers since the transmit list fragment pointers are 2429 * physical addresses. 2430 */ 2431 2432 static void 2433 xl_start(struct ifnet *ifp) 2434 { 2435 struct xl_softc *sc = ifp->if_softc; 2436 2437 XL_LOCK(sc); 2438 2439 if (sc->xl_type == XL_TYPE_905B) 2440 xl_start_90xB_locked(ifp); 2441 else 2442 xl_start_locked(ifp); 2443 2444 XL_UNLOCK(sc); 2445 } 2446 2447 static void 2448 xl_start_locked(struct ifnet *ifp) 2449 { 2450 struct xl_softc *sc = ifp->if_softc; 2451 struct mbuf *m_head; 2452 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2453 struct xl_chain *prev_tx; 2454 int error; 2455 2456 XL_LOCK_ASSERT(sc); 2457 2458 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2459 IFF_DRV_RUNNING) 2460 return; 2461 /* 2462 * Check for an available queue slot. If there are none, 2463 * punt. 2464 */ 2465 if (sc->xl_cdata.xl_tx_free == NULL) { 2466 xl_txeoc(sc); 2467 xl_txeof(sc); 2468 if (sc->xl_cdata.xl_tx_free == NULL) { 2469 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2470 return; 2471 } 2472 } 2473 2474 start_tx = sc->xl_cdata.xl_tx_free; 2475 2476 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2477 sc->xl_cdata.xl_tx_free != NULL;) { 2478 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2479 if (m_head == NULL) 2480 break; 2481 2482 /* Pick a descriptor off the free list. */ 2483 prev_tx = cur_tx; 2484 cur_tx = sc->xl_cdata.xl_tx_free; 2485 2486 /* Pack the data into the descriptor. */ 2487 error = xl_encap(sc, cur_tx, &m_head); 2488 if (error) { 2489 cur_tx = prev_tx; 2490 if (m_head == NULL) 2491 break; 2492 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2493 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2494 break; 2495 } 2496 2497 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2498 cur_tx->xl_next = NULL; 2499 2500 /* Chain it together. */ 2501 if (prev != NULL) { 2502 prev->xl_next = cur_tx; 2503 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2504 } 2505 prev = cur_tx; 2506 2507 /* 2508 * If there's a BPF listener, bounce a copy of this frame 2509 * to him. 2510 */ 2511 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2512 } 2513 2514 /* 2515 * If there are no packets queued, bail. 2516 */ 2517 if (cur_tx == NULL) 2518 return; 2519 2520 /* 2521 * Place the request for the upload interrupt 2522 * in the last descriptor in the chain. This way, if 2523 * we're chaining several packets at once, we'll only 2524 * get an interrupt once for the whole chain rather than 2525 * once for each packet. 2526 */ 2527 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2528 2529 /* 2530 * Queue the packets. If the TX channel is clear, update 2531 * the downlist pointer register. 2532 */ 2533 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2534 xl_wait(sc); 2535 2536 if (sc->xl_cdata.xl_tx_head != NULL) { 2537 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2538 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2539 htole32(start_tx->xl_phys); 2540 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &= 2541 htole32(~XL_TXSTAT_DL_INTR); 2542 sc->xl_cdata.xl_tx_tail = cur_tx; 2543 } else { 2544 sc->xl_cdata.xl_tx_head = start_tx; 2545 sc->xl_cdata.xl_tx_tail = cur_tx; 2546 } 2547 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2548 BUS_DMASYNC_PREWRITE); 2549 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2550 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2551 2552 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2553 2554 XL_SEL_WIN(7); 2555 2556 /* 2557 * Set a timeout in case the chip goes out to lunch. 2558 */ 2559 sc->xl_wdog_timer = 5; 2560 2561 /* 2562 * XXX Under certain conditions, usually on slower machines 2563 * where interrupts may be dropped, it's possible for the 2564 * adapter to chew up all the buffers in the receive ring 2565 * and stall, without us being able to do anything about it. 2566 * To guard against this, we need to make a pass over the 2567 * RX queue to make sure there aren't any packets pending. 2568 * Doing it here means we can flush the receive ring at the 2569 * same time the chip is DMAing the transmit descriptors we 2570 * just gave it. 2571 * 2572 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2573 * nature of their chips in all their marketing literature; 2574 * we may as well take advantage of it. :) 2575 */ 2576 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2577 } 2578 2579 static void 2580 xl_start_90xB_locked(struct ifnet *ifp) 2581 { 2582 struct xl_softc *sc = ifp->if_softc; 2583 struct mbuf *m_head; 2584 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2585 struct xl_chain *prev_tx; 2586 int error, idx; 2587 2588 XL_LOCK_ASSERT(sc); 2589 2590 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2591 IFF_DRV_RUNNING) 2592 return; 2593 2594 idx = sc->xl_cdata.xl_tx_prod; 2595 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2596 2597 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2598 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { 2599 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2600 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2601 break; 2602 } 2603 2604 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2605 if (m_head == NULL) 2606 break; 2607 2608 prev_tx = cur_tx; 2609 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2610 2611 /* Pack the data into the descriptor. */ 2612 error = xl_encap(sc, cur_tx, &m_head); 2613 if (error) { 2614 cur_tx = prev_tx; 2615 if (m_head == NULL) 2616 break; 2617 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2618 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2619 break; 2620 } 2621 2622 /* Chain it together. */ 2623 if (prev != NULL) 2624 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2625 prev = cur_tx; 2626 2627 /* 2628 * If there's a BPF listener, bounce a copy of this frame 2629 * to him. 2630 */ 2631 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2632 2633 XL_INC(idx, XL_TX_LIST_CNT); 2634 sc->xl_cdata.xl_tx_cnt++; 2635 } 2636 2637 /* 2638 * If there are no packets queued, bail. 2639 */ 2640 if (cur_tx == NULL) 2641 return; 2642 2643 /* 2644 * Place the request for the upload interrupt 2645 * in the last descriptor in the chain. This way, if 2646 * we're chaining several packets at once, we'll only 2647 * get an interrupt once for the whole chain rather than 2648 * once for each packet. 2649 */ 2650 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2651 2652 /* Start transmission */ 2653 sc->xl_cdata.xl_tx_prod = idx; 2654 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2655 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2656 BUS_DMASYNC_PREWRITE); 2657 2658 /* 2659 * Set a timeout in case the chip goes out to lunch. 2660 */ 2661 sc->xl_wdog_timer = 5; 2662 } 2663 2664 static void 2665 xl_init(void *xsc) 2666 { 2667 struct xl_softc *sc = xsc; 2668 2669 XL_LOCK(sc); 2670 xl_init_locked(sc); 2671 XL_UNLOCK(sc); 2672 } 2673 2674 static void 2675 xl_init_locked(struct xl_softc *sc) 2676 { 2677 struct ifnet *ifp = sc->xl_ifp; 2678 int error, i; 2679 struct mii_data *mii = NULL; 2680 2681 XL_LOCK_ASSERT(sc); 2682 2683 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2684 return; 2685 /* 2686 * Cancel pending I/O and free all RX/TX buffers. 2687 */ 2688 xl_stop(sc); 2689 2690 /* Reset the chip to a known state. */ 2691 xl_reset(sc); 2692 2693 if (sc->xl_miibus == NULL) { 2694 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2695 xl_wait(sc); 2696 } 2697 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2698 xl_wait(sc); 2699 DELAY(10000); 2700 2701 if (sc->xl_miibus != NULL) 2702 mii = device_get_softc(sc->xl_miibus); 2703 2704 /* 2705 * Clear WOL status and disable all WOL feature as WOL 2706 * would interfere Rx operation under normal environments. 2707 */ 2708 if ((sc->xl_flags & XL_FLAG_WOL) != 0) { 2709 XL_SEL_WIN(7); 2710 CSR_READ_2(sc, XL_W7_BM_PME); 2711 CSR_WRITE_2(sc, XL_W7_BM_PME, 0); 2712 } 2713 /* Init our MAC address */ 2714 XL_SEL_WIN(2); 2715 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2716 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2717 IF_LLADDR(sc->xl_ifp)[i]); 2718 } 2719 2720 /* Clear the station mask. */ 2721 for (i = 0; i < 3; i++) 2722 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2723 #ifdef notdef 2724 /* Reset TX and RX. */ 2725 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2726 xl_wait(sc); 2727 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2728 xl_wait(sc); 2729 #endif 2730 /* Init circular RX list. */ 2731 error = xl_list_rx_init(sc); 2732 if (error) { 2733 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n", 2734 error); 2735 xl_stop(sc); 2736 return; 2737 } 2738 2739 /* Init TX descriptors. */ 2740 if (sc->xl_type == XL_TYPE_905B) 2741 error = xl_list_tx_init_90xB(sc); 2742 else 2743 error = xl_list_tx_init(sc); 2744 if (error) { 2745 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n", 2746 error); 2747 xl_stop(sc); 2748 return; 2749 } 2750 2751 /* 2752 * Set the TX freethresh value. 2753 * Note that this has no effect on 3c905B "cyclone" 2754 * cards but is required for 3c900/3c905 "boomerang" 2755 * cards in order to enable the download engine. 2756 */ 2757 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2758 2759 /* Set the TX start threshold for best performance. */ 2760 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2761 2762 /* 2763 * If this is a 3c905B, also set the tx reclaim threshold. 2764 * This helps cut down on the number of tx reclaim errors 2765 * that could happen on a busy network. The chip multiplies 2766 * the register value by 16 to obtain the actual threshold 2767 * in bytes, so we divide by 16 when setting the value here. 2768 * The existing threshold value can be examined by reading 2769 * the register at offset 9 in window 5. 2770 */ 2771 if (sc->xl_type == XL_TYPE_905B) { 2772 CSR_WRITE_2(sc, XL_COMMAND, 2773 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2774 } 2775 2776 /* Set RX filter bits. */ 2777 xl_rxfilter(sc); 2778 2779 /* 2780 * Load the address of the RX list. We have to 2781 * stall the upload engine before we can manipulate 2782 * the uplist pointer register, then unstall it when 2783 * we're finished. We also have to wait for the 2784 * stall command to complete before proceeding. 2785 * Note that we have to do this after any RX resets 2786 * have completed since the uplist register is cleared 2787 * by a reset. 2788 */ 2789 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2790 xl_wait(sc); 2791 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2792 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2793 xl_wait(sc); 2794 2795 if (sc->xl_type == XL_TYPE_905B) { 2796 /* Set polling interval */ 2797 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2798 /* Load the address of the TX list */ 2799 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2800 xl_wait(sc); 2801 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2802 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2803 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2804 xl_wait(sc); 2805 } 2806 2807 /* 2808 * If the coax transceiver is on, make sure to enable 2809 * the DC-DC converter. 2810 */ 2811 XL_SEL_WIN(3); 2812 if (sc->xl_xcvr == XL_XCVR_COAX) 2813 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2814 else 2815 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2816 2817 /* 2818 * increase packet size to allow reception of 802.1q or ISL packets. 2819 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2820 * control register. For 3c90xB/C chips, use the RX packet size 2821 * register. 2822 */ 2823 2824 if (sc->xl_type == XL_TYPE_905B) 2825 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2826 else { 2827 u_int8_t macctl; 2828 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2829 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2830 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2831 } 2832 2833 /* Clear out the stats counters. */ 2834 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2835 xl_stats_update(sc); 2836 XL_SEL_WIN(4); 2837 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2838 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2839 2840 /* 2841 * Enable interrupts. 2842 */ 2843 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2844 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2845 #ifdef DEVICE_POLLING 2846 /* Disable interrupts if we are polling. */ 2847 if (ifp->if_capenable & IFCAP_POLLING) 2848 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2849 else 2850 #endif 2851 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2852 if (sc->xl_flags & XL_FLAG_FUNCREG) 2853 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2854 2855 /* Set the RX early threshold */ 2856 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2857 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2858 2859 /* Enable receiver and transmitter. */ 2860 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2861 xl_wait(sc); 2862 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2863 xl_wait(sc); 2864 2865 /* XXX Downcall to miibus. */ 2866 if (mii != NULL) 2867 mii_mediachg(mii); 2868 2869 /* Select window 7 for normal operations. */ 2870 XL_SEL_WIN(7); 2871 2872 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2873 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2874 2875 sc->xl_wdog_timer = 0; 2876 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc); 2877 } 2878 2879 /* 2880 * Set media options. 2881 */ 2882 static int 2883 xl_ifmedia_upd(struct ifnet *ifp) 2884 { 2885 struct xl_softc *sc = ifp->if_softc; 2886 struct ifmedia *ifm = NULL; 2887 struct mii_data *mii = NULL; 2888 2889 XL_LOCK(sc); 2890 2891 if (sc->xl_miibus != NULL) 2892 mii = device_get_softc(sc->xl_miibus); 2893 if (mii == NULL) 2894 ifm = &sc->ifmedia; 2895 else 2896 ifm = &mii->mii_media; 2897 2898 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2899 case IFM_100_FX: 2900 case IFM_10_FL: 2901 case IFM_10_2: 2902 case IFM_10_5: 2903 xl_setmode(sc, ifm->ifm_media); 2904 XL_UNLOCK(sc); 2905 return (0); 2906 } 2907 2908 if (sc->xl_media & XL_MEDIAOPT_MII || 2909 sc->xl_media & XL_MEDIAOPT_BTX || 2910 sc->xl_media & XL_MEDIAOPT_BT4) { 2911 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2912 xl_init_locked(sc); 2913 } else { 2914 xl_setmode(sc, ifm->ifm_media); 2915 } 2916 2917 XL_UNLOCK(sc); 2918 2919 return (0); 2920 } 2921 2922 /* 2923 * Report current media status. 2924 */ 2925 static void 2926 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2927 { 2928 struct xl_softc *sc = ifp->if_softc; 2929 u_int32_t icfg; 2930 u_int16_t status = 0; 2931 struct mii_data *mii = NULL; 2932 2933 XL_LOCK(sc); 2934 2935 if (sc->xl_miibus != NULL) 2936 mii = device_get_softc(sc->xl_miibus); 2937 2938 XL_SEL_WIN(4); 2939 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 2940 2941 XL_SEL_WIN(3); 2942 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2943 icfg >>= XL_ICFG_CONNECTOR_BITS; 2944 2945 ifmr->ifm_active = IFM_ETHER; 2946 ifmr->ifm_status = IFM_AVALID; 2947 2948 if ((status & XL_MEDIASTAT_CARRIER) == 0) 2949 ifmr->ifm_status |= IFM_ACTIVE; 2950 2951 switch (icfg) { 2952 case XL_XCVR_10BT: 2953 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2954 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2955 ifmr->ifm_active |= IFM_FDX; 2956 else 2957 ifmr->ifm_active |= IFM_HDX; 2958 break; 2959 case XL_XCVR_AUI: 2960 if (sc->xl_type == XL_TYPE_905B && 2961 sc->xl_media == XL_MEDIAOPT_10FL) { 2962 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 2963 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2964 ifmr->ifm_active |= IFM_FDX; 2965 else 2966 ifmr->ifm_active |= IFM_HDX; 2967 } else 2968 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2969 break; 2970 case XL_XCVR_COAX: 2971 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 2972 break; 2973 /* 2974 * XXX MII and BTX/AUTO should be separate cases. 2975 */ 2976 2977 case XL_XCVR_100BTX: 2978 case XL_XCVR_AUTO: 2979 case XL_XCVR_MII: 2980 if (mii != NULL) { 2981 mii_pollstat(mii); 2982 ifmr->ifm_active = mii->mii_media_active; 2983 ifmr->ifm_status = mii->mii_media_status; 2984 } 2985 break; 2986 case XL_XCVR_100BFX: 2987 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 2988 break; 2989 default: 2990 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 2991 break; 2992 } 2993 2994 XL_UNLOCK(sc); 2995 } 2996 2997 static int 2998 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2999 { 3000 struct xl_softc *sc = ifp->if_softc; 3001 struct ifreq *ifr = (struct ifreq *) data; 3002 int error = 0, mask; 3003 struct mii_data *mii = NULL; 3004 3005 switch (command) { 3006 case SIOCSIFFLAGS: 3007 XL_LOCK(sc); 3008 if (ifp->if_flags & IFF_UP) { 3009 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3010 (ifp->if_flags ^ sc->xl_if_flags) & 3011 (IFF_PROMISC | IFF_ALLMULTI)) 3012 xl_rxfilter(sc); 3013 else 3014 xl_init_locked(sc); 3015 } else { 3016 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3017 xl_stop(sc); 3018 } 3019 sc->xl_if_flags = ifp->if_flags; 3020 XL_UNLOCK(sc); 3021 break; 3022 case SIOCADDMULTI: 3023 case SIOCDELMULTI: 3024 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3025 XL_LOCK(sc); 3026 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3027 xl_rxfilter(sc); 3028 XL_UNLOCK(sc); 3029 break; 3030 case SIOCGIFMEDIA: 3031 case SIOCSIFMEDIA: 3032 if (sc->xl_miibus != NULL) 3033 mii = device_get_softc(sc->xl_miibus); 3034 if (mii == NULL) 3035 error = ifmedia_ioctl(ifp, ifr, 3036 &sc->ifmedia, command); 3037 else 3038 error = ifmedia_ioctl(ifp, ifr, 3039 &mii->mii_media, command); 3040 break; 3041 case SIOCSIFCAP: 3042 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3043 #ifdef DEVICE_POLLING 3044 if ((mask & IFCAP_POLLING) != 0 && 3045 (ifp->if_capabilities & IFCAP_POLLING) != 0) { 3046 ifp->if_capenable ^= IFCAP_POLLING; 3047 if ((ifp->if_capenable & IFCAP_POLLING) != 0) { 3048 error = ether_poll_register(xl_poll, ifp); 3049 if (error) 3050 break; 3051 XL_LOCK(sc); 3052 /* Disable interrupts */ 3053 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3054 ifp->if_capenable |= IFCAP_POLLING; 3055 XL_UNLOCK(sc); 3056 } else { 3057 error = ether_poll_deregister(ifp); 3058 /* Enable interrupts. */ 3059 XL_LOCK(sc); 3060 CSR_WRITE_2(sc, XL_COMMAND, 3061 XL_CMD_INTR_ACK | 0xFF); 3062 CSR_WRITE_2(sc, XL_COMMAND, 3063 XL_CMD_INTR_ENB | XL_INTRS); 3064 if (sc->xl_flags & XL_FLAG_FUNCREG) 3065 bus_space_write_4(sc->xl_ftag, 3066 sc->xl_fhandle, 4, 0x8000); 3067 XL_UNLOCK(sc); 3068 } 3069 } 3070 #endif /* DEVICE_POLLING */ 3071 XL_LOCK(sc); 3072 if ((mask & IFCAP_TXCSUM) != 0 && 3073 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3074 ifp->if_capenable ^= IFCAP_TXCSUM; 3075 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3076 ifp->if_hwassist |= XL905B_CSUM_FEATURES; 3077 else 3078 ifp->if_hwassist &= ~XL905B_CSUM_FEATURES; 3079 } 3080 if ((mask & IFCAP_RXCSUM) != 0 && 3081 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3082 ifp->if_capenable ^= IFCAP_RXCSUM; 3083 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3084 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3085 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3086 XL_UNLOCK(sc); 3087 break; 3088 default: 3089 error = ether_ioctl(ifp, command, data); 3090 break; 3091 } 3092 3093 return (error); 3094 } 3095 3096 static int 3097 xl_watchdog(struct xl_softc *sc) 3098 { 3099 struct ifnet *ifp = sc->xl_ifp; 3100 u_int16_t status = 0; 3101 int misintr; 3102 3103 XL_LOCK_ASSERT(sc); 3104 3105 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) 3106 return (0); 3107 3108 xl_rxeof(sc); 3109 xl_txeoc(sc); 3110 misintr = 0; 3111 if (sc->xl_type == XL_TYPE_905B) { 3112 xl_txeof_90xB(sc); 3113 if (sc->xl_cdata.xl_tx_cnt == 0) 3114 misintr++; 3115 } else { 3116 xl_txeof(sc); 3117 if (sc->xl_cdata.xl_tx_head == NULL) 3118 misintr++; 3119 } 3120 if (misintr != 0) { 3121 device_printf(sc->xl_dev, 3122 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 3123 return (0); 3124 } 3125 3126 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3127 XL_SEL_WIN(4); 3128 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3129 device_printf(sc->xl_dev, "watchdog timeout\n"); 3130 3131 if (status & XL_MEDIASTAT_CARRIER) 3132 device_printf(sc->xl_dev, 3133 "no carrier - transceiver cable problem?\n"); 3134 3135 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3136 xl_init_locked(sc); 3137 3138 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 3139 if (sc->xl_type == XL_TYPE_905B) 3140 xl_start_90xB_locked(ifp); 3141 else 3142 xl_start_locked(ifp); 3143 } 3144 3145 return (EJUSTRETURN); 3146 } 3147 3148 /* 3149 * Stop the adapter and free any mbufs allocated to the 3150 * RX and TX lists. 3151 */ 3152 static void 3153 xl_stop(struct xl_softc *sc) 3154 { 3155 register int i; 3156 struct ifnet *ifp = sc->xl_ifp; 3157 3158 XL_LOCK_ASSERT(sc); 3159 3160 sc->xl_wdog_timer = 0; 3161 3162 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3163 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3164 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3166 xl_wait(sc); 3167 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3168 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3169 DELAY(800); 3170 3171 #ifdef foo 3172 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3173 xl_wait(sc); 3174 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3175 xl_wait(sc); 3176 #endif 3177 3178 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3179 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3180 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3181 if (sc->xl_flags & XL_FLAG_FUNCREG) 3182 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3183 3184 /* Stop the stats updater. */ 3185 callout_stop(&sc->xl_tick_callout); 3186 3187 /* 3188 * Free data in the RX lists. 3189 */ 3190 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3191 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3192 bus_dmamap_unload(sc->xl_mtag, 3193 sc->xl_cdata.xl_rx_chain[i].xl_map); 3194 bus_dmamap_destroy(sc->xl_mtag, 3195 sc->xl_cdata.xl_rx_chain[i].xl_map); 3196 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3197 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3198 } 3199 } 3200 if (sc->xl_ldata.xl_rx_list != NULL) 3201 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3202 /* 3203 * Free the TX list buffers. 3204 */ 3205 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3206 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3207 bus_dmamap_unload(sc->xl_mtag, 3208 sc->xl_cdata.xl_tx_chain[i].xl_map); 3209 bus_dmamap_destroy(sc->xl_mtag, 3210 sc->xl_cdata.xl_tx_chain[i].xl_map); 3211 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3212 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3213 } 3214 } 3215 if (sc->xl_ldata.xl_tx_list != NULL) 3216 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3217 3218 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3219 } 3220 3221 /* 3222 * Stop all chip I/O so that the kernel's probe routines don't 3223 * get confused by errant DMAs when rebooting. 3224 */ 3225 static int 3226 xl_shutdown(device_t dev) 3227 { 3228 3229 return (xl_suspend(dev)); 3230 } 3231 3232 static int 3233 xl_suspend(device_t dev) 3234 { 3235 struct xl_softc *sc; 3236 3237 sc = device_get_softc(dev); 3238 3239 XL_LOCK(sc); 3240 xl_stop(sc); 3241 xl_setwol(sc); 3242 XL_UNLOCK(sc); 3243 3244 return (0); 3245 } 3246 3247 static int 3248 xl_resume(device_t dev) 3249 { 3250 struct xl_softc *sc; 3251 struct ifnet *ifp; 3252 3253 sc = device_get_softc(dev); 3254 ifp = sc->xl_ifp; 3255 3256 XL_LOCK(sc); 3257 3258 if (ifp->if_flags & IFF_UP) { 3259 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3260 xl_init_locked(sc); 3261 } 3262 3263 XL_UNLOCK(sc); 3264 3265 return (0); 3266 } 3267 3268 static void 3269 xl_setwol(struct xl_softc *sc) 3270 { 3271 struct ifnet *ifp; 3272 u_int16_t cfg, pmstat; 3273 3274 if ((sc->xl_flags & XL_FLAG_WOL) == 0) 3275 return; 3276 3277 ifp = sc->xl_ifp; 3278 XL_SEL_WIN(7); 3279 /* Clear any pending PME events. */ 3280 CSR_READ_2(sc, XL_W7_BM_PME); 3281 cfg = 0; 3282 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3283 cfg |= XL_BM_PME_MAGIC; 3284 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg); 3285 /* Enable RX. */ 3286 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3287 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 3288 /* Request PME. */ 3289 pmstat = pci_read_config(sc->xl_dev, 3290 sc->xl_pmcap + PCIR_POWER_STATUS, 2); 3291 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3292 pmstat |= PCIM_PSTAT_PMEENABLE; 3293 else 3294 pmstat &= ~PCIM_PSTAT_PMEENABLE; 3295 pci_write_config(sc->xl_dev, 3296 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2); 3297 } 3298