1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 /* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 */ 100 101 #ifdef HAVE_KERNEL_OPTION_HEADERS 102 #include "opt_device_polling.h" 103 #endif 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/sockio.h> 108 #include <sys/endian.h> 109 #include <sys/mbuf.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/taskqueue.h> 114 115 #include <net/if.h> 116 #include <net/if_arp.h> 117 #include <net/ethernet.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 #include <net/if_types.h> 121 122 #include <net/bpf.h> 123 124 #include <machine/bus.h> 125 #include <machine/resource.h> 126 #include <sys/bus.h> 127 #include <sys/rman.h> 128 129 #include <dev/mii/mii.h> 130 #include <dev/mii/miivar.h> 131 132 #include <dev/pci/pcireg.h> 133 #include <dev/pci/pcivar.h> 134 135 MODULE_DEPEND(xl, pci, 1, 1, 1); 136 MODULE_DEPEND(xl, ether, 1, 1, 1); 137 MODULE_DEPEND(xl, miibus, 1, 1, 1); 138 139 /* "device miibus" required. See GENERIC if you get errors here. */ 140 #include "miibus_if.h" 141 142 #include <dev/xl/if_xlreg.h> 143 144 /* 145 * TX Checksumming is disabled by default for two reasons: 146 * - TX Checksumming will occasionally produce corrupt packets 147 * - TX Checksumming seems to reduce performance 148 * 149 * Only 905B/C cards were reported to have this problem, it is possible 150 * that later chips _may_ be immune. 151 */ 152 #define XL905B_TXCSUM_BROKEN 1 153 154 #ifdef XL905B_TXCSUM_BROKEN 155 #define XL905B_CSUM_FEATURES 0 156 #else 157 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 #endif 159 160 /* 161 * Various supported device vendors/types and their names. 162 */ 163 static const struct xl_type xl_devs[] = { 164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 165 "3Com 3c900-TPO Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 167 "3Com 3c900-COMBO Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 169 "3Com 3c905-TX Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 171 "3Com 3c905-T4 Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 173 "3Com 3c900B-TPO Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 175 "3Com 3c900B-COMBO Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 177 "3Com 3c900B-TPC Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 179 "3Com 3c900B-FL Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 181 "3Com 3c905B-TX Fast Etherlink XL" }, 182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 183 "3Com 3c905B-T4 Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 185 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 187 "3Com 3c905B-COMBO Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 189 "3Com 3c905C-TX Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 191 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 193 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 195 "3Com 3c980 Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 197 "3Com 3c980C Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 199 "3Com 3cSOHO100-TX OfficeConnect" }, 200 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 201 "3Com 3c450-TX HomeConnect" }, 202 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 203 "3Com 3c555 Fast Etherlink XL" }, 204 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 205 "3Com 3c556 Fast Etherlink XL" }, 206 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 207 "3Com 3c556B Fast Etherlink XL" }, 208 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 209 "3Com 3c575TX Fast Etherlink XL" }, 210 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 211 "3Com 3c575B Fast Etherlink XL" }, 212 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 213 "3Com 3c575C Fast Etherlink XL" }, 214 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 215 "3Com 3c656 Fast Etherlink XL" }, 216 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 217 "3Com 3c656B Fast Etherlink XL" }, 218 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 219 "3Com 3c656C Fast Etherlink XL" }, 220 { 0, 0, NULL } 221 }; 222 223 static int xl_probe(device_t); 224 static int xl_attach(device_t); 225 static int xl_detach(device_t); 226 227 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 228 static void xl_stats_update(void *); 229 static void xl_stats_update_locked(struct xl_softc *); 230 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); 231 static void xl_rxeof(struct xl_softc *); 232 static void xl_rxeof_task(void *, int); 233 static int xl_rx_resync(struct xl_softc *); 234 static void xl_txeof(struct xl_softc *); 235 static void xl_txeof_90xB(struct xl_softc *); 236 static void xl_txeoc(struct xl_softc *); 237 static void xl_intr(void *); 238 static void xl_start(struct ifnet *); 239 static void xl_start_locked(struct ifnet *); 240 static void xl_start_90xB_locked(struct ifnet *); 241 static int xl_ioctl(struct ifnet *, u_long, caddr_t); 242 static void xl_init(void *); 243 static void xl_init_locked(struct xl_softc *); 244 static void xl_stop(struct xl_softc *); 245 static int xl_watchdog(struct xl_softc *); 246 static int xl_shutdown(device_t); 247 static int xl_suspend(device_t); 248 static int xl_resume(device_t); 249 250 #ifdef DEVICE_POLLING 251 static void xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 252 static void xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 253 #endif 254 255 static int xl_ifmedia_upd(struct ifnet *); 256 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 257 258 static int xl_eeprom_wait(struct xl_softc *); 259 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 260 static void xl_mii_sync(struct xl_softc *); 261 static void xl_mii_send(struct xl_softc *, u_int32_t, int); 262 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *); 263 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *); 264 265 static void xl_setcfg(struct xl_softc *); 266 static void xl_setmode(struct xl_softc *, int); 267 static void xl_setmulti(struct xl_softc *); 268 static void xl_setmulti_hash(struct xl_softc *); 269 static void xl_reset(struct xl_softc *); 270 static int xl_list_rx_init(struct xl_softc *); 271 static int xl_list_tx_init(struct xl_softc *); 272 static int xl_list_tx_init_90xB(struct xl_softc *); 273 static void xl_wait(struct xl_softc *); 274 static void xl_mediacheck(struct xl_softc *); 275 static void xl_choose_media(struct xl_softc *sc, int *media); 276 static void xl_choose_xcvr(struct xl_softc *, int); 277 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 278 #ifdef notdef 279 static void xl_testpacket(struct xl_softc *); 280 #endif 281 282 static int xl_miibus_readreg(device_t, int, int); 283 static int xl_miibus_writereg(device_t, int, int, int); 284 static void xl_miibus_statchg(device_t); 285 static void xl_miibus_mediainit(device_t); 286 287 static device_method_t xl_methods[] = { 288 /* Device interface */ 289 DEVMETHOD(device_probe, xl_probe), 290 DEVMETHOD(device_attach, xl_attach), 291 DEVMETHOD(device_detach, xl_detach), 292 DEVMETHOD(device_shutdown, xl_shutdown), 293 DEVMETHOD(device_suspend, xl_suspend), 294 DEVMETHOD(device_resume, xl_resume), 295 296 /* bus interface */ 297 DEVMETHOD(bus_print_child, bus_generic_print_child), 298 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 299 300 /* MII interface */ 301 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 302 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 303 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 304 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 305 306 { 0, 0 } 307 }; 308 309 static driver_t xl_driver = { 310 "xl", 311 xl_methods, 312 sizeof(struct xl_softc) 313 }; 314 315 static devclass_t xl_devclass; 316 317 DRIVER_MODULE(xl, cardbus, xl_driver, xl_devclass, 0, 0); 318 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0); 319 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 320 321 static void 322 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 323 { 324 u_int32_t *paddr; 325 326 paddr = arg; 327 *paddr = segs->ds_addr; 328 } 329 330 /* 331 * Murphy's law says that it's possible the chip can wedge and 332 * the 'command in progress' bit may never clear. Hence, we wait 333 * only a finite amount of time to avoid getting caught in an 334 * infinite loop. Normally this delay routine would be a macro, 335 * but it isn't called during normal operation so we can afford 336 * to make it a function. 337 */ 338 static void 339 xl_wait(struct xl_softc *sc) 340 { 341 register int i; 342 343 for (i = 0; i < XL_TIMEOUT; i++) { 344 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 345 break; 346 } 347 348 if (i == XL_TIMEOUT) 349 device_printf(sc->xl_dev, "command never completed!\n"); 350 } 351 352 /* 353 * MII access routines are provided for adapters with external 354 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 355 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 356 * Note: if you don't perform the MDIO operations just right, 357 * it's possible to end up with code that works correctly with 358 * some chips/CPUs/processor speeds/bus speeds/etc but not 359 * with others. 360 */ 361 #define MII_SET(x) \ 362 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 363 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 364 365 #define MII_CLR(x) \ 366 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 367 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 368 369 /* 370 * Sync the PHYs by setting data bit and strobing the clock 32 times. 371 */ 372 static void 373 xl_mii_sync(struct xl_softc *sc) 374 { 375 register int i; 376 377 XL_SEL_WIN(4); 378 MII_SET(XL_MII_DIR|XL_MII_DATA); 379 380 for (i = 0; i < 32; i++) { 381 MII_SET(XL_MII_CLK); 382 MII_SET(XL_MII_DATA); 383 MII_SET(XL_MII_DATA); 384 MII_CLR(XL_MII_CLK); 385 MII_SET(XL_MII_DATA); 386 MII_SET(XL_MII_DATA); 387 } 388 } 389 390 /* 391 * Clock a series of bits through the MII. 392 */ 393 static void 394 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 395 { 396 int i; 397 398 XL_SEL_WIN(4); 399 MII_CLR(XL_MII_CLK); 400 401 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 402 if (bits & i) { 403 MII_SET(XL_MII_DATA); 404 } else { 405 MII_CLR(XL_MII_DATA); 406 } 407 MII_CLR(XL_MII_CLK); 408 MII_SET(XL_MII_CLK); 409 } 410 } 411 412 /* 413 * Read an PHY register through the MII. 414 */ 415 static int 416 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 417 { 418 int i, ack; 419 420 /* Set up frame for RX. */ 421 frame->mii_stdelim = XL_MII_STARTDELIM; 422 frame->mii_opcode = XL_MII_READOP; 423 frame->mii_turnaround = 0; 424 frame->mii_data = 0; 425 426 /* Select register window 4. */ 427 XL_SEL_WIN(4); 428 429 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 430 /* Turn on data xmit. */ 431 MII_SET(XL_MII_DIR); 432 433 xl_mii_sync(sc); 434 435 /* Send command/address info. */ 436 xl_mii_send(sc, frame->mii_stdelim, 2); 437 xl_mii_send(sc, frame->mii_opcode, 2); 438 xl_mii_send(sc, frame->mii_phyaddr, 5); 439 xl_mii_send(sc, frame->mii_regaddr, 5); 440 441 /* Idle bit */ 442 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 443 MII_SET(XL_MII_CLK); 444 445 /* Turn off xmit. */ 446 MII_CLR(XL_MII_DIR); 447 448 /* Check for ack */ 449 MII_CLR(XL_MII_CLK); 450 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 451 MII_SET(XL_MII_CLK); 452 453 /* 454 * Now try reading data bits. If the ack failed, we still 455 * need to clock through 16 cycles to keep the PHY(s) in sync. 456 */ 457 if (ack) { 458 for (i = 0; i < 16; i++) { 459 MII_CLR(XL_MII_CLK); 460 MII_SET(XL_MII_CLK); 461 } 462 goto fail; 463 } 464 465 for (i = 0x8000; i; i >>= 1) { 466 MII_CLR(XL_MII_CLK); 467 if (!ack) { 468 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 469 frame->mii_data |= i; 470 } 471 MII_SET(XL_MII_CLK); 472 } 473 474 fail: 475 MII_CLR(XL_MII_CLK); 476 MII_SET(XL_MII_CLK); 477 478 return (ack ? 1 : 0); 479 } 480 481 /* 482 * Write to a PHY register through the MII. 483 */ 484 static int 485 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 486 { 487 488 /* Set up frame for TX. */ 489 frame->mii_stdelim = XL_MII_STARTDELIM; 490 frame->mii_opcode = XL_MII_WRITEOP; 491 frame->mii_turnaround = XL_MII_TURNAROUND; 492 493 /* Select the window 4. */ 494 XL_SEL_WIN(4); 495 496 /* Turn on data output. */ 497 MII_SET(XL_MII_DIR); 498 499 xl_mii_sync(sc); 500 501 xl_mii_send(sc, frame->mii_stdelim, 2); 502 xl_mii_send(sc, frame->mii_opcode, 2); 503 xl_mii_send(sc, frame->mii_phyaddr, 5); 504 xl_mii_send(sc, frame->mii_regaddr, 5); 505 xl_mii_send(sc, frame->mii_turnaround, 2); 506 xl_mii_send(sc, frame->mii_data, 16); 507 508 /* Idle bit. */ 509 MII_SET(XL_MII_CLK); 510 MII_CLR(XL_MII_CLK); 511 512 /* Turn off xmit. */ 513 MII_CLR(XL_MII_DIR); 514 515 return (0); 516 } 517 518 static int 519 xl_miibus_readreg(device_t dev, int phy, int reg) 520 { 521 struct xl_softc *sc; 522 struct xl_mii_frame frame; 523 524 sc = device_get_softc(dev); 525 526 /* 527 * Pretend that PHYs are only available at MII address 24. 528 * This is to guard against problems with certain 3Com ASIC 529 * revisions that incorrectly map the internal transceiver 530 * control registers at all MII addresses. This can cause 531 * the miibus code to attach the same PHY several times over. 532 */ 533 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) 534 return (0); 535 536 bzero((char *)&frame, sizeof(frame)); 537 frame.mii_phyaddr = phy; 538 frame.mii_regaddr = reg; 539 540 xl_mii_readreg(sc, &frame); 541 542 return (frame.mii_data); 543 } 544 545 static int 546 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 547 { 548 struct xl_softc *sc; 549 struct xl_mii_frame frame; 550 551 sc = device_get_softc(dev); 552 553 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) 554 return (0); 555 556 bzero((char *)&frame, sizeof(frame)); 557 frame.mii_phyaddr = phy; 558 frame.mii_regaddr = reg; 559 frame.mii_data = data; 560 561 xl_mii_writereg(sc, &frame); 562 563 return (0); 564 } 565 566 static void 567 xl_miibus_statchg(device_t dev) 568 { 569 struct xl_softc *sc; 570 struct mii_data *mii; 571 572 sc = device_get_softc(dev); 573 mii = device_get_softc(sc->xl_miibus); 574 575 xl_setcfg(sc); 576 577 /* Set ASIC's duplex mode to match the PHY. */ 578 XL_SEL_WIN(3); 579 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 580 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 581 else 582 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 583 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 584 } 585 586 /* 587 * Special support for the 3c905B-COMBO. This card has 10/100 support 588 * plus BNC and AUI ports. This means we will have both an miibus attached 589 * plus some non-MII media settings. In order to allow this, we have to 590 * add the extra media to the miibus's ifmedia struct, but we can't do 591 * that during xl_attach() because the miibus hasn't been attached yet. 592 * So instead, we wait until the miibus probe/attach is done, at which 593 * point we will get a callback telling is that it's safe to add our 594 * extra media. 595 */ 596 static void 597 xl_miibus_mediainit(device_t dev) 598 { 599 struct xl_softc *sc; 600 struct mii_data *mii; 601 struct ifmedia *ifm; 602 603 sc = device_get_softc(dev); 604 mii = device_get_softc(sc->xl_miibus); 605 ifm = &mii->mii_media; 606 607 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 608 /* 609 * Check for a 10baseFL board in disguise. 610 */ 611 if (sc->xl_type == XL_TYPE_905B && 612 sc->xl_media == XL_MEDIAOPT_10FL) { 613 if (bootverbose) 614 device_printf(sc->xl_dev, "found 10baseFL\n"); 615 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 616 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 617 NULL); 618 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 619 ifmedia_add(ifm, 620 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 621 } else { 622 if (bootverbose) 623 device_printf(sc->xl_dev, "found AUI\n"); 624 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 625 } 626 } 627 628 if (sc->xl_media & XL_MEDIAOPT_BNC) { 629 if (bootverbose) 630 device_printf(sc->xl_dev, "found BNC\n"); 631 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 632 } 633 } 634 635 /* 636 * The EEPROM is slow: give it time to come ready after issuing 637 * it a command. 638 */ 639 static int 640 xl_eeprom_wait(struct xl_softc *sc) 641 { 642 int i; 643 644 for (i = 0; i < 100; i++) { 645 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 646 DELAY(162); 647 else 648 break; 649 } 650 651 if (i == 100) { 652 device_printf(sc->xl_dev, "eeprom failed to come ready\n"); 653 return (1); 654 } 655 656 return (0); 657 } 658 659 /* 660 * Read a sequence of words from the EEPROM. Note that ethernet address 661 * data is stored in the EEPROM in network byte order. 662 */ 663 static int 664 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 665 { 666 int err = 0, i; 667 u_int16_t word = 0, *ptr; 668 669 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 670 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 671 /* 672 * XXX: WARNING! DANGER! 673 * It's easy to accidentally overwrite the rom content! 674 * Note: the 3c575 uses 8bit EEPROM offsets. 675 */ 676 XL_SEL_WIN(0); 677 678 if (xl_eeprom_wait(sc)) 679 return (1); 680 681 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 682 off += 0x30; 683 684 for (i = 0; i < cnt; i++) { 685 if (sc->xl_flags & XL_FLAG_8BITROM) 686 CSR_WRITE_2(sc, XL_W0_EE_CMD, 687 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 688 else 689 CSR_WRITE_2(sc, XL_W0_EE_CMD, 690 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 691 err = xl_eeprom_wait(sc); 692 if (err) 693 break; 694 word = CSR_READ_2(sc, XL_W0_EE_DATA); 695 ptr = (u_int16_t *)(dest + (i * 2)); 696 if (swap) 697 *ptr = ntohs(word); 698 else 699 *ptr = word; 700 } 701 702 return (err ? 1 : 0); 703 } 704 705 /* 706 * NICs older than the 3c905B have only one multicast option, which 707 * is to enable reception of all multicast frames. 708 */ 709 static void 710 xl_setmulti(struct xl_softc *sc) 711 { 712 struct ifnet *ifp = sc->xl_ifp; 713 struct ifmultiaddr *ifma; 714 u_int8_t rxfilt; 715 int mcnt = 0; 716 717 XL_LOCK_ASSERT(sc); 718 719 XL_SEL_WIN(5); 720 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 721 722 if (ifp->if_flags & IFF_ALLMULTI) { 723 rxfilt |= XL_RXFILTER_ALLMULTI; 724 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 725 return; 726 } 727 728 IF_ADDR_LOCK(ifp); 729 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 730 mcnt++; 731 IF_ADDR_UNLOCK(ifp); 732 733 if (mcnt) 734 rxfilt |= XL_RXFILTER_ALLMULTI; 735 else 736 rxfilt &= ~XL_RXFILTER_ALLMULTI; 737 738 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 739 } 740 741 /* 742 * 3c905B adapters have a hash filter that we can program. 743 */ 744 static void 745 xl_setmulti_hash(struct xl_softc *sc) 746 { 747 struct ifnet *ifp = sc->xl_ifp; 748 int h = 0, i; 749 struct ifmultiaddr *ifma; 750 u_int8_t rxfilt; 751 int mcnt = 0; 752 753 XL_LOCK_ASSERT(sc); 754 755 XL_SEL_WIN(5); 756 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 757 758 if (ifp->if_flags & IFF_ALLMULTI) { 759 rxfilt |= XL_RXFILTER_ALLMULTI; 760 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 761 return; 762 } else 763 rxfilt &= ~XL_RXFILTER_ALLMULTI; 764 765 /* first, zot all the existing hash bits */ 766 for (i = 0; i < XL_HASHFILT_SIZE; i++) 767 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 768 769 /* now program new ones */ 770 IF_ADDR_LOCK(ifp); 771 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 772 if (ifma->ifma_addr->sa_family != AF_LINK) 773 continue; 774 /* 775 * Note: the 3c905B currently only supports a 64-bit hash 776 * table, which means we really only need 6 bits, but the 777 * manual indicates that future chip revisions will have a 778 * 256-bit hash table, hence the routine is set up to 779 * calculate 8 bits of position info in case we need it some 780 * day. 781 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have 782 * a 256 bit hash table. This means we have to use all 8 bits 783 * regardless. On older cards, the upper 2 bits will be 784 * ignored. Grrrr.... 785 */ 786 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 787 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 788 CSR_WRITE_2(sc, XL_COMMAND, 789 h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 790 mcnt++; 791 } 792 IF_ADDR_UNLOCK(ifp); 793 794 if (mcnt) 795 rxfilt |= XL_RXFILTER_MULTIHASH; 796 else 797 rxfilt &= ~XL_RXFILTER_MULTIHASH; 798 799 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 800 } 801 802 #ifdef notdef 803 static void 804 xl_testpacket(struct xl_softc *sc) 805 { 806 struct mbuf *m; 807 struct ifnet *ifp = sc->xl_ifp; 808 809 MGETHDR(m, M_DONTWAIT, MT_DATA); 810 811 if (m == NULL) 812 return; 813 814 bcopy(IF_LLADDR(sc->xl_ifp), 815 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 816 bcopy(IF_LLADDR(sc->xl_ifp), 817 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 818 mtod(m, struct ether_header *)->ether_type = htons(3); 819 mtod(m, unsigned char *)[14] = 0; 820 mtod(m, unsigned char *)[15] = 0; 821 mtod(m, unsigned char *)[16] = 0xE3; 822 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 823 IFQ_ENQUEUE(&ifp->if_snd, m); 824 xl_start(ifp); 825 } 826 #endif 827 828 static void 829 xl_setcfg(struct xl_softc *sc) 830 { 831 u_int32_t icfg; 832 833 /*XL_LOCK_ASSERT(sc);*/ 834 835 XL_SEL_WIN(3); 836 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 837 icfg &= ~XL_ICFG_CONNECTOR_MASK; 838 if (sc->xl_media & XL_MEDIAOPT_MII || 839 sc->xl_media & XL_MEDIAOPT_BT4) 840 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 841 if (sc->xl_media & XL_MEDIAOPT_BTX) 842 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 843 844 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 845 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 846 } 847 848 static void 849 xl_setmode(struct xl_softc *sc, int media) 850 { 851 u_int32_t icfg; 852 u_int16_t mediastat; 853 char *pmsg = "", *dmsg = ""; 854 855 XL_LOCK_ASSERT(sc); 856 857 XL_SEL_WIN(4); 858 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 859 XL_SEL_WIN(3); 860 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 861 862 if (sc->xl_media & XL_MEDIAOPT_BT) { 863 if (IFM_SUBTYPE(media) == IFM_10_T) { 864 pmsg = "10baseT transceiver"; 865 sc->xl_xcvr = XL_XCVR_10BT; 866 icfg &= ~XL_ICFG_CONNECTOR_MASK; 867 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 868 mediastat |= XL_MEDIASTAT_LINKBEAT | 869 XL_MEDIASTAT_JABGUARD; 870 mediastat &= ~XL_MEDIASTAT_SQEENB; 871 } 872 } 873 874 if (sc->xl_media & XL_MEDIAOPT_BFX) { 875 if (IFM_SUBTYPE(media) == IFM_100_FX) { 876 pmsg = "100baseFX port"; 877 sc->xl_xcvr = XL_XCVR_100BFX; 878 icfg &= ~XL_ICFG_CONNECTOR_MASK; 879 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 880 mediastat |= XL_MEDIASTAT_LINKBEAT; 881 mediastat &= ~XL_MEDIASTAT_SQEENB; 882 } 883 } 884 885 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 886 if (IFM_SUBTYPE(media) == IFM_10_5) { 887 pmsg = "AUI port"; 888 sc->xl_xcvr = XL_XCVR_AUI; 889 icfg &= ~XL_ICFG_CONNECTOR_MASK; 890 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 891 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 892 XL_MEDIASTAT_JABGUARD); 893 mediastat |= ~XL_MEDIASTAT_SQEENB; 894 } 895 if (IFM_SUBTYPE(media) == IFM_10_FL) { 896 pmsg = "10baseFL transceiver"; 897 sc->xl_xcvr = XL_XCVR_AUI; 898 icfg &= ~XL_ICFG_CONNECTOR_MASK; 899 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 900 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 901 XL_MEDIASTAT_JABGUARD); 902 mediastat |= ~XL_MEDIASTAT_SQEENB; 903 } 904 } 905 906 if (sc->xl_media & XL_MEDIAOPT_BNC) { 907 if (IFM_SUBTYPE(media) == IFM_10_2) { 908 pmsg = "AUI port"; 909 sc->xl_xcvr = XL_XCVR_COAX; 910 icfg &= ~XL_ICFG_CONNECTOR_MASK; 911 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 912 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 913 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 914 } 915 } 916 917 if ((media & IFM_GMASK) == IFM_FDX || 918 IFM_SUBTYPE(media) == IFM_100_FX) { 919 dmsg = "full"; 920 XL_SEL_WIN(3); 921 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 922 } else { 923 dmsg = "half"; 924 XL_SEL_WIN(3); 925 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 926 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 927 } 928 929 if (IFM_SUBTYPE(media) == IFM_10_2) 930 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 931 else 932 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 933 934 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 935 XL_SEL_WIN(4); 936 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 937 938 DELAY(800); 939 XL_SEL_WIN(7); 940 941 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg); 942 } 943 944 static void 945 xl_reset(struct xl_softc *sc) 946 { 947 register int i; 948 949 XL_LOCK_ASSERT(sc); 950 951 XL_SEL_WIN(0); 952 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 953 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 954 XL_RESETOPT_DISADVFD:0)); 955 956 /* 957 * If we're using memory mapped register mode, pause briefly 958 * after issuing the reset command before trying to access any 959 * other registers. With my 3c575C cardbus card, failing to do 960 * this results in the system locking up while trying to poll 961 * the command busy bit in the status register. 962 */ 963 if (sc->xl_flags & XL_FLAG_USE_MMIO) 964 DELAY(100000); 965 966 for (i = 0; i < XL_TIMEOUT; i++) { 967 DELAY(10); 968 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 969 break; 970 } 971 972 if (i == XL_TIMEOUT) 973 device_printf(sc->xl_dev, "reset didn't complete\n"); 974 975 /* Reset TX and RX. */ 976 /* Note: the RX reset takes an absurd amount of time 977 * on newer versions of the Tornado chips such as those 978 * on the 3c905CX and newer 3c908C cards. We wait an 979 * extra amount of time so that xl_wait() doesn't complain 980 * and annoy the users. 981 */ 982 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 983 DELAY(100000); 984 xl_wait(sc); 985 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 986 xl_wait(sc); 987 988 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 989 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 990 XL_SEL_WIN(2); 991 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 992 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 993 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 994 XL_RESETOPT_INVERT_LED : 0) | 995 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 996 XL_RESETOPT_INVERT_MII : 0)); 997 } 998 999 /* Wait a little while for the chip to get its brains in order. */ 1000 DELAY(100000); 1001 } 1002 1003 /* 1004 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1005 * IDs against our list and return a device name if we find a match. 1006 */ 1007 static int 1008 xl_probe(device_t dev) 1009 { 1010 const struct xl_type *t; 1011 1012 t = xl_devs; 1013 1014 while (t->xl_name != NULL) { 1015 if ((pci_get_vendor(dev) == t->xl_vid) && 1016 (pci_get_device(dev) == t->xl_did)) { 1017 device_set_desc(dev, t->xl_name); 1018 return (BUS_PROBE_DEFAULT); 1019 } 1020 t++; 1021 } 1022 1023 return (ENXIO); 1024 } 1025 1026 /* 1027 * This routine is a kludge to work around possible hardware faults 1028 * or manufacturing defects that can cause the media options register 1029 * (or reset options register, as it's called for the first generation 1030 * 3c90x adapters) to return an incorrect result. I have encountered 1031 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1032 * which doesn't have any of the 'mediaopt' bits set. This screws up 1033 * the attach routine pretty badly because it doesn't know what media 1034 * to look for. If we find ourselves in this predicament, this routine 1035 * will try to guess the media options values and warn the user of a 1036 * possible manufacturing defect with his adapter/system/whatever. 1037 */ 1038 static void 1039 xl_mediacheck(struct xl_softc *sc) 1040 { 1041 1042 /* 1043 * If some of the media options bits are set, assume they are 1044 * correct. If not, try to figure it out down below. 1045 * XXX I should check for 10baseFL, but I don't have an adapter 1046 * to test with. 1047 */ 1048 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1049 /* 1050 * Check the XCVR value. If it's not in the normal range 1051 * of values, we need to fake it up here. 1052 */ 1053 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1054 return; 1055 else { 1056 device_printf(sc->xl_dev, 1057 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 1058 device_printf(sc->xl_dev, 1059 "choosing new default based on card type\n"); 1060 } 1061 } else { 1062 if (sc->xl_type == XL_TYPE_905B && 1063 sc->xl_media & XL_MEDIAOPT_10FL) 1064 return; 1065 device_printf(sc->xl_dev, 1066 "WARNING: no media options bits set in the media options register!!\n"); 1067 device_printf(sc->xl_dev, 1068 "this could be a manufacturing defect in your adapter or system\n"); 1069 device_printf(sc->xl_dev, 1070 "attempting to guess media type; you should probably consult your vendor\n"); 1071 } 1072 1073 xl_choose_xcvr(sc, 1); 1074 } 1075 1076 static void 1077 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1078 { 1079 u_int16_t devid; 1080 1081 /* 1082 * Read the device ID from the EEPROM. 1083 * This is what's loaded into the PCI device ID register, so it has 1084 * to be correct otherwise we wouldn't have gotten this far. 1085 */ 1086 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1087 1088 switch (devid) { 1089 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1090 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1091 sc->xl_media = XL_MEDIAOPT_BT; 1092 sc->xl_xcvr = XL_XCVR_10BT; 1093 if (verbose) 1094 device_printf(sc->xl_dev, 1095 "guessing 10BaseT transceiver\n"); 1096 break; 1097 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1098 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1099 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1100 sc->xl_xcvr = XL_XCVR_10BT; 1101 if (verbose) 1102 device_printf(sc->xl_dev, 1103 "guessing COMBO (AUI/BNC/TP)\n"); 1104 break; 1105 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1106 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1107 sc->xl_xcvr = XL_XCVR_10BT; 1108 if (verbose) 1109 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n"); 1110 break; 1111 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1112 sc->xl_media = XL_MEDIAOPT_10FL; 1113 sc->xl_xcvr = XL_XCVR_AUI; 1114 if (verbose) 1115 device_printf(sc->xl_dev, "guessing 10baseFL\n"); 1116 break; 1117 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1118 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1119 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1120 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1121 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1122 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1123 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1124 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1125 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1126 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1127 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1128 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1129 sc->xl_media = XL_MEDIAOPT_MII; 1130 sc->xl_xcvr = XL_XCVR_MII; 1131 if (verbose) 1132 device_printf(sc->xl_dev, "guessing MII\n"); 1133 break; 1134 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1135 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1136 sc->xl_media = XL_MEDIAOPT_BT4; 1137 sc->xl_xcvr = XL_XCVR_MII; 1138 if (verbose) 1139 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n"); 1140 break; 1141 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1142 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1143 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1144 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1145 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1146 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1147 sc->xl_media = XL_MEDIAOPT_BTX; 1148 sc->xl_xcvr = XL_XCVR_AUTO; 1149 if (verbose) 1150 device_printf(sc->xl_dev, "guessing 10/100 internal\n"); 1151 break; 1152 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1153 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1154 sc->xl_xcvr = XL_XCVR_AUTO; 1155 if (verbose) 1156 device_printf(sc->xl_dev, 1157 "guessing 10/100 plus BNC/AUI\n"); 1158 break; 1159 default: 1160 device_printf(sc->xl_dev, 1161 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1162 sc->xl_media = XL_MEDIAOPT_BT; 1163 break; 1164 } 1165 } 1166 1167 /* 1168 * Attach the interface. Allocate softc structures, do ifmedia 1169 * setup and ethernet/BPF attach. 1170 */ 1171 static int 1172 xl_attach(device_t dev) 1173 { 1174 u_char eaddr[ETHER_ADDR_LEN]; 1175 u_int16_t xcvr[2]; 1176 struct xl_softc *sc; 1177 struct ifnet *ifp; 1178 int media; 1179 int unit, error = 0, rid, res; 1180 uint16_t did; 1181 1182 sc = device_get_softc(dev); 1183 sc->xl_dev = dev; 1184 1185 unit = device_get_unit(dev); 1186 1187 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1188 MTX_DEF); 1189 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1190 1191 did = pci_get_device(dev); 1192 1193 sc->xl_flags = 0; 1194 if (did == TC_DEVICEID_HURRICANE_555) 1195 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1196 if (did == TC_DEVICEID_HURRICANE_556 || 1197 did == TC_DEVICEID_HURRICANE_556B) 1198 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1199 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1200 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1201 if (did == TC_DEVICEID_HURRICANE_555 || 1202 did == TC_DEVICEID_HURRICANE_556) 1203 sc->xl_flags |= XL_FLAG_8BITROM; 1204 if (did == TC_DEVICEID_HURRICANE_556B) 1205 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1206 1207 if (did == TC_DEVICEID_HURRICANE_575B || 1208 did == TC_DEVICEID_HURRICANE_575C || 1209 did == TC_DEVICEID_HURRICANE_656B || 1210 did == TC_DEVICEID_TORNADO_656C) 1211 sc->xl_flags |= XL_FLAG_FUNCREG; 1212 if (did == TC_DEVICEID_HURRICANE_575A || 1213 did == TC_DEVICEID_HURRICANE_575B || 1214 did == TC_DEVICEID_HURRICANE_575C || 1215 did == TC_DEVICEID_HURRICANE_656B || 1216 did == TC_DEVICEID_TORNADO_656C) 1217 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1218 XL_FLAG_8BITROM; 1219 if (did == TC_DEVICEID_HURRICANE_656) 1220 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1221 if (did == TC_DEVICEID_HURRICANE_575B) 1222 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1223 if (did == TC_DEVICEID_HURRICANE_575C) 1224 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1225 if (did == TC_DEVICEID_TORNADO_656C) 1226 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1227 if (did == TC_DEVICEID_HURRICANE_656 || 1228 did == TC_DEVICEID_HURRICANE_656B) 1229 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1230 XL_FLAG_INVERT_LED_PWR; 1231 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1232 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1233 sc->xl_flags |= XL_FLAG_PHYOK; 1234 1235 switch (did) { 1236 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1237 case TC_DEVICEID_HURRICANE_575A: 1238 case TC_DEVICEID_HURRICANE_575B: 1239 case TC_DEVICEID_HURRICANE_575C: 1240 sc->xl_flags |= XL_FLAG_NO_MMIO; 1241 break; 1242 default: 1243 break; 1244 } 1245 1246 /* 1247 * Map control/status registers. 1248 */ 1249 pci_enable_busmaster(dev); 1250 1251 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1252 rid = XL_PCI_LOMEM; 1253 res = SYS_RES_MEMORY; 1254 1255 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1256 } 1257 1258 if (sc->xl_res != NULL) { 1259 sc->xl_flags |= XL_FLAG_USE_MMIO; 1260 if (bootverbose) 1261 device_printf(dev, "using memory mapped I/O\n"); 1262 } else { 1263 rid = XL_PCI_LOIO; 1264 res = SYS_RES_IOPORT; 1265 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1266 if (sc->xl_res == NULL) { 1267 device_printf(dev, "couldn't map ports/memory\n"); 1268 error = ENXIO; 1269 goto fail; 1270 } 1271 if (bootverbose) 1272 device_printf(dev, "using port I/O\n"); 1273 } 1274 1275 sc->xl_btag = rman_get_bustag(sc->xl_res); 1276 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1277 1278 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1279 rid = XL_PCI_FUNCMEM; 1280 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1281 RF_ACTIVE); 1282 1283 if (sc->xl_fres == NULL) { 1284 device_printf(dev, "couldn't map funcreg memory\n"); 1285 error = ENXIO; 1286 goto fail; 1287 } 1288 1289 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1290 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1291 } 1292 1293 /* Allocate interrupt */ 1294 rid = 0; 1295 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1296 RF_SHAREABLE | RF_ACTIVE); 1297 if (sc->xl_irq == NULL) { 1298 device_printf(dev, "couldn't map interrupt\n"); 1299 error = ENXIO; 1300 goto fail; 1301 } 1302 1303 /* Initialize interface name. */ 1304 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1305 if (ifp == NULL) { 1306 device_printf(dev, "can not if_alloc()\n"); 1307 error = ENOSPC; 1308 goto fail; 1309 } 1310 ifp->if_softc = sc; 1311 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1312 1313 /* Reset the adapter. */ 1314 XL_LOCK(sc); 1315 xl_reset(sc); 1316 XL_UNLOCK(sc); 1317 1318 /* 1319 * Get station address from the EEPROM. 1320 */ 1321 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1322 device_printf(dev, "failed to read station address\n"); 1323 error = ENXIO; 1324 goto fail; 1325 } 1326 1327 callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0); 1328 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1329 1330 /* 1331 * Now allocate a tag for the DMA descriptor lists and a chunk 1332 * of DMA-able memory based on the tag. Also obtain the DMA 1333 * addresses of the RX and TX ring, which we'll need later. 1334 * All of our lists are allocated as a contiguous block 1335 * of memory. 1336 */ 1337 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1338 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1339 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1340 &sc->xl_ldata.xl_rx_tag); 1341 if (error) { 1342 device_printf(dev, "failed to allocate rx dma tag\n"); 1343 goto fail; 1344 } 1345 1346 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1347 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1348 &sc->xl_ldata.xl_rx_dmamap); 1349 if (error) { 1350 device_printf(dev, "no memory for rx list buffers!\n"); 1351 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1352 sc->xl_ldata.xl_rx_tag = NULL; 1353 goto fail; 1354 } 1355 1356 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1357 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1358 XL_RX_LIST_SZ, xl_dma_map_addr, 1359 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1360 if (error) { 1361 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1362 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1363 sc->xl_ldata.xl_rx_dmamap); 1364 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1365 sc->xl_ldata.xl_rx_tag = NULL; 1366 goto fail; 1367 } 1368 1369 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1370 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1371 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1372 &sc->xl_ldata.xl_tx_tag); 1373 if (error) { 1374 device_printf(dev, "failed to allocate tx dma tag\n"); 1375 goto fail; 1376 } 1377 1378 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1379 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1380 &sc->xl_ldata.xl_tx_dmamap); 1381 if (error) { 1382 device_printf(dev, "no memory for list buffers!\n"); 1383 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1384 sc->xl_ldata.xl_tx_tag = NULL; 1385 goto fail; 1386 } 1387 1388 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1389 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1390 XL_TX_LIST_SZ, xl_dma_map_addr, 1391 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1392 if (error) { 1393 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1394 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1395 sc->xl_ldata.xl_tx_dmamap); 1396 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1397 sc->xl_ldata.xl_tx_tag = NULL; 1398 goto fail; 1399 } 1400 1401 /* 1402 * Allocate a DMA tag for the mapping of mbufs. 1403 */ 1404 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1405 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1406 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1407 NULL, &sc->xl_mtag); 1408 if (error) { 1409 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1410 goto fail; 1411 } 1412 1413 /* We need a spare DMA map for the RX ring. */ 1414 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1415 if (error) 1416 goto fail; 1417 1418 /* 1419 * Figure out the card type. 3c905B adapters have the 1420 * 'supportsNoTxLength' bit set in the capabilities 1421 * word in the EEPROM. 1422 * Note: my 3c575C cardbus card lies. It returns a value 1423 * of 0x1578 for its capabilities word, which is somewhat 1424 * nonsensical. Another way to distinguish a 3c90x chip 1425 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1426 * bit. This will only be set for 3c90x boomerage chips. 1427 */ 1428 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1429 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1430 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1431 sc->xl_type = XL_TYPE_905B; 1432 else 1433 sc->xl_type = XL_TYPE_90X; 1434 1435 /* Set the TX start threshold for best performance. */ 1436 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1437 1438 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1439 ifp->if_ioctl = xl_ioctl; 1440 ifp->if_capabilities = IFCAP_VLAN_MTU; 1441 if (sc->xl_type == XL_TYPE_905B) { 1442 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1443 #ifdef XL905B_TXCSUM_BROKEN 1444 ifp->if_capabilities |= IFCAP_RXCSUM; 1445 #else 1446 ifp->if_capabilities |= IFCAP_HWCSUM; 1447 #endif 1448 } 1449 ifp->if_capenable = ifp->if_capabilities; 1450 #ifdef DEVICE_POLLING 1451 ifp->if_capabilities |= IFCAP_POLLING; 1452 #endif 1453 ifp->if_start = xl_start; 1454 ifp->if_init = xl_init; 1455 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1456 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1; 1457 IFQ_SET_READY(&ifp->if_snd); 1458 1459 /* 1460 * Now we have to see what sort of media we have. 1461 * This includes probing for an MII interace and a 1462 * possible PHY. 1463 */ 1464 XL_SEL_WIN(3); 1465 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1466 if (bootverbose) 1467 device_printf(dev, "media options word: %x\n", sc->xl_media); 1468 1469 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1470 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1471 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1472 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1473 1474 xl_mediacheck(sc); 1475 1476 if (sc->xl_media & XL_MEDIAOPT_MII || 1477 sc->xl_media & XL_MEDIAOPT_BTX || 1478 sc->xl_media & XL_MEDIAOPT_BT4) { 1479 if (bootverbose) 1480 device_printf(dev, "found MII/AUTO\n"); 1481 xl_setcfg(sc); 1482 if (mii_phy_probe(dev, &sc->xl_miibus, 1483 xl_ifmedia_upd, xl_ifmedia_sts)) { 1484 device_printf(dev, "no PHY found!\n"); 1485 error = ENXIO; 1486 goto fail; 1487 } 1488 goto done; 1489 } 1490 1491 /* 1492 * Sanity check. If the user has selected "auto" and this isn't 1493 * a 10/100 card of some kind, we need to force the transceiver 1494 * type to something sane. 1495 */ 1496 if (sc->xl_xcvr == XL_XCVR_AUTO) 1497 xl_choose_xcvr(sc, bootverbose); 1498 1499 /* 1500 * Do ifmedia setup. 1501 */ 1502 if (sc->xl_media & XL_MEDIAOPT_BT) { 1503 if (bootverbose) 1504 device_printf(dev, "found 10baseT\n"); 1505 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1506 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1507 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1508 ifmedia_add(&sc->ifmedia, 1509 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1510 } 1511 1512 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1513 /* 1514 * Check for a 10baseFL board in disguise. 1515 */ 1516 if (sc->xl_type == XL_TYPE_905B && 1517 sc->xl_media == XL_MEDIAOPT_10FL) { 1518 if (bootverbose) 1519 device_printf(dev, "found 10baseFL\n"); 1520 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1521 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1522 0, NULL); 1523 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1524 ifmedia_add(&sc->ifmedia, 1525 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1526 } else { 1527 if (bootverbose) 1528 device_printf(dev, "found AUI\n"); 1529 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1530 } 1531 } 1532 1533 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1534 if (bootverbose) 1535 device_printf(dev, "found BNC\n"); 1536 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1537 } 1538 1539 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1540 if (bootverbose) 1541 device_printf(dev, "found 100baseFX\n"); 1542 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1543 } 1544 1545 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1546 xl_choose_media(sc, &media); 1547 1548 if (sc->xl_miibus == NULL) 1549 ifmedia_set(&sc->ifmedia, media); 1550 1551 done: 1552 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1553 XL_SEL_WIN(0); 1554 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1555 } 1556 1557 /* 1558 * Call MI attach routine. 1559 */ 1560 ether_ifattach(ifp, eaddr); 1561 1562 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1563 NULL, xl_intr, sc, &sc->xl_intrhand); 1564 if (error) { 1565 device_printf(dev, "couldn't set up irq\n"); 1566 ether_ifdetach(ifp); 1567 goto fail; 1568 } 1569 1570 fail: 1571 if (error) 1572 xl_detach(dev); 1573 1574 return (error); 1575 } 1576 1577 /* 1578 * Choose a default media. 1579 * XXX This is a leaf function only called by xl_attach() and 1580 * acquires/releases the non-recursible driver mutex to 1581 * satisfy lock assertions. 1582 */ 1583 static void 1584 xl_choose_media(struct xl_softc *sc, int *media) 1585 { 1586 1587 XL_LOCK(sc); 1588 1589 switch (sc->xl_xcvr) { 1590 case XL_XCVR_10BT: 1591 *media = IFM_ETHER|IFM_10_T; 1592 xl_setmode(sc, *media); 1593 break; 1594 case XL_XCVR_AUI: 1595 if (sc->xl_type == XL_TYPE_905B && 1596 sc->xl_media == XL_MEDIAOPT_10FL) { 1597 *media = IFM_ETHER|IFM_10_FL; 1598 xl_setmode(sc, *media); 1599 } else { 1600 *media = IFM_ETHER|IFM_10_5; 1601 xl_setmode(sc, *media); 1602 } 1603 break; 1604 case XL_XCVR_COAX: 1605 *media = IFM_ETHER|IFM_10_2; 1606 xl_setmode(sc, *media); 1607 break; 1608 case XL_XCVR_AUTO: 1609 case XL_XCVR_100BTX: 1610 case XL_XCVR_MII: 1611 /* Chosen by miibus */ 1612 break; 1613 case XL_XCVR_100BFX: 1614 *media = IFM_ETHER|IFM_100_FX; 1615 break; 1616 default: 1617 device_printf(sc->xl_dev, "unknown XCVR type: %d\n", 1618 sc->xl_xcvr); 1619 /* 1620 * This will probably be wrong, but it prevents 1621 * the ifmedia code from panicking. 1622 */ 1623 *media = IFM_ETHER|IFM_10_T; 1624 break; 1625 } 1626 1627 XL_UNLOCK(sc); 1628 } 1629 1630 /* 1631 * Shutdown hardware and free up resources. This can be called any 1632 * time after the mutex has been initialized. It is called in both 1633 * the error case in attach and the normal detach case so it needs 1634 * to be careful about only freeing resources that have actually been 1635 * allocated. 1636 */ 1637 static int 1638 xl_detach(device_t dev) 1639 { 1640 struct xl_softc *sc; 1641 struct ifnet *ifp; 1642 int rid, res; 1643 1644 sc = device_get_softc(dev); 1645 ifp = sc->xl_ifp; 1646 1647 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1648 1649 #ifdef DEVICE_POLLING 1650 if (ifp && ifp->if_capenable & IFCAP_POLLING) 1651 ether_poll_deregister(ifp); 1652 #endif 1653 1654 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1655 rid = XL_PCI_LOMEM; 1656 res = SYS_RES_MEMORY; 1657 } else { 1658 rid = XL_PCI_LOIO; 1659 res = SYS_RES_IOPORT; 1660 } 1661 1662 /* These should only be active if attach succeeded */ 1663 if (device_is_attached(dev)) { 1664 XL_LOCK(sc); 1665 xl_reset(sc); 1666 xl_stop(sc); 1667 XL_UNLOCK(sc); 1668 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1669 callout_drain(&sc->xl_stat_callout); 1670 ether_ifdetach(ifp); 1671 } 1672 if (sc->xl_miibus) 1673 device_delete_child(dev, sc->xl_miibus); 1674 bus_generic_detach(dev); 1675 ifmedia_removeall(&sc->ifmedia); 1676 1677 if (sc->xl_intrhand) 1678 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1679 if (sc->xl_irq) 1680 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1681 if (sc->xl_fres != NULL) 1682 bus_release_resource(dev, SYS_RES_MEMORY, 1683 XL_PCI_FUNCMEM, sc->xl_fres); 1684 if (sc->xl_res) 1685 bus_release_resource(dev, res, rid, sc->xl_res); 1686 1687 if (ifp) 1688 if_free(ifp); 1689 1690 if (sc->xl_mtag) { 1691 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1692 bus_dma_tag_destroy(sc->xl_mtag); 1693 } 1694 if (sc->xl_ldata.xl_rx_tag) { 1695 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1696 sc->xl_ldata.xl_rx_dmamap); 1697 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1698 sc->xl_ldata.xl_rx_dmamap); 1699 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1700 } 1701 if (sc->xl_ldata.xl_tx_tag) { 1702 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1703 sc->xl_ldata.xl_tx_dmamap); 1704 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1705 sc->xl_ldata.xl_tx_dmamap); 1706 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1707 } 1708 1709 mtx_destroy(&sc->xl_mtx); 1710 1711 return (0); 1712 } 1713 1714 /* 1715 * Initialize the transmit descriptors. 1716 */ 1717 static int 1718 xl_list_tx_init(struct xl_softc *sc) 1719 { 1720 struct xl_chain_data *cd; 1721 struct xl_list_data *ld; 1722 int error, i; 1723 1724 XL_LOCK_ASSERT(sc); 1725 1726 cd = &sc->xl_cdata; 1727 ld = &sc->xl_ldata; 1728 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1729 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1730 error = bus_dmamap_create(sc->xl_mtag, 0, 1731 &cd->xl_tx_chain[i].xl_map); 1732 if (error) 1733 return (error); 1734 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1735 i * sizeof(struct xl_list); 1736 if (i == (XL_TX_LIST_CNT - 1)) 1737 cd->xl_tx_chain[i].xl_next = NULL; 1738 else 1739 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1740 } 1741 1742 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1743 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1744 1745 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1746 return (0); 1747 } 1748 1749 /* 1750 * Initialize the transmit descriptors. 1751 */ 1752 static int 1753 xl_list_tx_init_90xB(struct xl_softc *sc) 1754 { 1755 struct xl_chain_data *cd; 1756 struct xl_list_data *ld; 1757 int error, i; 1758 1759 XL_LOCK_ASSERT(sc); 1760 1761 cd = &sc->xl_cdata; 1762 ld = &sc->xl_ldata; 1763 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1764 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1765 error = bus_dmamap_create(sc->xl_mtag, 0, 1766 &cd->xl_tx_chain[i].xl_map); 1767 if (error) 1768 return (error); 1769 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1770 i * sizeof(struct xl_list); 1771 if (i == (XL_TX_LIST_CNT - 1)) 1772 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1773 else 1774 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1775 if (i == 0) 1776 cd->xl_tx_chain[i].xl_prev = 1777 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1778 else 1779 cd->xl_tx_chain[i].xl_prev = 1780 &cd->xl_tx_chain[i - 1]; 1781 } 1782 1783 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1784 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1785 1786 cd->xl_tx_prod = 1; 1787 cd->xl_tx_cons = 1; 1788 cd->xl_tx_cnt = 0; 1789 1790 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1791 return (0); 1792 } 1793 1794 /* 1795 * Initialize the RX descriptors and allocate mbufs for them. Note that 1796 * we arrange the descriptors in a closed ring, so that the last descriptor 1797 * points back to the first. 1798 */ 1799 static int 1800 xl_list_rx_init(struct xl_softc *sc) 1801 { 1802 struct xl_chain_data *cd; 1803 struct xl_list_data *ld; 1804 int error, i, next; 1805 u_int32_t nextptr; 1806 1807 XL_LOCK_ASSERT(sc); 1808 1809 cd = &sc->xl_cdata; 1810 ld = &sc->xl_ldata; 1811 1812 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1813 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1814 error = bus_dmamap_create(sc->xl_mtag, 0, 1815 &cd->xl_rx_chain[i].xl_map); 1816 if (error) 1817 return (error); 1818 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1819 if (error) 1820 return (error); 1821 if (i == (XL_RX_LIST_CNT - 1)) 1822 next = 0; 1823 else 1824 next = i + 1; 1825 nextptr = ld->xl_rx_dmaaddr + 1826 next * sizeof(struct xl_list_onefrag); 1827 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1828 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1829 } 1830 1831 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1832 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1833 1834 return (0); 1835 } 1836 1837 /* 1838 * Initialize an RX descriptor and attach an MBUF cluster. 1839 * If we fail to do so, we need to leave the old mbuf and 1840 * the old DMA map untouched so that it can be reused. 1841 */ 1842 static int 1843 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1844 { 1845 struct mbuf *m_new = NULL; 1846 bus_dmamap_t map; 1847 bus_dma_segment_t segs[1]; 1848 int error, nseg; 1849 1850 XL_LOCK_ASSERT(sc); 1851 1852 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1853 if (m_new == NULL) 1854 return (ENOBUFS); 1855 1856 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1857 1858 /* Force longword alignment for packet payload. */ 1859 m_adj(m_new, ETHER_ALIGN); 1860 1861 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, 1862 segs, &nseg, BUS_DMA_NOWAIT); 1863 if (error) { 1864 m_freem(m_new); 1865 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", 1866 error); 1867 return (error); 1868 } 1869 KASSERT(nseg == 1, 1870 ("%s: too many DMA segments (%d)", __func__, nseg)); 1871 1872 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1873 map = c->xl_map; 1874 c->xl_map = sc->xl_tmpmap; 1875 sc->xl_tmpmap = map; 1876 c->xl_mbuf = m_new; 1877 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1878 c->xl_ptr->xl_status = 0; 1879 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); 1880 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1881 return (0); 1882 } 1883 1884 static int 1885 xl_rx_resync(struct xl_softc *sc) 1886 { 1887 struct xl_chain_onefrag *pos; 1888 int i; 1889 1890 XL_LOCK_ASSERT(sc); 1891 1892 pos = sc->xl_cdata.xl_rx_head; 1893 1894 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1895 if (pos->xl_ptr->xl_status) 1896 break; 1897 pos = pos->xl_next; 1898 } 1899 1900 if (i == XL_RX_LIST_CNT) 1901 return (0); 1902 1903 sc->xl_cdata.xl_rx_head = pos; 1904 1905 return (EAGAIN); 1906 } 1907 1908 /* 1909 * A frame has been uploaded: pass the resulting mbuf chain up to 1910 * the higher level protocols. 1911 */ 1912 static void 1913 xl_rxeof(struct xl_softc *sc) 1914 { 1915 struct mbuf *m; 1916 struct ifnet *ifp = sc->xl_ifp; 1917 struct xl_chain_onefrag *cur_rx; 1918 int total_len = 0; 1919 u_int32_t rxstat; 1920 1921 XL_LOCK_ASSERT(sc); 1922 again: 1923 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1924 BUS_DMASYNC_POSTREAD); 1925 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1926 #ifdef DEVICE_POLLING 1927 if (ifp->if_capenable & IFCAP_POLLING) { 1928 if (sc->rxcycles <= 0) 1929 break; 1930 sc->rxcycles--; 1931 } 1932 #endif 1933 cur_rx = sc->xl_cdata.xl_rx_head; 1934 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1935 total_len = rxstat & XL_RXSTAT_LENMASK; 1936 1937 /* 1938 * Since we have told the chip to allow large frames, 1939 * we need to trap giant frame errors in software. We allow 1940 * a little more than the normal frame size to account for 1941 * frames with VLAN tags. 1942 */ 1943 if (total_len > XL_MAX_FRAMELEN) 1944 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1945 1946 /* 1947 * If an error occurs, update stats, clear the 1948 * status word and leave the mbuf cluster in place: 1949 * it should simply get re-used next time this descriptor 1950 * comes up in the ring. 1951 */ 1952 if (rxstat & XL_RXSTAT_UP_ERROR) { 1953 ifp->if_ierrors++; 1954 cur_rx->xl_ptr->xl_status = 0; 1955 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1956 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1957 continue; 1958 } 1959 1960 /* 1961 * If the error bit was not set, the upload complete 1962 * bit should be set which means we have a valid packet. 1963 * If not, something truly strange has happened. 1964 */ 1965 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1966 device_printf(sc->xl_dev, 1967 "bad receive status -- packet dropped\n"); 1968 ifp->if_ierrors++; 1969 cur_rx->xl_ptr->xl_status = 0; 1970 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1971 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1972 continue; 1973 } 1974 1975 /* No errors; receive the packet. */ 1976 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 1977 BUS_DMASYNC_POSTREAD); 1978 m = cur_rx->xl_mbuf; 1979 1980 /* 1981 * Try to conjure up a new mbuf cluster. If that 1982 * fails, it means we have an out of memory condition and 1983 * should leave the buffer in place and continue. This will 1984 * result in a lost packet, but there's little else we 1985 * can do in this situation. 1986 */ 1987 if (xl_newbuf(sc, cur_rx)) { 1988 ifp->if_ierrors++; 1989 cur_rx->xl_ptr->xl_status = 0; 1990 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1991 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1992 continue; 1993 } 1994 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1995 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1996 1997 ifp->if_ipackets++; 1998 m->m_pkthdr.rcvif = ifp; 1999 m->m_pkthdr.len = m->m_len = total_len; 2000 2001 if (ifp->if_capenable & IFCAP_RXCSUM) { 2002 /* Do IP checksum checking. */ 2003 if (rxstat & XL_RXSTAT_IPCKOK) 2004 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2005 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2006 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2007 if ((rxstat & XL_RXSTAT_TCPCOK && 2008 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2009 (rxstat & XL_RXSTAT_UDPCKOK && 2010 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2011 m->m_pkthdr.csum_flags |= 2012 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2013 m->m_pkthdr.csum_data = 0xffff; 2014 } 2015 } 2016 2017 XL_UNLOCK(sc); 2018 (*ifp->if_input)(ifp, m); 2019 XL_LOCK(sc); 2020 2021 /* 2022 * If we are running from the taskqueue, the interface 2023 * might have been stopped while we were passing the last 2024 * packet up the network stack. 2025 */ 2026 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 2027 return; 2028 } 2029 2030 /* 2031 * Handle the 'end of channel' condition. When the upload 2032 * engine hits the end of the RX ring, it will stall. This 2033 * is our cue to flush the RX ring, reload the uplist pointer 2034 * register and unstall the engine. 2035 * XXX This is actually a little goofy. With the ThunderLAN 2036 * chip, you get an interrupt when the receiver hits the end 2037 * of the receive ring, which tells you exactly when you 2038 * you need to reload the ring pointer. Here we have to 2039 * fake it. I'm mad at myself for not being clever enough 2040 * to avoid the use of a goto here. 2041 */ 2042 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2043 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2044 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2045 xl_wait(sc); 2046 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2047 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2048 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2049 goto again; 2050 } 2051 } 2052 2053 /* 2054 * Taskqueue wrapper for xl_rxeof(). 2055 */ 2056 static void 2057 xl_rxeof_task(void *arg, int pending) 2058 { 2059 struct xl_softc *sc = (struct xl_softc *)arg; 2060 2061 XL_LOCK(sc); 2062 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING) 2063 xl_rxeof(sc); 2064 XL_UNLOCK(sc); 2065 } 2066 2067 /* 2068 * A frame was downloaded to the chip. It's safe for us to clean up 2069 * the list buffers. 2070 */ 2071 static void 2072 xl_txeof(struct xl_softc *sc) 2073 { 2074 struct xl_chain *cur_tx; 2075 struct ifnet *ifp = sc->xl_ifp; 2076 2077 XL_LOCK_ASSERT(sc); 2078 2079 /* 2080 * Go through our tx list and free mbufs for those 2081 * frames that have been uploaded. Note: the 3c905B 2082 * sets a special bit in the status word to let us 2083 * know that a frame has been downloaded, but the 2084 * original 3c900/3c905 adapters don't do that. 2085 * Consequently, we have to use a different test if 2086 * xl_type != XL_TYPE_905B. 2087 */ 2088 while (sc->xl_cdata.xl_tx_head != NULL) { 2089 cur_tx = sc->xl_cdata.xl_tx_head; 2090 2091 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2092 break; 2093 2094 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2095 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2096 BUS_DMASYNC_POSTWRITE); 2097 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2098 m_freem(cur_tx->xl_mbuf); 2099 cur_tx->xl_mbuf = NULL; 2100 ifp->if_opackets++; 2101 2102 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2103 sc->xl_cdata.xl_tx_free = cur_tx; 2104 } 2105 2106 if (sc->xl_cdata.xl_tx_head == NULL) { 2107 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2108 sc->xl_wdog_timer = 0; 2109 sc->xl_cdata.xl_tx_tail = NULL; 2110 } else { 2111 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2112 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2113 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2114 sc->xl_cdata.xl_tx_head->xl_phys); 2115 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2116 } 2117 } 2118 } 2119 2120 static void 2121 xl_txeof_90xB(struct xl_softc *sc) 2122 { 2123 struct xl_chain *cur_tx = NULL; 2124 struct ifnet *ifp = sc->xl_ifp; 2125 int idx; 2126 2127 XL_LOCK_ASSERT(sc); 2128 2129 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2130 BUS_DMASYNC_POSTREAD); 2131 idx = sc->xl_cdata.xl_tx_cons; 2132 while (idx != sc->xl_cdata.xl_tx_prod) { 2133 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2134 2135 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2136 XL_TXSTAT_DL_COMPLETE)) 2137 break; 2138 2139 if (cur_tx->xl_mbuf != NULL) { 2140 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2141 BUS_DMASYNC_POSTWRITE); 2142 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2143 m_freem(cur_tx->xl_mbuf); 2144 cur_tx->xl_mbuf = NULL; 2145 } 2146 2147 ifp->if_opackets++; 2148 2149 sc->xl_cdata.xl_tx_cnt--; 2150 XL_INC(idx, XL_TX_LIST_CNT); 2151 } 2152 2153 if (sc->xl_cdata.xl_tx_cnt == 0) 2154 sc->xl_wdog_timer = 0; 2155 sc->xl_cdata.xl_tx_cons = idx; 2156 2157 if (cur_tx != NULL) 2158 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2159 } 2160 2161 /* 2162 * TX 'end of channel' interrupt handler. Actually, we should 2163 * only get a 'TX complete' interrupt if there's a transmit error, 2164 * so this is really TX error handler. 2165 */ 2166 static void 2167 xl_txeoc(struct xl_softc *sc) 2168 { 2169 u_int8_t txstat; 2170 2171 XL_LOCK_ASSERT(sc); 2172 2173 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2174 if (txstat & XL_TXSTATUS_UNDERRUN || 2175 txstat & XL_TXSTATUS_JABBER || 2176 txstat & XL_TXSTATUS_RECLAIM) { 2177 device_printf(sc->xl_dev, 2178 "transmission error: %x\n", txstat); 2179 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2180 xl_wait(sc); 2181 if (sc->xl_type == XL_TYPE_905B) { 2182 if (sc->xl_cdata.xl_tx_cnt) { 2183 int i; 2184 struct xl_chain *c; 2185 2186 i = sc->xl_cdata.xl_tx_cons; 2187 c = &sc->xl_cdata.xl_tx_chain[i]; 2188 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2189 c->xl_phys); 2190 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2191 } 2192 } else { 2193 if (sc->xl_cdata.xl_tx_head != NULL) 2194 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2195 sc->xl_cdata.xl_tx_head->xl_phys); 2196 } 2197 /* 2198 * Remember to set this for the 2199 * first generation 3c90X chips. 2200 */ 2201 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2202 if (txstat & XL_TXSTATUS_UNDERRUN && 2203 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2204 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2205 device_printf(sc->xl_dev, 2206 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2207 } 2208 CSR_WRITE_2(sc, XL_COMMAND, 2209 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2210 if (sc->xl_type == XL_TYPE_905B) { 2211 CSR_WRITE_2(sc, XL_COMMAND, 2212 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2213 } 2214 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2215 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2216 } else { 2217 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2218 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2219 } 2220 /* 2221 * Write an arbitrary byte to the TX_STATUS register 2222 * to clear this interrupt/error and advance to the next. 2223 */ 2224 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2225 } 2226 } 2227 2228 static void 2229 xl_intr(void *arg) 2230 { 2231 struct xl_softc *sc = arg; 2232 struct ifnet *ifp = sc->xl_ifp; 2233 u_int16_t status; 2234 2235 XL_LOCK(sc); 2236 2237 #ifdef DEVICE_POLLING 2238 if (ifp->if_capenable & IFCAP_POLLING) { 2239 XL_UNLOCK(sc); 2240 return; 2241 } 2242 #endif 2243 2244 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && 2245 status != 0xFFFF) { 2246 CSR_WRITE_2(sc, XL_COMMAND, 2247 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2248 2249 if (status & XL_STAT_UP_COMPLETE) { 2250 int curpkts; 2251 2252 curpkts = ifp->if_ipackets; 2253 xl_rxeof(sc); 2254 if (curpkts == ifp->if_ipackets) { 2255 while (xl_rx_resync(sc)) 2256 xl_rxeof(sc); 2257 } 2258 } 2259 2260 if (status & XL_STAT_DOWN_COMPLETE) { 2261 if (sc->xl_type == XL_TYPE_905B) 2262 xl_txeof_90xB(sc); 2263 else 2264 xl_txeof(sc); 2265 } 2266 2267 if (status & XL_STAT_TX_COMPLETE) { 2268 ifp->if_oerrors++; 2269 xl_txeoc(sc); 2270 } 2271 2272 if (status & XL_STAT_ADFAIL) { 2273 xl_reset(sc); 2274 xl_init_locked(sc); 2275 } 2276 2277 if (status & XL_STAT_STATSOFLOW) { 2278 sc->xl_stats_no_timeout = 1; 2279 xl_stats_update_locked(sc); 2280 sc->xl_stats_no_timeout = 0; 2281 } 2282 } 2283 2284 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2285 if (sc->xl_type == XL_TYPE_905B) 2286 xl_start_90xB_locked(ifp); 2287 else 2288 xl_start_locked(ifp); 2289 } 2290 2291 XL_UNLOCK(sc); 2292 } 2293 2294 #ifdef DEVICE_POLLING 2295 static void 2296 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2297 { 2298 struct xl_softc *sc = ifp->if_softc; 2299 2300 XL_LOCK(sc); 2301 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2302 xl_poll_locked(ifp, cmd, count); 2303 XL_UNLOCK(sc); 2304 } 2305 2306 static void 2307 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2308 { 2309 struct xl_softc *sc = ifp->if_softc; 2310 2311 XL_LOCK_ASSERT(sc); 2312 2313 sc->rxcycles = count; 2314 xl_rxeof(sc); 2315 if (sc->xl_type == XL_TYPE_905B) 2316 xl_txeof_90xB(sc); 2317 else 2318 xl_txeof(sc); 2319 2320 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2321 if (sc->xl_type == XL_TYPE_905B) 2322 xl_start_90xB_locked(ifp); 2323 else 2324 xl_start_locked(ifp); 2325 } 2326 2327 if (cmd == POLL_AND_CHECK_STATUS) { 2328 u_int16_t status; 2329 2330 status = CSR_READ_2(sc, XL_STATUS); 2331 if (status & XL_INTRS && status != 0xFFFF) { 2332 CSR_WRITE_2(sc, XL_COMMAND, 2333 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2334 2335 if (status & XL_STAT_TX_COMPLETE) { 2336 ifp->if_oerrors++; 2337 xl_txeoc(sc); 2338 } 2339 2340 if (status & XL_STAT_ADFAIL) { 2341 xl_reset(sc); 2342 xl_init_locked(sc); 2343 } 2344 2345 if (status & XL_STAT_STATSOFLOW) { 2346 sc->xl_stats_no_timeout = 1; 2347 xl_stats_update_locked(sc); 2348 sc->xl_stats_no_timeout = 0; 2349 } 2350 } 2351 } 2352 } 2353 #endif /* DEVICE_POLLING */ 2354 2355 /* 2356 * XXX: This is an entry point for callout which needs to take the lock. 2357 */ 2358 static void 2359 xl_stats_update(void *xsc) 2360 { 2361 struct xl_softc *sc = xsc; 2362 2363 XL_LOCK_ASSERT(sc); 2364 2365 if (xl_watchdog(sc) == EJUSTRETURN) 2366 return; 2367 2368 xl_stats_update_locked(sc); 2369 } 2370 2371 static void 2372 xl_stats_update_locked(struct xl_softc *sc) 2373 { 2374 struct ifnet *ifp = sc->xl_ifp; 2375 struct xl_stats xl_stats; 2376 u_int8_t *p; 2377 int i; 2378 struct mii_data *mii = NULL; 2379 2380 XL_LOCK_ASSERT(sc); 2381 2382 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2383 2384 if (sc->xl_miibus != NULL) 2385 mii = device_get_softc(sc->xl_miibus); 2386 2387 p = (u_int8_t *)&xl_stats; 2388 2389 /* Read all the stats registers. */ 2390 XL_SEL_WIN(6); 2391 2392 for (i = 0; i < 16; i++) 2393 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2394 2395 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2396 2397 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2398 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision; 2399 2400 /* 2401 * Boomerang and cyclone chips have an extra stats counter 2402 * in window 4 (BadSSD). We have to read this too in order 2403 * to clear out all the stats registers and avoid a statsoflow 2404 * interrupt. 2405 */ 2406 XL_SEL_WIN(4); 2407 CSR_READ_1(sc, XL_W4_BADSSD); 2408 2409 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2410 mii_tick(mii); 2411 2412 XL_SEL_WIN(7); 2413 2414 if (!sc->xl_stats_no_timeout) 2415 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2416 } 2417 2418 /* 2419 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2420 * pointers to the fragment pointers. 2421 */ 2422 static int 2423 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) 2424 { 2425 struct mbuf *m_new; 2426 struct ifnet *ifp = sc->xl_ifp; 2427 int error, i, nseg, total_len; 2428 u_int32_t status; 2429 2430 XL_LOCK_ASSERT(sc); 2431 2432 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, 2433 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2434 2435 if (error && error != EFBIG) { 2436 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2437 return (error); 2438 } 2439 2440 /* 2441 * Handle special case: we used up all 63 fragments, 2442 * but we have more mbufs left in the chain. Copy the 2443 * data into an mbuf cluster. Note that we don't 2444 * bother clearing the values in the other fragment 2445 * pointers/counters; it wouldn't gain us anything, 2446 * and would waste cycles. 2447 */ 2448 if (error) { 2449 m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS); 2450 if (m_new == NULL) { 2451 m_freem(*m_head); 2452 *m_head = NULL; 2453 return (ENOBUFS); 2454 } 2455 *m_head = m_new; 2456 2457 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, 2458 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2459 if (error) { 2460 m_freem(*m_head); 2461 *m_head = NULL; 2462 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2463 return (error); 2464 } 2465 } 2466 2467 KASSERT(nseg <= XL_MAXFRAGS, 2468 ("%s: too many DMA segments (%d)", __func__, nseg)); 2469 if (nseg == 0) { 2470 m_freem(*m_head); 2471 *m_head = NULL; 2472 return (EIO); 2473 } 2474 2475 total_len = 0; 2476 for (i = 0; i < nseg; i++) { 2477 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, 2478 ("segment size too large")); 2479 c->xl_ptr->xl_frag[i].xl_addr = 2480 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); 2481 c->xl_ptr->xl_frag[i].xl_len = 2482 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); 2483 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; 2484 } 2485 c->xl_ptr->xl_frag[nseg - 1].xl_len = 2486 htole32(sc->xl_cdata.xl_tx_segs[nseg - 1].ds_len | XL_LAST_FRAG); 2487 c->xl_ptr->xl_status = htole32(total_len); 2488 c->xl_ptr->xl_next = 0; 2489 2490 if (sc->xl_type == XL_TYPE_905B) { 2491 status = XL_TXSTAT_RND_DEFEAT; 2492 2493 #ifndef XL905B_TXCSUM_BROKEN 2494 if (m_head->m_pkthdr.csum_flags) { 2495 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2496 status |= XL_TXSTAT_IPCKSUM; 2497 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2498 status |= XL_TXSTAT_TCPCKSUM; 2499 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2500 status |= XL_TXSTAT_UDPCKSUM; 2501 } 2502 #endif 2503 c->xl_ptr->xl_status = htole32(status); 2504 } 2505 2506 c->xl_mbuf = *m_head; 2507 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2508 return (0); 2509 } 2510 2511 /* 2512 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2513 * to the mbuf data regions directly in the transmit lists. We also save a 2514 * copy of the pointers since the transmit list fragment pointers are 2515 * physical addresses. 2516 */ 2517 2518 static void 2519 xl_start(struct ifnet *ifp) 2520 { 2521 struct xl_softc *sc = ifp->if_softc; 2522 2523 XL_LOCK(sc); 2524 2525 if (sc->xl_type == XL_TYPE_905B) 2526 xl_start_90xB_locked(ifp); 2527 else 2528 xl_start_locked(ifp); 2529 2530 XL_UNLOCK(sc); 2531 } 2532 2533 static void 2534 xl_start_locked(struct ifnet *ifp) 2535 { 2536 struct xl_softc *sc = ifp->if_softc; 2537 struct mbuf *m_head = NULL; 2538 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2539 u_int32_t status; 2540 int error; 2541 2542 XL_LOCK_ASSERT(sc); 2543 2544 /* 2545 * Check for an available queue slot. If there are none, 2546 * punt. 2547 */ 2548 if (sc->xl_cdata.xl_tx_free == NULL) { 2549 xl_txeoc(sc); 2550 xl_txeof(sc); 2551 if (sc->xl_cdata.xl_tx_free == NULL) { 2552 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2553 return; 2554 } 2555 } 2556 2557 start_tx = sc->xl_cdata.xl_tx_free; 2558 2559 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2560 sc->xl_cdata.xl_tx_free != NULL;) { 2561 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2562 if (m_head == NULL) 2563 break; 2564 2565 /* Pick a descriptor off the free list. */ 2566 cur_tx = sc->xl_cdata.xl_tx_free; 2567 2568 /* Pack the data into the descriptor. */ 2569 error = xl_encap(sc, cur_tx, &m_head); 2570 if (error) { 2571 if (m_head == NULL) 2572 break; 2573 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2574 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2575 break; 2576 } 2577 2578 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2579 cur_tx->xl_next = NULL; 2580 2581 /* Chain it together. */ 2582 if (prev != NULL) { 2583 prev->xl_next = cur_tx; 2584 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2585 } 2586 prev = cur_tx; 2587 2588 /* 2589 * If there's a BPF listener, bounce a copy of this frame 2590 * to him. 2591 */ 2592 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2593 } 2594 2595 /* 2596 * If there are no packets queued, bail. 2597 */ 2598 if (cur_tx == NULL) 2599 return; 2600 2601 /* 2602 * Place the request for the upload interrupt 2603 * in the last descriptor in the chain. This way, if 2604 * we're chaining several packets at once, we'll only 2605 * get an interrupt once for the whole chain rather than 2606 * once for each packet. 2607 */ 2608 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2609 XL_TXSTAT_DL_INTR); 2610 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2611 BUS_DMASYNC_PREWRITE); 2612 2613 /* 2614 * Queue the packets. If the TX channel is clear, update 2615 * the downlist pointer register. 2616 */ 2617 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2618 xl_wait(sc); 2619 2620 if (sc->xl_cdata.xl_tx_head != NULL) { 2621 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2622 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2623 htole32(start_tx->xl_phys); 2624 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2625 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2626 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2627 sc->xl_cdata.xl_tx_tail = cur_tx; 2628 } else { 2629 sc->xl_cdata.xl_tx_head = start_tx; 2630 sc->xl_cdata.xl_tx_tail = cur_tx; 2631 } 2632 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2633 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2634 2635 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2636 2637 XL_SEL_WIN(7); 2638 2639 /* 2640 * Set a timeout in case the chip goes out to lunch. 2641 */ 2642 sc->xl_wdog_timer = 5; 2643 2644 /* 2645 * XXX Under certain conditions, usually on slower machines 2646 * where interrupts may be dropped, it's possible for the 2647 * adapter to chew up all the buffers in the receive ring 2648 * and stall, without us being able to do anything about it. 2649 * To guard against this, we need to make a pass over the 2650 * RX queue to make sure there aren't any packets pending. 2651 * Doing it here means we can flush the receive ring at the 2652 * same time the chip is DMAing the transmit descriptors we 2653 * just gave it. 2654 * 2655 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2656 * nature of their chips in all their marketing literature; 2657 * we may as well take advantage of it. :) 2658 */ 2659 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2660 } 2661 2662 static void 2663 xl_start_90xB_locked(struct ifnet *ifp) 2664 { 2665 struct xl_softc *sc = ifp->if_softc; 2666 struct mbuf *m_head = NULL; 2667 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2668 int error, idx; 2669 2670 XL_LOCK_ASSERT(sc); 2671 2672 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 2673 return; 2674 2675 idx = sc->xl_cdata.xl_tx_prod; 2676 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2677 2678 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2679 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { 2680 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2681 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2682 break; 2683 } 2684 2685 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2686 if (m_head == NULL) 2687 break; 2688 2689 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2690 2691 /* Pack the data into the descriptor. */ 2692 error = xl_encap(sc, cur_tx, &m_head); 2693 if (error) { 2694 if (m_head == NULL) 2695 break; 2696 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2697 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2698 break; 2699 } 2700 2701 /* Chain it together. */ 2702 if (prev != NULL) 2703 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2704 prev = cur_tx; 2705 2706 /* 2707 * If there's a BPF listener, bounce a copy of this frame 2708 * to him. 2709 */ 2710 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2711 2712 XL_INC(idx, XL_TX_LIST_CNT); 2713 sc->xl_cdata.xl_tx_cnt++; 2714 } 2715 2716 /* 2717 * If there are no packets queued, bail. 2718 */ 2719 if (cur_tx == NULL) 2720 return; 2721 2722 /* 2723 * Place the request for the upload interrupt 2724 * in the last descriptor in the chain. This way, if 2725 * we're chaining several packets at once, we'll only 2726 * get an interrupt once for the whole chain rather than 2727 * once for each packet. 2728 */ 2729 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2730 XL_TXSTAT_DL_INTR); 2731 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2732 BUS_DMASYNC_PREWRITE); 2733 2734 /* Start transmission */ 2735 sc->xl_cdata.xl_tx_prod = idx; 2736 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2737 2738 /* 2739 * Set a timeout in case the chip goes out to lunch. 2740 */ 2741 sc->xl_wdog_timer = 5; 2742 } 2743 2744 static void 2745 xl_init(void *xsc) 2746 { 2747 struct xl_softc *sc = xsc; 2748 2749 XL_LOCK(sc); 2750 xl_init_locked(sc); 2751 XL_UNLOCK(sc); 2752 } 2753 2754 static void 2755 xl_init_locked(struct xl_softc *sc) 2756 { 2757 struct ifnet *ifp = sc->xl_ifp; 2758 int error, i; 2759 u_int16_t rxfilt = 0; 2760 struct mii_data *mii = NULL; 2761 2762 XL_LOCK_ASSERT(sc); 2763 2764 /* 2765 * Cancel pending I/O and free all RX/TX buffers. 2766 */ 2767 xl_stop(sc); 2768 2769 if (sc->xl_miibus == NULL) { 2770 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2771 xl_wait(sc); 2772 } 2773 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2774 xl_wait(sc); 2775 DELAY(10000); 2776 2777 if (sc->xl_miibus != NULL) 2778 mii = device_get_softc(sc->xl_miibus); 2779 2780 /* Init our MAC address */ 2781 XL_SEL_WIN(2); 2782 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2783 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2784 IF_LLADDR(sc->xl_ifp)[i]); 2785 } 2786 2787 /* Clear the station mask. */ 2788 for (i = 0; i < 3; i++) 2789 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2790 #ifdef notdef 2791 /* Reset TX and RX. */ 2792 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2793 xl_wait(sc); 2794 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2795 xl_wait(sc); 2796 #endif 2797 /* Init circular RX list. */ 2798 error = xl_list_rx_init(sc); 2799 if (error) { 2800 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n", 2801 error); 2802 xl_stop(sc); 2803 return; 2804 } 2805 2806 /* Init TX descriptors. */ 2807 if (sc->xl_type == XL_TYPE_905B) 2808 error = xl_list_tx_init_90xB(sc); 2809 else 2810 error = xl_list_tx_init(sc); 2811 if (error) { 2812 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n", 2813 error); 2814 xl_stop(sc); 2815 return; 2816 } 2817 2818 /* 2819 * Set the TX freethresh value. 2820 * Note that this has no effect on 3c905B "cyclone" 2821 * cards but is required for 3c900/3c905 "boomerang" 2822 * cards in order to enable the download engine. 2823 */ 2824 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2825 2826 /* Set the TX start threshold for best performance. */ 2827 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2828 2829 /* 2830 * If this is a 3c905B, also set the tx reclaim threshold. 2831 * This helps cut down on the number of tx reclaim errors 2832 * that could happen on a busy network. The chip multiplies 2833 * the register value by 16 to obtain the actual threshold 2834 * in bytes, so we divide by 16 when setting the value here. 2835 * The existing threshold value can be examined by reading 2836 * the register at offset 9 in window 5. 2837 */ 2838 if (sc->xl_type == XL_TYPE_905B) { 2839 CSR_WRITE_2(sc, XL_COMMAND, 2840 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2841 } 2842 2843 /* Set RX filter bits. */ 2844 XL_SEL_WIN(5); 2845 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2846 2847 /* Set the individual bit to receive frames for this host only. */ 2848 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2849 2850 /* If we want promiscuous mode, set the allframes bit. */ 2851 if (ifp->if_flags & IFF_PROMISC) { 2852 rxfilt |= XL_RXFILTER_ALLFRAMES; 2853 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2854 } else { 2855 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2856 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2857 } 2858 2859 /* 2860 * Set capture broadcast bit to capture broadcast frames. 2861 */ 2862 if (ifp->if_flags & IFF_BROADCAST) { 2863 rxfilt |= XL_RXFILTER_BROADCAST; 2864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2865 } else { 2866 rxfilt &= ~XL_RXFILTER_BROADCAST; 2867 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2868 } 2869 2870 /* 2871 * Program the multicast filter, if necessary. 2872 */ 2873 if (sc->xl_type == XL_TYPE_905B) 2874 xl_setmulti_hash(sc); 2875 else 2876 xl_setmulti(sc); 2877 2878 /* 2879 * Load the address of the RX list. We have to 2880 * stall the upload engine before we can manipulate 2881 * the uplist pointer register, then unstall it when 2882 * we're finished. We also have to wait for the 2883 * stall command to complete before proceeding. 2884 * Note that we have to do this after any RX resets 2885 * have completed since the uplist register is cleared 2886 * by a reset. 2887 */ 2888 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2889 xl_wait(sc); 2890 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2891 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2892 xl_wait(sc); 2893 2894 if (sc->xl_type == XL_TYPE_905B) { 2895 /* Set polling interval */ 2896 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2897 /* Load the address of the TX list */ 2898 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2899 xl_wait(sc); 2900 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2901 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2902 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2903 xl_wait(sc); 2904 } 2905 2906 /* 2907 * If the coax transceiver is on, make sure to enable 2908 * the DC-DC converter. 2909 */ 2910 XL_SEL_WIN(3); 2911 if (sc->xl_xcvr == XL_XCVR_COAX) 2912 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2913 else 2914 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2915 2916 /* 2917 * increase packet size to allow reception of 802.1q or ISL packets. 2918 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2919 * control register. For 3c90xB/C chips, use the RX packet size 2920 * register. 2921 */ 2922 2923 if (sc->xl_type == XL_TYPE_905B) 2924 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2925 else { 2926 u_int8_t macctl; 2927 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2928 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2929 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2930 } 2931 2932 /* Clear out the stats counters. */ 2933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2934 sc->xl_stats_no_timeout = 1; 2935 xl_stats_update_locked(sc); 2936 sc->xl_stats_no_timeout = 0; 2937 XL_SEL_WIN(4); 2938 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2939 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2940 2941 /* 2942 * Enable interrupts. 2943 */ 2944 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2946 #ifdef DEVICE_POLLING 2947 /* Disable interrupts if we are polling. */ 2948 if (ifp->if_capenable & IFCAP_POLLING) 2949 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2950 else 2951 #endif 2952 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2953 if (sc->xl_flags & XL_FLAG_FUNCREG) 2954 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2955 2956 /* Set the RX early threshold */ 2957 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2958 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2959 2960 /* Enable receiver and transmitter. */ 2961 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2962 xl_wait(sc); 2963 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2964 xl_wait(sc); 2965 2966 /* XXX Downcall to miibus. */ 2967 if (mii != NULL) 2968 mii_mediachg(mii); 2969 2970 /* Select window 7 for normal operations. */ 2971 XL_SEL_WIN(7); 2972 2973 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2974 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2975 2976 sc->xl_wdog_timer = 0; 2977 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2978 } 2979 2980 /* 2981 * Set media options. 2982 */ 2983 static int 2984 xl_ifmedia_upd(struct ifnet *ifp) 2985 { 2986 struct xl_softc *sc = ifp->if_softc; 2987 struct ifmedia *ifm = NULL; 2988 struct mii_data *mii = NULL; 2989 2990 XL_LOCK(sc); 2991 2992 if (sc->xl_miibus != NULL) 2993 mii = device_get_softc(sc->xl_miibus); 2994 if (mii == NULL) 2995 ifm = &sc->ifmedia; 2996 else 2997 ifm = &mii->mii_media; 2998 2999 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3000 case IFM_100_FX: 3001 case IFM_10_FL: 3002 case IFM_10_2: 3003 case IFM_10_5: 3004 xl_setmode(sc, ifm->ifm_media); 3005 XL_UNLOCK(sc); 3006 return (0); 3007 } 3008 3009 if (sc->xl_media & XL_MEDIAOPT_MII || 3010 sc->xl_media & XL_MEDIAOPT_BTX || 3011 sc->xl_media & XL_MEDIAOPT_BT4) { 3012 xl_init_locked(sc); 3013 } else { 3014 xl_setmode(sc, ifm->ifm_media); 3015 } 3016 3017 XL_UNLOCK(sc); 3018 3019 return (0); 3020 } 3021 3022 /* 3023 * Report current media status. 3024 */ 3025 static void 3026 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3027 { 3028 struct xl_softc *sc = ifp->if_softc; 3029 u_int32_t icfg; 3030 u_int16_t status = 0; 3031 struct mii_data *mii = NULL; 3032 3033 XL_LOCK(sc); 3034 3035 if (sc->xl_miibus != NULL) 3036 mii = device_get_softc(sc->xl_miibus); 3037 3038 XL_SEL_WIN(4); 3039 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3040 3041 XL_SEL_WIN(3); 3042 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3043 icfg >>= XL_ICFG_CONNECTOR_BITS; 3044 3045 ifmr->ifm_active = IFM_ETHER; 3046 ifmr->ifm_status = IFM_AVALID; 3047 3048 if ((status & XL_MEDIASTAT_CARRIER) == 0) 3049 ifmr->ifm_status |= IFM_ACTIVE; 3050 3051 switch (icfg) { 3052 case XL_XCVR_10BT: 3053 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3054 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3055 ifmr->ifm_active |= IFM_FDX; 3056 else 3057 ifmr->ifm_active |= IFM_HDX; 3058 break; 3059 case XL_XCVR_AUI: 3060 if (sc->xl_type == XL_TYPE_905B && 3061 sc->xl_media == XL_MEDIAOPT_10FL) { 3062 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3063 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3064 ifmr->ifm_active |= IFM_FDX; 3065 else 3066 ifmr->ifm_active |= IFM_HDX; 3067 } else 3068 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3069 break; 3070 case XL_XCVR_COAX: 3071 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3072 break; 3073 /* 3074 * XXX MII and BTX/AUTO should be separate cases. 3075 */ 3076 3077 case XL_XCVR_100BTX: 3078 case XL_XCVR_AUTO: 3079 case XL_XCVR_MII: 3080 if (mii != NULL) { 3081 mii_pollstat(mii); 3082 ifmr->ifm_active = mii->mii_media_active; 3083 ifmr->ifm_status = mii->mii_media_status; 3084 } 3085 break; 3086 case XL_XCVR_100BFX: 3087 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3088 break; 3089 default: 3090 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3091 break; 3092 } 3093 3094 XL_UNLOCK(sc); 3095 } 3096 3097 static int 3098 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3099 { 3100 struct xl_softc *sc = ifp->if_softc; 3101 struct ifreq *ifr = (struct ifreq *) data; 3102 int error = 0; 3103 struct mii_data *mii = NULL; 3104 u_int8_t rxfilt; 3105 3106 switch (command) { 3107 case SIOCSIFFLAGS: 3108 XL_LOCK(sc); 3109 3110 XL_SEL_WIN(5); 3111 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3112 if (ifp->if_flags & IFF_UP) { 3113 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3114 ifp->if_flags & IFF_PROMISC && 3115 !(sc->xl_if_flags & IFF_PROMISC)) { 3116 rxfilt |= XL_RXFILTER_ALLFRAMES; 3117 CSR_WRITE_2(sc, XL_COMMAND, 3118 XL_CMD_RX_SET_FILT|rxfilt); 3119 XL_SEL_WIN(7); 3120 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3121 !(ifp->if_flags & IFF_PROMISC) && 3122 sc->xl_if_flags & IFF_PROMISC) { 3123 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3124 CSR_WRITE_2(sc, XL_COMMAND, 3125 XL_CMD_RX_SET_FILT|rxfilt); 3126 XL_SEL_WIN(7); 3127 } else { 3128 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3129 xl_init_locked(sc); 3130 } 3131 } else { 3132 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3133 xl_stop(sc); 3134 } 3135 sc->xl_if_flags = ifp->if_flags; 3136 XL_UNLOCK(sc); 3137 error = 0; 3138 break; 3139 case SIOCADDMULTI: 3140 case SIOCDELMULTI: 3141 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3142 XL_LOCK(sc); 3143 if (sc->xl_type == XL_TYPE_905B) 3144 xl_setmulti_hash(sc); 3145 else 3146 xl_setmulti(sc); 3147 XL_UNLOCK(sc); 3148 error = 0; 3149 break; 3150 case SIOCGIFMEDIA: 3151 case SIOCSIFMEDIA: 3152 if (sc->xl_miibus != NULL) 3153 mii = device_get_softc(sc->xl_miibus); 3154 if (mii == NULL) 3155 error = ifmedia_ioctl(ifp, ifr, 3156 &sc->ifmedia, command); 3157 else 3158 error = ifmedia_ioctl(ifp, ifr, 3159 &mii->mii_media, command); 3160 break; 3161 case SIOCSIFCAP: 3162 #ifdef DEVICE_POLLING 3163 if (ifr->ifr_reqcap & IFCAP_POLLING && 3164 !(ifp->if_capenable & IFCAP_POLLING)) { 3165 error = ether_poll_register(xl_poll, ifp); 3166 if (error) 3167 return(error); 3168 XL_LOCK(sc); 3169 /* Disable interrupts */ 3170 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3171 ifp->if_capenable |= IFCAP_POLLING; 3172 XL_UNLOCK(sc); 3173 return (error); 3174 } 3175 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3176 ifp->if_capenable & IFCAP_POLLING) { 3177 error = ether_poll_deregister(ifp); 3178 /* Enable interrupts. */ 3179 XL_LOCK(sc); 3180 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 3181 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 3182 if (sc->xl_flags & XL_FLAG_FUNCREG) 3183 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 3184 4, 0x8000); 3185 ifp->if_capenable &= ~IFCAP_POLLING; 3186 XL_UNLOCK(sc); 3187 return (error); 3188 } 3189 #endif /* DEVICE_POLLING */ 3190 XL_LOCK(sc); 3191 ifp->if_capenable = ifr->ifr_reqcap; 3192 if (ifp->if_capenable & IFCAP_TXCSUM) 3193 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3194 else 3195 ifp->if_hwassist = 0; 3196 XL_UNLOCK(sc); 3197 break; 3198 default: 3199 error = ether_ioctl(ifp, command, data); 3200 break; 3201 } 3202 3203 return (error); 3204 } 3205 3206 static int 3207 xl_watchdog(struct xl_softc *sc) 3208 { 3209 struct ifnet *ifp = sc->xl_ifp; 3210 u_int16_t status = 0; 3211 3212 XL_LOCK_ASSERT(sc); 3213 3214 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) 3215 return (0); 3216 3217 ifp->if_oerrors++; 3218 XL_SEL_WIN(4); 3219 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3220 device_printf(sc->xl_dev, "watchdog timeout\n"); 3221 3222 if (status & XL_MEDIASTAT_CARRIER) 3223 device_printf(sc->xl_dev, 3224 "no carrier - transceiver cable problem?\n"); 3225 3226 xl_txeoc(sc); 3227 xl_txeof(sc); 3228 xl_rxeof(sc); 3229 xl_reset(sc); 3230 xl_init_locked(sc); 3231 3232 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 3233 if (sc->xl_type == XL_TYPE_905B) 3234 xl_start_90xB_locked(ifp); 3235 else 3236 xl_start_locked(ifp); 3237 } 3238 3239 return (EJUSTRETURN); 3240 } 3241 3242 /* 3243 * Stop the adapter and free any mbufs allocated to the 3244 * RX and TX lists. 3245 */ 3246 static void 3247 xl_stop(struct xl_softc *sc) 3248 { 3249 register int i; 3250 struct ifnet *ifp = sc->xl_ifp; 3251 3252 XL_LOCK_ASSERT(sc); 3253 3254 sc->xl_wdog_timer = 0; 3255 3256 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3257 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3258 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3259 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3260 xl_wait(sc); 3261 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3262 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3263 DELAY(800); 3264 3265 #ifdef foo 3266 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3267 xl_wait(sc); 3268 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3269 xl_wait(sc); 3270 #endif 3271 3272 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3273 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3274 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3275 if (sc->xl_flags & XL_FLAG_FUNCREG) 3276 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3277 3278 /* Stop the stats updater. */ 3279 callout_stop(&sc->xl_stat_callout); 3280 3281 /* 3282 * Free data in the RX lists. 3283 */ 3284 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3285 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3286 bus_dmamap_unload(sc->xl_mtag, 3287 sc->xl_cdata.xl_rx_chain[i].xl_map); 3288 bus_dmamap_destroy(sc->xl_mtag, 3289 sc->xl_cdata.xl_rx_chain[i].xl_map); 3290 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3291 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3292 } 3293 } 3294 if (sc->xl_ldata.xl_rx_list != NULL) 3295 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3296 /* 3297 * Free the TX list buffers. 3298 */ 3299 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3300 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3301 bus_dmamap_unload(sc->xl_mtag, 3302 sc->xl_cdata.xl_tx_chain[i].xl_map); 3303 bus_dmamap_destroy(sc->xl_mtag, 3304 sc->xl_cdata.xl_tx_chain[i].xl_map); 3305 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3306 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3307 } 3308 } 3309 if (sc->xl_ldata.xl_tx_list != NULL) 3310 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3311 3312 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3313 } 3314 3315 /* 3316 * Stop all chip I/O so that the kernel's probe routines don't 3317 * get confused by errant DMAs when rebooting. 3318 */ 3319 static int 3320 xl_shutdown(device_t dev) 3321 { 3322 struct xl_softc *sc; 3323 3324 sc = device_get_softc(dev); 3325 3326 XL_LOCK(sc); 3327 xl_reset(sc); 3328 xl_stop(sc); 3329 XL_UNLOCK(sc); 3330 3331 return (0); 3332 } 3333 3334 static int 3335 xl_suspend(device_t dev) 3336 { 3337 struct xl_softc *sc; 3338 3339 sc = device_get_softc(dev); 3340 3341 XL_LOCK(sc); 3342 xl_stop(sc); 3343 XL_UNLOCK(sc); 3344 3345 return (0); 3346 } 3347 3348 static int 3349 xl_resume(device_t dev) 3350 { 3351 struct xl_softc *sc; 3352 struct ifnet *ifp; 3353 3354 sc = device_get_softc(dev); 3355 ifp = sc->xl_ifp; 3356 3357 XL_LOCK(sc); 3358 3359 xl_reset(sc); 3360 if (ifp->if_flags & IFF_UP) 3361 xl_init_locked(sc); 3362 3363 XL_UNLOCK(sc); 3364 3365 return (0); 3366 } 3367