1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 /* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 */ 100 101 #ifdef HAVE_KERNEL_OPTION_HEADERS 102 #include "opt_device_polling.h" 103 #endif 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/sockio.h> 108 #include <sys/endian.h> 109 #include <sys/mbuf.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/taskqueue.h> 114 115 #include <net/if.h> 116 #include <net/if_arp.h> 117 #include <net/ethernet.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 #include <net/if_types.h> 121 122 #include <net/bpf.h> 123 124 #include <machine/bus.h> 125 #include <machine/resource.h> 126 #include <sys/bus.h> 127 #include <sys/rman.h> 128 129 #include <dev/mii/mii.h> 130 #include <dev/mii/miivar.h> 131 132 #include <dev/pci/pcireg.h> 133 #include <dev/pci/pcivar.h> 134 135 MODULE_DEPEND(xl, pci, 1, 1, 1); 136 MODULE_DEPEND(xl, ether, 1, 1, 1); 137 MODULE_DEPEND(xl, miibus, 1, 1, 1); 138 139 /* "device miibus" required. See GENERIC if you get errors here. */ 140 #include "miibus_if.h" 141 142 #include <dev/xl/if_xlreg.h> 143 144 /* 145 * TX Checksumming is disabled by default for two reasons: 146 * - TX Checksumming will occasionally produce corrupt packets 147 * - TX Checksumming seems to reduce performance 148 * 149 * Only 905B/C cards were reported to have this problem, it is possible 150 * that later chips _may_ be immune. 151 */ 152 #define XL905B_TXCSUM_BROKEN 1 153 154 #ifdef XL905B_TXCSUM_BROKEN 155 #define XL905B_CSUM_FEATURES 0 156 #else 157 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 #endif 159 160 /* 161 * Various supported device vendors/types and their names. 162 */ 163 static const struct xl_type xl_devs[] = { 164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 165 "3Com 3c900-TPO Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 167 "3Com 3c900-COMBO Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 169 "3Com 3c905-TX Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 171 "3Com 3c905-T4 Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 173 "3Com 3c900B-TPO Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 175 "3Com 3c900B-COMBO Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 177 "3Com 3c900B-TPC Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 179 "3Com 3c900B-FL Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 181 "3Com 3c905B-TX Fast Etherlink XL" }, 182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 183 "3Com 3c905B-T4 Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 185 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 187 "3Com 3c905B-COMBO Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 189 "3Com 3c905C-TX Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 191 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 193 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 195 "3Com 3c980 Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 197 "3Com 3c980C Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 199 "3Com 3cSOHO100-TX OfficeConnect" }, 200 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 201 "3Com 3c450-TX HomeConnect" }, 202 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 203 "3Com 3c555 Fast Etherlink XL" }, 204 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 205 "3Com 3c556 Fast Etherlink XL" }, 206 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 207 "3Com 3c556B Fast Etherlink XL" }, 208 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 209 "3Com 3c575TX Fast Etherlink XL" }, 210 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 211 "3Com 3c575B Fast Etherlink XL" }, 212 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 213 "3Com 3c575C Fast Etherlink XL" }, 214 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 215 "3Com 3c656 Fast Etherlink XL" }, 216 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 217 "3Com 3c656B Fast Etherlink XL" }, 218 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 219 "3Com 3c656C Fast Etherlink XL" }, 220 { 0, 0, NULL } 221 }; 222 223 static int xl_probe(device_t); 224 static int xl_attach(device_t); 225 static int xl_detach(device_t); 226 227 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 228 static void xl_stats_update(void *); 229 static void xl_stats_update_locked(struct xl_softc *); 230 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); 231 static int xl_rxeof(struct xl_softc *); 232 static void xl_rxeof_task(void *, int); 233 static int xl_rx_resync(struct xl_softc *); 234 static void xl_txeof(struct xl_softc *); 235 static void xl_txeof_90xB(struct xl_softc *); 236 static void xl_txeoc(struct xl_softc *); 237 static void xl_intr(void *); 238 static void xl_start(struct ifnet *); 239 static void xl_start_locked(struct ifnet *); 240 static void xl_start_90xB_locked(struct ifnet *); 241 static int xl_ioctl(struct ifnet *, u_long, caddr_t); 242 static void xl_init(void *); 243 static void xl_init_locked(struct xl_softc *); 244 static void xl_stop(struct xl_softc *); 245 static int xl_watchdog(struct xl_softc *); 246 static int xl_shutdown(device_t); 247 static int xl_suspend(device_t); 248 static int xl_resume(device_t); 249 static void xl_setwol(struct xl_softc *); 250 251 #ifdef DEVICE_POLLING 252 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 253 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 254 #endif 255 256 static int xl_ifmedia_upd(struct ifnet *); 257 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 258 259 static int xl_eeprom_wait(struct xl_softc *); 260 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 261 static void xl_mii_sync(struct xl_softc *); 262 static void xl_mii_send(struct xl_softc *, u_int32_t, int); 263 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *); 264 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *); 265 266 static void xl_setcfg(struct xl_softc *); 267 static void xl_setmode(struct xl_softc *, int); 268 static void xl_setmulti(struct xl_softc *); 269 static void xl_setmulti_hash(struct xl_softc *); 270 static void xl_reset(struct xl_softc *); 271 static int xl_list_rx_init(struct xl_softc *); 272 static int xl_list_tx_init(struct xl_softc *); 273 static int xl_list_tx_init_90xB(struct xl_softc *); 274 static void xl_wait(struct xl_softc *); 275 static void xl_mediacheck(struct xl_softc *); 276 static void xl_choose_media(struct xl_softc *sc, int *media); 277 static void xl_choose_xcvr(struct xl_softc *, int); 278 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 279 #ifdef notdef 280 static void xl_testpacket(struct xl_softc *); 281 #endif 282 283 static int xl_miibus_readreg(device_t, int, int); 284 static int xl_miibus_writereg(device_t, int, int, int); 285 static void xl_miibus_statchg(device_t); 286 static void xl_miibus_mediainit(device_t); 287 288 static device_method_t xl_methods[] = { 289 /* Device interface */ 290 DEVMETHOD(device_probe, xl_probe), 291 DEVMETHOD(device_attach, xl_attach), 292 DEVMETHOD(device_detach, xl_detach), 293 DEVMETHOD(device_shutdown, xl_shutdown), 294 DEVMETHOD(device_suspend, xl_suspend), 295 DEVMETHOD(device_resume, xl_resume), 296 297 /* bus interface */ 298 DEVMETHOD(bus_print_child, bus_generic_print_child), 299 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 300 301 /* MII interface */ 302 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 303 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 304 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 305 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 306 307 { 0, 0 } 308 }; 309 310 static driver_t xl_driver = { 311 "xl", 312 xl_methods, 313 sizeof(struct xl_softc) 314 }; 315 316 static devclass_t xl_devclass; 317 318 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0); 319 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 320 321 static void 322 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 323 { 324 u_int32_t *paddr; 325 326 paddr = arg; 327 *paddr = segs->ds_addr; 328 } 329 330 /* 331 * Murphy's law says that it's possible the chip can wedge and 332 * the 'command in progress' bit may never clear. Hence, we wait 333 * only a finite amount of time to avoid getting caught in an 334 * infinite loop. Normally this delay routine would be a macro, 335 * but it isn't called during normal operation so we can afford 336 * to make it a function. 337 */ 338 static void 339 xl_wait(struct xl_softc *sc) 340 { 341 register int i; 342 343 for (i = 0; i < XL_TIMEOUT; i++) { 344 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 345 break; 346 } 347 348 if (i == XL_TIMEOUT) 349 device_printf(sc->xl_dev, "command never completed!\n"); 350 } 351 352 /* 353 * MII access routines are provided for adapters with external 354 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 355 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 356 * Note: if you don't perform the MDIO operations just right, 357 * it's possible to end up with code that works correctly with 358 * some chips/CPUs/processor speeds/bus speeds/etc but not 359 * with others. 360 */ 361 #define MII_SET(x) \ 362 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 363 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 364 365 #define MII_CLR(x) \ 366 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 367 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 368 369 /* 370 * Sync the PHYs by setting data bit and strobing the clock 32 times. 371 */ 372 static void 373 xl_mii_sync(struct xl_softc *sc) 374 { 375 register int i; 376 377 XL_SEL_WIN(4); 378 MII_SET(XL_MII_DIR|XL_MII_DATA); 379 380 for (i = 0; i < 32; i++) { 381 MII_SET(XL_MII_CLK); 382 MII_SET(XL_MII_DATA); 383 MII_SET(XL_MII_DATA); 384 MII_CLR(XL_MII_CLK); 385 MII_SET(XL_MII_DATA); 386 MII_SET(XL_MII_DATA); 387 } 388 } 389 390 /* 391 * Clock a series of bits through the MII. 392 */ 393 static void 394 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 395 { 396 int i; 397 398 XL_SEL_WIN(4); 399 MII_CLR(XL_MII_CLK); 400 401 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 402 if (bits & i) { 403 MII_SET(XL_MII_DATA); 404 } else { 405 MII_CLR(XL_MII_DATA); 406 } 407 MII_CLR(XL_MII_CLK); 408 MII_SET(XL_MII_CLK); 409 } 410 } 411 412 /* 413 * Read an PHY register through the MII. 414 */ 415 static int 416 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 417 { 418 int i, ack; 419 420 /* Set up frame for RX. */ 421 frame->mii_stdelim = XL_MII_STARTDELIM; 422 frame->mii_opcode = XL_MII_READOP; 423 frame->mii_turnaround = 0; 424 frame->mii_data = 0; 425 426 /* Select register window 4. */ 427 XL_SEL_WIN(4); 428 429 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 430 /* Turn on data xmit. */ 431 MII_SET(XL_MII_DIR); 432 433 xl_mii_sync(sc); 434 435 /* Send command/address info. */ 436 xl_mii_send(sc, frame->mii_stdelim, 2); 437 xl_mii_send(sc, frame->mii_opcode, 2); 438 xl_mii_send(sc, frame->mii_phyaddr, 5); 439 xl_mii_send(sc, frame->mii_regaddr, 5); 440 441 /* Idle bit */ 442 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 443 MII_SET(XL_MII_CLK); 444 445 /* Turn off xmit. */ 446 MII_CLR(XL_MII_DIR); 447 448 /* Check for ack */ 449 MII_CLR(XL_MII_CLK); 450 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 451 MII_SET(XL_MII_CLK); 452 453 /* 454 * Now try reading data bits. If the ack failed, we still 455 * need to clock through 16 cycles to keep the PHY(s) in sync. 456 */ 457 if (ack) { 458 for (i = 0; i < 16; i++) { 459 MII_CLR(XL_MII_CLK); 460 MII_SET(XL_MII_CLK); 461 } 462 goto fail; 463 } 464 465 for (i = 0x8000; i; i >>= 1) { 466 MII_CLR(XL_MII_CLK); 467 if (!ack) { 468 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 469 frame->mii_data |= i; 470 } 471 MII_SET(XL_MII_CLK); 472 } 473 474 fail: 475 MII_CLR(XL_MII_CLK); 476 MII_SET(XL_MII_CLK); 477 478 return (ack ? 1 : 0); 479 } 480 481 /* 482 * Write to a PHY register through the MII. 483 */ 484 static int 485 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 486 { 487 488 /* Set up frame for TX. */ 489 frame->mii_stdelim = XL_MII_STARTDELIM; 490 frame->mii_opcode = XL_MII_WRITEOP; 491 frame->mii_turnaround = XL_MII_TURNAROUND; 492 493 /* Select the window 4. */ 494 XL_SEL_WIN(4); 495 496 /* Turn on data output. */ 497 MII_SET(XL_MII_DIR); 498 499 xl_mii_sync(sc); 500 501 xl_mii_send(sc, frame->mii_stdelim, 2); 502 xl_mii_send(sc, frame->mii_opcode, 2); 503 xl_mii_send(sc, frame->mii_phyaddr, 5); 504 xl_mii_send(sc, frame->mii_regaddr, 5); 505 xl_mii_send(sc, frame->mii_turnaround, 2); 506 xl_mii_send(sc, frame->mii_data, 16); 507 508 /* Idle bit. */ 509 MII_SET(XL_MII_CLK); 510 MII_CLR(XL_MII_CLK); 511 512 /* Turn off xmit. */ 513 MII_CLR(XL_MII_DIR); 514 515 return (0); 516 } 517 518 static int 519 xl_miibus_readreg(device_t dev, int phy, int reg) 520 { 521 struct xl_softc *sc; 522 struct xl_mii_frame frame; 523 524 sc = device_get_softc(dev); 525 526 bzero((char *)&frame, sizeof(frame)); 527 frame.mii_phyaddr = phy; 528 frame.mii_regaddr = reg; 529 530 xl_mii_readreg(sc, &frame); 531 532 return (frame.mii_data); 533 } 534 535 static int 536 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 537 { 538 struct xl_softc *sc; 539 struct xl_mii_frame frame; 540 541 sc = device_get_softc(dev); 542 543 bzero((char *)&frame, sizeof(frame)); 544 frame.mii_phyaddr = phy; 545 frame.mii_regaddr = reg; 546 frame.mii_data = data; 547 548 xl_mii_writereg(sc, &frame); 549 550 return (0); 551 } 552 553 static void 554 xl_miibus_statchg(device_t dev) 555 { 556 struct xl_softc *sc; 557 struct mii_data *mii; 558 uint8_t macctl; 559 560 sc = device_get_softc(dev); 561 mii = device_get_softc(sc->xl_miibus); 562 563 xl_setcfg(sc); 564 565 /* Set ASIC's duplex mode to match the PHY. */ 566 XL_SEL_WIN(3); 567 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 568 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 569 macctl |= XL_MACCTRL_DUPLEX; 570 if (sc->xl_type == XL_TYPE_905B) { 571 if ((IFM_OPTIONS(mii->mii_media_active) & 572 IFM_ETH_RXPAUSE) != 0) 573 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB; 574 else 575 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 576 } 577 } else { 578 macctl &= ~XL_MACCTRL_DUPLEX; 579 if (sc->xl_type == XL_TYPE_905B) 580 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 581 } 582 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 583 } 584 585 /* 586 * Special support for the 3c905B-COMBO. This card has 10/100 support 587 * plus BNC and AUI ports. This means we will have both an miibus attached 588 * plus some non-MII media settings. In order to allow this, we have to 589 * add the extra media to the miibus's ifmedia struct, but we can't do 590 * that during xl_attach() because the miibus hasn't been attached yet. 591 * So instead, we wait until the miibus probe/attach is done, at which 592 * point we will get a callback telling is that it's safe to add our 593 * extra media. 594 */ 595 static void 596 xl_miibus_mediainit(device_t dev) 597 { 598 struct xl_softc *sc; 599 struct mii_data *mii; 600 struct ifmedia *ifm; 601 602 sc = device_get_softc(dev); 603 mii = device_get_softc(sc->xl_miibus); 604 ifm = &mii->mii_media; 605 606 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 607 /* 608 * Check for a 10baseFL board in disguise. 609 */ 610 if (sc->xl_type == XL_TYPE_905B && 611 sc->xl_media == XL_MEDIAOPT_10FL) { 612 if (bootverbose) 613 device_printf(sc->xl_dev, "found 10baseFL\n"); 614 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 615 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 616 NULL); 617 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 618 ifmedia_add(ifm, 619 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 620 } else { 621 if (bootverbose) 622 device_printf(sc->xl_dev, "found AUI\n"); 623 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 624 } 625 } 626 627 if (sc->xl_media & XL_MEDIAOPT_BNC) { 628 if (bootverbose) 629 device_printf(sc->xl_dev, "found BNC\n"); 630 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 631 } 632 } 633 634 /* 635 * The EEPROM is slow: give it time to come ready after issuing 636 * it a command. 637 */ 638 static int 639 xl_eeprom_wait(struct xl_softc *sc) 640 { 641 int i; 642 643 for (i = 0; i < 100; i++) { 644 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 645 DELAY(162); 646 else 647 break; 648 } 649 650 if (i == 100) { 651 device_printf(sc->xl_dev, "eeprom failed to come ready\n"); 652 return (1); 653 } 654 655 return (0); 656 } 657 658 /* 659 * Read a sequence of words from the EEPROM. Note that ethernet address 660 * data is stored in the EEPROM in network byte order. 661 */ 662 static int 663 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 664 { 665 int err = 0, i; 666 u_int16_t word = 0, *ptr; 667 668 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 669 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 670 /* 671 * XXX: WARNING! DANGER! 672 * It's easy to accidentally overwrite the rom content! 673 * Note: the 3c575 uses 8bit EEPROM offsets. 674 */ 675 XL_SEL_WIN(0); 676 677 if (xl_eeprom_wait(sc)) 678 return (1); 679 680 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 681 off += 0x30; 682 683 for (i = 0; i < cnt; i++) { 684 if (sc->xl_flags & XL_FLAG_8BITROM) 685 CSR_WRITE_2(sc, XL_W0_EE_CMD, 686 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 687 else 688 CSR_WRITE_2(sc, XL_W0_EE_CMD, 689 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 690 err = xl_eeprom_wait(sc); 691 if (err) 692 break; 693 word = CSR_READ_2(sc, XL_W0_EE_DATA); 694 ptr = (u_int16_t *)(dest + (i * 2)); 695 if (swap) 696 *ptr = ntohs(word); 697 else 698 *ptr = word; 699 } 700 701 return (err ? 1 : 0); 702 } 703 704 /* 705 * NICs older than the 3c905B have only one multicast option, which 706 * is to enable reception of all multicast frames. 707 */ 708 static void 709 xl_setmulti(struct xl_softc *sc) 710 { 711 struct ifnet *ifp = sc->xl_ifp; 712 struct ifmultiaddr *ifma; 713 u_int8_t rxfilt; 714 int mcnt = 0; 715 716 XL_LOCK_ASSERT(sc); 717 718 XL_SEL_WIN(5); 719 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 720 721 if (ifp->if_flags & IFF_ALLMULTI) { 722 rxfilt |= XL_RXFILTER_ALLMULTI; 723 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 724 return; 725 } 726 727 if_maddr_rlock(ifp); 728 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 729 mcnt++; 730 if_maddr_runlock(ifp); 731 732 if (mcnt) 733 rxfilt |= XL_RXFILTER_ALLMULTI; 734 else 735 rxfilt &= ~XL_RXFILTER_ALLMULTI; 736 737 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 738 } 739 740 /* 741 * 3c905B adapters have a hash filter that we can program. 742 */ 743 static void 744 xl_setmulti_hash(struct xl_softc *sc) 745 { 746 struct ifnet *ifp = sc->xl_ifp; 747 int h = 0, i; 748 struct ifmultiaddr *ifma; 749 u_int8_t rxfilt; 750 int mcnt = 0; 751 752 XL_LOCK_ASSERT(sc); 753 754 XL_SEL_WIN(5); 755 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 756 757 if (ifp->if_flags & IFF_ALLMULTI) { 758 rxfilt |= XL_RXFILTER_ALLMULTI; 759 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 760 return; 761 } else 762 rxfilt &= ~XL_RXFILTER_ALLMULTI; 763 764 /* first, zot all the existing hash bits */ 765 for (i = 0; i < XL_HASHFILT_SIZE; i++) 766 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 767 768 /* now program new ones */ 769 if_maddr_rlock(ifp); 770 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 771 if (ifma->ifma_addr->sa_family != AF_LINK) 772 continue; 773 /* 774 * Note: the 3c905B currently only supports a 64-bit hash 775 * table, which means we really only need 6 bits, but the 776 * manual indicates that future chip revisions will have a 777 * 256-bit hash table, hence the routine is set up to 778 * calculate 8 bits of position info in case we need it some 779 * day. 780 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have 781 * a 256 bit hash table. This means we have to use all 8 bits 782 * regardless. On older cards, the upper 2 bits will be 783 * ignored. Grrrr.... 784 */ 785 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 786 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 787 CSR_WRITE_2(sc, XL_COMMAND, 788 h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 789 mcnt++; 790 } 791 if_maddr_runlock(ifp); 792 793 if (mcnt) 794 rxfilt |= XL_RXFILTER_MULTIHASH; 795 else 796 rxfilt &= ~XL_RXFILTER_MULTIHASH; 797 798 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 799 } 800 801 static void 802 xl_setcfg(struct xl_softc *sc) 803 { 804 u_int32_t icfg; 805 806 /*XL_LOCK_ASSERT(sc);*/ 807 808 XL_SEL_WIN(3); 809 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 810 icfg &= ~XL_ICFG_CONNECTOR_MASK; 811 if (sc->xl_media & XL_MEDIAOPT_MII || 812 sc->xl_media & XL_MEDIAOPT_BT4) 813 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 814 if (sc->xl_media & XL_MEDIAOPT_BTX) 815 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 816 817 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 819 } 820 821 static void 822 xl_setmode(struct xl_softc *sc, int media) 823 { 824 u_int32_t icfg; 825 u_int16_t mediastat; 826 char *pmsg = "", *dmsg = ""; 827 828 XL_LOCK_ASSERT(sc); 829 830 XL_SEL_WIN(4); 831 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 832 XL_SEL_WIN(3); 833 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 834 835 if (sc->xl_media & XL_MEDIAOPT_BT) { 836 if (IFM_SUBTYPE(media) == IFM_10_T) { 837 pmsg = "10baseT transceiver"; 838 sc->xl_xcvr = XL_XCVR_10BT; 839 icfg &= ~XL_ICFG_CONNECTOR_MASK; 840 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 841 mediastat |= XL_MEDIASTAT_LINKBEAT | 842 XL_MEDIASTAT_JABGUARD; 843 mediastat &= ~XL_MEDIASTAT_SQEENB; 844 } 845 } 846 847 if (sc->xl_media & XL_MEDIAOPT_BFX) { 848 if (IFM_SUBTYPE(media) == IFM_100_FX) { 849 pmsg = "100baseFX port"; 850 sc->xl_xcvr = XL_XCVR_100BFX; 851 icfg &= ~XL_ICFG_CONNECTOR_MASK; 852 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 853 mediastat |= XL_MEDIASTAT_LINKBEAT; 854 mediastat &= ~XL_MEDIASTAT_SQEENB; 855 } 856 } 857 858 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 859 if (IFM_SUBTYPE(media) == IFM_10_5) { 860 pmsg = "AUI port"; 861 sc->xl_xcvr = XL_XCVR_AUI; 862 icfg &= ~XL_ICFG_CONNECTOR_MASK; 863 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 864 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 865 XL_MEDIASTAT_JABGUARD); 866 mediastat |= ~XL_MEDIASTAT_SQEENB; 867 } 868 if (IFM_SUBTYPE(media) == IFM_10_FL) { 869 pmsg = "10baseFL transceiver"; 870 sc->xl_xcvr = XL_XCVR_AUI; 871 icfg &= ~XL_ICFG_CONNECTOR_MASK; 872 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 873 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 874 XL_MEDIASTAT_JABGUARD); 875 mediastat |= ~XL_MEDIASTAT_SQEENB; 876 } 877 } 878 879 if (sc->xl_media & XL_MEDIAOPT_BNC) { 880 if (IFM_SUBTYPE(media) == IFM_10_2) { 881 pmsg = "AUI port"; 882 sc->xl_xcvr = XL_XCVR_COAX; 883 icfg &= ~XL_ICFG_CONNECTOR_MASK; 884 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 885 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 886 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 887 } 888 } 889 890 if ((media & IFM_GMASK) == IFM_FDX || 891 IFM_SUBTYPE(media) == IFM_100_FX) { 892 dmsg = "full"; 893 XL_SEL_WIN(3); 894 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 895 } else { 896 dmsg = "half"; 897 XL_SEL_WIN(3); 898 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 899 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 900 } 901 902 if (IFM_SUBTYPE(media) == IFM_10_2) 903 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 904 else 905 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 906 907 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 908 XL_SEL_WIN(4); 909 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 910 911 DELAY(800); 912 XL_SEL_WIN(7); 913 914 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg); 915 } 916 917 static void 918 xl_reset(struct xl_softc *sc) 919 { 920 register int i; 921 922 XL_LOCK_ASSERT(sc); 923 924 XL_SEL_WIN(0); 925 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 926 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 927 XL_RESETOPT_DISADVFD:0)); 928 929 /* 930 * If we're using memory mapped register mode, pause briefly 931 * after issuing the reset command before trying to access any 932 * other registers. With my 3c575C CardBus card, failing to do 933 * this results in the system locking up while trying to poll 934 * the command busy bit in the status register. 935 */ 936 if (sc->xl_flags & XL_FLAG_USE_MMIO) 937 DELAY(100000); 938 939 for (i = 0; i < XL_TIMEOUT; i++) { 940 DELAY(10); 941 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 942 break; 943 } 944 945 if (i == XL_TIMEOUT) 946 device_printf(sc->xl_dev, "reset didn't complete\n"); 947 948 /* Reset TX and RX. */ 949 /* Note: the RX reset takes an absurd amount of time 950 * on newer versions of the Tornado chips such as those 951 * on the 3c905CX and newer 3c908C cards. We wait an 952 * extra amount of time so that xl_wait() doesn't complain 953 * and annoy the users. 954 */ 955 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 956 DELAY(100000); 957 xl_wait(sc); 958 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 959 xl_wait(sc); 960 961 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 962 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 963 XL_SEL_WIN(2); 964 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 965 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 966 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 967 XL_RESETOPT_INVERT_LED : 0) | 968 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 969 XL_RESETOPT_INVERT_MII : 0)); 970 } 971 972 /* Wait a little while for the chip to get its brains in order. */ 973 DELAY(100000); 974 } 975 976 /* 977 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 978 * IDs against our list and return a device name if we find a match. 979 */ 980 static int 981 xl_probe(device_t dev) 982 { 983 const struct xl_type *t; 984 985 t = xl_devs; 986 987 while (t->xl_name != NULL) { 988 if ((pci_get_vendor(dev) == t->xl_vid) && 989 (pci_get_device(dev) == t->xl_did)) { 990 device_set_desc(dev, t->xl_name); 991 return (BUS_PROBE_DEFAULT); 992 } 993 t++; 994 } 995 996 return (ENXIO); 997 } 998 999 /* 1000 * This routine is a kludge to work around possible hardware faults 1001 * or manufacturing defects that can cause the media options register 1002 * (or reset options register, as it's called for the first generation 1003 * 3c90x adapters) to return an incorrect result. I have encountered 1004 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1005 * which doesn't have any of the 'mediaopt' bits set. This screws up 1006 * the attach routine pretty badly because it doesn't know what media 1007 * to look for. If we find ourselves in this predicament, this routine 1008 * will try to guess the media options values and warn the user of a 1009 * possible manufacturing defect with his adapter/system/whatever. 1010 */ 1011 static void 1012 xl_mediacheck(struct xl_softc *sc) 1013 { 1014 1015 /* 1016 * If some of the media options bits are set, assume they are 1017 * correct. If not, try to figure it out down below. 1018 * XXX I should check for 10baseFL, but I don't have an adapter 1019 * to test with. 1020 */ 1021 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1022 /* 1023 * Check the XCVR value. If it's not in the normal range 1024 * of values, we need to fake it up here. 1025 */ 1026 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1027 return; 1028 else { 1029 device_printf(sc->xl_dev, 1030 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 1031 device_printf(sc->xl_dev, 1032 "choosing new default based on card type\n"); 1033 } 1034 } else { 1035 if (sc->xl_type == XL_TYPE_905B && 1036 sc->xl_media & XL_MEDIAOPT_10FL) 1037 return; 1038 device_printf(sc->xl_dev, 1039 "WARNING: no media options bits set in the media options register!!\n"); 1040 device_printf(sc->xl_dev, 1041 "this could be a manufacturing defect in your adapter or system\n"); 1042 device_printf(sc->xl_dev, 1043 "attempting to guess media type; you should probably consult your vendor\n"); 1044 } 1045 1046 xl_choose_xcvr(sc, 1); 1047 } 1048 1049 static void 1050 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1051 { 1052 u_int16_t devid; 1053 1054 /* 1055 * Read the device ID from the EEPROM. 1056 * This is what's loaded into the PCI device ID register, so it has 1057 * to be correct otherwise we wouldn't have gotten this far. 1058 */ 1059 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1060 1061 switch (devid) { 1062 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1063 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1064 sc->xl_media = XL_MEDIAOPT_BT; 1065 sc->xl_xcvr = XL_XCVR_10BT; 1066 if (verbose) 1067 device_printf(sc->xl_dev, 1068 "guessing 10BaseT transceiver\n"); 1069 break; 1070 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1071 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1072 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1073 sc->xl_xcvr = XL_XCVR_10BT; 1074 if (verbose) 1075 device_printf(sc->xl_dev, 1076 "guessing COMBO (AUI/BNC/TP)\n"); 1077 break; 1078 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1079 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1080 sc->xl_xcvr = XL_XCVR_10BT; 1081 if (verbose) 1082 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n"); 1083 break; 1084 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1085 sc->xl_media = XL_MEDIAOPT_10FL; 1086 sc->xl_xcvr = XL_XCVR_AUI; 1087 if (verbose) 1088 device_printf(sc->xl_dev, "guessing 10baseFL\n"); 1089 break; 1090 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1091 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1092 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1093 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1094 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1095 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1096 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1097 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1098 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1099 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1100 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1101 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1102 sc->xl_media = XL_MEDIAOPT_MII; 1103 sc->xl_xcvr = XL_XCVR_MII; 1104 if (verbose) 1105 device_printf(sc->xl_dev, "guessing MII\n"); 1106 break; 1107 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1108 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1109 sc->xl_media = XL_MEDIAOPT_BT4; 1110 sc->xl_xcvr = XL_XCVR_MII; 1111 if (verbose) 1112 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n"); 1113 break; 1114 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1115 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1116 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1117 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1118 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1119 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1120 sc->xl_media = XL_MEDIAOPT_BTX; 1121 sc->xl_xcvr = XL_XCVR_AUTO; 1122 if (verbose) 1123 device_printf(sc->xl_dev, "guessing 10/100 internal\n"); 1124 break; 1125 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1126 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1127 sc->xl_xcvr = XL_XCVR_AUTO; 1128 if (verbose) 1129 device_printf(sc->xl_dev, 1130 "guessing 10/100 plus BNC/AUI\n"); 1131 break; 1132 default: 1133 device_printf(sc->xl_dev, 1134 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1135 sc->xl_media = XL_MEDIAOPT_BT; 1136 break; 1137 } 1138 } 1139 1140 /* 1141 * Attach the interface. Allocate softc structures, do ifmedia 1142 * setup and ethernet/BPF attach. 1143 */ 1144 static int 1145 xl_attach(device_t dev) 1146 { 1147 u_char eaddr[ETHER_ADDR_LEN]; 1148 u_int16_t sinfo2, xcvr[2]; 1149 struct xl_softc *sc; 1150 struct ifnet *ifp; 1151 int media, pmcap; 1152 int error = 0, phy, rid, res, unit; 1153 uint16_t did; 1154 1155 sc = device_get_softc(dev); 1156 sc->xl_dev = dev; 1157 1158 unit = device_get_unit(dev); 1159 1160 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1161 MTX_DEF); 1162 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1163 1164 did = pci_get_device(dev); 1165 1166 sc->xl_flags = 0; 1167 if (did == TC_DEVICEID_HURRICANE_555) 1168 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1169 if (did == TC_DEVICEID_HURRICANE_556 || 1170 did == TC_DEVICEID_HURRICANE_556B) 1171 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1172 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1173 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1174 if (did == TC_DEVICEID_HURRICANE_555 || 1175 did == TC_DEVICEID_HURRICANE_556) 1176 sc->xl_flags |= XL_FLAG_8BITROM; 1177 if (did == TC_DEVICEID_HURRICANE_556B) 1178 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1179 1180 if (did == TC_DEVICEID_HURRICANE_575B || 1181 did == TC_DEVICEID_HURRICANE_575C || 1182 did == TC_DEVICEID_HURRICANE_656B || 1183 did == TC_DEVICEID_TORNADO_656C) 1184 sc->xl_flags |= XL_FLAG_FUNCREG; 1185 if (did == TC_DEVICEID_HURRICANE_575A || 1186 did == TC_DEVICEID_HURRICANE_575B || 1187 did == TC_DEVICEID_HURRICANE_575C || 1188 did == TC_DEVICEID_HURRICANE_656B || 1189 did == TC_DEVICEID_TORNADO_656C) 1190 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1191 XL_FLAG_8BITROM; 1192 if (did == TC_DEVICEID_HURRICANE_656) 1193 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1194 if (did == TC_DEVICEID_HURRICANE_575B) 1195 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1196 if (did == TC_DEVICEID_HURRICANE_575C) 1197 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1198 if (did == TC_DEVICEID_TORNADO_656C) 1199 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1200 if (did == TC_DEVICEID_HURRICANE_656 || 1201 did == TC_DEVICEID_HURRICANE_656B) 1202 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1203 XL_FLAG_INVERT_LED_PWR; 1204 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1205 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1206 sc->xl_flags |= XL_FLAG_PHYOK; 1207 1208 switch (did) { 1209 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1210 case TC_DEVICEID_HURRICANE_575A: 1211 case TC_DEVICEID_HURRICANE_575B: 1212 case TC_DEVICEID_HURRICANE_575C: 1213 sc->xl_flags |= XL_FLAG_NO_MMIO; 1214 break; 1215 default: 1216 break; 1217 } 1218 1219 /* 1220 * Map control/status registers. 1221 */ 1222 pci_enable_busmaster(dev); 1223 1224 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1225 rid = XL_PCI_LOMEM; 1226 res = SYS_RES_MEMORY; 1227 1228 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1229 } 1230 1231 if (sc->xl_res != NULL) { 1232 sc->xl_flags |= XL_FLAG_USE_MMIO; 1233 if (bootverbose) 1234 device_printf(dev, "using memory mapped I/O\n"); 1235 } else { 1236 rid = XL_PCI_LOIO; 1237 res = SYS_RES_IOPORT; 1238 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1239 if (sc->xl_res == NULL) { 1240 device_printf(dev, "couldn't map ports/memory\n"); 1241 error = ENXIO; 1242 goto fail; 1243 } 1244 if (bootverbose) 1245 device_printf(dev, "using port I/O\n"); 1246 } 1247 1248 sc->xl_btag = rman_get_bustag(sc->xl_res); 1249 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1250 1251 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1252 rid = XL_PCI_FUNCMEM; 1253 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1254 RF_ACTIVE); 1255 1256 if (sc->xl_fres == NULL) { 1257 device_printf(dev, "couldn't map funcreg memory\n"); 1258 error = ENXIO; 1259 goto fail; 1260 } 1261 1262 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1263 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1264 } 1265 1266 /* Allocate interrupt */ 1267 rid = 0; 1268 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1269 RF_SHAREABLE | RF_ACTIVE); 1270 if (sc->xl_irq == NULL) { 1271 device_printf(dev, "couldn't map interrupt\n"); 1272 error = ENXIO; 1273 goto fail; 1274 } 1275 1276 /* Initialize interface name. */ 1277 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1278 if (ifp == NULL) { 1279 device_printf(dev, "can not if_alloc()\n"); 1280 error = ENOSPC; 1281 goto fail; 1282 } 1283 ifp->if_softc = sc; 1284 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1285 1286 /* Reset the adapter. */ 1287 XL_LOCK(sc); 1288 xl_reset(sc); 1289 XL_UNLOCK(sc); 1290 1291 /* 1292 * Get station address from the EEPROM. 1293 */ 1294 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1295 device_printf(dev, "failed to read station address\n"); 1296 error = ENXIO; 1297 goto fail; 1298 } 1299 1300 callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0); 1301 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1302 1303 /* 1304 * Now allocate a tag for the DMA descriptor lists and a chunk 1305 * of DMA-able memory based on the tag. Also obtain the DMA 1306 * addresses of the RX and TX ring, which we'll need later. 1307 * All of our lists are allocated as a contiguous block 1308 * of memory. 1309 */ 1310 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1311 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1312 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1313 &sc->xl_ldata.xl_rx_tag); 1314 if (error) { 1315 device_printf(dev, "failed to allocate rx dma tag\n"); 1316 goto fail; 1317 } 1318 1319 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1320 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | 1321 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap); 1322 if (error) { 1323 device_printf(dev, "no memory for rx list buffers!\n"); 1324 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1325 sc->xl_ldata.xl_rx_tag = NULL; 1326 goto fail; 1327 } 1328 1329 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1330 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1331 XL_RX_LIST_SZ, xl_dma_map_addr, 1332 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1333 if (error) { 1334 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1335 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1336 sc->xl_ldata.xl_rx_dmamap); 1337 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1338 sc->xl_ldata.xl_rx_tag = NULL; 1339 goto fail; 1340 } 1341 1342 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1343 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1344 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1345 &sc->xl_ldata.xl_tx_tag); 1346 if (error) { 1347 device_printf(dev, "failed to allocate tx dma tag\n"); 1348 goto fail; 1349 } 1350 1351 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1352 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | 1353 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap); 1354 if (error) { 1355 device_printf(dev, "no memory for list buffers!\n"); 1356 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1357 sc->xl_ldata.xl_tx_tag = NULL; 1358 goto fail; 1359 } 1360 1361 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1362 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1363 XL_TX_LIST_SZ, xl_dma_map_addr, 1364 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1365 if (error) { 1366 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1367 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1368 sc->xl_ldata.xl_tx_dmamap); 1369 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1370 sc->xl_ldata.xl_tx_tag = NULL; 1371 goto fail; 1372 } 1373 1374 /* 1375 * Allocate a DMA tag for the mapping of mbufs. 1376 */ 1377 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1378 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1379 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1380 NULL, &sc->xl_mtag); 1381 if (error) { 1382 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1383 goto fail; 1384 } 1385 1386 /* We need a spare DMA map for the RX ring. */ 1387 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1388 if (error) 1389 goto fail; 1390 1391 /* 1392 * Figure out the card type. 3c905B adapters have the 1393 * 'supportsNoTxLength' bit set in the capabilities 1394 * word in the EEPROM. 1395 * Note: my 3c575C CardBus card lies. It returns a value 1396 * of 0x1578 for its capabilities word, which is somewhat 1397 * nonsensical. Another way to distinguish a 3c90x chip 1398 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1399 * bit. This will only be set for 3c90x boomerage chips. 1400 */ 1401 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1402 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1403 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1404 sc->xl_type = XL_TYPE_905B; 1405 else 1406 sc->xl_type = XL_TYPE_90X; 1407 1408 /* Check availability of WOL. */ 1409 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 && 1410 pci_find_extcap(dev, PCIY_PMG, &pmcap) == 0) { 1411 sc->xl_pmcap = pmcap; 1412 sc->xl_flags |= XL_FLAG_WOL; 1413 sinfo2 = 0; 1414 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0); 1415 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose) 1416 device_printf(dev, 1417 "No auxiliary remote wakeup connector!\n"); 1418 } 1419 1420 /* Set the TX start threshold for best performance. */ 1421 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1422 1423 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1424 ifp->if_ioctl = xl_ioctl; 1425 ifp->if_capabilities = IFCAP_VLAN_MTU; 1426 if (sc->xl_type == XL_TYPE_905B) { 1427 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1428 #ifdef XL905B_TXCSUM_BROKEN 1429 ifp->if_capabilities |= IFCAP_RXCSUM; 1430 #else 1431 ifp->if_capabilities |= IFCAP_HWCSUM; 1432 #endif 1433 } 1434 if ((sc->xl_flags & XL_FLAG_WOL) != 0) 1435 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1436 ifp->if_capenable = ifp->if_capabilities; 1437 #ifdef DEVICE_POLLING 1438 ifp->if_capabilities |= IFCAP_POLLING; 1439 #endif 1440 ifp->if_start = xl_start; 1441 ifp->if_init = xl_init; 1442 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1443 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1; 1444 IFQ_SET_READY(&ifp->if_snd); 1445 1446 /* 1447 * Now we have to see what sort of media we have. 1448 * This includes probing for an MII interace and a 1449 * possible PHY. 1450 */ 1451 XL_SEL_WIN(3); 1452 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1453 if (bootverbose) 1454 device_printf(dev, "media options word: %x\n", sc->xl_media); 1455 1456 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1457 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1458 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1459 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1460 1461 xl_mediacheck(sc); 1462 1463 if (sc->xl_media & XL_MEDIAOPT_MII || 1464 sc->xl_media & XL_MEDIAOPT_BTX || 1465 sc->xl_media & XL_MEDIAOPT_BT4) { 1466 if (bootverbose) 1467 device_printf(dev, "found MII/AUTO\n"); 1468 xl_setcfg(sc); 1469 /* 1470 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK. 1471 * This is to guard against problems with certain 3Com ASIC 1472 * revisions that incorrectly map the internal transceiver 1473 * control registers at all MII addresses. 1474 */ 1475 phy = MII_PHY_ANY; 1476 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0) 1477 phy = 24; 1478 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd, 1479 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 1480 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0); 1481 if (error != 0) { 1482 device_printf(dev, "attaching PHYs failed\n"); 1483 goto fail; 1484 } 1485 goto done; 1486 } 1487 1488 /* 1489 * Sanity check. If the user has selected "auto" and this isn't 1490 * a 10/100 card of some kind, we need to force the transceiver 1491 * type to something sane. 1492 */ 1493 if (sc->xl_xcvr == XL_XCVR_AUTO) 1494 xl_choose_xcvr(sc, bootverbose); 1495 1496 /* 1497 * Do ifmedia setup. 1498 */ 1499 if (sc->xl_media & XL_MEDIAOPT_BT) { 1500 if (bootverbose) 1501 device_printf(dev, "found 10baseT\n"); 1502 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1503 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1504 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1505 ifmedia_add(&sc->ifmedia, 1506 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1507 } 1508 1509 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1510 /* 1511 * Check for a 10baseFL board in disguise. 1512 */ 1513 if (sc->xl_type == XL_TYPE_905B && 1514 sc->xl_media == XL_MEDIAOPT_10FL) { 1515 if (bootverbose) 1516 device_printf(dev, "found 10baseFL\n"); 1517 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1518 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1519 0, NULL); 1520 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1521 ifmedia_add(&sc->ifmedia, 1522 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1523 } else { 1524 if (bootverbose) 1525 device_printf(dev, "found AUI\n"); 1526 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1527 } 1528 } 1529 1530 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1531 if (bootverbose) 1532 device_printf(dev, "found BNC\n"); 1533 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1534 } 1535 1536 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1537 if (bootverbose) 1538 device_printf(dev, "found 100baseFX\n"); 1539 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1540 } 1541 1542 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1543 xl_choose_media(sc, &media); 1544 1545 if (sc->xl_miibus == NULL) 1546 ifmedia_set(&sc->ifmedia, media); 1547 1548 done: 1549 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1550 XL_SEL_WIN(0); 1551 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1552 } 1553 1554 /* 1555 * Call MI attach routine. 1556 */ 1557 ether_ifattach(ifp, eaddr); 1558 1559 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1560 NULL, xl_intr, sc, &sc->xl_intrhand); 1561 if (error) { 1562 device_printf(dev, "couldn't set up irq\n"); 1563 ether_ifdetach(ifp); 1564 goto fail; 1565 } 1566 1567 fail: 1568 if (error) 1569 xl_detach(dev); 1570 1571 return (error); 1572 } 1573 1574 /* 1575 * Choose a default media. 1576 * XXX This is a leaf function only called by xl_attach() and 1577 * acquires/releases the non-recursible driver mutex to 1578 * satisfy lock assertions. 1579 */ 1580 static void 1581 xl_choose_media(struct xl_softc *sc, int *media) 1582 { 1583 1584 XL_LOCK(sc); 1585 1586 switch (sc->xl_xcvr) { 1587 case XL_XCVR_10BT: 1588 *media = IFM_ETHER|IFM_10_T; 1589 xl_setmode(sc, *media); 1590 break; 1591 case XL_XCVR_AUI: 1592 if (sc->xl_type == XL_TYPE_905B && 1593 sc->xl_media == XL_MEDIAOPT_10FL) { 1594 *media = IFM_ETHER|IFM_10_FL; 1595 xl_setmode(sc, *media); 1596 } else { 1597 *media = IFM_ETHER|IFM_10_5; 1598 xl_setmode(sc, *media); 1599 } 1600 break; 1601 case XL_XCVR_COAX: 1602 *media = IFM_ETHER|IFM_10_2; 1603 xl_setmode(sc, *media); 1604 break; 1605 case XL_XCVR_AUTO: 1606 case XL_XCVR_100BTX: 1607 case XL_XCVR_MII: 1608 /* Chosen by miibus */ 1609 break; 1610 case XL_XCVR_100BFX: 1611 *media = IFM_ETHER|IFM_100_FX; 1612 break; 1613 default: 1614 device_printf(sc->xl_dev, "unknown XCVR type: %d\n", 1615 sc->xl_xcvr); 1616 /* 1617 * This will probably be wrong, but it prevents 1618 * the ifmedia code from panicking. 1619 */ 1620 *media = IFM_ETHER|IFM_10_T; 1621 break; 1622 } 1623 1624 XL_UNLOCK(sc); 1625 } 1626 1627 /* 1628 * Shutdown hardware and free up resources. This can be called any 1629 * time after the mutex has been initialized. It is called in both 1630 * the error case in attach and the normal detach case so it needs 1631 * to be careful about only freeing resources that have actually been 1632 * allocated. 1633 */ 1634 static int 1635 xl_detach(device_t dev) 1636 { 1637 struct xl_softc *sc; 1638 struct ifnet *ifp; 1639 int rid, res; 1640 1641 sc = device_get_softc(dev); 1642 ifp = sc->xl_ifp; 1643 1644 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1645 1646 #ifdef DEVICE_POLLING 1647 if (ifp && ifp->if_capenable & IFCAP_POLLING) 1648 ether_poll_deregister(ifp); 1649 #endif 1650 1651 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1652 rid = XL_PCI_LOMEM; 1653 res = SYS_RES_MEMORY; 1654 } else { 1655 rid = XL_PCI_LOIO; 1656 res = SYS_RES_IOPORT; 1657 } 1658 1659 /* These should only be active if attach succeeded */ 1660 if (device_is_attached(dev)) { 1661 XL_LOCK(sc); 1662 xl_stop(sc); 1663 XL_UNLOCK(sc); 1664 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1665 callout_drain(&sc->xl_stat_callout); 1666 ether_ifdetach(ifp); 1667 } 1668 if (sc->xl_miibus) 1669 device_delete_child(dev, sc->xl_miibus); 1670 bus_generic_detach(dev); 1671 ifmedia_removeall(&sc->ifmedia); 1672 1673 if (sc->xl_intrhand) 1674 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1675 if (sc->xl_irq) 1676 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1677 if (sc->xl_fres != NULL) 1678 bus_release_resource(dev, SYS_RES_MEMORY, 1679 XL_PCI_FUNCMEM, sc->xl_fres); 1680 if (sc->xl_res) 1681 bus_release_resource(dev, res, rid, sc->xl_res); 1682 1683 if (ifp) 1684 if_free(ifp); 1685 1686 if (sc->xl_mtag) { 1687 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1688 bus_dma_tag_destroy(sc->xl_mtag); 1689 } 1690 if (sc->xl_ldata.xl_rx_tag) { 1691 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1692 sc->xl_ldata.xl_rx_dmamap); 1693 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1694 sc->xl_ldata.xl_rx_dmamap); 1695 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1696 } 1697 if (sc->xl_ldata.xl_tx_tag) { 1698 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1699 sc->xl_ldata.xl_tx_dmamap); 1700 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1701 sc->xl_ldata.xl_tx_dmamap); 1702 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1703 } 1704 1705 mtx_destroy(&sc->xl_mtx); 1706 1707 return (0); 1708 } 1709 1710 /* 1711 * Initialize the transmit descriptors. 1712 */ 1713 static int 1714 xl_list_tx_init(struct xl_softc *sc) 1715 { 1716 struct xl_chain_data *cd; 1717 struct xl_list_data *ld; 1718 int error, i; 1719 1720 XL_LOCK_ASSERT(sc); 1721 1722 cd = &sc->xl_cdata; 1723 ld = &sc->xl_ldata; 1724 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1725 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1726 error = bus_dmamap_create(sc->xl_mtag, 0, 1727 &cd->xl_tx_chain[i].xl_map); 1728 if (error) 1729 return (error); 1730 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1731 i * sizeof(struct xl_list); 1732 if (i == (XL_TX_LIST_CNT - 1)) 1733 cd->xl_tx_chain[i].xl_next = NULL; 1734 else 1735 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1736 } 1737 1738 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1739 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1740 1741 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1742 return (0); 1743 } 1744 1745 /* 1746 * Initialize the transmit descriptors. 1747 */ 1748 static int 1749 xl_list_tx_init_90xB(struct xl_softc *sc) 1750 { 1751 struct xl_chain_data *cd; 1752 struct xl_list_data *ld; 1753 int error, i; 1754 1755 XL_LOCK_ASSERT(sc); 1756 1757 cd = &sc->xl_cdata; 1758 ld = &sc->xl_ldata; 1759 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1760 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1761 error = bus_dmamap_create(sc->xl_mtag, 0, 1762 &cd->xl_tx_chain[i].xl_map); 1763 if (error) 1764 return (error); 1765 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1766 i * sizeof(struct xl_list); 1767 if (i == (XL_TX_LIST_CNT - 1)) 1768 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1769 else 1770 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1771 if (i == 0) 1772 cd->xl_tx_chain[i].xl_prev = 1773 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1774 else 1775 cd->xl_tx_chain[i].xl_prev = 1776 &cd->xl_tx_chain[i - 1]; 1777 } 1778 1779 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1780 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1781 1782 cd->xl_tx_prod = 1; 1783 cd->xl_tx_cons = 1; 1784 cd->xl_tx_cnt = 0; 1785 1786 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1787 return (0); 1788 } 1789 1790 /* 1791 * Initialize the RX descriptors and allocate mbufs for them. Note that 1792 * we arrange the descriptors in a closed ring, so that the last descriptor 1793 * points back to the first. 1794 */ 1795 static int 1796 xl_list_rx_init(struct xl_softc *sc) 1797 { 1798 struct xl_chain_data *cd; 1799 struct xl_list_data *ld; 1800 int error, i, next; 1801 u_int32_t nextptr; 1802 1803 XL_LOCK_ASSERT(sc); 1804 1805 cd = &sc->xl_cdata; 1806 ld = &sc->xl_ldata; 1807 1808 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1809 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1810 error = bus_dmamap_create(sc->xl_mtag, 0, 1811 &cd->xl_rx_chain[i].xl_map); 1812 if (error) 1813 return (error); 1814 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1815 if (error) 1816 return (error); 1817 if (i == (XL_RX_LIST_CNT - 1)) 1818 next = 0; 1819 else 1820 next = i + 1; 1821 nextptr = ld->xl_rx_dmaaddr + 1822 next * sizeof(struct xl_list_onefrag); 1823 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1824 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1825 } 1826 1827 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1828 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1829 1830 return (0); 1831 } 1832 1833 /* 1834 * Initialize an RX descriptor and attach an MBUF cluster. 1835 * If we fail to do so, we need to leave the old mbuf and 1836 * the old DMA map untouched so that it can be reused. 1837 */ 1838 static int 1839 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1840 { 1841 struct mbuf *m_new = NULL; 1842 bus_dmamap_t map; 1843 bus_dma_segment_t segs[1]; 1844 int error, nseg; 1845 1846 XL_LOCK_ASSERT(sc); 1847 1848 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1849 if (m_new == NULL) 1850 return (ENOBUFS); 1851 1852 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1853 1854 /* Force longword alignment for packet payload. */ 1855 m_adj(m_new, ETHER_ALIGN); 1856 1857 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, 1858 segs, &nseg, BUS_DMA_NOWAIT); 1859 if (error) { 1860 m_freem(m_new); 1861 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", 1862 error); 1863 return (error); 1864 } 1865 KASSERT(nseg == 1, 1866 ("%s: too many DMA segments (%d)", __func__, nseg)); 1867 1868 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1869 map = c->xl_map; 1870 c->xl_map = sc->xl_tmpmap; 1871 sc->xl_tmpmap = map; 1872 c->xl_mbuf = m_new; 1873 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1874 c->xl_ptr->xl_status = 0; 1875 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); 1876 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1877 return (0); 1878 } 1879 1880 static int 1881 xl_rx_resync(struct xl_softc *sc) 1882 { 1883 struct xl_chain_onefrag *pos; 1884 int i; 1885 1886 XL_LOCK_ASSERT(sc); 1887 1888 pos = sc->xl_cdata.xl_rx_head; 1889 1890 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1891 if (pos->xl_ptr->xl_status) 1892 break; 1893 pos = pos->xl_next; 1894 } 1895 1896 if (i == XL_RX_LIST_CNT) 1897 return (0); 1898 1899 sc->xl_cdata.xl_rx_head = pos; 1900 1901 return (EAGAIN); 1902 } 1903 1904 /* 1905 * A frame has been uploaded: pass the resulting mbuf chain up to 1906 * the higher level protocols. 1907 */ 1908 static int 1909 xl_rxeof(struct xl_softc *sc) 1910 { 1911 struct mbuf *m; 1912 struct ifnet *ifp = sc->xl_ifp; 1913 struct xl_chain_onefrag *cur_rx; 1914 int total_len = 0; 1915 int rx_npkts = 0; 1916 u_int32_t rxstat; 1917 1918 XL_LOCK_ASSERT(sc); 1919 again: 1920 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1921 BUS_DMASYNC_POSTREAD); 1922 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1923 #ifdef DEVICE_POLLING 1924 if (ifp->if_capenable & IFCAP_POLLING) { 1925 if (sc->rxcycles <= 0) 1926 break; 1927 sc->rxcycles--; 1928 } 1929 #endif 1930 cur_rx = sc->xl_cdata.xl_rx_head; 1931 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1932 total_len = rxstat & XL_RXSTAT_LENMASK; 1933 1934 /* 1935 * Since we have told the chip to allow large frames, 1936 * we need to trap giant frame errors in software. We allow 1937 * a little more than the normal frame size to account for 1938 * frames with VLAN tags. 1939 */ 1940 if (total_len > XL_MAX_FRAMELEN) 1941 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1942 1943 /* 1944 * If an error occurs, update stats, clear the 1945 * status word and leave the mbuf cluster in place: 1946 * it should simply get re-used next time this descriptor 1947 * comes up in the ring. 1948 */ 1949 if (rxstat & XL_RXSTAT_UP_ERROR) { 1950 ifp->if_ierrors++; 1951 cur_rx->xl_ptr->xl_status = 0; 1952 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1953 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1954 continue; 1955 } 1956 1957 /* 1958 * If the error bit was not set, the upload complete 1959 * bit should be set which means we have a valid packet. 1960 * If not, something truly strange has happened. 1961 */ 1962 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1963 device_printf(sc->xl_dev, 1964 "bad receive status -- packet dropped\n"); 1965 ifp->if_ierrors++; 1966 cur_rx->xl_ptr->xl_status = 0; 1967 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1968 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1969 continue; 1970 } 1971 1972 /* No errors; receive the packet. */ 1973 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 1974 BUS_DMASYNC_POSTREAD); 1975 m = cur_rx->xl_mbuf; 1976 1977 /* 1978 * Try to conjure up a new mbuf cluster. If that 1979 * fails, it means we have an out of memory condition and 1980 * should leave the buffer in place and continue. This will 1981 * result in a lost packet, but there's little else we 1982 * can do in this situation. 1983 */ 1984 if (xl_newbuf(sc, cur_rx)) { 1985 ifp->if_ierrors++; 1986 cur_rx->xl_ptr->xl_status = 0; 1987 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1988 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1989 continue; 1990 } 1991 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1992 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1993 1994 ifp->if_ipackets++; 1995 m->m_pkthdr.rcvif = ifp; 1996 m->m_pkthdr.len = m->m_len = total_len; 1997 1998 if (ifp->if_capenable & IFCAP_RXCSUM) { 1999 /* Do IP checksum checking. */ 2000 if (rxstat & XL_RXSTAT_IPCKOK) 2001 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2002 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2003 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2004 if ((rxstat & XL_RXSTAT_TCPCOK && 2005 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2006 (rxstat & XL_RXSTAT_UDPCKOK && 2007 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2008 m->m_pkthdr.csum_flags |= 2009 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2010 m->m_pkthdr.csum_data = 0xffff; 2011 } 2012 } 2013 2014 XL_UNLOCK(sc); 2015 (*ifp->if_input)(ifp, m); 2016 XL_LOCK(sc); 2017 rx_npkts++; 2018 2019 /* 2020 * If we are running from the taskqueue, the interface 2021 * might have been stopped while we were passing the last 2022 * packet up the network stack. 2023 */ 2024 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 2025 return (rx_npkts); 2026 } 2027 2028 /* 2029 * Handle the 'end of channel' condition. When the upload 2030 * engine hits the end of the RX ring, it will stall. This 2031 * is our cue to flush the RX ring, reload the uplist pointer 2032 * register and unstall the engine. 2033 * XXX This is actually a little goofy. With the ThunderLAN 2034 * chip, you get an interrupt when the receiver hits the end 2035 * of the receive ring, which tells you exactly when you 2036 * you need to reload the ring pointer. Here we have to 2037 * fake it. I'm mad at myself for not being clever enough 2038 * to avoid the use of a goto here. 2039 */ 2040 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2041 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2042 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2043 xl_wait(sc); 2044 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2045 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2046 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2047 goto again; 2048 } 2049 return (rx_npkts); 2050 } 2051 2052 /* 2053 * Taskqueue wrapper for xl_rxeof(). 2054 */ 2055 static void 2056 xl_rxeof_task(void *arg, int pending) 2057 { 2058 struct xl_softc *sc = (struct xl_softc *)arg; 2059 2060 XL_LOCK(sc); 2061 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING) 2062 xl_rxeof(sc); 2063 XL_UNLOCK(sc); 2064 } 2065 2066 /* 2067 * A frame was downloaded to the chip. It's safe for us to clean up 2068 * the list buffers. 2069 */ 2070 static void 2071 xl_txeof(struct xl_softc *sc) 2072 { 2073 struct xl_chain *cur_tx; 2074 struct ifnet *ifp = sc->xl_ifp; 2075 2076 XL_LOCK_ASSERT(sc); 2077 2078 /* 2079 * Go through our tx list and free mbufs for those 2080 * frames that have been uploaded. Note: the 3c905B 2081 * sets a special bit in the status word to let us 2082 * know that a frame has been downloaded, but the 2083 * original 3c900/3c905 adapters don't do that. 2084 * Consequently, we have to use a different test if 2085 * xl_type != XL_TYPE_905B. 2086 */ 2087 while (sc->xl_cdata.xl_tx_head != NULL) { 2088 cur_tx = sc->xl_cdata.xl_tx_head; 2089 2090 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2091 break; 2092 2093 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2094 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2095 BUS_DMASYNC_POSTWRITE); 2096 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2097 m_freem(cur_tx->xl_mbuf); 2098 cur_tx->xl_mbuf = NULL; 2099 ifp->if_opackets++; 2100 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2101 2102 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2103 sc->xl_cdata.xl_tx_free = cur_tx; 2104 } 2105 2106 if (sc->xl_cdata.xl_tx_head == NULL) { 2107 sc->xl_wdog_timer = 0; 2108 sc->xl_cdata.xl_tx_tail = NULL; 2109 } else { 2110 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2111 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2112 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2113 sc->xl_cdata.xl_tx_head->xl_phys); 2114 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2115 } 2116 } 2117 } 2118 2119 static void 2120 xl_txeof_90xB(struct xl_softc *sc) 2121 { 2122 struct xl_chain *cur_tx = NULL; 2123 struct ifnet *ifp = sc->xl_ifp; 2124 int idx; 2125 2126 XL_LOCK_ASSERT(sc); 2127 2128 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2129 BUS_DMASYNC_POSTREAD); 2130 idx = sc->xl_cdata.xl_tx_cons; 2131 while (idx != sc->xl_cdata.xl_tx_prod) { 2132 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2133 2134 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2135 XL_TXSTAT_DL_COMPLETE)) 2136 break; 2137 2138 if (cur_tx->xl_mbuf != NULL) { 2139 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2140 BUS_DMASYNC_POSTWRITE); 2141 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2142 m_freem(cur_tx->xl_mbuf); 2143 cur_tx->xl_mbuf = NULL; 2144 } 2145 2146 ifp->if_opackets++; 2147 2148 sc->xl_cdata.xl_tx_cnt--; 2149 XL_INC(idx, XL_TX_LIST_CNT); 2150 } 2151 2152 if (sc->xl_cdata.xl_tx_cnt == 0) 2153 sc->xl_wdog_timer = 0; 2154 sc->xl_cdata.xl_tx_cons = idx; 2155 2156 if (cur_tx != NULL) 2157 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2158 } 2159 2160 /* 2161 * TX 'end of channel' interrupt handler. Actually, we should 2162 * only get a 'TX complete' interrupt if there's a transmit error, 2163 * so this is really TX error handler. 2164 */ 2165 static void 2166 xl_txeoc(struct xl_softc *sc) 2167 { 2168 u_int8_t txstat; 2169 2170 XL_LOCK_ASSERT(sc); 2171 2172 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2173 if (txstat & XL_TXSTATUS_UNDERRUN || 2174 txstat & XL_TXSTATUS_JABBER || 2175 txstat & XL_TXSTATUS_RECLAIM) { 2176 device_printf(sc->xl_dev, 2177 "transmission error: %x\n", txstat); 2178 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2179 xl_wait(sc); 2180 if (sc->xl_type == XL_TYPE_905B) { 2181 if (sc->xl_cdata.xl_tx_cnt) { 2182 int i; 2183 struct xl_chain *c; 2184 2185 i = sc->xl_cdata.xl_tx_cons; 2186 c = &sc->xl_cdata.xl_tx_chain[i]; 2187 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2188 c->xl_phys); 2189 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2190 } 2191 } else { 2192 if (sc->xl_cdata.xl_tx_head != NULL) 2193 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2194 sc->xl_cdata.xl_tx_head->xl_phys); 2195 } 2196 /* 2197 * Remember to set this for the 2198 * first generation 3c90X chips. 2199 */ 2200 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2201 if (txstat & XL_TXSTATUS_UNDERRUN && 2202 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2203 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2204 device_printf(sc->xl_dev, 2205 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2206 } 2207 CSR_WRITE_2(sc, XL_COMMAND, 2208 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2209 if (sc->xl_type == XL_TYPE_905B) { 2210 CSR_WRITE_2(sc, XL_COMMAND, 2211 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2212 } 2213 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2214 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2215 } else { 2216 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2217 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2218 } 2219 /* 2220 * Write an arbitrary byte to the TX_STATUS register 2221 * to clear this interrupt/error and advance to the next. 2222 */ 2223 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2224 } 2225 } 2226 2227 static void 2228 xl_intr(void *arg) 2229 { 2230 struct xl_softc *sc = arg; 2231 struct ifnet *ifp = sc->xl_ifp; 2232 u_int16_t status; 2233 2234 XL_LOCK(sc); 2235 2236 #ifdef DEVICE_POLLING 2237 if (ifp->if_capenable & IFCAP_POLLING) { 2238 XL_UNLOCK(sc); 2239 return; 2240 } 2241 #endif 2242 2243 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && 2244 status != 0xFFFF) { 2245 CSR_WRITE_2(sc, XL_COMMAND, 2246 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2247 2248 if (status & XL_STAT_UP_COMPLETE) { 2249 int curpkts; 2250 2251 curpkts = ifp->if_ipackets; 2252 xl_rxeof(sc); 2253 if (curpkts == ifp->if_ipackets) { 2254 while (xl_rx_resync(sc)) 2255 xl_rxeof(sc); 2256 } 2257 } 2258 2259 if (status & XL_STAT_DOWN_COMPLETE) { 2260 if (sc->xl_type == XL_TYPE_905B) 2261 xl_txeof_90xB(sc); 2262 else 2263 xl_txeof(sc); 2264 } 2265 2266 if (status & XL_STAT_TX_COMPLETE) { 2267 ifp->if_oerrors++; 2268 xl_txeoc(sc); 2269 } 2270 2271 if (status & XL_STAT_ADFAIL) { 2272 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2273 xl_init_locked(sc); 2274 } 2275 2276 if (status & XL_STAT_STATSOFLOW) { 2277 sc->xl_stats_no_timeout = 1; 2278 xl_stats_update_locked(sc); 2279 sc->xl_stats_no_timeout = 0; 2280 } 2281 } 2282 2283 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2284 if (sc->xl_type == XL_TYPE_905B) 2285 xl_start_90xB_locked(ifp); 2286 else 2287 xl_start_locked(ifp); 2288 } 2289 2290 XL_UNLOCK(sc); 2291 } 2292 2293 #ifdef DEVICE_POLLING 2294 static int 2295 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2296 { 2297 struct xl_softc *sc = ifp->if_softc; 2298 int rx_npkts = 0; 2299 2300 XL_LOCK(sc); 2301 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2302 rx_npkts = xl_poll_locked(ifp, cmd, count); 2303 XL_UNLOCK(sc); 2304 return (rx_npkts); 2305 } 2306 2307 static int 2308 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2309 { 2310 struct xl_softc *sc = ifp->if_softc; 2311 int rx_npkts; 2312 2313 XL_LOCK_ASSERT(sc); 2314 2315 sc->rxcycles = count; 2316 rx_npkts = xl_rxeof(sc); 2317 if (sc->xl_type == XL_TYPE_905B) 2318 xl_txeof_90xB(sc); 2319 else 2320 xl_txeof(sc); 2321 2322 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2323 if (sc->xl_type == XL_TYPE_905B) 2324 xl_start_90xB_locked(ifp); 2325 else 2326 xl_start_locked(ifp); 2327 } 2328 2329 if (cmd == POLL_AND_CHECK_STATUS) { 2330 u_int16_t status; 2331 2332 status = CSR_READ_2(sc, XL_STATUS); 2333 if (status & XL_INTRS && status != 0xFFFF) { 2334 CSR_WRITE_2(sc, XL_COMMAND, 2335 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2336 2337 if (status & XL_STAT_TX_COMPLETE) { 2338 ifp->if_oerrors++; 2339 xl_txeoc(sc); 2340 } 2341 2342 if (status & XL_STAT_ADFAIL) { 2343 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2344 xl_init_locked(sc); 2345 } 2346 2347 if (status & XL_STAT_STATSOFLOW) { 2348 sc->xl_stats_no_timeout = 1; 2349 xl_stats_update_locked(sc); 2350 sc->xl_stats_no_timeout = 0; 2351 } 2352 } 2353 } 2354 return (rx_npkts); 2355 } 2356 #endif /* DEVICE_POLLING */ 2357 2358 /* 2359 * XXX: This is an entry point for callout which needs to take the lock. 2360 */ 2361 static void 2362 xl_stats_update(void *xsc) 2363 { 2364 struct xl_softc *sc = xsc; 2365 2366 XL_LOCK_ASSERT(sc); 2367 2368 if (xl_watchdog(sc) == EJUSTRETURN) 2369 return; 2370 2371 xl_stats_update_locked(sc); 2372 } 2373 2374 static void 2375 xl_stats_update_locked(struct xl_softc *sc) 2376 { 2377 struct ifnet *ifp = sc->xl_ifp; 2378 struct xl_stats xl_stats; 2379 u_int8_t *p; 2380 int i; 2381 struct mii_data *mii = NULL; 2382 2383 XL_LOCK_ASSERT(sc); 2384 2385 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2386 2387 if (sc->xl_miibus != NULL) 2388 mii = device_get_softc(sc->xl_miibus); 2389 2390 p = (u_int8_t *)&xl_stats; 2391 2392 /* Read all the stats registers. */ 2393 XL_SEL_WIN(6); 2394 2395 for (i = 0; i < 16; i++) 2396 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2397 2398 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2399 2400 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2401 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision; 2402 2403 /* 2404 * Boomerang and cyclone chips have an extra stats counter 2405 * in window 4 (BadSSD). We have to read this too in order 2406 * to clear out all the stats registers and avoid a statsoflow 2407 * interrupt. 2408 */ 2409 XL_SEL_WIN(4); 2410 CSR_READ_1(sc, XL_W4_BADSSD); 2411 2412 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2413 mii_tick(mii); 2414 2415 XL_SEL_WIN(7); 2416 2417 if (!sc->xl_stats_no_timeout) 2418 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2419 } 2420 2421 /* 2422 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2423 * pointers to the fragment pointers. 2424 */ 2425 static int 2426 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) 2427 { 2428 struct mbuf *m_new; 2429 struct ifnet *ifp = sc->xl_ifp; 2430 int error, i, nseg, total_len; 2431 u_int32_t status; 2432 2433 XL_LOCK_ASSERT(sc); 2434 2435 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, 2436 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2437 2438 if (error && error != EFBIG) { 2439 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2440 return (error); 2441 } 2442 2443 /* 2444 * Handle special case: we used up all 63 fragments, 2445 * but we have more mbufs left in the chain. Copy the 2446 * data into an mbuf cluster. Note that we don't 2447 * bother clearing the values in the other fragment 2448 * pointers/counters; it wouldn't gain us anything, 2449 * and would waste cycles. 2450 */ 2451 if (error) { 2452 m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS); 2453 if (m_new == NULL) { 2454 m_freem(*m_head); 2455 *m_head = NULL; 2456 return (ENOBUFS); 2457 } 2458 *m_head = m_new; 2459 2460 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, 2461 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2462 if (error) { 2463 m_freem(*m_head); 2464 *m_head = NULL; 2465 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2466 return (error); 2467 } 2468 } 2469 2470 KASSERT(nseg <= XL_MAXFRAGS, 2471 ("%s: too many DMA segments (%d)", __func__, nseg)); 2472 if (nseg == 0) { 2473 m_freem(*m_head); 2474 *m_head = NULL; 2475 return (EIO); 2476 } 2477 2478 total_len = 0; 2479 for (i = 0; i < nseg; i++) { 2480 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, 2481 ("segment size too large")); 2482 c->xl_ptr->xl_frag[i].xl_addr = 2483 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); 2484 c->xl_ptr->xl_frag[i].xl_len = 2485 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); 2486 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; 2487 } 2488 c->xl_ptr->xl_frag[nseg - 1].xl_len = 2489 htole32(sc->xl_cdata.xl_tx_segs[nseg - 1].ds_len | XL_LAST_FRAG); 2490 c->xl_ptr->xl_status = htole32(total_len); 2491 c->xl_ptr->xl_next = 0; 2492 2493 if (sc->xl_type == XL_TYPE_905B) { 2494 status = XL_TXSTAT_RND_DEFEAT; 2495 2496 #ifndef XL905B_TXCSUM_BROKEN 2497 if ((*m_head)->m_pkthdr.csum_flags) { 2498 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2499 status |= XL_TXSTAT_IPCKSUM; 2500 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2501 status |= XL_TXSTAT_TCPCKSUM; 2502 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2503 status |= XL_TXSTAT_UDPCKSUM; 2504 } 2505 #endif 2506 c->xl_ptr->xl_status = htole32(status); 2507 } 2508 2509 c->xl_mbuf = *m_head; 2510 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2511 return (0); 2512 } 2513 2514 /* 2515 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2516 * to the mbuf data regions directly in the transmit lists. We also save a 2517 * copy of the pointers since the transmit list fragment pointers are 2518 * physical addresses. 2519 */ 2520 2521 static void 2522 xl_start(struct ifnet *ifp) 2523 { 2524 struct xl_softc *sc = ifp->if_softc; 2525 2526 XL_LOCK(sc); 2527 2528 if (sc->xl_type == XL_TYPE_905B) 2529 xl_start_90xB_locked(ifp); 2530 else 2531 xl_start_locked(ifp); 2532 2533 XL_UNLOCK(sc); 2534 } 2535 2536 static void 2537 xl_start_locked(struct ifnet *ifp) 2538 { 2539 struct xl_softc *sc = ifp->if_softc; 2540 struct mbuf *m_head = NULL; 2541 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2542 u_int32_t status; 2543 int error; 2544 2545 XL_LOCK_ASSERT(sc); 2546 2547 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2548 IFF_DRV_RUNNING) 2549 return; 2550 /* 2551 * Check for an available queue slot. If there are none, 2552 * punt. 2553 */ 2554 if (sc->xl_cdata.xl_tx_free == NULL) { 2555 xl_txeoc(sc); 2556 xl_txeof(sc); 2557 if (sc->xl_cdata.xl_tx_free == NULL) { 2558 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2559 return; 2560 } 2561 } 2562 2563 start_tx = sc->xl_cdata.xl_tx_free; 2564 2565 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2566 sc->xl_cdata.xl_tx_free != NULL;) { 2567 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2568 if (m_head == NULL) 2569 break; 2570 2571 /* Pick a descriptor off the free list. */ 2572 cur_tx = sc->xl_cdata.xl_tx_free; 2573 2574 /* Pack the data into the descriptor. */ 2575 error = xl_encap(sc, cur_tx, &m_head); 2576 if (error) { 2577 if (m_head == NULL) 2578 break; 2579 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2580 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2581 break; 2582 } 2583 2584 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2585 cur_tx->xl_next = NULL; 2586 2587 /* Chain it together. */ 2588 if (prev != NULL) { 2589 prev->xl_next = cur_tx; 2590 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2591 } 2592 prev = cur_tx; 2593 2594 /* 2595 * If there's a BPF listener, bounce a copy of this frame 2596 * to him. 2597 */ 2598 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2599 } 2600 2601 /* 2602 * If there are no packets queued, bail. 2603 */ 2604 if (cur_tx == NULL) 2605 return; 2606 2607 /* 2608 * Place the request for the upload interrupt 2609 * in the last descriptor in the chain. This way, if 2610 * we're chaining several packets at once, we'll only 2611 * get an interrupt once for the whole chain rather than 2612 * once for each packet. 2613 */ 2614 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2615 XL_TXSTAT_DL_INTR); 2616 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2617 BUS_DMASYNC_PREWRITE); 2618 2619 /* 2620 * Queue the packets. If the TX channel is clear, update 2621 * the downlist pointer register. 2622 */ 2623 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2624 xl_wait(sc); 2625 2626 if (sc->xl_cdata.xl_tx_head != NULL) { 2627 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2628 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2629 htole32(start_tx->xl_phys); 2630 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2631 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2632 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2633 sc->xl_cdata.xl_tx_tail = cur_tx; 2634 } else { 2635 sc->xl_cdata.xl_tx_head = start_tx; 2636 sc->xl_cdata.xl_tx_tail = cur_tx; 2637 } 2638 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2639 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2640 2641 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2642 2643 XL_SEL_WIN(7); 2644 2645 /* 2646 * Set a timeout in case the chip goes out to lunch. 2647 */ 2648 sc->xl_wdog_timer = 5; 2649 2650 /* 2651 * XXX Under certain conditions, usually on slower machines 2652 * where interrupts may be dropped, it's possible for the 2653 * adapter to chew up all the buffers in the receive ring 2654 * and stall, without us being able to do anything about it. 2655 * To guard against this, we need to make a pass over the 2656 * RX queue to make sure there aren't any packets pending. 2657 * Doing it here means we can flush the receive ring at the 2658 * same time the chip is DMAing the transmit descriptors we 2659 * just gave it. 2660 * 2661 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2662 * nature of their chips in all their marketing literature; 2663 * we may as well take advantage of it. :) 2664 */ 2665 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2666 } 2667 2668 static void 2669 xl_start_90xB_locked(struct ifnet *ifp) 2670 { 2671 struct xl_softc *sc = ifp->if_softc; 2672 struct mbuf *m_head = NULL; 2673 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2674 int error, idx; 2675 2676 XL_LOCK_ASSERT(sc); 2677 2678 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2679 IFF_DRV_RUNNING) 2680 return; 2681 2682 idx = sc->xl_cdata.xl_tx_prod; 2683 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2684 2685 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2686 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { 2687 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2688 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2689 break; 2690 } 2691 2692 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2693 if (m_head == NULL) 2694 break; 2695 2696 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2697 2698 /* Pack the data into the descriptor. */ 2699 error = xl_encap(sc, cur_tx, &m_head); 2700 if (error) { 2701 if (m_head == NULL) 2702 break; 2703 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2704 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2705 break; 2706 } 2707 2708 /* Chain it together. */ 2709 if (prev != NULL) 2710 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2711 prev = cur_tx; 2712 2713 /* 2714 * If there's a BPF listener, bounce a copy of this frame 2715 * to him. 2716 */ 2717 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2718 2719 XL_INC(idx, XL_TX_LIST_CNT); 2720 sc->xl_cdata.xl_tx_cnt++; 2721 } 2722 2723 /* 2724 * If there are no packets queued, bail. 2725 */ 2726 if (cur_tx == NULL) 2727 return; 2728 2729 /* 2730 * Place the request for the upload interrupt 2731 * in the last descriptor in the chain. This way, if 2732 * we're chaining several packets at once, we'll only 2733 * get an interrupt once for the whole chain rather than 2734 * once for each packet. 2735 */ 2736 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2737 XL_TXSTAT_DL_INTR); 2738 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2739 BUS_DMASYNC_PREWRITE); 2740 2741 /* Start transmission */ 2742 sc->xl_cdata.xl_tx_prod = idx; 2743 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2744 2745 /* 2746 * Set a timeout in case the chip goes out to lunch. 2747 */ 2748 sc->xl_wdog_timer = 5; 2749 } 2750 2751 static void 2752 xl_init(void *xsc) 2753 { 2754 struct xl_softc *sc = xsc; 2755 2756 XL_LOCK(sc); 2757 xl_init_locked(sc); 2758 XL_UNLOCK(sc); 2759 } 2760 2761 static void 2762 xl_init_locked(struct xl_softc *sc) 2763 { 2764 struct ifnet *ifp = sc->xl_ifp; 2765 int error, i; 2766 u_int16_t rxfilt = 0; 2767 struct mii_data *mii = NULL; 2768 2769 XL_LOCK_ASSERT(sc); 2770 2771 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2772 return; 2773 /* 2774 * Cancel pending I/O and free all RX/TX buffers. 2775 */ 2776 xl_stop(sc); 2777 2778 /* Reset the chip to a known state. */ 2779 xl_reset(sc); 2780 2781 if (sc->xl_miibus == NULL) { 2782 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2783 xl_wait(sc); 2784 } 2785 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2786 xl_wait(sc); 2787 DELAY(10000); 2788 2789 if (sc->xl_miibus != NULL) 2790 mii = device_get_softc(sc->xl_miibus); 2791 2792 /* 2793 * Clear WOL status and disable all WOL feature as WOL 2794 * would interfere Rx operation under normal environments. 2795 */ 2796 if ((sc->xl_flags & XL_FLAG_WOL) != 0) { 2797 XL_SEL_WIN(7); 2798 CSR_READ_2(sc, XL_W7_BM_PME); 2799 CSR_WRITE_2(sc, XL_W7_BM_PME, 0); 2800 } 2801 /* Init our MAC address */ 2802 XL_SEL_WIN(2); 2803 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2804 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2805 IF_LLADDR(sc->xl_ifp)[i]); 2806 } 2807 2808 /* Clear the station mask. */ 2809 for (i = 0; i < 3; i++) 2810 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2811 #ifdef notdef 2812 /* Reset TX and RX. */ 2813 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2814 xl_wait(sc); 2815 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2816 xl_wait(sc); 2817 #endif 2818 /* Init circular RX list. */ 2819 error = xl_list_rx_init(sc); 2820 if (error) { 2821 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n", 2822 error); 2823 xl_stop(sc); 2824 return; 2825 } 2826 2827 /* Init TX descriptors. */ 2828 if (sc->xl_type == XL_TYPE_905B) 2829 error = xl_list_tx_init_90xB(sc); 2830 else 2831 error = xl_list_tx_init(sc); 2832 if (error) { 2833 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n", 2834 error); 2835 xl_stop(sc); 2836 return; 2837 } 2838 2839 /* 2840 * Set the TX freethresh value. 2841 * Note that this has no effect on 3c905B "cyclone" 2842 * cards but is required for 3c900/3c905 "boomerang" 2843 * cards in order to enable the download engine. 2844 */ 2845 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2846 2847 /* Set the TX start threshold for best performance. */ 2848 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2849 2850 /* 2851 * If this is a 3c905B, also set the tx reclaim threshold. 2852 * This helps cut down on the number of tx reclaim errors 2853 * that could happen on a busy network. The chip multiplies 2854 * the register value by 16 to obtain the actual threshold 2855 * in bytes, so we divide by 16 when setting the value here. 2856 * The existing threshold value can be examined by reading 2857 * the register at offset 9 in window 5. 2858 */ 2859 if (sc->xl_type == XL_TYPE_905B) { 2860 CSR_WRITE_2(sc, XL_COMMAND, 2861 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2862 } 2863 2864 /* Set RX filter bits. */ 2865 XL_SEL_WIN(5); 2866 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2867 2868 /* Set the individual bit to receive frames for this host only. */ 2869 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2870 2871 /* If we want promiscuous mode, set the allframes bit. */ 2872 if (ifp->if_flags & IFF_PROMISC) { 2873 rxfilt |= XL_RXFILTER_ALLFRAMES; 2874 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2875 } else { 2876 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2877 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2878 } 2879 2880 /* 2881 * Set capture broadcast bit to capture broadcast frames. 2882 */ 2883 if (ifp->if_flags & IFF_BROADCAST) { 2884 rxfilt |= XL_RXFILTER_BROADCAST; 2885 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2886 } else { 2887 rxfilt &= ~XL_RXFILTER_BROADCAST; 2888 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2889 } 2890 2891 /* 2892 * Program the multicast filter, if necessary. 2893 */ 2894 if (sc->xl_type == XL_TYPE_905B) 2895 xl_setmulti_hash(sc); 2896 else 2897 xl_setmulti(sc); 2898 2899 /* 2900 * Load the address of the RX list. We have to 2901 * stall the upload engine before we can manipulate 2902 * the uplist pointer register, then unstall it when 2903 * we're finished. We also have to wait for the 2904 * stall command to complete before proceeding. 2905 * Note that we have to do this after any RX resets 2906 * have completed since the uplist register is cleared 2907 * by a reset. 2908 */ 2909 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2910 xl_wait(sc); 2911 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2912 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2913 xl_wait(sc); 2914 2915 if (sc->xl_type == XL_TYPE_905B) { 2916 /* Set polling interval */ 2917 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2918 /* Load the address of the TX list */ 2919 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2920 xl_wait(sc); 2921 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2922 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2923 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2924 xl_wait(sc); 2925 } 2926 2927 /* 2928 * If the coax transceiver is on, make sure to enable 2929 * the DC-DC converter. 2930 */ 2931 XL_SEL_WIN(3); 2932 if (sc->xl_xcvr == XL_XCVR_COAX) 2933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2934 else 2935 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2936 2937 /* 2938 * increase packet size to allow reception of 802.1q or ISL packets. 2939 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2940 * control register. For 3c90xB/C chips, use the RX packet size 2941 * register. 2942 */ 2943 2944 if (sc->xl_type == XL_TYPE_905B) 2945 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2946 else { 2947 u_int8_t macctl; 2948 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2949 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2950 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2951 } 2952 2953 /* Clear out the stats counters. */ 2954 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2955 sc->xl_stats_no_timeout = 1; 2956 xl_stats_update_locked(sc); 2957 sc->xl_stats_no_timeout = 0; 2958 XL_SEL_WIN(4); 2959 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2961 2962 /* 2963 * Enable interrupts. 2964 */ 2965 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2966 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2967 #ifdef DEVICE_POLLING 2968 /* Disable interrupts if we are polling. */ 2969 if (ifp->if_capenable & IFCAP_POLLING) 2970 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2971 else 2972 #endif 2973 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2974 if (sc->xl_flags & XL_FLAG_FUNCREG) 2975 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2976 2977 /* Set the RX early threshold */ 2978 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2979 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2980 2981 /* Enable receiver and transmitter. */ 2982 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2983 xl_wait(sc); 2984 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2985 xl_wait(sc); 2986 2987 /* XXX Downcall to miibus. */ 2988 if (mii != NULL) 2989 mii_mediachg(mii); 2990 2991 /* Select window 7 for normal operations. */ 2992 XL_SEL_WIN(7); 2993 2994 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2995 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2996 2997 sc->xl_wdog_timer = 0; 2998 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2999 } 3000 3001 /* 3002 * Set media options. 3003 */ 3004 static int 3005 xl_ifmedia_upd(struct ifnet *ifp) 3006 { 3007 struct xl_softc *sc = ifp->if_softc; 3008 struct ifmedia *ifm = NULL; 3009 struct mii_data *mii = NULL; 3010 3011 XL_LOCK(sc); 3012 3013 if (sc->xl_miibus != NULL) 3014 mii = device_get_softc(sc->xl_miibus); 3015 if (mii == NULL) 3016 ifm = &sc->ifmedia; 3017 else 3018 ifm = &mii->mii_media; 3019 3020 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3021 case IFM_100_FX: 3022 case IFM_10_FL: 3023 case IFM_10_2: 3024 case IFM_10_5: 3025 xl_setmode(sc, ifm->ifm_media); 3026 XL_UNLOCK(sc); 3027 return (0); 3028 } 3029 3030 if (sc->xl_media & XL_MEDIAOPT_MII || 3031 sc->xl_media & XL_MEDIAOPT_BTX || 3032 sc->xl_media & XL_MEDIAOPT_BT4) { 3033 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3034 xl_init_locked(sc); 3035 } else { 3036 xl_setmode(sc, ifm->ifm_media); 3037 } 3038 3039 XL_UNLOCK(sc); 3040 3041 return (0); 3042 } 3043 3044 /* 3045 * Report current media status. 3046 */ 3047 static void 3048 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3049 { 3050 struct xl_softc *sc = ifp->if_softc; 3051 u_int32_t icfg; 3052 u_int16_t status = 0; 3053 struct mii_data *mii = NULL; 3054 3055 XL_LOCK(sc); 3056 3057 if (sc->xl_miibus != NULL) 3058 mii = device_get_softc(sc->xl_miibus); 3059 3060 XL_SEL_WIN(4); 3061 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3062 3063 XL_SEL_WIN(3); 3064 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3065 icfg >>= XL_ICFG_CONNECTOR_BITS; 3066 3067 ifmr->ifm_active = IFM_ETHER; 3068 ifmr->ifm_status = IFM_AVALID; 3069 3070 if ((status & XL_MEDIASTAT_CARRIER) == 0) 3071 ifmr->ifm_status |= IFM_ACTIVE; 3072 3073 switch (icfg) { 3074 case XL_XCVR_10BT: 3075 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3076 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3077 ifmr->ifm_active |= IFM_FDX; 3078 else 3079 ifmr->ifm_active |= IFM_HDX; 3080 break; 3081 case XL_XCVR_AUI: 3082 if (sc->xl_type == XL_TYPE_905B && 3083 sc->xl_media == XL_MEDIAOPT_10FL) { 3084 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3085 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3086 ifmr->ifm_active |= IFM_FDX; 3087 else 3088 ifmr->ifm_active |= IFM_HDX; 3089 } else 3090 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3091 break; 3092 case XL_XCVR_COAX: 3093 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3094 break; 3095 /* 3096 * XXX MII and BTX/AUTO should be separate cases. 3097 */ 3098 3099 case XL_XCVR_100BTX: 3100 case XL_XCVR_AUTO: 3101 case XL_XCVR_MII: 3102 if (mii != NULL) { 3103 mii_pollstat(mii); 3104 ifmr->ifm_active = mii->mii_media_active; 3105 ifmr->ifm_status = mii->mii_media_status; 3106 } 3107 break; 3108 case XL_XCVR_100BFX: 3109 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3110 break; 3111 default: 3112 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3113 break; 3114 } 3115 3116 XL_UNLOCK(sc); 3117 } 3118 3119 static int 3120 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3121 { 3122 struct xl_softc *sc = ifp->if_softc; 3123 struct ifreq *ifr = (struct ifreq *) data; 3124 int error = 0, mask; 3125 struct mii_data *mii = NULL; 3126 u_int8_t rxfilt; 3127 3128 switch (command) { 3129 case SIOCSIFFLAGS: 3130 XL_LOCK(sc); 3131 3132 XL_SEL_WIN(5); 3133 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3134 if (ifp->if_flags & IFF_UP) { 3135 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3136 ifp->if_flags & IFF_PROMISC && 3137 !(sc->xl_if_flags & IFF_PROMISC)) { 3138 rxfilt |= XL_RXFILTER_ALLFRAMES; 3139 CSR_WRITE_2(sc, XL_COMMAND, 3140 XL_CMD_RX_SET_FILT|rxfilt); 3141 XL_SEL_WIN(7); 3142 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3143 !(ifp->if_flags & IFF_PROMISC) && 3144 sc->xl_if_flags & IFF_PROMISC) { 3145 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3146 CSR_WRITE_2(sc, XL_COMMAND, 3147 XL_CMD_RX_SET_FILT|rxfilt); 3148 XL_SEL_WIN(7); 3149 } else 3150 xl_init_locked(sc); 3151 } else { 3152 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3153 xl_stop(sc); 3154 } 3155 sc->xl_if_flags = ifp->if_flags; 3156 XL_UNLOCK(sc); 3157 error = 0; 3158 break; 3159 case SIOCADDMULTI: 3160 case SIOCDELMULTI: 3161 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3162 XL_LOCK(sc); 3163 if (sc->xl_type == XL_TYPE_905B) 3164 xl_setmulti_hash(sc); 3165 else 3166 xl_setmulti(sc); 3167 XL_UNLOCK(sc); 3168 error = 0; 3169 break; 3170 case SIOCGIFMEDIA: 3171 case SIOCSIFMEDIA: 3172 if (sc->xl_miibus != NULL) 3173 mii = device_get_softc(sc->xl_miibus); 3174 if (mii == NULL) 3175 error = ifmedia_ioctl(ifp, ifr, 3176 &sc->ifmedia, command); 3177 else 3178 error = ifmedia_ioctl(ifp, ifr, 3179 &mii->mii_media, command); 3180 break; 3181 case SIOCSIFCAP: 3182 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3183 #ifdef DEVICE_POLLING 3184 if ((mask & IFCAP_POLLING) != 0 && 3185 (ifp->if_capabilities & IFCAP_POLLING) != 0) { 3186 ifp->if_capenable ^= IFCAP_POLLING; 3187 if ((ifp->if_capenable & IFCAP_POLLING) != 0) { 3188 error = ether_poll_register(xl_poll, ifp); 3189 if (error) 3190 break; 3191 XL_LOCK(sc); 3192 /* Disable interrupts */ 3193 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3194 ifp->if_capenable |= IFCAP_POLLING; 3195 XL_UNLOCK(sc); 3196 } else { 3197 error = ether_poll_deregister(ifp); 3198 /* Enable interrupts. */ 3199 XL_LOCK(sc); 3200 CSR_WRITE_2(sc, XL_COMMAND, 3201 XL_CMD_INTR_ACK | 0xFF); 3202 CSR_WRITE_2(sc, XL_COMMAND, 3203 XL_CMD_INTR_ENB | XL_INTRS); 3204 if (sc->xl_flags & XL_FLAG_FUNCREG) 3205 bus_space_write_4(sc->xl_ftag, 3206 sc->xl_fhandle, 4, 0x8000); 3207 XL_UNLOCK(sc); 3208 } 3209 } 3210 #endif /* DEVICE_POLLING */ 3211 XL_LOCK(sc); 3212 if ((mask & IFCAP_TXCSUM) != 0 && 3213 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3214 ifp->if_capenable ^= IFCAP_TXCSUM; 3215 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3216 ifp->if_hwassist |= XL905B_CSUM_FEATURES; 3217 else 3218 ifp->if_hwassist &= ~XL905B_CSUM_FEATURES; 3219 } 3220 if ((mask & IFCAP_RXCSUM) != 0 && 3221 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3222 ifp->if_capenable ^= IFCAP_RXCSUM; 3223 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3224 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3225 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3226 XL_UNLOCK(sc); 3227 break; 3228 default: 3229 error = ether_ioctl(ifp, command, data); 3230 break; 3231 } 3232 3233 return (error); 3234 } 3235 3236 static int 3237 xl_watchdog(struct xl_softc *sc) 3238 { 3239 struct ifnet *ifp = sc->xl_ifp; 3240 u_int16_t status = 0; 3241 int misintr; 3242 3243 XL_LOCK_ASSERT(sc); 3244 3245 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) 3246 return (0); 3247 3248 xl_rxeof(sc); 3249 xl_txeoc(sc); 3250 misintr = 0; 3251 if (sc->xl_type == XL_TYPE_905B) { 3252 xl_txeof_90xB(sc); 3253 if (sc->xl_cdata.xl_tx_cnt == 0) 3254 misintr++; 3255 } else { 3256 xl_txeof(sc); 3257 if (sc->xl_cdata.xl_tx_head == NULL) 3258 misintr++; 3259 } 3260 if (misintr != 0) { 3261 device_printf(sc->xl_dev, 3262 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 3263 return (0); 3264 } 3265 3266 ifp->if_oerrors++; 3267 XL_SEL_WIN(4); 3268 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3269 device_printf(sc->xl_dev, "watchdog timeout\n"); 3270 3271 if (status & XL_MEDIASTAT_CARRIER) 3272 device_printf(sc->xl_dev, 3273 "no carrier - transceiver cable problem?\n"); 3274 3275 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3276 xl_init_locked(sc); 3277 3278 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 3279 if (sc->xl_type == XL_TYPE_905B) 3280 xl_start_90xB_locked(ifp); 3281 else 3282 xl_start_locked(ifp); 3283 } 3284 3285 return (EJUSTRETURN); 3286 } 3287 3288 /* 3289 * Stop the adapter and free any mbufs allocated to the 3290 * RX and TX lists. 3291 */ 3292 static void 3293 xl_stop(struct xl_softc *sc) 3294 { 3295 register int i; 3296 struct ifnet *ifp = sc->xl_ifp; 3297 3298 XL_LOCK_ASSERT(sc); 3299 3300 sc->xl_wdog_timer = 0; 3301 3302 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3303 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3304 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3305 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3306 xl_wait(sc); 3307 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3308 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3309 DELAY(800); 3310 3311 #ifdef foo 3312 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3313 xl_wait(sc); 3314 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3315 xl_wait(sc); 3316 #endif 3317 3318 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3319 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3320 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3321 if (sc->xl_flags & XL_FLAG_FUNCREG) 3322 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3323 3324 /* Stop the stats updater. */ 3325 callout_stop(&sc->xl_stat_callout); 3326 3327 /* 3328 * Free data in the RX lists. 3329 */ 3330 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3331 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3332 bus_dmamap_unload(sc->xl_mtag, 3333 sc->xl_cdata.xl_rx_chain[i].xl_map); 3334 bus_dmamap_destroy(sc->xl_mtag, 3335 sc->xl_cdata.xl_rx_chain[i].xl_map); 3336 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3337 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3338 } 3339 } 3340 if (sc->xl_ldata.xl_rx_list != NULL) 3341 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3342 /* 3343 * Free the TX list buffers. 3344 */ 3345 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3346 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3347 bus_dmamap_unload(sc->xl_mtag, 3348 sc->xl_cdata.xl_tx_chain[i].xl_map); 3349 bus_dmamap_destroy(sc->xl_mtag, 3350 sc->xl_cdata.xl_tx_chain[i].xl_map); 3351 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3352 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3353 } 3354 } 3355 if (sc->xl_ldata.xl_tx_list != NULL) 3356 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3357 3358 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3359 } 3360 3361 /* 3362 * Stop all chip I/O so that the kernel's probe routines don't 3363 * get confused by errant DMAs when rebooting. 3364 */ 3365 static int 3366 xl_shutdown(device_t dev) 3367 { 3368 3369 return (xl_suspend(dev)); 3370 } 3371 3372 static int 3373 xl_suspend(device_t dev) 3374 { 3375 struct xl_softc *sc; 3376 3377 sc = device_get_softc(dev); 3378 3379 XL_LOCK(sc); 3380 xl_stop(sc); 3381 xl_setwol(sc); 3382 XL_UNLOCK(sc); 3383 3384 return (0); 3385 } 3386 3387 static int 3388 xl_resume(device_t dev) 3389 { 3390 struct xl_softc *sc; 3391 struct ifnet *ifp; 3392 3393 sc = device_get_softc(dev); 3394 ifp = sc->xl_ifp; 3395 3396 XL_LOCK(sc); 3397 3398 if (ifp->if_flags & IFF_UP) { 3399 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3400 xl_init_locked(sc); 3401 } 3402 3403 XL_UNLOCK(sc); 3404 3405 return (0); 3406 } 3407 3408 static void 3409 xl_setwol(struct xl_softc *sc) 3410 { 3411 struct ifnet *ifp; 3412 u_int16_t cfg, pmstat; 3413 3414 if ((sc->xl_flags & XL_FLAG_WOL) == 0) 3415 return; 3416 3417 ifp = sc->xl_ifp; 3418 XL_SEL_WIN(7); 3419 /* Clear any pending PME events. */ 3420 CSR_READ_2(sc, XL_W7_BM_PME); 3421 cfg = 0; 3422 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3423 cfg |= XL_BM_PME_MAGIC; 3424 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg); 3425 /* Enable RX. */ 3426 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3427 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 3428 /* Request PME. */ 3429 pmstat = pci_read_config(sc->xl_dev, 3430 sc->xl_pmcap + PCIR_POWER_STATUS, 2); 3431 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3432 pmstat |= PCIM_PSTAT_PMEENABLE; 3433 else 3434 pmstat &= ~PCIM_PSTAT_PMEENABLE; 3435 pci_write_config(sc->xl_dev, 3436 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2); 3437 } 3438