1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 /* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 */ 100 101 #ifdef HAVE_KERNEL_OPTION_HEADERS 102 #include "opt_device_polling.h" 103 #endif 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/sockio.h> 108 #include <sys/endian.h> 109 #include <sys/mbuf.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/taskqueue.h> 114 115 #include <net/if.h> 116 #include <net/if_arp.h> 117 #include <net/ethernet.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 #include <net/if_types.h> 121 122 #include <net/bpf.h> 123 124 #include <machine/bus.h> 125 #include <machine/resource.h> 126 #include <sys/bus.h> 127 #include <sys/rman.h> 128 129 #include <dev/mii/mii.h> 130 #include <dev/mii/miivar.h> 131 132 #include <dev/pci/pcireg.h> 133 #include <dev/pci/pcivar.h> 134 135 MODULE_DEPEND(xl, pci, 1, 1, 1); 136 MODULE_DEPEND(xl, ether, 1, 1, 1); 137 MODULE_DEPEND(xl, miibus, 1, 1, 1); 138 139 /* "device miibus" required. See GENERIC if you get errors here. */ 140 #include "miibus_if.h" 141 142 #include <dev/xl/if_xlreg.h> 143 144 /* 145 * TX Checksumming is disabled by default for two reasons: 146 * - TX Checksumming will occasionally produce corrupt packets 147 * - TX Checksumming seems to reduce performance 148 * 149 * Only 905B/C cards were reported to have this problem, it is possible 150 * that later chips _may_ be immune. 151 */ 152 #define XL905B_TXCSUM_BROKEN 1 153 154 #ifdef XL905B_TXCSUM_BROKEN 155 #define XL905B_CSUM_FEATURES 0 156 #else 157 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 #endif 159 160 /* 161 * Various supported device vendors/types and their names. 162 */ 163 static const struct xl_type xl_devs[] = { 164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 165 "3Com 3c900-TPO Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 167 "3Com 3c900-COMBO Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 169 "3Com 3c905-TX Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 171 "3Com 3c905-T4 Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 173 "3Com 3c900B-TPO Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 175 "3Com 3c900B-COMBO Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 177 "3Com 3c900B-TPC Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 179 "3Com 3c900B-FL Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 181 "3Com 3c905B-TX Fast Etherlink XL" }, 182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 183 "3Com 3c905B-T4 Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 185 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 187 "3Com 3c905B-COMBO Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 189 "3Com 3c905C-TX Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 191 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 193 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 195 "3Com 3c980 Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 197 "3Com 3c980C Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 199 "3Com 3cSOHO100-TX OfficeConnect" }, 200 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 201 "3Com 3c450-TX HomeConnect" }, 202 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 203 "3Com 3c555 Fast Etherlink XL" }, 204 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 205 "3Com 3c556 Fast Etherlink XL" }, 206 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 207 "3Com 3c556B Fast Etherlink XL" }, 208 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 209 "3Com 3c575TX Fast Etherlink XL" }, 210 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 211 "3Com 3c575B Fast Etherlink XL" }, 212 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 213 "3Com 3c575C Fast Etherlink XL" }, 214 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 215 "3Com 3c656 Fast Etherlink XL" }, 216 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 217 "3Com 3c656B Fast Etherlink XL" }, 218 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 219 "3Com 3c656C Fast Etherlink XL" }, 220 { 0, 0, NULL } 221 }; 222 223 static int xl_probe(device_t); 224 static int xl_attach(device_t); 225 static int xl_detach(device_t); 226 227 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 228 static void xl_stats_update(void *); 229 static void xl_stats_update_locked(struct xl_softc *); 230 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); 231 static int xl_rxeof(struct xl_softc *); 232 static void xl_rxeof_task(void *, int); 233 static int xl_rx_resync(struct xl_softc *); 234 static void xl_txeof(struct xl_softc *); 235 static void xl_txeof_90xB(struct xl_softc *); 236 static void xl_txeoc(struct xl_softc *); 237 static void xl_intr(void *); 238 static void xl_start(struct ifnet *); 239 static void xl_start_locked(struct ifnet *); 240 static void xl_start_90xB_locked(struct ifnet *); 241 static int xl_ioctl(struct ifnet *, u_long, caddr_t); 242 static void xl_init(void *); 243 static void xl_init_locked(struct xl_softc *); 244 static void xl_stop(struct xl_softc *); 245 static int xl_watchdog(struct xl_softc *); 246 static int xl_shutdown(device_t); 247 static int xl_suspend(device_t); 248 static int xl_resume(device_t); 249 static void xl_setwol(struct xl_softc *); 250 251 #ifdef DEVICE_POLLING 252 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 253 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 254 #endif 255 256 static int xl_ifmedia_upd(struct ifnet *); 257 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 258 259 static int xl_eeprom_wait(struct xl_softc *); 260 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 261 static void xl_mii_sync(struct xl_softc *); 262 static void xl_mii_send(struct xl_softc *, u_int32_t, int); 263 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *); 264 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *); 265 266 static void xl_setcfg(struct xl_softc *); 267 static void xl_setmode(struct xl_softc *, int); 268 static void xl_setmulti(struct xl_softc *); 269 static void xl_setmulti_hash(struct xl_softc *); 270 static void xl_reset(struct xl_softc *); 271 static int xl_list_rx_init(struct xl_softc *); 272 static int xl_list_tx_init(struct xl_softc *); 273 static int xl_list_tx_init_90xB(struct xl_softc *); 274 static void xl_wait(struct xl_softc *); 275 static void xl_mediacheck(struct xl_softc *); 276 static void xl_choose_media(struct xl_softc *sc, int *media); 277 static void xl_choose_xcvr(struct xl_softc *, int); 278 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 279 #ifdef notdef 280 static void xl_testpacket(struct xl_softc *); 281 #endif 282 283 static int xl_miibus_readreg(device_t, int, int); 284 static int xl_miibus_writereg(device_t, int, int, int); 285 static void xl_miibus_statchg(device_t); 286 static void xl_miibus_mediainit(device_t); 287 288 static device_method_t xl_methods[] = { 289 /* Device interface */ 290 DEVMETHOD(device_probe, xl_probe), 291 DEVMETHOD(device_attach, xl_attach), 292 DEVMETHOD(device_detach, xl_detach), 293 DEVMETHOD(device_shutdown, xl_shutdown), 294 DEVMETHOD(device_suspend, xl_suspend), 295 DEVMETHOD(device_resume, xl_resume), 296 297 /* bus interface */ 298 DEVMETHOD(bus_print_child, bus_generic_print_child), 299 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 300 301 /* MII interface */ 302 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 303 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 304 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 305 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 306 307 { 0, 0 } 308 }; 309 310 static driver_t xl_driver = { 311 "xl", 312 xl_methods, 313 sizeof(struct xl_softc) 314 }; 315 316 static devclass_t xl_devclass; 317 318 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0); 319 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 320 321 static void 322 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 323 { 324 u_int32_t *paddr; 325 326 paddr = arg; 327 *paddr = segs->ds_addr; 328 } 329 330 /* 331 * Murphy's law says that it's possible the chip can wedge and 332 * the 'command in progress' bit may never clear. Hence, we wait 333 * only a finite amount of time to avoid getting caught in an 334 * infinite loop. Normally this delay routine would be a macro, 335 * but it isn't called during normal operation so we can afford 336 * to make it a function. 337 */ 338 static void 339 xl_wait(struct xl_softc *sc) 340 { 341 register int i; 342 343 for (i = 0; i < XL_TIMEOUT; i++) { 344 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 345 break; 346 } 347 348 if (i == XL_TIMEOUT) 349 device_printf(sc->xl_dev, "command never completed!\n"); 350 } 351 352 /* 353 * MII access routines are provided for adapters with external 354 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 355 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 356 * Note: if you don't perform the MDIO operations just right, 357 * it's possible to end up with code that works correctly with 358 * some chips/CPUs/processor speeds/bus speeds/etc but not 359 * with others. 360 */ 361 #define MII_SET(x) \ 362 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 363 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 364 365 #define MII_CLR(x) \ 366 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 367 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 368 369 /* 370 * Sync the PHYs by setting data bit and strobing the clock 32 times. 371 */ 372 static void 373 xl_mii_sync(struct xl_softc *sc) 374 { 375 register int i; 376 377 XL_SEL_WIN(4); 378 MII_SET(XL_MII_DIR|XL_MII_DATA); 379 380 for (i = 0; i < 32; i++) { 381 MII_SET(XL_MII_CLK); 382 MII_SET(XL_MII_DATA); 383 MII_SET(XL_MII_DATA); 384 MII_CLR(XL_MII_CLK); 385 MII_SET(XL_MII_DATA); 386 MII_SET(XL_MII_DATA); 387 } 388 } 389 390 /* 391 * Clock a series of bits through the MII. 392 */ 393 static void 394 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 395 { 396 int i; 397 398 XL_SEL_WIN(4); 399 MII_CLR(XL_MII_CLK); 400 401 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 402 if (bits & i) { 403 MII_SET(XL_MII_DATA); 404 } else { 405 MII_CLR(XL_MII_DATA); 406 } 407 MII_CLR(XL_MII_CLK); 408 MII_SET(XL_MII_CLK); 409 } 410 } 411 412 /* 413 * Read an PHY register through the MII. 414 */ 415 static int 416 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 417 { 418 int i, ack; 419 420 /* Set up frame for RX. */ 421 frame->mii_stdelim = XL_MII_STARTDELIM; 422 frame->mii_opcode = XL_MII_READOP; 423 frame->mii_turnaround = 0; 424 frame->mii_data = 0; 425 426 /* Select register window 4. */ 427 XL_SEL_WIN(4); 428 429 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 430 /* Turn on data xmit. */ 431 MII_SET(XL_MII_DIR); 432 433 xl_mii_sync(sc); 434 435 /* Send command/address info. */ 436 xl_mii_send(sc, frame->mii_stdelim, 2); 437 xl_mii_send(sc, frame->mii_opcode, 2); 438 xl_mii_send(sc, frame->mii_phyaddr, 5); 439 xl_mii_send(sc, frame->mii_regaddr, 5); 440 441 /* Idle bit */ 442 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 443 MII_SET(XL_MII_CLK); 444 445 /* Turn off xmit. */ 446 MII_CLR(XL_MII_DIR); 447 448 /* Check for ack */ 449 MII_CLR(XL_MII_CLK); 450 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 451 MII_SET(XL_MII_CLK); 452 453 /* 454 * Now try reading data bits. If the ack failed, we still 455 * need to clock through 16 cycles to keep the PHY(s) in sync. 456 */ 457 if (ack) { 458 for (i = 0; i < 16; i++) { 459 MII_CLR(XL_MII_CLK); 460 MII_SET(XL_MII_CLK); 461 } 462 goto fail; 463 } 464 465 for (i = 0x8000; i; i >>= 1) { 466 MII_CLR(XL_MII_CLK); 467 if (!ack) { 468 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 469 frame->mii_data |= i; 470 } 471 MII_SET(XL_MII_CLK); 472 } 473 474 fail: 475 MII_CLR(XL_MII_CLK); 476 MII_SET(XL_MII_CLK); 477 478 return (ack ? 1 : 0); 479 } 480 481 /* 482 * Write to a PHY register through the MII. 483 */ 484 static int 485 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 486 { 487 488 /* Set up frame for TX. */ 489 frame->mii_stdelim = XL_MII_STARTDELIM; 490 frame->mii_opcode = XL_MII_WRITEOP; 491 frame->mii_turnaround = XL_MII_TURNAROUND; 492 493 /* Select the window 4. */ 494 XL_SEL_WIN(4); 495 496 /* Turn on data output. */ 497 MII_SET(XL_MII_DIR); 498 499 xl_mii_sync(sc); 500 501 xl_mii_send(sc, frame->mii_stdelim, 2); 502 xl_mii_send(sc, frame->mii_opcode, 2); 503 xl_mii_send(sc, frame->mii_phyaddr, 5); 504 xl_mii_send(sc, frame->mii_regaddr, 5); 505 xl_mii_send(sc, frame->mii_turnaround, 2); 506 xl_mii_send(sc, frame->mii_data, 16); 507 508 /* Idle bit. */ 509 MII_SET(XL_MII_CLK); 510 MII_CLR(XL_MII_CLK); 511 512 /* Turn off xmit. */ 513 MII_CLR(XL_MII_DIR); 514 515 return (0); 516 } 517 518 static int 519 xl_miibus_readreg(device_t dev, int phy, int reg) 520 { 521 struct xl_softc *sc; 522 struct xl_mii_frame frame; 523 524 sc = device_get_softc(dev); 525 526 bzero((char *)&frame, sizeof(frame)); 527 frame.mii_phyaddr = phy; 528 frame.mii_regaddr = reg; 529 530 xl_mii_readreg(sc, &frame); 531 532 return (frame.mii_data); 533 } 534 535 static int 536 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 537 { 538 struct xl_softc *sc; 539 struct xl_mii_frame frame; 540 541 sc = device_get_softc(dev); 542 543 bzero((char *)&frame, sizeof(frame)); 544 frame.mii_phyaddr = phy; 545 frame.mii_regaddr = reg; 546 frame.mii_data = data; 547 548 xl_mii_writereg(sc, &frame); 549 550 return (0); 551 } 552 553 static void 554 xl_miibus_statchg(device_t dev) 555 { 556 struct xl_softc *sc; 557 struct mii_data *mii; 558 559 sc = device_get_softc(dev); 560 mii = device_get_softc(sc->xl_miibus); 561 562 xl_setcfg(sc); 563 564 /* Set ASIC's duplex mode to match the PHY. */ 565 XL_SEL_WIN(3); 566 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 567 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 568 else 569 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 570 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 571 } 572 573 /* 574 * Special support for the 3c905B-COMBO. This card has 10/100 support 575 * plus BNC and AUI ports. This means we will have both an miibus attached 576 * plus some non-MII media settings. In order to allow this, we have to 577 * add the extra media to the miibus's ifmedia struct, but we can't do 578 * that during xl_attach() because the miibus hasn't been attached yet. 579 * So instead, we wait until the miibus probe/attach is done, at which 580 * point we will get a callback telling is that it's safe to add our 581 * extra media. 582 */ 583 static void 584 xl_miibus_mediainit(device_t dev) 585 { 586 struct xl_softc *sc; 587 struct mii_data *mii; 588 struct ifmedia *ifm; 589 590 sc = device_get_softc(dev); 591 mii = device_get_softc(sc->xl_miibus); 592 ifm = &mii->mii_media; 593 594 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 595 /* 596 * Check for a 10baseFL board in disguise. 597 */ 598 if (sc->xl_type == XL_TYPE_905B && 599 sc->xl_media == XL_MEDIAOPT_10FL) { 600 if (bootverbose) 601 device_printf(sc->xl_dev, "found 10baseFL\n"); 602 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 603 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 604 NULL); 605 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 606 ifmedia_add(ifm, 607 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 608 } else { 609 if (bootverbose) 610 device_printf(sc->xl_dev, "found AUI\n"); 611 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 612 } 613 } 614 615 if (sc->xl_media & XL_MEDIAOPT_BNC) { 616 if (bootverbose) 617 device_printf(sc->xl_dev, "found BNC\n"); 618 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 619 } 620 } 621 622 /* 623 * The EEPROM is slow: give it time to come ready after issuing 624 * it a command. 625 */ 626 static int 627 xl_eeprom_wait(struct xl_softc *sc) 628 { 629 int i; 630 631 for (i = 0; i < 100; i++) { 632 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 633 DELAY(162); 634 else 635 break; 636 } 637 638 if (i == 100) { 639 device_printf(sc->xl_dev, "eeprom failed to come ready\n"); 640 return (1); 641 } 642 643 return (0); 644 } 645 646 /* 647 * Read a sequence of words from the EEPROM. Note that ethernet address 648 * data is stored in the EEPROM in network byte order. 649 */ 650 static int 651 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 652 { 653 int err = 0, i; 654 u_int16_t word = 0, *ptr; 655 656 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 657 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 658 /* 659 * XXX: WARNING! DANGER! 660 * It's easy to accidentally overwrite the rom content! 661 * Note: the 3c575 uses 8bit EEPROM offsets. 662 */ 663 XL_SEL_WIN(0); 664 665 if (xl_eeprom_wait(sc)) 666 return (1); 667 668 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 669 off += 0x30; 670 671 for (i = 0; i < cnt; i++) { 672 if (sc->xl_flags & XL_FLAG_8BITROM) 673 CSR_WRITE_2(sc, XL_W0_EE_CMD, 674 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 675 else 676 CSR_WRITE_2(sc, XL_W0_EE_CMD, 677 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 678 err = xl_eeprom_wait(sc); 679 if (err) 680 break; 681 word = CSR_READ_2(sc, XL_W0_EE_DATA); 682 ptr = (u_int16_t *)(dest + (i * 2)); 683 if (swap) 684 *ptr = ntohs(word); 685 else 686 *ptr = word; 687 } 688 689 return (err ? 1 : 0); 690 } 691 692 /* 693 * NICs older than the 3c905B have only one multicast option, which 694 * is to enable reception of all multicast frames. 695 */ 696 static void 697 xl_setmulti(struct xl_softc *sc) 698 { 699 struct ifnet *ifp = sc->xl_ifp; 700 struct ifmultiaddr *ifma; 701 u_int8_t rxfilt; 702 int mcnt = 0; 703 704 XL_LOCK_ASSERT(sc); 705 706 XL_SEL_WIN(5); 707 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 708 709 if (ifp->if_flags & IFF_ALLMULTI) { 710 rxfilt |= XL_RXFILTER_ALLMULTI; 711 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 712 return; 713 } 714 715 if_maddr_rlock(ifp); 716 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 717 mcnt++; 718 if_maddr_runlock(ifp); 719 720 if (mcnt) 721 rxfilt |= XL_RXFILTER_ALLMULTI; 722 else 723 rxfilt &= ~XL_RXFILTER_ALLMULTI; 724 725 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 726 } 727 728 /* 729 * 3c905B adapters have a hash filter that we can program. 730 */ 731 static void 732 xl_setmulti_hash(struct xl_softc *sc) 733 { 734 struct ifnet *ifp = sc->xl_ifp; 735 int h = 0, i; 736 struct ifmultiaddr *ifma; 737 u_int8_t rxfilt; 738 int mcnt = 0; 739 740 XL_LOCK_ASSERT(sc); 741 742 XL_SEL_WIN(5); 743 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 744 745 if (ifp->if_flags & IFF_ALLMULTI) { 746 rxfilt |= XL_RXFILTER_ALLMULTI; 747 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 748 return; 749 } else 750 rxfilt &= ~XL_RXFILTER_ALLMULTI; 751 752 /* first, zot all the existing hash bits */ 753 for (i = 0; i < XL_HASHFILT_SIZE; i++) 754 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 755 756 /* now program new ones */ 757 if_maddr_rlock(ifp); 758 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 759 if (ifma->ifma_addr->sa_family != AF_LINK) 760 continue; 761 /* 762 * Note: the 3c905B currently only supports a 64-bit hash 763 * table, which means we really only need 6 bits, but the 764 * manual indicates that future chip revisions will have a 765 * 256-bit hash table, hence the routine is set up to 766 * calculate 8 bits of position info in case we need it some 767 * day. 768 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have 769 * a 256 bit hash table. This means we have to use all 8 bits 770 * regardless. On older cards, the upper 2 bits will be 771 * ignored. Grrrr.... 772 */ 773 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 774 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 775 CSR_WRITE_2(sc, XL_COMMAND, 776 h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 777 mcnt++; 778 } 779 if_maddr_runlock(ifp); 780 781 if (mcnt) 782 rxfilt |= XL_RXFILTER_MULTIHASH; 783 else 784 rxfilt &= ~XL_RXFILTER_MULTIHASH; 785 786 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 787 } 788 789 static void 790 xl_setcfg(struct xl_softc *sc) 791 { 792 u_int32_t icfg; 793 794 /*XL_LOCK_ASSERT(sc);*/ 795 796 XL_SEL_WIN(3); 797 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 798 icfg &= ~XL_ICFG_CONNECTOR_MASK; 799 if (sc->xl_media & XL_MEDIAOPT_MII || 800 sc->xl_media & XL_MEDIAOPT_BT4) 801 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 802 if (sc->xl_media & XL_MEDIAOPT_BTX) 803 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 804 805 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 807 } 808 809 static void 810 xl_setmode(struct xl_softc *sc, int media) 811 { 812 u_int32_t icfg; 813 u_int16_t mediastat; 814 char *pmsg = "", *dmsg = ""; 815 816 XL_LOCK_ASSERT(sc); 817 818 XL_SEL_WIN(4); 819 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 820 XL_SEL_WIN(3); 821 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 822 823 if (sc->xl_media & XL_MEDIAOPT_BT) { 824 if (IFM_SUBTYPE(media) == IFM_10_T) { 825 pmsg = "10baseT transceiver"; 826 sc->xl_xcvr = XL_XCVR_10BT; 827 icfg &= ~XL_ICFG_CONNECTOR_MASK; 828 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 829 mediastat |= XL_MEDIASTAT_LINKBEAT | 830 XL_MEDIASTAT_JABGUARD; 831 mediastat &= ~XL_MEDIASTAT_SQEENB; 832 } 833 } 834 835 if (sc->xl_media & XL_MEDIAOPT_BFX) { 836 if (IFM_SUBTYPE(media) == IFM_100_FX) { 837 pmsg = "100baseFX port"; 838 sc->xl_xcvr = XL_XCVR_100BFX; 839 icfg &= ~XL_ICFG_CONNECTOR_MASK; 840 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 841 mediastat |= XL_MEDIASTAT_LINKBEAT; 842 mediastat &= ~XL_MEDIASTAT_SQEENB; 843 } 844 } 845 846 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 847 if (IFM_SUBTYPE(media) == IFM_10_5) { 848 pmsg = "AUI port"; 849 sc->xl_xcvr = XL_XCVR_AUI; 850 icfg &= ~XL_ICFG_CONNECTOR_MASK; 851 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 852 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 853 XL_MEDIASTAT_JABGUARD); 854 mediastat |= ~XL_MEDIASTAT_SQEENB; 855 } 856 if (IFM_SUBTYPE(media) == IFM_10_FL) { 857 pmsg = "10baseFL transceiver"; 858 sc->xl_xcvr = XL_XCVR_AUI; 859 icfg &= ~XL_ICFG_CONNECTOR_MASK; 860 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 861 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 862 XL_MEDIASTAT_JABGUARD); 863 mediastat |= ~XL_MEDIASTAT_SQEENB; 864 } 865 } 866 867 if (sc->xl_media & XL_MEDIAOPT_BNC) { 868 if (IFM_SUBTYPE(media) == IFM_10_2) { 869 pmsg = "AUI port"; 870 sc->xl_xcvr = XL_XCVR_COAX; 871 icfg &= ~XL_ICFG_CONNECTOR_MASK; 872 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 873 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 874 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 875 } 876 } 877 878 if ((media & IFM_GMASK) == IFM_FDX || 879 IFM_SUBTYPE(media) == IFM_100_FX) { 880 dmsg = "full"; 881 XL_SEL_WIN(3); 882 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 883 } else { 884 dmsg = "half"; 885 XL_SEL_WIN(3); 886 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 887 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 888 } 889 890 if (IFM_SUBTYPE(media) == IFM_10_2) 891 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 892 else 893 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 894 895 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 896 XL_SEL_WIN(4); 897 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 898 899 DELAY(800); 900 XL_SEL_WIN(7); 901 902 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg); 903 } 904 905 static void 906 xl_reset(struct xl_softc *sc) 907 { 908 register int i; 909 910 XL_LOCK_ASSERT(sc); 911 912 XL_SEL_WIN(0); 913 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 914 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 915 XL_RESETOPT_DISADVFD:0)); 916 917 /* 918 * If we're using memory mapped register mode, pause briefly 919 * after issuing the reset command before trying to access any 920 * other registers. With my 3c575C CardBus card, failing to do 921 * this results in the system locking up while trying to poll 922 * the command busy bit in the status register. 923 */ 924 if (sc->xl_flags & XL_FLAG_USE_MMIO) 925 DELAY(100000); 926 927 for (i = 0; i < XL_TIMEOUT; i++) { 928 DELAY(10); 929 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 930 break; 931 } 932 933 if (i == XL_TIMEOUT) 934 device_printf(sc->xl_dev, "reset didn't complete\n"); 935 936 /* Reset TX and RX. */ 937 /* Note: the RX reset takes an absurd amount of time 938 * on newer versions of the Tornado chips such as those 939 * on the 3c905CX and newer 3c908C cards. We wait an 940 * extra amount of time so that xl_wait() doesn't complain 941 * and annoy the users. 942 */ 943 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 944 DELAY(100000); 945 xl_wait(sc); 946 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 947 xl_wait(sc); 948 949 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 950 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 951 XL_SEL_WIN(2); 952 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 953 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 954 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 955 XL_RESETOPT_INVERT_LED : 0) | 956 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 957 XL_RESETOPT_INVERT_MII : 0)); 958 } 959 960 /* Wait a little while for the chip to get its brains in order. */ 961 DELAY(100000); 962 } 963 964 /* 965 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 966 * IDs against our list and return a device name if we find a match. 967 */ 968 static int 969 xl_probe(device_t dev) 970 { 971 const struct xl_type *t; 972 973 t = xl_devs; 974 975 while (t->xl_name != NULL) { 976 if ((pci_get_vendor(dev) == t->xl_vid) && 977 (pci_get_device(dev) == t->xl_did)) { 978 device_set_desc(dev, t->xl_name); 979 return (BUS_PROBE_DEFAULT); 980 } 981 t++; 982 } 983 984 return (ENXIO); 985 } 986 987 /* 988 * This routine is a kludge to work around possible hardware faults 989 * or manufacturing defects that can cause the media options register 990 * (or reset options register, as it's called for the first generation 991 * 3c90x adapters) to return an incorrect result. I have encountered 992 * one Dell Latitude laptop docking station with an integrated 3c905-TX 993 * which doesn't have any of the 'mediaopt' bits set. This screws up 994 * the attach routine pretty badly because it doesn't know what media 995 * to look for. If we find ourselves in this predicament, this routine 996 * will try to guess the media options values and warn the user of a 997 * possible manufacturing defect with his adapter/system/whatever. 998 */ 999 static void 1000 xl_mediacheck(struct xl_softc *sc) 1001 { 1002 1003 /* 1004 * If some of the media options bits are set, assume they are 1005 * correct. If not, try to figure it out down below. 1006 * XXX I should check for 10baseFL, but I don't have an adapter 1007 * to test with. 1008 */ 1009 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1010 /* 1011 * Check the XCVR value. If it's not in the normal range 1012 * of values, we need to fake it up here. 1013 */ 1014 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1015 return; 1016 else { 1017 device_printf(sc->xl_dev, 1018 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 1019 device_printf(sc->xl_dev, 1020 "choosing new default based on card type\n"); 1021 } 1022 } else { 1023 if (sc->xl_type == XL_TYPE_905B && 1024 sc->xl_media & XL_MEDIAOPT_10FL) 1025 return; 1026 device_printf(sc->xl_dev, 1027 "WARNING: no media options bits set in the media options register!!\n"); 1028 device_printf(sc->xl_dev, 1029 "this could be a manufacturing defect in your adapter or system\n"); 1030 device_printf(sc->xl_dev, 1031 "attempting to guess media type; you should probably consult your vendor\n"); 1032 } 1033 1034 xl_choose_xcvr(sc, 1); 1035 } 1036 1037 static void 1038 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1039 { 1040 u_int16_t devid; 1041 1042 /* 1043 * Read the device ID from the EEPROM. 1044 * This is what's loaded into the PCI device ID register, so it has 1045 * to be correct otherwise we wouldn't have gotten this far. 1046 */ 1047 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1048 1049 switch (devid) { 1050 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1051 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1052 sc->xl_media = XL_MEDIAOPT_BT; 1053 sc->xl_xcvr = XL_XCVR_10BT; 1054 if (verbose) 1055 device_printf(sc->xl_dev, 1056 "guessing 10BaseT transceiver\n"); 1057 break; 1058 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1059 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1060 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1061 sc->xl_xcvr = XL_XCVR_10BT; 1062 if (verbose) 1063 device_printf(sc->xl_dev, 1064 "guessing COMBO (AUI/BNC/TP)\n"); 1065 break; 1066 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1067 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1068 sc->xl_xcvr = XL_XCVR_10BT; 1069 if (verbose) 1070 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n"); 1071 break; 1072 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1073 sc->xl_media = XL_MEDIAOPT_10FL; 1074 sc->xl_xcvr = XL_XCVR_AUI; 1075 if (verbose) 1076 device_printf(sc->xl_dev, "guessing 10baseFL\n"); 1077 break; 1078 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1079 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1080 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1081 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1082 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1083 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1084 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1085 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1086 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1087 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1088 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1089 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1090 sc->xl_media = XL_MEDIAOPT_MII; 1091 sc->xl_xcvr = XL_XCVR_MII; 1092 if (verbose) 1093 device_printf(sc->xl_dev, "guessing MII\n"); 1094 break; 1095 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1096 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1097 sc->xl_media = XL_MEDIAOPT_BT4; 1098 sc->xl_xcvr = XL_XCVR_MII; 1099 if (verbose) 1100 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n"); 1101 break; 1102 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1103 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1104 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1105 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1106 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1107 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1108 sc->xl_media = XL_MEDIAOPT_BTX; 1109 sc->xl_xcvr = XL_XCVR_AUTO; 1110 if (verbose) 1111 device_printf(sc->xl_dev, "guessing 10/100 internal\n"); 1112 break; 1113 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1114 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1115 sc->xl_xcvr = XL_XCVR_AUTO; 1116 if (verbose) 1117 device_printf(sc->xl_dev, 1118 "guessing 10/100 plus BNC/AUI\n"); 1119 break; 1120 default: 1121 device_printf(sc->xl_dev, 1122 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1123 sc->xl_media = XL_MEDIAOPT_BT; 1124 break; 1125 } 1126 } 1127 1128 /* 1129 * Attach the interface. Allocate softc structures, do ifmedia 1130 * setup and ethernet/BPF attach. 1131 */ 1132 static int 1133 xl_attach(device_t dev) 1134 { 1135 u_char eaddr[ETHER_ADDR_LEN]; 1136 u_int16_t sinfo2, xcvr[2]; 1137 struct xl_softc *sc; 1138 struct ifnet *ifp; 1139 int media, pmcap; 1140 int error = 0, phy, rid, res, unit; 1141 uint16_t did; 1142 1143 sc = device_get_softc(dev); 1144 sc->xl_dev = dev; 1145 1146 unit = device_get_unit(dev); 1147 1148 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1149 MTX_DEF); 1150 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1151 1152 did = pci_get_device(dev); 1153 1154 sc->xl_flags = 0; 1155 if (did == TC_DEVICEID_HURRICANE_555) 1156 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1157 if (did == TC_DEVICEID_HURRICANE_556 || 1158 did == TC_DEVICEID_HURRICANE_556B) 1159 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1160 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1161 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1162 if (did == TC_DEVICEID_HURRICANE_555 || 1163 did == TC_DEVICEID_HURRICANE_556) 1164 sc->xl_flags |= XL_FLAG_8BITROM; 1165 if (did == TC_DEVICEID_HURRICANE_556B) 1166 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1167 1168 if (did == TC_DEVICEID_HURRICANE_575B || 1169 did == TC_DEVICEID_HURRICANE_575C || 1170 did == TC_DEVICEID_HURRICANE_656B || 1171 did == TC_DEVICEID_TORNADO_656C) 1172 sc->xl_flags |= XL_FLAG_FUNCREG; 1173 if (did == TC_DEVICEID_HURRICANE_575A || 1174 did == TC_DEVICEID_HURRICANE_575B || 1175 did == TC_DEVICEID_HURRICANE_575C || 1176 did == TC_DEVICEID_HURRICANE_656B || 1177 did == TC_DEVICEID_TORNADO_656C) 1178 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1179 XL_FLAG_8BITROM; 1180 if (did == TC_DEVICEID_HURRICANE_656) 1181 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1182 if (did == TC_DEVICEID_HURRICANE_575B) 1183 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1184 if (did == TC_DEVICEID_HURRICANE_575C) 1185 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1186 if (did == TC_DEVICEID_TORNADO_656C) 1187 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1188 if (did == TC_DEVICEID_HURRICANE_656 || 1189 did == TC_DEVICEID_HURRICANE_656B) 1190 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1191 XL_FLAG_INVERT_LED_PWR; 1192 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1193 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1194 sc->xl_flags |= XL_FLAG_PHYOK; 1195 1196 switch (did) { 1197 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1198 case TC_DEVICEID_HURRICANE_575A: 1199 case TC_DEVICEID_HURRICANE_575B: 1200 case TC_DEVICEID_HURRICANE_575C: 1201 sc->xl_flags |= XL_FLAG_NO_MMIO; 1202 break; 1203 default: 1204 break; 1205 } 1206 1207 /* 1208 * Map control/status registers. 1209 */ 1210 pci_enable_busmaster(dev); 1211 1212 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1213 rid = XL_PCI_LOMEM; 1214 res = SYS_RES_MEMORY; 1215 1216 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1217 } 1218 1219 if (sc->xl_res != NULL) { 1220 sc->xl_flags |= XL_FLAG_USE_MMIO; 1221 if (bootverbose) 1222 device_printf(dev, "using memory mapped I/O\n"); 1223 } else { 1224 rid = XL_PCI_LOIO; 1225 res = SYS_RES_IOPORT; 1226 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1227 if (sc->xl_res == NULL) { 1228 device_printf(dev, "couldn't map ports/memory\n"); 1229 error = ENXIO; 1230 goto fail; 1231 } 1232 if (bootverbose) 1233 device_printf(dev, "using port I/O\n"); 1234 } 1235 1236 sc->xl_btag = rman_get_bustag(sc->xl_res); 1237 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1238 1239 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1240 rid = XL_PCI_FUNCMEM; 1241 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1242 RF_ACTIVE); 1243 1244 if (sc->xl_fres == NULL) { 1245 device_printf(dev, "couldn't map funcreg memory\n"); 1246 error = ENXIO; 1247 goto fail; 1248 } 1249 1250 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1251 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1252 } 1253 1254 /* Allocate interrupt */ 1255 rid = 0; 1256 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1257 RF_SHAREABLE | RF_ACTIVE); 1258 if (sc->xl_irq == NULL) { 1259 device_printf(dev, "couldn't map interrupt\n"); 1260 error = ENXIO; 1261 goto fail; 1262 } 1263 1264 /* Initialize interface name. */ 1265 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1266 if (ifp == NULL) { 1267 device_printf(dev, "can not if_alloc()\n"); 1268 error = ENOSPC; 1269 goto fail; 1270 } 1271 ifp->if_softc = sc; 1272 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1273 1274 /* Reset the adapter. */ 1275 XL_LOCK(sc); 1276 xl_reset(sc); 1277 XL_UNLOCK(sc); 1278 1279 /* 1280 * Get station address from the EEPROM. 1281 */ 1282 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1283 device_printf(dev, "failed to read station address\n"); 1284 error = ENXIO; 1285 goto fail; 1286 } 1287 1288 callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0); 1289 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1290 1291 /* 1292 * Now allocate a tag for the DMA descriptor lists and a chunk 1293 * of DMA-able memory based on the tag. Also obtain the DMA 1294 * addresses of the RX and TX ring, which we'll need later. 1295 * All of our lists are allocated as a contiguous block 1296 * of memory. 1297 */ 1298 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1299 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1300 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1301 &sc->xl_ldata.xl_rx_tag); 1302 if (error) { 1303 device_printf(dev, "failed to allocate rx dma tag\n"); 1304 goto fail; 1305 } 1306 1307 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1308 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1309 &sc->xl_ldata.xl_rx_dmamap); 1310 if (error) { 1311 device_printf(dev, "no memory for rx list buffers!\n"); 1312 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1313 sc->xl_ldata.xl_rx_tag = NULL; 1314 goto fail; 1315 } 1316 1317 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1318 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1319 XL_RX_LIST_SZ, xl_dma_map_addr, 1320 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1321 if (error) { 1322 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1323 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1324 sc->xl_ldata.xl_rx_dmamap); 1325 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1326 sc->xl_ldata.xl_rx_tag = NULL; 1327 goto fail; 1328 } 1329 1330 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1331 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1332 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1333 &sc->xl_ldata.xl_tx_tag); 1334 if (error) { 1335 device_printf(dev, "failed to allocate tx dma tag\n"); 1336 goto fail; 1337 } 1338 1339 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1340 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1341 &sc->xl_ldata.xl_tx_dmamap); 1342 if (error) { 1343 device_printf(dev, "no memory for list buffers!\n"); 1344 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1345 sc->xl_ldata.xl_tx_tag = NULL; 1346 goto fail; 1347 } 1348 1349 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1350 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1351 XL_TX_LIST_SZ, xl_dma_map_addr, 1352 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1353 if (error) { 1354 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1355 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1356 sc->xl_ldata.xl_tx_dmamap); 1357 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1358 sc->xl_ldata.xl_tx_tag = NULL; 1359 goto fail; 1360 } 1361 1362 /* 1363 * Allocate a DMA tag for the mapping of mbufs. 1364 */ 1365 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1366 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1367 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1368 NULL, &sc->xl_mtag); 1369 if (error) { 1370 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1371 goto fail; 1372 } 1373 1374 /* We need a spare DMA map for the RX ring. */ 1375 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1376 if (error) 1377 goto fail; 1378 1379 /* 1380 * Figure out the card type. 3c905B adapters have the 1381 * 'supportsNoTxLength' bit set in the capabilities 1382 * word in the EEPROM. 1383 * Note: my 3c575C CardBus card lies. It returns a value 1384 * of 0x1578 for its capabilities word, which is somewhat 1385 * nonsensical. Another way to distinguish a 3c90x chip 1386 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1387 * bit. This will only be set for 3c90x boomerage chips. 1388 */ 1389 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1390 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1391 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1392 sc->xl_type = XL_TYPE_905B; 1393 else 1394 sc->xl_type = XL_TYPE_90X; 1395 1396 /* Check availability of WOL. */ 1397 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 && 1398 pci_find_extcap(dev, PCIY_PMG, &pmcap) == 0) { 1399 sc->xl_pmcap = pmcap; 1400 sc->xl_flags |= XL_FLAG_WOL; 1401 sinfo2 = 0; 1402 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0); 1403 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose) 1404 device_printf(dev, 1405 "No auxiliary remote wakeup connector!\n"); 1406 } 1407 1408 /* Set the TX start threshold for best performance. */ 1409 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1410 1411 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1412 ifp->if_ioctl = xl_ioctl; 1413 ifp->if_capabilities = IFCAP_VLAN_MTU; 1414 if (sc->xl_type == XL_TYPE_905B) { 1415 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1416 #ifdef XL905B_TXCSUM_BROKEN 1417 ifp->if_capabilities |= IFCAP_RXCSUM; 1418 #else 1419 ifp->if_capabilities |= IFCAP_HWCSUM; 1420 #endif 1421 } 1422 if ((sc->xl_flags & XL_FLAG_WOL) != 0) 1423 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1424 ifp->if_capenable = ifp->if_capabilities; 1425 #ifdef DEVICE_POLLING 1426 ifp->if_capabilities |= IFCAP_POLLING; 1427 #endif 1428 ifp->if_start = xl_start; 1429 ifp->if_init = xl_init; 1430 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1431 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1; 1432 IFQ_SET_READY(&ifp->if_snd); 1433 1434 /* 1435 * Now we have to see what sort of media we have. 1436 * This includes probing for an MII interace and a 1437 * possible PHY. 1438 */ 1439 XL_SEL_WIN(3); 1440 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1441 if (bootverbose) 1442 device_printf(dev, "media options word: %x\n", sc->xl_media); 1443 1444 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1445 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1446 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1447 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1448 1449 xl_mediacheck(sc); 1450 1451 if (sc->xl_media & XL_MEDIAOPT_MII || 1452 sc->xl_media & XL_MEDIAOPT_BTX || 1453 sc->xl_media & XL_MEDIAOPT_BT4) { 1454 if (bootverbose) 1455 device_printf(dev, "found MII/AUTO\n"); 1456 xl_setcfg(sc); 1457 /* 1458 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK. 1459 * This is to guard against problems with certain 3Com ASIC 1460 * revisions that incorrectly map the internal transceiver 1461 * control registers at all MII addresses. 1462 */ 1463 phy = MII_PHY_ANY; 1464 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0) 1465 phy = 24; 1466 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd, 1467 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 1468 if (error != 0) { 1469 device_printf(dev, "attaching PHYs failed\n"); 1470 goto fail; 1471 } 1472 goto done; 1473 } 1474 1475 /* 1476 * Sanity check. If the user has selected "auto" and this isn't 1477 * a 10/100 card of some kind, we need to force the transceiver 1478 * type to something sane. 1479 */ 1480 if (sc->xl_xcvr == XL_XCVR_AUTO) 1481 xl_choose_xcvr(sc, bootverbose); 1482 1483 /* 1484 * Do ifmedia setup. 1485 */ 1486 if (sc->xl_media & XL_MEDIAOPT_BT) { 1487 if (bootverbose) 1488 device_printf(dev, "found 10baseT\n"); 1489 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1490 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1491 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1492 ifmedia_add(&sc->ifmedia, 1493 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1494 } 1495 1496 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1497 /* 1498 * Check for a 10baseFL board in disguise. 1499 */ 1500 if (sc->xl_type == XL_TYPE_905B && 1501 sc->xl_media == XL_MEDIAOPT_10FL) { 1502 if (bootverbose) 1503 device_printf(dev, "found 10baseFL\n"); 1504 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1505 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1506 0, NULL); 1507 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1508 ifmedia_add(&sc->ifmedia, 1509 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1510 } else { 1511 if (bootverbose) 1512 device_printf(dev, "found AUI\n"); 1513 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1514 } 1515 } 1516 1517 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1518 if (bootverbose) 1519 device_printf(dev, "found BNC\n"); 1520 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1521 } 1522 1523 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1524 if (bootverbose) 1525 device_printf(dev, "found 100baseFX\n"); 1526 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1527 } 1528 1529 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1530 xl_choose_media(sc, &media); 1531 1532 if (sc->xl_miibus == NULL) 1533 ifmedia_set(&sc->ifmedia, media); 1534 1535 done: 1536 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1537 XL_SEL_WIN(0); 1538 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1539 } 1540 1541 /* 1542 * Call MI attach routine. 1543 */ 1544 ether_ifattach(ifp, eaddr); 1545 1546 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1547 NULL, xl_intr, sc, &sc->xl_intrhand); 1548 if (error) { 1549 device_printf(dev, "couldn't set up irq\n"); 1550 ether_ifdetach(ifp); 1551 goto fail; 1552 } 1553 1554 fail: 1555 if (error) 1556 xl_detach(dev); 1557 1558 return (error); 1559 } 1560 1561 /* 1562 * Choose a default media. 1563 * XXX This is a leaf function only called by xl_attach() and 1564 * acquires/releases the non-recursible driver mutex to 1565 * satisfy lock assertions. 1566 */ 1567 static void 1568 xl_choose_media(struct xl_softc *sc, int *media) 1569 { 1570 1571 XL_LOCK(sc); 1572 1573 switch (sc->xl_xcvr) { 1574 case XL_XCVR_10BT: 1575 *media = IFM_ETHER|IFM_10_T; 1576 xl_setmode(sc, *media); 1577 break; 1578 case XL_XCVR_AUI: 1579 if (sc->xl_type == XL_TYPE_905B && 1580 sc->xl_media == XL_MEDIAOPT_10FL) { 1581 *media = IFM_ETHER|IFM_10_FL; 1582 xl_setmode(sc, *media); 1583 } else { 1584 *media = IFM_ETHER|IFM_10_5; 1585 xl_setmode(sc, *media); 1586 } 1587 break; 1588 case XL_XCVR_COAX: 1589 *media = IFM_ETHER|IFM_10_2; 1590 xl_setmode(sc, *media); 1591 break; 1592 case XL_XCVR_AUTO: 1593 case XL_XCVR_100BTX: 1594 case XL_XCVR_MII: 1595 /* Chosen by miibus */ 1596 break; 1597 case XL_XCVR_100BFX: 1598 *media = IFM_ETHER|IFM_100_FX; 1599 break; 1600 default: 1601 device_printf(sc->xl_dev, "unknown XCVR type: %d\n", 1602 sc->xl_xcvr); 1603 /* 1604 * This will probably be wrong, but it prevents 1605 * the ifmedia code from panicking. 1606 */ 1607 *media = IFM_ETHER|IFM_10_T; 1608 break; 1609 } 1610 1611 XL_UNLOCK(sc); 1612 } 1613 1614 /* 1615 * Shutdown hardware and free up resources. This can be called any 1616 * time after the mutex has been initialized. It is called in both 1617 * the error case in attach and the normal detach case so it needs 1618 * to be careful about only freeing resources that have actually been 1619 * allocated. 1620 */ 1621 static int 1622 xl_detach(device_t dev) 1623 { 1624 struct xl_softc *sc; 1625 struct ifnet *ifp; 1626 int rid, res; 1627 1628 sc = device_get_softc(dev); 1629 ifp = sc->xl_ifp; 1630 1631 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1632 1633 #ifdef DEVICE_POLLING 1634 if (ifp && ifp->if_capenable & IFCAP_POLLING) 1635 ether_poll_deregister(ifp); 1636 #endif 1637 1638 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1639 rid = XL_PCI_LOMEM; 1640 res = SYS_RES_MEMORY; 1641 } else { 1642 rid = XL_PCI_LOIO; 1643 res = SYS_RES_IOPORT; 1644 } 1645 1646 /* These should only be active if attach succeeded */ 1647 if (device_is_attached(dev)) { 1648 XL_LOCK(sc); 1649 xl_stop(sc); 1650 XL_UNLOCK(sc); 1651 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1652 callout_drain(&sc->xl_stat_callout); 1653 ether_ifdetach(ifp); 1654 } 1655 if (sc->xl_miibus) 1656 device_delete_child(dev, sc->xl_miibus); 1657 bus_generic_detach(dev); 1658 ifmedia_removeall(&sc->ifmedia); 1659 1660 if (sc->xl_intrhand) 1661 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1662 if (sc->xl_irq) 1663 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1664 if (sc->xl_fres != NULL) 1665 bus_release_resource(dev, SYS_RES_MEMORY, 1666 XL_PCI_FUNCMEM, sc->xl_fres); 1667 if (sc->xl_res) 1668 bus_release_resource(dev, res, rid, sc->xl_res); 1669 1670 if (ifp) 1671 if_free(ifp); 1672 1673 if (sc->xl_mtag) { 1674 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1675 bus_dma_tag_destroy(sc->xl_mtag); 1676 } 1677 if (sc->xl_ldata.xl_rx_tag) { 1678 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1679 sc->xl_ldata.xl_rx_dmamap); 1680 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1681 sc->xl_ldata.xl_rx_dmamap); 1682 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1683 } 1684 if (sc->xl_ldata.xl_tx_tag) { 1685 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1686 sc->xl_ldata.xl_tx_dmamap); 1687 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1688 sc->xl_ldata.xl_tx_dmamap); 1689 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1690 } 1691 1692 mtx_destroy(&sc->xl_mtx); 1693 1694 return (0); 1695 } 1696 1697 /* 1698 * Initialize the transmit descriptors. 1699 */ 1700 static int 1701 xl_list_tx_init(struct xl_softc *sc) 1702 { 1703 struct xl_chain_data *cd; 1704 struct xl_list_data *ld; 1705 int error, i; 1706 1707 XL_LOCK_ASSERT(sc); 1708 1709 cd = &sc->xl_cdata; 1710 ld = &sc->xl_ldata; 1711 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1712 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1713 error = bus_dmamap_create(sc->xl_mtag, 0, 1714 &cd->xl_tx_chain[i].xl_map); 1715 if (error) 1716 return (error); 1717 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1718 i * sizeof(struct xl_list); 1719 if (i == (XL_TX_LIST_CNT - 1)) 1720 cd->xl_tx_chain[i].xl_next = NULL; 1721 else 1722 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1723 } 1724 1725 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1726 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1727 1728 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1729 return (0); 1730 } 1731 1732 /* 1733 * Initialize the transmit descriptors. 1734 */ 1735 static int 1736 xl_list_tx_init_90xB(struct xl_softc *sc) 1737 { 1738 struct xl_chain_data *cd; 1739 struct xl_list_data *ld; 1740 int error, i; 1741 1742 XL_LOCK_ASSERT(sc); 1743 1744 cd = &sc->xl_cdata; 1745 ld = &sc->xl_ldata; 1746 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1747 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1748 error = bus_dmamap_create(sc->xl_mtag, 0, 1749 &cd->xl_tx_chain[i].xl_map); 1750 if (error) 1751 return (error); 1752 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1753 i * sizeof(struct xl_list); 1754 if (i == (XL_TX_LIST_CNT - 1)) 1755 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1756 else 1757 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1758 if (i == 0) 1759 cd->xl_tx_chain[i].xl_prev = 1760 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1761 else 1762 cd->xl_tx_chain[i].xl_prev = 1763 &cd->xl_tx_chain[i - 1]; 1764 } 1765 1766 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1767 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1768 1769 cd->xl_tx_prod = 1; 1770 cd->xl_tx_cons = 1; 1771 cd->xl_tx_cnt = 0; 1772 1773 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1774 return (0); 1775 } 1776 1777 /* 1778 * Initialize the RX descriptors and allocate mbufs for them. Note that 1779 * we arrange the descriptors in a closed ring, so that the last descriptor 1780 * points back to the first. 1781 */ 1782 static int 1783 xl_list_rx_init(struct xl_softc *sc) 1784 { 1785 struct xl_chain_data *cd; 1786 struct xl_list_data *ld; 1787 int error, i, next; 1788 u_int32_t nextptr; 1789 1790 XL_LOCK_ASSERT(sc); 1791 1792 cd = &sc->xl_cdata; 1793 ld = &sc->xl_ldata; 1794 1795 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1796 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1797 error = bus_dmamap_create(sc->xl_mtag, 0, 1798 &cd->xl_rx_chain[i].xl_map); 1799 if (error) 1800 return (error); 1801 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1802 if (error) 1803 return (error); 1804 if (i == (XL_RX_LIST_CNT - 1)) 1805 next = 0; 1806 else 1807 next = i + 1; 1808 nextptr = ld->xl_rx_dmaaddr + 1809 next * sizeof(struct xl_list_onefrag); 1810 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1811 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1812 } 1813 1814 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1815 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1816 1817 return (0); 1818 } 1819 1820 /* 1821 * Initialize an RX descriptor and attach an MBUF cluster. 1822 * If we fail to do so, we need to leave the old mbuf and 1823 * the old DMA map untouched so that it can be reused. 1824 */ 1825 static int 1826 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1827 { 1828 struct mbuf *m_new = NULL; 1829 bus_dmamap_t map; 1830 bus_dma_segment_t segs[1]; 1831 int error, nseg; 1832 1833 XL_LOCK_ASSERT(sc); 1834 1835 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1836 if (m_new == NULL) 1837 return (ENOBUFS); 1838 1839 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1840 1841 /* Force longword alignment for packet payload. */ 1842 m_adj(m_new, ETHER_ALIGN); 1843 1844 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, 1845 segs, &nseg, BUS_DMA_NOWAIT); 1846 if (error) { 1847 m_freem(m_new); 1848 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", 1849 error); 1850 return (error); 1851 } 1852 KASSERT(nseg == 1, 1853 ("%s: too many DMA segments (%d)", __func__, nseg)); 1854 1855 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1856 map = c->xl_map; 1857 c->xl_map = sc->xl_tmpmap; 1858 sc->xl_tmpmap = map; 1859 c->xl_mbuf = m_new; 1860 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1861 c->xl_ptr->xl_status = 0; 1862 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); 1863 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1864 return (0); 1865 } 1866 1867 static int 1868 xl_rx_resync(struct xl_softc *sc) 1869 { 1870 struct xl_chain_onefrag *pos; 1871 int i; 1872 1873 XL_LOCK_ASSERT(sc); 1874 1875 pos = sc->xl_cdata.xl_rx_head; 1876 1877 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1878 if (pos->xl_ptr->xl_status) 1879 break; 1880 pos = pos->xl_next; 1881 } 1882 1883 if (i == XL_RX_LIST_CNT) 1884 return (0); 1885 1886 sc->xl_cdata.xl_rx_head = pos; 1887 1888 return (EAGAIN); 1889 } 1890 1891 /* 1892 * A frame has been uploaded: pass the resulting mbuf chain up to 1893 * the higher level protocols. 1894 */ 1895 static int 1896 xl_rxeof(struct xl_softc *sc) 1897 { 1898 struct mbuf *m; 1899 struct ifnet *ifp = sc->xl_ifp; 1900 struct xl_chain_onefrag *cur_rx; 1901 int total_len = 0; 1902 int rx_npkts = 0; 1903 u_int32_t rxstat; 1904 1905 XL_LOCK_ASSERT(sc); 1906 again: 1907 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1908 BUS_DMASYNC_POSTREAD); 1909 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1910 #ifdef DEVICE_POLLING 1911 if (ifp->if_capenable & IFCAP_POLLING) { 1912 if (sc->rxcycles <= 0) 1913 break; 1914 sc->rxcycles--; 1915 } 1916 #endif 1917 cur_rx = sc->xl_cdata.xl_rx_head; 1918 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1919 total_len = rxstat & XL_RXSTAT_LENMASK; 1920 1921 /* 1922 * Since we have told the chip to allow large frames, 1923 * we need to trap giant frame errors in software. We allow 1924 * a little more than the normal frame size to account for 1925 * frames with VLAN tags. 1926 */ 1927 if (total_len > XL_MAX_FRAMELEN) 1928 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1929 1930 /* 1931 * If an error occurs, update stats, clear the 1932 * status word and leave the mbuf cluster in place: 1933 * it should simply get re-used next time this descriptor 1934 * comes up in the ring. 1935 */ 1936 if (rxstat & XL_RXSTAT_UP_ERROR) { 1937 ifp->if_ierrors++; 1938 cur_rx->xl_ptr->xl_status = 0; 1939 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1940 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1941 continue; 1942 } 1943 1944 /* 1945 * If the error bit was not set, the upload complete 1946 * bit should be set which means we have a valid packet. 1947 * If not, something truly strange has happened. 1948 */ 1949 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1950 device_printf(sc->xl_dev, 1951 "bad receive status -- packet dropped\n"); 1952 ifp->if_ierrors++; 1953 cur_rx->xl_ptr->xl_status = 0; 1954 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1955 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1956 continue; 1957 } 1958 1959 /* No errors; receive the packet. */ 1960 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 1961 BUS_DMASYNC_POSTREAD); 1962 m = cur_rx->xl_mbuf; 1963 1964 /* 1965 * Try to conjure up a new mbuf cluster. If that 1966 * fails, it means we have an out of memory condition and 1967 * should leave the buffer in place and continue. This will 1968 * result in a lost packet, but there's little else we 1969 * can do in this situation. 1970 */ 1971 if (xl_newbuf(sc, cur_rx)) { 1972 ifp->if_ierrors++; 1973 cur_rx->xl_ptr->xl_status = 0; 1974 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1975 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1976 continue; 1977 } 1978 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1979 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1980 1981 ifp->if_ipackets++; 1982 m->m_pkthdr.rcvif = ifp; 1983 m->m_pkthdr.len = m->m_len = total_len; 1984 1985 if (ifp->if_capenable & IFCAP_RXCSUM) { 1986 /* Do IP checksum checking. */ 1987 if (rxstat & XL_RXSTAT_IPCKOK) 1988 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1989 if (!(rxstat & XL_RXSTAT_IPCKERR)) 1990 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1991 if ((rxstat & XL_RXSTAT_TCPCOK && 1992 !(rxstat & XL_RXSTAT_TCPCKERR)) || 1993 (rxstat & XL_RXSTAT_UDPCKOK && 1994 !(rxstat & XL_RXSTAT_UDPCKERR))) { 1995 m->m_pkthdr.csum_flags |= 1996 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1997 m->m_pkthdr.csum_data = 0xffff; 1998 } 1999 } 2000 2001 XL_UNLOCK(sc); 2002 (*ifp->if_input)(ifp, m); 2003 XL_LOCK(sc); 2004 rx_npkts++; 2005 2006 /* 2007 * If we are running from the taskqueue, the interface 2008 * might have been stopped while we were passing the last 2009 * packet up the network stack. 2010 */ 2011 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 2012 return (rx_npkts); 2013 } 2014 2015 /* 2016 * Handle the 'end of channel' condition. When the upload 2017 * engine hits the end of the RX ring, it will stall. This 2018 * is our cue to flush the RX ring, reload the uplist pointer 2019 * register and unstall the engine. 2020 * XXX This is actually a little goofy. With the ThunderLAN 2021 * chip, you get an interrupt when the receiver hits the end 2022 * of the receive ring, which tells you exactly when you 2023 * you need to reload the ring pointer. Here we have to 2024 * fake it. I'm mad at myself for not being clever enough 2025 * to avoid the use of a goto here. 2026 */ 2027 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2028 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2029 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2030 xl_wait(sc); 2031 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2032 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2033 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2034 goto again; 2035 } 2036 return (rx_npkts); 2037 } 2038 2039 /* 2040 * Taskqueue wrapper for xl_rxeof(). 2041 */ 2042 static void 2043 xl_rxeof_task(void *arg, int pending) 2044 { 2045 struct xl_softc *sc = (struct xl_softc *)arg; 2046 2047 XL_LOCK(sc); 2048 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING) 2049 xl_rxeof(sc); 2050 XL_UNLOCK(sc); 2051 } 2052 2053 /* 2054 * A frame was downloaded to the chip. It's safe for us to clean up 2055 * the list buffers. 2056 */ 2057 static void 2058 xl_txeof(struct xl_softc *sc) 2059 { 2060 struct xl_chain *cur_tx; 2061 struct ifnet *ifp = sc->xl_ifp; 2062 2063 XL_LOCK_ASSERT(sc); 2064 2065 /* 2066 * Go through our tx list and free mbufs for those 2067 * frames that have been uploaded. Note: the 3c905B 2068 * sets a special bit in the status word to let us 2069 * know that a frame has been downloaded, but the 2070 * original 3c900/3c905 adapters don't do that. 2071 * Consequently, we have to use a different test if 2072 * xl_type != XL_TYPE_905B. 2073 */ 2074 while (sc->xl_cdata.xl_tx_head != NULL) { 2075 cur_tx = sc->xl_cdata.xl_tx_head; 2076 2077 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2078 break; 2079 2080 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2081 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2082 BUS_DMASYNC_POSTWRITE); 2083 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2084 m_freem(cur_tx->xl_mbuf); 2085 cur_tx->xl_mbuf = NULL; 2086 ifp->if_opackets++; 2087 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2088 2089 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2090 sc->xl_cdata.xl_tx_free = cur_tx; 2091 } 2092 2093 if (sc->xl_cdata.xl_tx_head == NULL) { 2094 sc->xl_wdog_timer = 0; 2095 sc->xl_cdata.xl_tx_tail = NULL; 2096 } else { 2097 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2098 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2099 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2100 sc->xl_cdata.xl_tx_head->xl_phys); 2101 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2102 } 2103 } 2104 } 2105 2106 static void 2107 xl_txeof_90xB(struct xl_softc *sc) 2108 { 2109 struct xl_chain *cur_tx = NULL; 2110 struct ifnet *ifp = sc->xl_ifp; 2111 int idx; 2112 2113 XL_LOCK_ASSERT(sc); 2114 2115 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2116 BUS_DMASYNC_POSTREAD); 2117 idx = sc->xl_cdata.xl_tx_cons; 2118 while (idx != sc->xl_cdata.xl_tx_prod) { 2119 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2120 2121 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2122 XL_TXSTAT_DL_COMPLETE)) 2123 break; 2124 2125 if (cur_tx->xl_mbuf != NULL) { 2126 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2127 BUS_DMASYNC_POSTWRITE); 2128 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2129 m_freem(cur_tx->xl_mbuf); 2130 cur_tx->xl_mbuf = NULL; 2131 } 2132 2133 ifp->if_opackets++; 2134 2135 sc->xl_cdata.xl_tx_cnt--; 2136 XL_INC(idx, XL_TX_LIST_CNT); 2137 } 2138 2139 if (sc->xl_cdata.xl_tx_cnt == 0) 2140 sc->xl_wdog_timer = 0; 2141 sc->xl_cdata.xl_tx_cons = idx; 2142 2143 if (cur_tx != NULL) 2144 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2145 } 2146 2147 /* 2148 * TX 'end of channel' interrupt handler. Actually, we should 2149 * only get a 'TX complete' interrupt if there's a transmit error, 2150 * so this is really TX error handler. 2151 */ 2152 static void 2153 xl_txeoc(struct xl_softc *sc) 2154 { 2155 u_int8_t txstat; 2156 2157 XL_LOCK_ASSERT(sc); 2158 2159 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2160 if (txstat & XL_TXSTATUS_UNDERRUN || 2161 txstat & XL_TXSTATUS_JABBER || 2162 txstat & XL_TXSTATUS_RECLAIM) { 2163 device_printf(sc->xl_dev, 2164 "transmission error: %x\n", txstat); 2165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2166 xl_wait(sc); 2167 if (sc->xl_type == XL_TYPE_905B) { 2168 if (sc->xl_cdata.xl_tx_cnt) { 2169 int i; 2170 struct xl_chain *c; 2171 2172 i = sc->xl_cdata.xl_tx_cons; 2173 c = &sc->xl_cdata.xl_tx_chain[i]; 2174 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2175 c->xl_phys); 2176 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2177 } 2178 } else { 2179 if (sc->xl_cdata.xl_tx_head != NULL) 2180 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2181 sc->xl_cdata.xl_tx_head->xl_phys); 2182 } 2183 /* 2184 * Remember to set this for the 2185 * first generation 3c90X chips. 2186 */ 2187 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2188 if (txstat & XL_TXSTATUS_UNDERRUN && 2189 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2190 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2191 device_printf(sc->xl_dev, 2192 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2193 } 2194 CSR_WRITE_2(sc, XL_COMMAND, 2195 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2196 if (sc->xl_type == XL_TYPE_905B) { 2197 CSR_WRITE_2(sc, XL_COMMAND, 2198 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2199 } 2200 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2201 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2202 } else { 2203 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2204 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2205 } 2206 /* 2207 * Write an arbitrary byte to the TX_STATUS register 2208 * to clear this interrupt/error and advance to the next. 2209 */ 2210 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2211 } 2212 } 2213 2214 static void 2215 xl_intr(void *arg) 2216 { 2217 struct xl_softc *sc = arg; 2218 struct ifnet *ifp = sc->xl_ifp; 2219 u_int16_t status; 2220 2221 XL_LOCK(sc); 2222 2223 #ifdef DEVICE_POLLING 2224 if (ifp->if_capenable & IFCAP_POLLING) { 2225 XL_UNLOCK(sc); 2226 return; 2227 } 2228 #endif 2229 2230 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && 2231 status != 0xFFFF) { 2232 CSR_WRITE_2(sc, XL_COMMAND, 2233 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2234 2235 if (status & XL_STAT_UP_COMPLETE) { 2236 int curpkts; 2237 2238 curpkts = ifp->if_ipackets; 2239 xl_rxeof(sc); 2240 if (curpkts == ifp->if_ipackets) { 2241 while (xl_rx_resync(sc)) 2242 xl_rxeof(sc); 2243 } 2244 } 2245 2246 if (status & XL_STAT_DOWN_COMPLETE) { 2247 if (sc->xl_type == XL_TYPE_905B) 2248 xl_txeof_90xB(sc); 2249 else 2250 xl_txeof(sc); 2251 } 2252 2253 if (status & XL_STAT_TX_COMPLETE) { 2254 ifp->if_oerrors++; 2255 xl_txeoc(sc); 2256 } 2257 2258 if (status & XL_STAT_ADFAIL) { 2259 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2260 xl_init_locked(sc); 2261 } 2262 2263 if (status & XL_STAT_STATSOFLOW) { 2264 sc->xl_stats_no_timeout = 1; 2265 xl_stats_update_locked(sc); 2266 sc->xl_stats_no_timeout = 0; 2267 } 2268 } 2269 2270 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2271 if (sc->xl_type == XL_TYPE_905B) 2272 xl_start_90xB_locked(ifp); 2273 else 2274 xl_start_locked(ifp); 2275 } 2276 2277 XL_UNLOCK(sc); 2278 } 2279 2280 #ifdef DEVICE_POLLING 2281 static int 2282 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2283 { 2284 struct xl_softc *sc = ifp->if_softc; 2285 int rx_npkts = 0; 2286 2287 XL_LOCK(sc); 2288 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2289 rx_npkts = xl_poll_locked(ifp, cmd, count); 2290 XL_UNLOCK(sc); 2291 return (rx_npkts); 2292 } 2293 2294 static int 2295 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2296 { 2297 struct xl_softc *sc = ifp->if_softc; 2298 int rx_npkts; 2299 2300 XL_LOCK_ASSERT(sc); 2301 2302 sc->rxcycles = count; 2303 rx_npkts = xl_rxeof(sc); 2304 if (sc->xl_type == XL_TYPE_905B) 2305 xl_txeof_90xB(sc); 2306 else 2307 xl_txeof(sc); 2308 2309 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2310 if (sc->xl_type == XL_TYPE_905B) 2311 xl_start_90xB_locked(ifp); 2312 else 2313 xl_start_locked(ifp); 2314 } 2315 2316 if (cmd == POLL_AND_CHECK_STATUS) { 2317 u_int16_t status; 2318 2319 status = CSR_READ_2(sc, XL_STATUS); 2320 if (status & XL_INTRS && status != 0xFFFF) { 2321 CSR_WRITE_2(sc, XL_COMMAND, 2322 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2323 2324 if (status & XL_STAT_TX_COMPLETE) { 2325 ifp->if_oerrors++; 2326 xl_txeoc(sc); 2327 } 2328 2329 if (status & XL_STAT_ADFAIL) { 2330 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2331 xl_init_locked(sc); 2332 } 2333 2334 if (status & XL_STAT_STATSOFLOW) { 2335 sc->xl_stats_no_timeout = 1; 2336 xl_stats_update_locked(sc); 2337 sc->xl_stats_no_timeout = 0; 2338 } 2339 } 2340 } 2341 return (rx_npkts); 2342 } 2343 #endif /* DEVICE_POLLING */ 2344 2345 /* 2346 * XXX: This is an entry point for callout which needs to take the lock. 2347 */ 2348 static void 2349 xl_stats_update(void *xsc) 2350 { 2351 struct xl_softc *sc = xsc; 2352 2353 XL_LOCK_ASSERT(sc); 2354 2355 if (xl_watchdog(sc) == EJUSTRETURN) 2356 return; 2357 2358 xl_stats_update_locked(sc); 2359 } 2360 2361 static void 2362 xl_stats_update_locked(struct xl_softc *sc) 2363 { 2364 struct ifnet *ifp = sc->xl_ifp; 2365 struct xl_stats xl_stats; 2366 u_int8_t *p; 2367 int i; 2368 struct mii_data *mii = NULL; 2369 2370 XL_LOCK_ASSERT(sc); 2371 2372 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2373 2374 if (sc->xl_miibus != NULL) 2375 mii = device_get_softc(sc->xl_miibus); 2376 2377 p = (u_int8_t *)&xl_stats; 2378 2379 /* Read all the stats registers. */ 2380 XL_SEL_WIN(6); 2381 2382 for (i = 0; i < 16; i++) 2383 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2384 2385 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2386 2387 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2388 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision; 2389 2390 /* 2391 * Boomerang and cyclone chips have an extra stats counter 2392 * in window 4 (BadSSD). We have to read this too in order 2393 * to clear out all the stats registers and avoid a statsoflow 2394 * interrupt. 2395 */ 2396 XL_SEL_WIN(4); 2397 CSR_READ_1(sc, XL_W4_BADSSD); 2398 2399 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2400 mii_tick(mii); 2401 2402 XL_SEL_WIN(7); 2403 2404 if (!sc->xl_stats_no_timeout) 2405 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2406 } 2407 2408 /* 2409 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2410 * pointers to the fragment pointers. 2411 */ 2412 static int 2413 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) 2414 { 2415 struct mbuf *m_new; 2416 struct ifnet *ifp = sc->xl_ifp; 2417 int error, i, nseg, total_len; 2418 u_int32_t status; 2419 2420 XL_LOCK_ASSERT(sc); 2421 2422 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, 2423 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2424 2425 if (error && error != EFBIG) { 2426 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2427 return (error); 2428 } 2429 2430 /* 2431 * Handle special case: we used up all 63 fragments, 2432 * but we have more mbufs left in the chain. Copy the 2433 * data into an mbuf cluster. Note that we don't 2434 * bother clearing the values in the other fragment 2435 * pointers/counters; it wouldn't gain us anything, 2436 * and would waste cycles. 2437 */ 2438 if (error) { 2439 m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS); 2440 if (m_new == NULL) { 2441 m_freem(*m_head); 2442 *m_head = NULL; 2443 return (ENOBUFS); 2444 } 2445 *m_head = m_new; 2446 2447 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, 2448 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2449 if (error) { 2450 m_freem(*m_head); 2451 *m_head = NULL; 2452 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2453 return (error); 2454 } 2455 } 2456 2457 KASSERT(nseg <= XL_MAXFRAGS, 2458 ("%s: too many DMA segments (%d)", __func__, nseg)); 2459 if (nseg == 0) { 2460 m_freem(*m_head); 2461 *m_head = NULL; 2462 return (EIO); 2463 } 2464 2465 total_len = 0; 2466 for (i = 0; i < nseg; i++) { 2467 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, 2468 ("segment size too large")); 2469 c->xl_ptr->xl_frag[i].xl_addr = 2470 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); 2471 c->xl_ptr->xl_frag[i].xl_len = 2472 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); 2473 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; 2474 } 2475 c->xl_ptr->xl_frag[nseg - 1].xl_len = 2476 htole32(sc->xl_cdata.xl_tx_segs[nseg - 1].ds_len | XL_LAST_FRAG); 2477 c->xl_ptr->xl_status = htole32(total_len); 2478 c->xl_ptr->xl_next = 0; 2479 2480 if (sc->xl_type == XL_TYPE_905B) { 2481 status = XL_TXSTAT_RND_DEFEAT; 2482 2483 #ifndef XL905B_TXCSUM_BROKEN 2484 if ((*m_head)->m_pkthdr.csum_flags) { 2485 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2486 status |= XL_TXSTAT_IPCKSUM; 2487 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2488 status |= XL_TXSTAT_TCPCKSUM; 2489 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2490 status |= XL_TXSTAT_UDPCKSUM; 2491 } 2492 #endif 2493 c->xl_ptr->xl_status = htole32(status); 2494 } 2495 2496 c->xl_mbuf = *m_head; 2497 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2498 return (0); 2499 } 2500 2501 /* 2502 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2503 * to the mbuf data regions directly in the transmit lists. We also save a 2504 * copy of the pointers since the transmit list fragment pointers are 2505 * physical addresses. 2506 */ 2507 2508 static void 2509 xl_start(struct ifnet *ifp) 2510 { 2511 struct xl_softc *sc = ifp->if_softc; 2512 2513 XL_LOCK(sc); 2514 2515 if (sc->xl_type == XL_TYPE_905B) 2516 xl_start_90xB_locked(ifp); 2517 else 2518 xl_start_locked(ifp); 2519 2520 XL_UNLOCK(sc); 2521 } 2522 2523 static void 2524 xl_start_locked(struct ifnet *ifp) 2525 { 2526 struct xl_softc *sc = ifp->if_softc; 2527 struct mbuf *m_head = NULL; 2528 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2529 u_int32_t status; 2530 int error; 2531 2532 XL_LOCK_ASSERT(sc); 2533 2534 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2535 IFF_DRV_RUNNING) 2536 return; 2537 /* 2538 * Check for an available queue slot. If there are none, 2539 * punt. 2540 */ 2541 if (sc->xl_cdata.xl_tx_free == NULL) { 2542 xl_txeoc(sc); 2543 xl_txeof(sc); 2544 if (sc->xl_cdata.xl_tx_free == NULL) { 2545 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2546 return; 2547 } 2548 } 2549 2550 start_tx = sc->xl_cdata.xl_tx_free; 2551 2552 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2553 sc->xl_cdata.xl_tx_free != NULL;) { 2554 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2555 if (m_head == NULL) 2556 break; 2557 2558 /* Pick a descriptor off the free list. */ 2559 cur_tx = sc->xl_cdata.xl_tx_free; 2560 2561 /* Pack the data into the descriptor. */ 2562 error = xl_encap(sc, cur_tx, &m_head); 2563 if (error) { 2564 if (m_head == NULL) 2565 break; 2566 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2567 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2568 break; 2569 } 2570 2571 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2572 cur_tx->xl_next = NULL; 2573 2574 /* Chain it together. */ 2575 if (prev != NULL) { 2576 prev->xl_next = cur_tx; 2577 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2578 } 2579 prev = cur_tx; 2580 2581 /* 2582 * If there's a BPF listener, bounce a copy of this frame 2583 * to him. 2584 */ 2585 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2586 } 2587 2588 /* 2589 * If there are no packets queued, bail. 2590 */ 2591 if (cur_tx == NULL) 2592 return; 2593 2594 /* 2595 * Place the request for the upload interrupt 2596 * in the last descriptor in the chain. This way, if 2597 * we're chaining several packets at once, we'll only 2598 * get an interrupt once for the whole chain rather than 2599 * once for each packet. 2600 */ 2601 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2602 XL_TXSTAT_DL_INTR); 2603 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2604 BUS_DMASYNC_PREWRITE); 2605 2606 /* 2607 * Queue the packets. If the TX channel is clear, update 2608 * the downlist pointer register. 2609 */ 2610 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2611 xl_wait(sc); 2612 2613 if (sc->xl_cdata.xl_tx_head != NULL) { 2614 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2615 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2616 htole32(start_tx->xl_phys); 2617 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2618 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2619 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2620 sc->xl_cdata.xl_tx_tail = cur_tx; 2621 } else { 2622 sc->xl_cdata.xl_tx_head = start_tx; 2623 sc->xl_cdata.xl_tx_tail = cur_tx; 2624 } 2625 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2626 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2627 2628 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2629 2630 XL_SEL_WIN(7); 2631 2632 /* 2633 * Set a timeout in case the chip goes out to lunch. 2634 */ 2635 sc->xl_wdog_timer = 5; 2636 2637 /* 2638 * XXX Under certain conditions, usually on slower machines 2639 * where interrupts may be dropped, it's possible for the 2640 * adapter to chew up all the buffers in the receive ring 2641 * and stall, without us being able to do anything about it. 2642 * To guard against this, we need to make a pass over the 2643 * RX queue to make sure there aren't any packets pending. 2644 * Doing it here means we can flush the receive ring at the 2645 * same time the chip is DMAing the transmit descriptors we 2646 * just gave it. 2647 * 2648 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2649 * nature of their chips in all their marketing literature; 2650 * we may as well take advantage of it. :) 2651 */ 2652 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2653 } 2654 2655 static void 2656 xl_start_90xB_locked(struct ifnet *ifp) 2657 { 2658 struct xl_softc *sc = ifp->if_softc; 2659 struct mbuf *m_head = NULL; 2660 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2661 int error, idx; 2662 2663 XL_LOCK_ASSERT(sc); 2664 2665 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2666 IFF_DRV_RUNNING) 2667 return; 2668 2669 idx = sc->xl_cdata.xl_tx_prod; 2670 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2671 2672 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2673 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { 2674 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2675 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2676 break; 2677 } 2678 2679 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2680 if (m_head == NULL) 2681 break; 2682 2683 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2684 2685 /* Pack the data into the descriptor. */ 2686 error = xl_encap(sc, cur_tx, &m_head); 2687 if (error) { 2688 if (m_head == NULL) 2689 break; 2690 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2691 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2692 break; 2693 } 2694 2695 /* Chain it together. */ 2696 if (prev != NULL) 2697 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2698 prev = cur_tx; 2699 2700 /* 2701 * If there's a BPF listener, bounce a copy of this frame 2702 * to him. 2703 */ 2704 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2705 2706 XL_INC(idx, XL_TX_LIST_CNT); 2707 sc->xl_cdata.xl_tx_cnt++; 2708 } 2709 2710 /* 2711 * If there are no packets queued, bail. 2712 */ 2713 if (cur_tx == NULL) 2714 return; 2715 2716 /* 2717 * Place the request for the upload interrupt 2718 * in the last descriptor in the chain. This way, if 2719 * we're chaining several packets at once, we'll only 2720 * get an interrupt once for the whole chain rather than 2721 * once for each packet. 2722 */ 2723 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2724 XL_TXSTAT_DL_INTR); 2725 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2726 BUS_DMASYNC_PREWRITE); 2727 2728 /* Start transmission */ 2729 sc->xl_cdata.xl_tx_prod = idx; 2730 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2731 2732 /* 2733 * Set a timeout in case the chip goes out to lunch. 2734 */ 2735 sc->xl_wdog_timer = 5; 2736 } 2737 2738 static void 2739 xl_init(void *xsc) 2740 { 2741 struct xl_softc *sc = xsc; 2742 2743 XL_LOCK(sc); 2744 xl_init_locked(sc); 2745 XL_UNLOCK(sc); 2746 } 2747 2748 static void 2749 xl_init_locked(struct xl_softc *sc) 2750 { 2751 struct ifnet *ifp = sc->xl_ifp; 2752 int error, i; 2753 u_int16_t rxfilt = 0; 2754 struct mii_data *mii = NULL; 2755 2756 XL_LOCK_ASSERT(sc); 2757 2758 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2759 return; 2760 /* 2761 * Cancel pending I/O and free all RX/TX buffers. 2762 */ 2763 xl_stop(sc); 2764 2765 /* Reset the chip to a known state. */ 2766 xl_reset(sc); 2767 2768 if (sc->xl_miibus == NULL) { 2769 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2770 xl_wait(sc); 2771 } 2772 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2773 xl_wait(sc); 2774 DELAY(10000); 2775 2776 if (sc->xl_miibus != NULL) 2777 mii = device_get_softc(sc->xl_miibus); 2778 2779 /* 2780 * Clear WOL status and disable all WOL feature as WOL 2781 * would interfere Rx operation under normal environments. 2782 */ 2783 if ((sc->xl_flags & XL_FLAG_WOL) != 0) { 2784 XL_SEL_WIN(7); 2785 CSR_READ_2(sc, XL_W7_BM_PME); 2786 CSR_WRITE_2(sc, XL_W7_BM_PME, 0); 2787 } 2788 /* Init our MAC address */ 2789 XL_SEL_WIN(2); 2790 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2791 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2792 IF_LLADDR(sc->xl_ifp)[i]); 2793 } 2794 2795 /* Clear the station mask. */ 2796 for (i = 0; i < 3; i++) 2797 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2798 #ifdef notdef 2799 /* Reset TX and RX. */ 2800 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2801 xl_wait(sc); 2802 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2803 xl_wait(sc); 2804 #endif 2805 /* Init circular RX list. */ 2806 error = xl_list_rx_init(sc); 2807 if (error) { 2808 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n", 2809 error); 2810 xl_stop(sc); 2811 return; 2812 } 2813 2814 /* Init TX descriptors. */ 2815 if (sc->xl_type == XL_TYPE_905B) 2816 error = xl_list_tx_init_90xB(sc); 2817 else 2818 error = xl_list_tx_init(sc); 2819 if (error) { 2820 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n", 2821 error); 2822 xl_stop(sc); 2823 return; 2824 } 2825 2826 /* 2827 * Set the TX freethresh value. 2828 * Note that this has no effect on 3c905B "cyclone" 2829 * cards but is required for 3c900/3c905 "boomerang" 2830 * cards in order to enable the download engine. 2831 */ 2832 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2833 2834 /* Set the TX start threshold for best performance. */ 2835 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2836 2837 /* 2838 * If this is a 3c905B, also set the tx reclaim threshold. 2839 * This helps cut down on the number of tx reclaim errors 2840 * that could happen on a busy network. The chip multiplies 2841 * the register value by 16 to obtain the actual threshold 2842 * in bytes, so we divide by 16 when setting the value here. 2843 * The existing threshold value can be examined by reading 2844 * the register at offset 9 in window 5. 2845 */ 2846 if (sc->xl_type == XL_TYPE_905B) { 2847 CSR_WRITE_2(sc, XL_COMMAND, 2848 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2849 } 2850 2851 /* Set RX filter bits. */ 2852 XL_SEL_WIN(5); 2853 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2854 2855 /* Set the individual bit to receive frames for this host only. */ 2856 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2857 2858 /* If we want promiscuous mode, set the allframes bit. */ 2859 if (ifp->if_flags & IFF_PROMISC) { 2860 rxfilt |= XL_RXFILTER_ALLFRAMES; 2861 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2862 } else { 2863 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2865 } 2866 2867 /* 2868 * Set capture broadcast bit to capture broadcast frames. 2869 */ 2870 if (ifp->if_flags & IFF_BROADCAST) { 2871 rxfilt |= XL_RXFILTER_BROADCAST; 2872 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2873 } else { 2874 rxfilt &= ~XL_RXFILTER_BROADCAST; 2875 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2876 } 2877 2878 /* 2879 * Program the multicast filter, if necessary. 2880 */ 2881 if (sc->xl_type == XL_TYPE_905B) 2882 xl_setmulti_hash(sc); 2883 else 2884 xl_setmulti(sc); 2885 2886 /* 2887 * Load the address of the RX list. We have to 2888 * stall the upload engine before we can manipulate 2889 * the uplist pointer register, then unstall it when 2890 * we're finished. We also have to wait for the 2891 * stall command to complete before proceeding. 2892 * Note that we have to do this after any RX resets 2893 * have completed since the uplist register is cleared 2894 * by a reset. 2895 */ 2896 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2897 xl_wait(sc); 2898 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2899 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2900 xl_wait(sc); 2901 2902 if (sc->xl_type == XL_TYPE_905B) { 2903 /* Set polling interval */ 2904 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2905 /* Load the address of the TX list */ 2906 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2907 xl_wait(sc); 2908 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2909 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2910 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2911 xl_wait(sc); 2912 } 2913 2914 /* 2915 * If the coax transceiver is on, make sure to enable 2916 * the DC-DC converter. 2917 */ 2918 XL_SEL_WIN(3); 2919 if (sc->xl_xcvr == XL_XCVR_COAX) 2920 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2921 else 2922 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2923 2924 /* 2925 * increase packet size to allow reception of 802.1q or ISL packets. 2926 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2927 * control register. For 3c90xB/C chips, use the RX packet size 2928 * register. 2929 */ 2930 2931 if (sc->xl_type == XL_TYPE_905B) 2932 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2933 else { 2934 u_int8_t macctl; 2935 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2936 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2937 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2938 } 2939 2940 /* Clear out the stats counters. */ 2941 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2942 sc->xl_stats_no_timeout = 1; 2943 xl_stats_update_locked(sc); 2944 sc->xl_stats_no_timeout = 0; 2945 XL_SEL_WIN(4); 2946 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2947 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2948 2949 /* 2950 * Enable interrupts. 2951 */ 2952 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2953 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2954 #ifdef DEVICE_POLLING 2955 /* Disable interrupts if we are polling. */ 2956 if (ifp->if_capenable & IFCAP_POLLING) 2957 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2958 else 2959 #endif 2960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2961 if (sc->xl_flags & XL_FLAG_FUNCREG) 2962 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2963 2964 /* Set the RX early threshold */ 2965 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2966 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2967 2968 /* Enable receiver and transmitter. */ 2969 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2970 xl_wait(sc); 2971 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2972 xl_wait(sc); 2973 2974 /* XXX Downcall to miibus. */ 2975 if (mii != NULL) 2976 mii_mediachg(mii); 2977 2978 /* Select window 7 for normal operations. */ 2979 XL_SEL_WIN(7); 2980 2981 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2982 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2983 2984 sc->xl_wdog_timer = 0; 2985 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2986 } 2987 2988 /* 2989 * Set media options. 2990 */ 2991 static int 2992 xl_ifmedia_upd(struct ifnet *ifp) 2993 { 2994 struct xl_softc *sc = ifp->if_softc; 2995 struct ifmedia *ifm = NULL; 2996 struct mii_data *mii = NULL; 2997 2998 XL_LOCK(sc); 2999 3000 if (sc->xl_miibus != NULL) 3001 mii = device_get_softc(sc->xl_miibus); 3002 if (mii == NULL) 3003 ifm = &sc->ifmedia; 3004 else 3005 ifm = &mii->mii_media; 3006 3007 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3008 case IFM_100_FX: 3009 case IFM_10_FL: 3010 case IFM_10_2: 3011 case IFM_10_5: 3012 xl_setmode(sc, ifm->ifm_media); 3013 XL_UNLOCK(sc); 3014 return (0); 3015 } 3016 3017 if (sc->xl_media & XL_MEDIAOPT_MII || 3018 sc->xl_media & XL_MEDIAOPT_BTX || 3019 sc->xl_media & XL_MEDIAOPT_BT4) { 3020 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3021 xl_init_locked(sc); 3022 } else { 3023 xl_setmode(sc, ifm->ifm_media); 3024 } 3025 3026 XL_UNLOCK(sc); 3027 3028 return (0); 3029 } 3030 3031 /* 3032 * Report current media status. 3033 */ 3034 static void 3035 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3036 { 3037 struct xl_softc *sc = ifp->if_softc; 3038 u_int32_t icfg; 3039 u_int16_t status = 0; 3040 struct mii_data *mii = NULL; 3041 3042 XL_LOCK(sc); 3043 3044 if (sc->xl_miibus != NULL) 3045 mii = device_get_softc(sc->xl_miibus); 3046 3047 XL_SEL_WIN(4); 3048 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3049 3050 XL_SEL_WIN(3); 3051 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3052 icfg >>= XL_ICFG_CONNECTOR_BITS; 3053 3054 ifmr->ifm_active = IFM_ETHER; 3055 ifmr->ifm_status = IFM_AVALID; 3056 3057 if ((status & XL_MEDIASTAT_CARRIER) == 0) 3058 ifmr->ifm_status |= IFM_ACTIVE; 3059 3060 switch (icfg) { 3061 case XL_XCVR_10BT: 3062 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3063 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3064 ifmr->ifm_active |= IFM_FDX; 3065 else 3066 ifmr->ifm_active |= IFM_HDX; 3067 break; 3068 case XL_XCVR_AUI: 3069 if (sc->xl_type == XL_TYPE_905B && 3070 sc->xl_media == XL_MEDIAOPT_10FL) { 3071 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3072 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3073 ifmr->ifm_active |= IFM_FDX; 3074 else 3075 ifmr->ifm_active |= IFM_HDX; 3076 } else 3077 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3078 break; 3079 case XL_XCVR_COAX: 3080 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3081 break; 3082 /* 3083 * XXX MII and BTX/AUTO should be separate cases. 3084 */ 3085 3086 case XL_XCVR_100BTX: 3087 case XL_XCVR_AUTO: 3088 case XL_XCVR_MII: 3089 if (mii != NULL) { 3090 mii_pollstat(mii); 3091 ifmr->ifm_active = mii->mii_media_active; 3092 ifmr->ifm_status = mii->mii_media_status; 3093 } 3094 break; 3095 case XL_XCVR_100BFX: 3096 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3097 break; 3098 default: 3099 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3100 break; 3101 } 3102 3103 XL_UNLOCK(sc); 3104 } 3105 3106 static int 3107 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3108 { 3109 struct xl_softc *sc = ifp->if_softc; 3110 struct ifreq *ifr = (struct ifreq *) data; 3111 int error = 0, mask; 3112 struct mii_data *mii = NULL; 3113 u_int8_t rxfilt; 3114 3115 switch (command) { 3116 case SIOCSIFFLAGS: 3117 XL_LOCK(sc); 3118 3119 XL_SEL_WIN(5); 3120 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3121 if (ifp->if_flags & IFF_UP) { 3122 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3123 ifp->if_flags & IFF_PROMISC && 3124 !(sc->xl_if_flags & IFF_PROMISC)) { 3125 rxfilt |= XL_RXFILTER_ALLFRAMES; 3126 CSR_WRITE_2(sc, XL_COMMAND, 3127 XL_CMD_RX_SET_FILT|rxfilt); 3128 XL_SEL_WIN(7); 3129 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3130 !(ifp->if_flags & IFF_PROMISC) && 3131 sc->xl_if_flags & IFF_PROMISC) { 3132 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3133 CSR_WRITE_2(sc, XL_COMMAND, 3134 XL_CMD_RX_SET_FILT|rxfilt); 3135 XL_SEL_WIN(7); 3136 } else 3137 xl_init_locked(sc); 3138 } else { 3139 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3140 xl_stop(sc); 3141 } 3142 sc->xl_if_flags = ifp->if_flags; 3143 XL_UNLOCK(sc); 3144 error = 0; 3145 break; 3146 case SIOCADDMULTI: 3147 case SIOCDELMULTI: 3148 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3149 XL_LOCK(sc); 3150 if (sc->xl_type == XL_TYPE_905B) 3151 xl_setmulti_hash(sc); 3152 else 3153 xl_setmulti(sc); 3154 XL_UNLOCK(sc); 3155 error = 0; 3156 break; 3157 case SIOCGIFMEDIA: 3158 case SIOCSIFMEDIA: 3159 if (sc->xl_miibus != NULL) 3160 mii = device_get_softc(sc->xl_miibus); 3161 if (mii == NULL) 3162 error = ifmedia_ioctl(ifp, ifr, 3163 &sc->ifmedia, command); 3164 else 3165 error = ifmedia_ioctl(ifp, ifr, 3166 &mii->mii_media, command); 3167 break; 3168 case SIOCSIFCAP: 3169 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3170 #ifdef DEVICE_POLLING 3171 if ((mask & IFCAP_POLLING) != 0 && 3172 (ifp->if_capabilities & IFCAP_POLLING) != 0) { 3173 ifp->if_capenable ^= IFCAP_POLLING; 3174 if ((ifp->if_capenable & IFCAP_POLLING) != 0) { 3175 error = ether_poll_register(xl_poll, ifp); 3176 if (error) 3177 break; 3178 XL_LOCK(sc); 3179 /* Disable interrupts */ 3180 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3181 ifp->if_capenable |= IFCAP_POLLING; 3182 XL_UNLOCK(sc); 3183 } else { 3184 error = ether_poll_deregister(ifp); 3185 /* Enable interrupts. */ 3186 XL_LOCK(sc); 3187 CSR_WRITE_2(sc, XL_COMMAND, 3188 XL_CMD_INTR_ACK | 0xFF); 3189 CSR_WRITE_2(sc, XL_COMMAND, 3190 XL_CMD_INTR_ENB | XL_INTRS); 3191 if (sc->xl_flags & XL_FLAG_FUNCREG) 3192 bus_space_write_4(sc->xl_ftag, 3193 sc->xl_fhandle, 4, 0x8000); 3194 XL_UNLOCK(sc); 3195 } 3196 } 3197 #endif /* DEVICE_POLLING */ 3198 XL_LOCK(sc); 3199 if ((mask & IFCAP_TXCSUM) != 0 && 3200 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3201 ifp->if_capenable ^= IFCAP_TXCSUM; 3202 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3203 ifp->if_hwassist |= XL905B_CSUM_FEATURES; 3204 else 3205 ifp->if_hwassist &= ~XL905B_CSUM_FEATURES; 3206 } 3207 if ((mask & IFCAP_RXCSUM) != 0 && 3208 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3209 ifp->if_capenable ^= IFCAP_RXCSUM; 3210 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3211 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3212 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3213 XL_UNLOCK(sc); 3214 break; 3215 default: 3216 error = ether_ioctl(ifp, command, data); 3217 break; 3218 } 3219 3220 return (error); 3221 } 3222 3223 static int 3224 xl_watchdog(struct xl_softc *sc) 3225 { 3226 struct ifnet *ifp = sc->xl_ifp; 3227 u_int16_t status = 0; 3228 int misintr; 3229 3230 XL_LOCK_ASSERT(sc); 3231 3232 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) 3233 return (0); 3234 3235 xl_rxeof(sc); 3236 xl_txeoc(sc); 3237 misintr = 0; 3238 if (sc->xl_type == XL_TYPE_905B) { 3239 xl_txeof_90xB(sc); 3240 if (sc->xl_cdata.xl_tx_cnt == 0) 3241 misintr++; 3242 } else { 3243 xl_txeof(sc); 3244 if (sc->xl_cdata.xl_tx_head == NULL) 3245 misintr++; 3246 } 3247 if (misintr != 0) { 3248 device_printf(sc->xl_dev, 3249 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 3250 return (0); 3251 } 3252 3253 ifp->if_oerrors++; 3254 XL_SEL_WIN(4); 3255 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3256 device_printf(sc->xl_dev, "watchdog timeout\n"); 3257 3258 if (status & XL_MEDIASTAT_CARRIER) 3259 device_printf(sc->xl_dev, 3260 "no carrier - transceiver cable problem?\n"); 3261 3262 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3263 xl_init_locked(sc); 3264 3265 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 3266 if (sc->xl_type == XL_TYPE_905B) 3267 xl_start_90xB_locked(ifp); 3268 else 3269 xl_start_locked(ifp); 3270 } 3271 3272 return (EJUSTRETURN); 3273 } 3274 3275 /* 3276 * Stop the adapter and free any mbufs allocated to the 3277 * RX and TX lists. 3278 */ 3279 static void 3280 xl_stop(struct xl_softc *sc) 3281 { 3282 register int i; 3283 struct ifnet *ifp = sc->xl_ifp; 3284 3285 XL_LOCK_ASSERT(sc); 3286 3287 sc->xl_wdog_timer = 0; 3288 3289 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3290 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3291 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3292 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3293 xl_wait(sc); 3294 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3295 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3296 DELAY(800); 3297 3298 #ifdef foo 3299 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3300 xl_wait(sc); 3301 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3302 xl_wait(sc); 3303 #endif 3304 3305 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3306 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3307 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3308 if (sc->xl_flags & XL_FLAG_FUNCREG) 3309 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3310 3311 /* Stop the stats updater. */ 3312 callout_stop(&sc->xl_stat_callout); 3313 3314 /* 3315 * Free data in the RX lists. 3316 */ 3317 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3318 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3319 bus_dmamap_unload(sc->xl_mtag, 3320 sc->xl_cdata.xl_rx_chain[i].xl_map); 3321 bus_dmamap_destroy(sc->xl_mtag, 3322 sc->xl_cdata.xl_rx_chain[i].xl_map); 3323 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3324 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3325 } 3326 } 3327 if (sc->xl_ldata.xl_rx_list != NULL) 3328 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3329 /* 3330 * Free the TX list buffers. 3331 */ 3332 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3333 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3334 bus_dmamap_unload(sc->xl_mtag, 3335 sc->xl_cdata.xl_tx_chain[i].xl_map); 3336 bus_dmamap_destroy(sc->xl_mtag, 3337 sc->xl_cdata.xl_tx_chain[i].xl_map); 3338 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3339 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3340 } 3341 } 3342 if (sc->xl_ldata.xl_tx_list != NULL) 3343 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3344 3345 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3346 } 3347 3348 /* 3349 * Stop all chip I/O so that the kernel's probe routines don't 3350 * get confused by errant DMAs when rebooting. 3351 */ 3352 static int 3353 xl_shutdown(device_t dev) 3354 { 3355 3356 return (xl_suspend(dev)); 3357 } 3358 3359 static int 3360 xl_suspend(device_t dev) 3361 { 3362 struct xl_softc *sc; 3363 3364 sc = device_get_softc(dev); 3365 3366 XL_LOCK(sc); 3367 xl_stop(sc); 3368 xl_setwol(sc); 3369 XL_UNLOCK(sc); 3370 3371 return (0); 3372 } 3373 3374 static int 3375 xl_resume(device_t dev) 3376 { 3377 struct xl_softc *sc; 3378 struct ifnet *ifp; 3379 3380 sc = device_get_softc(dev); 3381 ifp = sc->xl_ifp; 3382 3383 XL_LOCK(sc); 3384 3385 if (ifp->if_flags & IFF_UP) { 3386 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3387 xl_init_locked(sc); 3388 } 3389 3390 XL_UNLOCK(sc); 3391 3392 return (0); 3393 } 3394 3395 static void 3396 xl_setwol(struct xl_softc *sc) 3397 { 3398 struct ifnet *ifp; 3399 u_int16_t cfg, pmstat; 3400 3401 if ((sc->xl_flags & XL_FLAG_WOL) == 0) 3402 return; 3403 3404 ifp = sc->xl_ifp; 3405 XL_SEL_WIN(7); 3406 /* Clear any pending PME events. */ 3407 CSR_READ_2(sc, XL_W7_BM_PME); 3408 cfg = 0; 3409 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3410 cfg |= XL_BM_PME_MAGIC; 3411 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg); 3412 /* Enable RX. */ 3413 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3414 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 3415 /* Request PME. */ 3416 pmstat = pci_read_config(sc->xl_dev, 3417 sc->xl_pmcap + PCIR_POWER_STATUS, 2); 3418 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3419 pmstat |= PCIM_PSTAT_PMEENABLE; 3420 else 3421 pmstat &= ~PCIM_PSTAT_PMEENABLE; 3422 pci_write_config(sc->xl_dev, 3423 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2); 3424 } 3425