1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * 3Com 3c90x Etherlink XL PCI NIC driver 40 * 41 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 42 * bus-master chips (3c90x cards and embedded controllers) including 43 * the following: 44 * 45 * 3Com 3c900-TPO 10Mbps/RJ-45 46 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 47 * 3Com 3c905-TX 10/100Mbps/RJ-45 48 * 3Com 3c905-T4 10/100Mbps/RJ-45 49 * 3Com 3c900B-TPO 10Mbps/RJ-45 50 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 51 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 52 * 3Com 3c900B-FL 10Mbps/Fiber-optic 53 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 54 * 3Com 3c905B-TX 10/100Mbps/RJ-45 55 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 56 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 57 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 58 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 59 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 60 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 61 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 62 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 63 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 64 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 68 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 69 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 70 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 71 * Dell on-board 3c920 10/100Mbps/RJ-45 72 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 73 * Dell Latitude laptop docking station embedded 3c905-TX 74 * 75 * Written by Bill Paul <wpaul@ctr.columbia.edu> 76 * Electrical Engineering Department 77 * Columbia University, New York City 78 */ 79 /* 80 * The 3c90x series chips use a bus-master DMA interface for transferring 81 * packets to and from the controller chip. Some of the "vortex" cards 82 * (3c59x) also supported a bus master mode, however for those chips 83 * you could only DMA packets to/from a contiguous memory buffer. For 84 * transmission this would mean copying the contents of the queued mbuf 85 * chain into an mbuf cluster and then DMAing the cluster. This extra 86 * copy would sort of defeat the purpose of the bus master support for 87 * any packet that doesn't fit into a single mbuf. 88 * 89 * By contrast, the 3c90x cards support a fragment-based bus master 90 * mode where mbuf chains can be encapsulated using TX descriptors. 91 * This is similar to other PCI chips such as the Texas Instruments 92 * ThunderLAN and the Intel 82557/82558. 93 * 94 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 95 * bus master chips because they maintain the old PIO interface for 96 * backwards compatibility, but starting with the 3c905B and the 97 * "cyclone" chips, the compatibility interface has been dropped. 98 * Since using bus master DMA is a big win, we use this driver to 99 * support the PCI "boomerang" chips even though they work with the 100 * "vortex" driver in order to obtain better performance. 101 */ 102 103 #ifdef HAVE_KERNEL_OPTION_HEADERS 104 #include "opt_device_polling.h" 105 #endif 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/sockio.h> 110 #include <sys/endian.h> 111 #include <sys/kernel.h> 112 #include <sys/malloc.h> 113 #include <sys/mbuf.h> 114 #include <sys/module.h> 115 #include <sys/socket.h> 116 #include <sys/taskqueue.h> 117 118 #include <net/if.h> 119 #include <net/if_var.h> 120 #include <net/if_arp.h> 121 #include <net/ethernet.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/if_types.h> 125 126 #include <net/bpf.h> 127 128 #include <machine/bus.h> 129 #include <machine/resource.h> 130 #include <sys/bus.h> 131 #include <sys/rman.h> 132 133 #include <dev/mii/mii.h> 134 #include <dev/mii/mii_bitbang.h> 135 #include <dev/mii/miivar.h> 136 137 #include <dev/pci/pcireg.h> 138 #include <dev/pci/pcivar.h> 139 140 MODULE_DEPEND(xl, pci, 1, 1, 1); 141 MODULE_DEPEND(xl, ether, 1, 1, 1); 142 MODULE_DEPEND(xl, miibus, 1, 1, 1); 143 144 /* "device miibus" required. See GENERIC if you get errors here. */ 145 #include "miibus_if.h" 146 147 #include <dev/xl/if_xlreg.h> 148 149 /* 150 * TX Checksumming is disabled by default for two reasons: 151 * - TX Checksumming will occasionally produce corrupt packets 152 * - TX Checksumming seems to reduce performance 153 * 154 * Only 905B/C cards were reported to have this problem, it is possible 155 * that later chips _may_ be immune. 156 */ 157 #define XL905B_TXCSUM_BROKEN 1 158 159 #ifdef XL905B_TXCSUM_BROKEN 160 #define XL905B_CSUM_FEATURES 0 161 #else 162 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 #endif 164 165 /* 166 * Various supported device vendors/types and their names. 167 */ 168 static const struct xl_type xl_devs[] = { 169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 170 "3Com 3c900-TPO Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 172 "3Com 3c900-COMBO Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 174 "3Com 3c905-TX Fast Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 176 "3Com 3c905-T4 Fast Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 178 "3Com 3c900B-TPO Etherlink XL" }, 179 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 180 "3Com 3c900B-COMBO Etherlink XL" }, 181 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 182 "3Com 3c900B-TPC Etherlink XL" }, 183 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 184 "3Com 3c900B-FL Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 186 "3Com 3c905B-TX Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 188 "3Com 3c905B-T4 Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 190 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 192 "3Com 3c905B-COMBO Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 194 "3Com 3c905C-TX Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 196 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 197 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 198 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 199 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 200 "3Com 3c980 Fast Etherlink XL" }, 201 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 202 "3Com 3c980C Fast Etherlink XL" }, 203 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 204 "3Com 3cSOHO100-TX OfficeConnect" }, 205 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 206 "3Com 3c450-TX HomeConnect" }, 207 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 208 "3Com 3c555 Fast Etherlink XL" }, 209 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 210 "3Com 3c556 Fast Etherlink XL" }, 211 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 212 "3Com 3c556B Fast Etherlink XL" }, 213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 214 "3Com 3c575TX Fast Etherlink XL" }, 215 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 216 "3Com 3c575B Fast Etherlink XL" }, 217 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 218 "3Com 3c575C Fast Etherlink XL" }, 219 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 220 "3Com 3c656 Fast Etherlink XL" }, 221 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 222 "3Com 3c656B Fast Etherlink XL" }, 223 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 224 "3Com 3c656C Fast Etherlink XL" }, 225 { 0, 0, NULL } 226 }; 227 228 static int xl_probe(device_t); 229 static int xl_attach(device_t); 230 static int xl_detach(device_t); 231 232 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 233 static void xl_tick(void *); 234 static void xl_stats_update(struct xl_softc *); 235 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); 236 static int xl_rxeof(struct xl_softc *); 237 static void xl_rxeof_task(void *, int); 238 static int xl_rx_resync(struct xl_softc *); 239 static void xl_txeof(struct xl_softc *); 240 static void xl_txeof_90xB(struct xl_softc *); 241 static void xl_txeoc(struct xl_softc *); 242 static void xl_intr(void *); 243 static void xl_start(if_t); 244 static void xl_start_locked(if_t); 245 static void xl_start_90xB_locked(if_t); 246 static int xl_ioctl(if_t, u_long, caddr_t); 247 static void xl_init(void *); 248 static void xl_init_locked(struct xl_softc *); 249 static void xl_stop(struct xl_softc *); 250 static int xl_watchdog(struct xl_softc *); 251 static int xl_shutdown(device_t); 252 static int xl_suspend(device_t); 253 static int xl_resume(device_t); 254 static void xl_setwol(struct xl_softc *); 255 256 #ifdef DEVICE_POLLING 257 static int xl_poll(if_t ifp, enum poll_cmd cmd, int count); 258 static int xl_poll_locked(if_t ifp, enum poll_cmd cmd, int count); 259 #endif 260 261 static int xl_ifmedia_upd(if_t); 262 static void xl_ifmedia_sts(if_t, struct ifmediareq *); 263 264 static int xl_eeprom_wait(struct xl_softc *); 265 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 266 267 static void xl_rxfilter(struct xl_softc *); 268 static void xl_rxfilter_90x(struct xl_softc *); 269 static void xl_rxfilter_90xB(struct xl_softc *); 270 static void xl_setcfg(struct xl_softc *); 271 static void xl_setmode(struct xl_softc *, int); 272 static void xl_reset(struct xl_softc *); 273 static int xl_list_rx_init(struct xl_softc *); 274 static int xl_list_tx_init(struct xl_softc *); 275 static int xl_list_tx_init_90xB(struct xl_softc *); 276 static void xl_wait(struct xl_softc *); 277 static void xl_mediacheck(struct xl_softc *); 278 static void xl_choose_media(struct xl_softc *sc, int *media); 279 static void xl_choose_xcvr(struct xl_softc *, int); 280 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 281 #ifdef notdef 282 static void xl_testpacket(struct xl_softc *); 283 #endif 284 285 static int xl_miibus_readreg(device_t, int, int); 286 static int xl_miibus_writereg(device_t, int, int, int); 287 static void xl_miibus_statchg(device_t); 288 static void xl_miibus_mediainit(device_t); 289 290 /* 291 * MII bit-bang glue 292 */ 293 static uint32_t xl_mii_bitbang_read(device_t); 294 static void xl_mii_bitbang_write(device_t, uint32_t); 295 296 static const struct mii_bitbang_ops xl_mii_bitbang_ops = { 297 xl_mii_bitbang_read, 298 xl_mii_bitbang_write, 299 { 300 XL_MII_DATA, /* MII_BIT_MDO */ 301 XL_MII_DATA, /* MII_BIT_MDI */ 302 XL_MII_CLK, /* MII_BIT_MDC */ 303 XL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 304 0, /* MII_BIT_DIR_PHY_HOST */ 305 } 306 }; 307 308 static device_method_t xl_methods[] = { 309 /* Device interface */ 310 DEVMETHOD(device_probe, xl_probe), 311 DEVMETHOD(device_attach, xl_attach), 312 DEVMETHOD(device_detach, xl_detach), 313 DEVMETHOD(device_shutdown, xl_shutdown), 314 DEVMETHOD(device_suspend, xl_suspend), 315 DEVMETHOD(device_resume, xl_resume), 316 317 /* MII interface */ 318 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 319 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 320 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 321 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 322 323 DEVMETHOD_END 324 }; 325 326 static driver_t xl_driver = { 327 "xl", 328 xl_methods, 329 sizeof(struct xl_softc) 330 }; 331 332 DRIVER_MODULE_ORDERED(xl, pci, xl_driver, NULL, NULL, SI_ORDER_ANY); 333 DRIVER_MODULE(miibus, xl, miibus_driver, NULL, NULL); 334 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, xl, xl_devs, 335 nitems(xl_devs) - 1); 336 337 static void 338 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 339 { 340 u_int32_t *paddr; 341 342 paddr = arg; 343 *paddr = segs->ds_addr; 344 } 345 346 /* 347 * Murphy's law says that it's possible the chip can wedge and 348 * the 'command in progress' bit may never clear. Hence, we wait 349 * only a finite amount of time to avoid getting caught in an 350 * infinite loop. Normally this delay routine would be a macro, 351 * but it isn't called during normal operation so we can afford 352 * to make it a function. Suppress warning when card gone. 353 */ 354 static void 355 xl_wait(struct xl_softc *sc) 356 { 357 int i; 358 359 for (i = 0; i < XL_TIMEOUT; i++) { 360 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 361 break; 362 } 363 364 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev)) 365 device_printf(sc->xl_dev, "command never completed!\n"); 366 } 367 368 /* 369 * MII access routines are provided for adapters with external 370 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 371 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 372 * Note: if you don't perform the MDIO operations just right, 373 * it's possible to end up with code that works correctly with 374 * some chips/CPUs/processor speeds/bus speeds/etc but not 375 * with others. 376 */ 377 378 /* 379 * Read the MII serial port for the MII bit-bang module. 380 */ 381 static uint32_t 382 xl_mii_bitbang_read(device_t dev) 383 { 384 struct xl_softc *sc; 385 uint32_t val; 386 387 sc = device_get_softc(dev); 388 389 /* We're already in window 4. */ 390 val = CSR_READ_2(sc, XL_W4_PHY_MGMT); 391 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 392 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 393 394 return (val); 395 } 396 397 /* 398 * Write the MII serial port for the MII bit-bang module. 399 */ 400 static void 401 xl_mii_bitbang_write(device_t dev, uint32_t val) 402 { 403 struct xl_softc *sc; 404 405 sc = device_get_softc(dev); 406 407 /* We're already in window 4. */ 408 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val); 409 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 410 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 411 } 412 413 static int 414 xl_miibus_readreg(device_t dev, int phy, int reg) 415 { 416 struct xl_softc *sc; 417 418 sc = device_get_softc(dev); 419 420 /* Select the window 4. */ 421 XL_SEL_WIN(4); 422 423 return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg)); 424 } 425 426 static int 427 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 428 { 429 struct xl_softc *sc; 430 431 sc = device_get_softc(dev); 432 433 /* Select the window 4. */ 434 XL_SEL_WIN(4); 435 436 mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data); 437 438 return (0); 439 } 440 441 static void 442 xl_miibus_statchg(device_t dev) 443 { 444 struct xl_softc *sc; 445 struct mii_data *mii; 446 uint8_t macctl; 447 448 sc = device_get_softc(dev); 449 mii = device_get_softc(sc->xl_miibus); 450 451 xl_setcfg(sc); 452 453 /* Set ASIC's duplex mode to match the PHY. */ 454 XL_SEL_WIN(3); 455 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 456 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 457 macctl |= XL_MACCTRL_DUPLEX; 458 if (sc->xl_type == XL_TYPE_905B) { 459 if ((IFM_OPTIONS(mii->mii_media_active) & 460 IFM_ETH_RXPAUSE) != 0) 461 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB; 462 else 463 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 464 } 465 } else { 466 macctl &= ~XL_MACCTRL_DUPLEX; 467 if (sc->xl_type == XL_TYPE_905B) 468 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 469 } 470 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 471 } 472 473 /* 474 * Special support for the 3c905B-COMBO. This card has 10/100 support 475 * plus BNC and AUI ports. This means we will have both an miibus attached 476 * plus some non-MII media settings. In order to allow this, we have to 477 * add the extra media to the miibus's ifmedia struct, but we can't do 478 * that during xl_attach() because the miibus hasn't been attached yet. 479 * So instead, we wait until the miibus probe/attach is done, at which 480 * point we will get a callback telling is that it's safe to add our 481 * extra media. 482 */ 483 static void 484 xl_miibus_mediainit(device_t dev) 485 { 486 struct xl_softc *sc; 487 struct mii_data *mii; 488 struct ifmedia *ifm; 489 490 sc = device_get_softc(dev); 491 mii = device_get_softc(sc->xl_miibus); 492 ifm = &mii->mii_media; 493 494 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 495 /* 496 * Check for a 10baseFL board in disguise. 497 */ 498 if (sc->xl_type == XL_TYPE_905B && 499 sc->xl_media == XL_MEDIAOPT_10FL) { 500 if (bootverbose) 501 device_printf(sc->xl_dev, "found 10baseFL\n"); 502 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 503 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 504 NULL); 505 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 506 ifmedia_add(ifm, 507 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 508 } else { 509 if (bootverbose) 510 device_printf(sc->xl_dev, "found AUI\n"); 511 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 512 } 513 } 514 515 if (sc->xl_media & XL_MEDIAOPT_BNC) { 516 if (bootverbose) 517 device_printf(sc->xl_dev, "found BNC\n"); 518 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 519 } 520 } 521 522 /* 523 * The EEPROM is slow: give it time to come ready after issuing 524 * it a command. 525 */ 526 static int 527 xl_eeprom_wait(struct xl_softc *sc) 528 { 529 int i; 530 531 for (i = 0; i < 100; i++) { 532 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 533 DELAY(162); 534 else 535 break; 536 } 537 538 if (i == 100) { 539 device_printf(sc->xl_dev, "eeprom failed to come ready\n"); 540 return (1); 541 } 542 543 return (0); 544 } 545 546 /* 547 * Read a sequence of words from the EEPROM. Note that ethernet address 548 * data is stored in the EEPROM in network byte order. 549 */ 550 static int 551 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 552 { 553 int err = 0, i; 554 u_int16_t word = 0, *ptr; 555 556 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 557 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 558 /* 559 * XXX: WARNING! DANGER! 560 * It's easy to accidentally overwrite the rom content! 561 * Note: the 3c575 uses 8bit EEPROM offsets. 562 */ 563 XL_SEL_WIN(0); 564 565 if (xl_eeprom_wait(sc)) 566 return (1); 567 568 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 569 off += 0x30; 570 571 for (i = 0; i < cnt; i++) { 572 if (sc->xl_flags & XL_FLAG_8BITROM) 573 CSR_WRITE_2(sc, XL_W0_EE_CMD, 574 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 575 else 576 CSR_WRITE_2(sc, XL_W0_EE_CMD, 577 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 578 err = xl_eeprom_wait(sc); 579 if (err) 580 break; 581 word = CSR_READ_2(sc, XL_W0_EE_DATA); 582 ptr = (u_int16_t *)(dest + (i * 2)); 583 if (swap) 584 *ptr = ntohs(word); 585 else 586 *ptr = word; 587 } 588 589 return (err ? 1 : 0); 590 } 591 592 static void 593 xl_rxfilter(struct xl_softc *sc) 594 { 595 596 if (sc->xl_type == XL_TYPE_905B) 597 xl_rxfilter_90xB(sc); 598 else 599 xl_rxfilter_90x(sc); 600 } 601 602 /* 603 * NICs older than the 3c905B have only one multicast option, which 604 * is to enable reception of all multicast frames. 605 */ 606 static u_int 607 xl_check_maddr_90x(void *arg, struct sockaddr_dl *sdl, u_int cnt) 608 { 609 uint8_t *rxfilt = arg; 610 611 *rxfilt |= XL_RXFILTER_ALLMULTI; 612 613 return (1); 614 } 615 616 static void 617 xl_rxfilter_90x(struct xl_softc *sc) 618 { 619 if_t ifp; 620 u_int8_t rxfilt; 621 622 XL_LOCK_ASSERT(sc); 623 624 ifp = sc->xl_ifp; 625 626 XL_SEL_WIN(5); 627 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 628 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 629 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL); 630 631 /* Set the individual bit to receive frames for this host only. */ 632 rxfilt |= XL_RXFILTER_INDIVIDUAL; 633 /* Set capture broadcast bit to capture broadcast frames. */ 634 if (if_getflags(ifp) & IFF_BROADCAST) 635 rxfilt |= XL_RXFILTER_BROADCAST; 636 637 /* If we want promiscuous mode, set the allframes bit. */ 638 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) { 639 if (if_getflags(ifp) & IFF_PROMISC) 640 rxfilt |= XL_RXFILTER_ALLFRAMES; 641 if (if_getflags(ifp) & IFF_ALLMULTI) 642 rxfilt |= XL_RXFILTER_ALLMULTI; 643 } else 644 if_foreach_llmaddr(sc->xl_ifp, xl_check_maddr_90x, &rxfilt); 645 646 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 647 XL_SEL_WIN(7); 648 } 649 650 /* 651 * 3c905B adapters have a hash filter that we can program. 652 * Note: the 3c905B currently only supports a 64-bit 653 * hash table, which means we really only need 6 bits, 654 * but the manual indicates that future chip revisions 655 * will have a 256-bit hash table, hence the routine 656 * is set up to calculate 8 bits of position info in 657 * case we need it some day. 658 * Note II, The Sequel: _CURRENT_ versions of the 659 * 3c905B have a 256 bit hash table. This means we have 660 * to use all 8 bits regardless. On older cards, the 661 * upper 2 bits will be ignored. Grrrr.... 662 */ 663 static u_int 664 xl_check_maddr_90xB(void *arg, struct sockaddr_dl *sdl, u_int count) 665 { 666 struct xl_softc *sc = arg; 667 uint16_t h; 668 669 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF; 670 CSR_WRITE_2(sc, XL_COMMAND, h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 671 672 return (1); 673 } 674 675 static void 676 xl_rxfilter_90xB(struct xl_softc *sc) 677 { 678 if_t ifp; 679 int i; 680 u_int8_t rxfilt; 681 682 XL_LOCK_ASSERT(sc); 683 684 ifp = sc->xl_ifp; 685 686 XL_SEL_WIN(5); 687 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 688 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 689 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL | 690 XL_RXFILTER_MULTIHASH); 691 692 /* Set the individual bit to receive frames for this host only. */ 693 rxfilt |= XL_RXFILTER_INDIVIDUAL; 694 /* Set capture broadcast bit to capture broadcast frames. */ 695 if (if_getflags(ifp) & IFF_BROADCAST) 696 rxfilt |= XL_RXFILTER_BROADCAST; 697 698 /* If we want promiscuous mode, set the allframes bit. */ 699 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) { 700 if (if_getflags(ifp) & IFF_PROMISC) 701 rxfilt |= XL_RXFILTER_ALLFRAMES; 702 if (if_getflags(ifp) & IFF_ALLMULTI) 703 rxfilt |= XL_RXFILTER_ALLMULTI; 704 } else { 705 /* First, zot all the existing hash bits. */ 706 for (i = 0; i < XL_HASHFILT_SIZE; i++) 707 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i); 708 709 /* Now program new ones. */ 710 if (if_foreach_llmaddr(sc->xl_ifp, xl_check_maddr_90xB, sc) > 0) 711 rxfilt |= XL_RXFILTER_MULTIHASH; 712 } 713 714 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 715 XL_SEL_WIN(7); 716 } 717 718 static void 719 xl_setcfg(struct xl_softc *sc) 720 { 721 u_int32_t icfg; 722 723 /*XL_LOCK_ASSERT(sc);*/ 724 725 XL_SEL_WIN(3); 726 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 727 icfg &= ~XL_ICFG_CONNECTOR_MASK; 728 if (sc->xl_media & XL_MEDIAOPT_MII || 729 sc->xl_media & XL_MEDIAOPT_BT4) 730 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 731 if (sc->xl_media & XL_MEDIAOPT_BTX) 732 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 733 734 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 735 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 736 } 737 738 static void 739 xl_setmode(struct xl_softc *sc, int media) 740 { 741 u_int32_t icfg; 742 u_int16_t mediastat; 743 char *pmsg = "", *dmsg = ""; 744 745 XL_LOCK_ASSERT(sc); 746 747 XL_SEL_WIN(4); 748 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 749 XL_SEL_WIN(3); 750 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 751 752 if (sc->xl_media & XL_MEDIAOPT_BT) { 753 if (IFM_SUBTYPE(media) == IFM_10_T) { 754 pmsg = "10baseT transceiver"; 755 sc->xl_xcvr = XL_XCVR_10BT; 756 icfg &= ~XL_ICFG_CONNECTOR_MASK; 757 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 758 mediastat |= XL_MEDIASTAT_LINKBEAT | 759 XL_MEDIASTAT_JABGUARD; 760 mediastat &= ~XL_MEDIASTAT_SQEENB; 761 } 762 } 763 764 if (sc->xl_media & XL_MEDIAOPT_BFX) { 765 if (IFM_SUBTYPE(media) == IFM_100_FX) { 766 pmsg = "100baseFX port"; 767 sc->xl_xcvr = XL_XCVR_100BFX; 768 icfg &= ~XL_ICFG_CONNECTOR_MASK; 769 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 770 mediastat |= XL_MEDIASTAT_LINKBEAT; 771 mediastat &= ~XL_MEDIASTAT_SQEENB; 772 } 773 } 774 775 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 776 if (IFM_SUBTYPE(media) == IFM_10_5) { 777 pmsg = "AUI port"; 778 sc->xl_xcvr = XL_XCVR_AUI; 779 icfg &= ~XL_ICFG_CONNECTOR_MASK; 780 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 781 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 782 XL_MEDIASTAT_JABGUARD); 783 mediastat |= ~XL_MEDIASTAT_SQEENB; 784 } 785 if (IFM_SUBTYPE(media) == IFM_10_FL) { 786 pmsg = "10baseFL transceiver"; 787 sc->xl_xcvr = XL_XCVR_AUI; 788 icfg &= ~XL_ICFG_CONNECTOR_MASK; 789 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 790 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 791 XL_MEDIASTAT_JABGUARD); 792 mediastat |= ~XL_MEDIASTAT_SQEENB; 793 } 794 } 795 796 if (sc->xl_media & XL_MEDIAOPT_BNC) { 797 if (IFM_SUBTYPE(media) == IFM_10_2) { 798 pmsg = "AUI port"; 799 sc->xl_xcvr = XL_XCVR_COAX; 800 icfg &= ~XL_ICFG_CONNECTOR_MASK; 801 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 802 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 803 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 804 } 805 } 806 807 if ((media & IFM_GMASK) == IFM_FDX || 808 IFM_SUBTYPE(media) == IFM_100_FX) { 809 dmsg = "full"; 810 XL_SEL_WIN(3); 811 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 812 } else { 813 dmsg = "half"; 814 XL_SEL_WIN(3); 815 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 816 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 817 } 818 819 if (IFM_SUBTYPE(media) == IFM_10_2) 820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 821 else 822 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 823 824 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 825 XL_SEL_WIN(4); 826 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 827 828 DELAY(800); 829 XL_SEL_WIN(7); 830 831 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg); 832 } 833 834 static void 835 xl_reset(struct xl_softc *sc) 836 { 837 int i; 838 839 XL_LOCK_ASSERT(sc); 840 841 XL_SEL_WIN(0); 842 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 843 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 844 XL_RESETOPT_DISADVFD:0)); 845 846 /* 847 * If we're using memory mapped register mode, pause briefly 848 * after issuing the reset command before trying to access any 849 * other registers. With my 3c575C CardBus card, failing to do 850 * this results in the system locking up while trying to poll 851 * the command busy bit in the status register. 852 */ 853 if (sc->xl_flags & XL_FLAG_USE_MMIO) 854 DELAY(100000); 855 856 for (i = 0; i < XL_TIMEOUT; i++) { 857 DELAY(10); 858 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 859 break; 860 } 861 862 if (i == XL_TIMEOUT) 863 device_printf(sc->xl_dev, "reset didn't complete\n"); 864 865 /* Reset TX and RX. */ 866 /* Note: the RX reset takes an absurd amount of time 867 * on newer versions of the Tornado chips such as those 868 * on the 3c905CX and newer 3c908C cards. We wait an 869 * extra amount of time so that xl_wait() doesn't complain 870 * and annoy the users. 871 */ 872 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 873 DELAY(100000); 874 xl_wait(sc); 875 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 876 xl_wait(sc); 877 878 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 879 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 880 XL_SEL_WIN(2); 881 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 882 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 883 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 884 XL_RESETOPT_INVERT_LED : 0) | 885 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 886 XL_RESETOPT_INVERT_MII : 0)); 887 } 888 889 /* Wait a little while for the chip to get its brains in order. */ 890 DELAY(100000); 891 } 892 893 /* 894 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 895 * IDs against our list and return a device name if we find a match. 896 */ 897 static int 898 xl_probe(device_t dev) 899 { 900 const struct xl_type *t; 901 902 t = xl_devs; 903 904 while (t->xl_name != NULL) { 905 if ((pci_get_vendor(dev) == t->xl_vid) && 906 (pci_get_device(dev) == t->xl_did)) { 907 device_set_desc(dev, t->xl_name); 908 return (BUS_PROBE_DEFAULT); 909 } 910 t++; 911 } 912 913 return (ENXIO); 914 } 915 916 /* 917 * This routine is a kludge to work around possible hardware faults 918 * or manufacturing defects that can cause the media options register 919 * (or reset options register, as it's called for the first generation 920 * 3c90x adapters) to return an incorrect result. I have encountered 921 * one Dell Latitude laptop docking station with an integrated 3c905-TX 922 * which doesn't have any of the 'mediaopt' bits set. This screws up 923 * the attach routine pretty badly because it doesn't know what media 924 * to look for. If we find ourselves in this predicament, this routine 925 * will try to guess the media options values and warn the user of a 926 * possible manufacturing defect with his adapter/system/whatever. 927 */ 928 static void 929 xl_mediacheck(struct xl_softc *sc) 930 { 931 932 /* 933 * If some of the media options bits are set, assume they are 934 * correct. If not, try to figure it out down below. 935 * XXX I should check for 10baseFL, but I don't have an adapter 936 * to test with. 937 */ 938 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 939 /* 940 * Check the XCVR value. If it's not in the normal range 941 * of values, we need to fake it up here. 942 */ 943 if (sc->xl_xcvr <= XL_XCVR_AUTO) 944 return; 945 else { 946 device_printf(sc->xl_dev, 947 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 948 device_printf(sc->xl_dev, 949 "choosing new default based on card type\n"); 950 } 951 } else { 952 if (sc->xl_type == XL_TYPE_905B && 953 sc->xl_media & XL_MEDIAOPT_10FL) 954 return; 955 device_printf(sc->xl_dev, 956 "WARNING: no media options bits set in the media options register!!\n"); 957 device_printf(sc->xl_dev, 958 "this could be a manufacturing defect in your adapter or system\n"); 959 device_printf(sc->xl_dev, 960 "attempting to guess media type; you should probably consult your vendor\n"); 961 } 962 963 xl_choose_xcvr(sc, 1); 964 } 965 966 static void 967 xl_choose_xcvr(struct xl_softc *sc, int verbose) 968 { 969 u_int16_t devid; 970 971 /* 972 * Read the device ID from the EEPROM. 973 * This is what's loaded into the PCI device ID register, so it has 974 * to be correct otherwise we wouldn't have gotten this far. 975 */ 976 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 977 978 switch (devid) { 979 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 980 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 981 sc->xl_media = XL_MEDIAOPT_BT; 982 sc->xl_xcvr = XL_XCVR_10BT; 983 if (verbose) 984 device_printf(sc->xl_dev, 985 "guessing 10BaseT transceiver\n"); 986 break; 987 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 988 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 989 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 990 sc->xl_xcvr = XL_XCVR_10BT; 991 if (verbose) 992 device_printf(sc->xl_dev, 993 "guessing COMBO (AUI/BNC/TP)\n"); 994 break; 995 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 996 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 997 sc->xl_xcvr = XL_XCVR_10BT; 998 if (verbose) 999 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n"); 1000 break; 1001 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1002 sc->xl_media = XL_MEDIAOPT_10FL; 1003 sc->xl_xcvr = XL_XCVR_AUI; 1004 if (verbose) 1005 device_printf(sc->xl_dev, "guessing 10baseFL\n"); 1006 break; 1007 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1008 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1009 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1010 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1011 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1012 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1013 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1014 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1015 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1016 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1017 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1018 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1019 sc->xl_media = XL_MEDIAOPT_MII; 1020 sc->xl_xcvr = XL_XCVR_MII; 1021 if (verbose) 1022 device_printf(sc->xl_dev, "guessing MII\n"); 1023 break; 1024 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1025 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1026 sc->xl_media = XL_MEDIAOPT_BT4; 1027 sc->xl_xcvr = XL_XCVR_MII; 1028 if (verbose) 1029 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n"); 1030 break; 1031 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1032 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1033 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1034 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1035 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1036 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1037 sc->xl_media = XL_MEDIAOPT_BTX; 1038 sc->xl_xcvr = XL_XCVR_AUTO; 1039 if (verbose) 1040 device_printf(sc->xl_dev, "guessing 10/100 internal\n"); 1041 break; 1042 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1043 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1044 sc->xl_xcvr = XL_XCVR_AUTO; 1045 if (verbose) 1046 device_printf(sc->xl_dev, 1047 "guessing 10/100 plus BNC/AUI\n"); 1048 break; 1049 default: 1050 device_printf(sc->xl_dev, 1051 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1052 sc->xl_media = XL_MEDIAOPT_BT; 1053 break; 1054 } 1055 } 1056 1057 /* 1058 * Attach the interface. Allocate softc structures, do ifmedia 1059 * setup and ethernet/BPF attach. 1060 */ 1061 static int 1062 xl_attach(device_t dev) 1063 { 1064 u_char eaddr[ETHER_ADDR_LEN]; 1065 u_int16_t sinfo2, xcvr[2]; 1066 struct xl_softc *sc; 1067 if_t ifp; 1068 int media, pmcap; 1069 int error = 0, phy, rid, res; 1070 uint16_t did; 1071 1072 sc = device_get_softc(dev); 1073 sc->xl_dev = dev; 1074 1075 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1076 MTX_DEF); 1077 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1078 1079 did = pci_get_device(dev); 1080 1081 sc->xl_flags = 0; 1082 if (did == TC_DEVICEID_HURRICANE_555) 1083 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1084 if (did == TC_DEVICEID_HURRICANE_556 || 1085 did == TC_DEVICEID_HURRICANE_556B) 1086 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1087 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1088 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1089 if (did == TC_DEVICEID_HURRICANE_555 || 1090 did == TC_DEVICEID_HURRICANE_556) 1091 sc->xl_flags |= XL_FLAG_8BITROM; 1092 if (did == TC_DEVICEID_HURRICANE_556B) 1093 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1094 1095 if (did == TC_DEVICEID_HURRICANE_575B || 1096 did == TC_DEVICEID_HURRICANE_575C || 1097 did == TC_DEVICEID_HURRICANE_656B || 1098 did == TC_DEVICEID_TORNADO_656C) 1099 sc->xl_flags |= XL_FLAG_FUNCREG; 1100 if (did == TC_DEVICEID_HURRICANE_575A || 1101 did == TC_DEVICEID_HURRICANE_575B || 1102 did == TC_DEVICEID_HURRICANE_575C || 1103 did == TC_DEVICEID_HURRICANE_656B || 1104 did == TC_DEVICEID_TORNADO_656C) 1105 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1106 XL_FLAG_8BITROM; 1107 if (did == TC_DEVICEID_HURRICANE_656) 1108 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1109 if (did == TC_DEVICEID_HURRICANE_575B) 1110 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1111 if (did == TC_DEVICEID_HURRICANE_575C) 1112 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1113 if (did == TC_DEVICEID_TORNADO_656C) 1114 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1115 if (did == TC_DEVICEID_HURRICANE_656 || 1116 did == TC_DEVICEID_HURRICANE_656B) 1117 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1118 XL_FLAG_INVERT_LED_PWR; 1119 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1120 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1121 sc->xl_flags |= XL_FLAG_PHYOK; 1122 1123 switch (did) { 1124 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1125 case TC_DEVICEID_HURRICANE_575A: 1126 case TC_DEVICEID_HURRICANE_575B: 1127 case TC_DEVICEID_HURRICANE_575C: 1128 sc->xl_flags |= XL_FLAG_NO_MMIO; 1129 break; 1130 default: 1131 break; 1132 } 1133 1134 /* 1135 * Map control/status registers. 1136 */ 1137 pci_enable_busmaster(dev); 1138 1139 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1140 rid = XL_PCI_LOMEM; 1141 res = SYS_RES_MEMORY; 1142 1143 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1144 } 1145 1146 if (sc->xl_res != NULL) { 1147 sc->xl_flags |= XL_FLAG_USE_MMIO; 1148 if (bootverbose) 1149 device_printf(dev, "using memory mapped I/O\n"); 1150 } else { 1151 rid = XL_PCI_LOIO; 1152 res = SYS_RES_IOPORT; 1153 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1154 if (sc->xl_res == NULL) { 1155 device_printf(dev, "couldn't map ports/memory\n"); 1156 error = ENXIO; 1157 goto fail; 1158 } 1159 if (bootverbose) 1160 device_printf(dev, "using port I/O\n"); 1161 } 1162 1163 sc->xl_btag = rman_get_bustag(sc->xl_res); 1164 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1165 1166 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1167 rid = XL_PCI_FUNCMEM; 1168 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1169 RF_ACTIVE); 1170 1171 if (sc->xl_fres == NULL) { 1172 device_printf(dev, "couldn't map funcreg memory\n"); 1173 error = ENXIO; 1174 goto fail; 1175 } 1176 1177 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1178 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1179 } 1180 1181 /* Allocate interrupt */ 1182 rid = 0; 1183 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1184 RF_SHAREABLE | RF_ACTIVE); 1185 if (sc->xl_irq == NULL) { 1186 device_printf(dev, "couldn't map interrupt\n"); 1187 error = ENXIO; 1188 goto fail; 1189 } 1190 1191 /* Initialize interface name. */ 1192 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1193 if (ifp == NULL) { 1194 device_printf(dev, "can not if_alloc()\n"); 1195 error = ENOSPC; 1196 goto fail; 1197 } 1198 if_setsoftc(ifp, sc); 1199 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1200 1201 /* Reset the adapter. */ 1202 XL_LOCK(sc); 1203 xl_reset(sc); 1204 XL_UNLOCK(sc); 1205 1206 /* 1207 * Get station address from the EEPROM. 1208 */ 1209 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1210 device_printf(dev, "failed to read station address\n"); 1211 error = ENXIO; 1212 goto fail; 1213 } 1214 1215 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0); 1216 NET_TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1217 1218 /* 1219 * Now allocate a tag for the DMA descriptor lists and a chunk 1220 * of DMA-able memory based on the tag. Also obtain the DMA 1221 * addresses of the RX and TX ring, which we'll need later. 1222 * All of our lists are allocated as a contiguous block 1223 * of memory. 1224 */ 1225 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1226 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1227 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1228 &sc->xl_ldata.xl_rx_tag); 1229 if (error) { 1230 device_printf(dev, "failed to allocate rx dma tag\n"); 1231 goto fail; 1232 } 1233 1234 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1235 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | 1236 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap); 1237 if (error) { 1238 device_printf(dev, "no memory for rx list buffers!\n"); 1239 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1240 sc->xl_ldata.xl_rx_tag = NULL; 1241 goto fail; 1242 } 1243 1244 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1245 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1246 XL_RX_LIST_SZ, xl_dma_map_addr, 1247 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1248 if (error) { 1249 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1250 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1251 sc->xl_ldata.xl_rx_dmamap); 1252 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1253 sc->xl_ldata.xl_rx_tag = NULL; 1254 goto fail; 1255 } 1256 1257 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1258 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1259 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1260 &sc->xl_ldata.xl_tx_tag); 1261 if (error) { 1262 device_printf(dev, "failed to allocate tx dma tag\n"); 1263 goto fail; 1264 } 1265 1266 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1267 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | 1268 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap); 1269 if (error) { 1270 device_printf(dev, "no memory for list buffers!\n"); 1271 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1272 sc->xl_ldata.xl_tx_tag = NULL; 1273 goto fail; 1274 } 1275 1276 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1277 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1278 XL_TX_LIST_SZ, xl_dma_map_addr, 1279 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1280 if (error) { 1281 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1282 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1283 sc->xl_ldata.xl_tx_dmamap); 1284 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1285 sc->xl_ldata.xl_tx_tag = NULL; 1286 goto fail; 1287 } 1288 1289 /* 1290 * Allocate a DMA tag for the mapping of mbufs. 1291 */ 1292 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1293 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1294 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1295 NULL, &sc->xl_mtag); 1296 if (error) { 1297 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1298 goto fail; 1299 } 1300 1301 /* We need a spare DMA map for the RX ring. */ 1302 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1303 if (error) 1304 goto fail; 1305 1306 /* 1307 * Figure out the card type. 3c905B adapters have the 1308 * 'supportsNoTxLength' bit set in the capabilities 1309 * word in the EEPROM. 1310 * Note: my 3c575C CardBus card lies. It returns a value 1311 * of 0x1578 for its capabilities word, which is somewhat 1312 * nonsensical. Another way to distinguish a 3c90x chip 1313 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1314 * bit. This will only be set for 3c90x boomerage chips. 1315 */ 1316 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1317 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1318 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1319 sc->xl_type = XL_TYPE_905B; 1320 else 1321 sc->xl_type = XL_TYPE_90X; 1322 1323 /* Check availability of WOL. */ 1324 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 && 1325 pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) { 1326 sc->xl_pmcap = pmcap; 1327 sc->xl_flags |= XL_FLAG_WOL; 1328 sinfo2 = 0; 1329 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0); 1330 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose) 1331 device_printf(dev, 1332 "No auxiliary remote wakeup connector!\n"); 1333 } 1334 1335 /* Set the TX start threshold for best performance. */ 1336 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1337 1338 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1339 if_setioctlfn(ifp, xl_ioctl); 1340 if_setcapabilities(ifp, IFCAP_VLAN_MTU); 1341 if (sc->xl_type == XL_TYPE_905B) { 1342 if_sethwassist(ifp, XL905B_CSUM_FEATURES); 1343 #ifdef XL905B_TXCSUM_BROKEN 1344 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 1345 #else 1346 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM, 0); 1347 #endif 1348 } 1349 if ((sc->xl_flags & XL_FLAG_WOL) != 0) 1350 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 1351 if_setcapenable(ifp, if_getcapabilities(ifp)); 1352 #ifdef DEVICE_POLLING 1353 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1354 #endif 1355 if_setstartfn(ifp, xl_start); 1356 if_setinitfn(ifp, xl_init); 1357 if_setsendqlen(ifp, XL_TX_LIST_CNT - 1); 1358 if_setsendqready(ifp); 1359 1360 /* 1361 * Now we have to see what sort of media we have. 1362 * This includes probing for an MII interace and a 1363 * possible PHY. 1364 */ 1365 XL_SEL_WIN(3); 1366 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1367 if (bootverbose) 1368 device_printf(dev, "media options word: %x\n", sc->xl_media); 1369 1370 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1371 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1372 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1373 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1374 1375 xl_mediacheck(sc); 1376 1377 if (sc->xl_media & XL_MEDIAOPT_MII || 1378 sc->xl_media & XL_MEDIAOPT_BTX || 1379 sc->xl_media & XL_MEDIAOPT_BT4) { 1380 if (bootverbose) 1381 device_printf(dev, "found MII/AUTO\n"); 1382 xl_setcfg(sc); 1383 /* 1384 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK. 1385 * This is to guard against problems with certain 3Com ASIC 1386 * revisions that incorrectly map the internal transceiver 1387 * control registers at all MII addresses. 1388 */ 1389 phy = MII_PHY_ANY; 1390 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0) 1391 phy = 24; 1392 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd, 1393 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 1394 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0); 1395 if (error != 0) { 1396 device_printf(dev, "attaching PHYs failed\n"); 1397 goto fail; 1398 } 1399 goto done; 1400 } 1401 1402 /* 1403 * Sanity check. If the user has selected "auto" and this isn't 1404 * a 10/100 card of some kind, we need to force the transceiver 1405 * type to something sane. 1406 */ 1407 if (sc->xl_xcvr == XL_XCVR_AUTO) 1408 xl_choose_xcvr(sc, bootverbose); 1409 1410 /* 1411 * Do ifmedia setup. 1412 */ 1413 if (sc->xl_media & XL_MEDIAOPT_BT) { 1414 if (bootverbose) 1415 device_printf(dev, "found 10baseT\n"); 1416 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1417 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1418 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1419 ifmedia_add(&sc->ifmedia, 1420 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1421 } 1422 1423 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1424 /* 1425 * Check for a 10baseFL board in disguise. 1426 */ 1427 if (sc->xl_type == XL_TYPE_905B && 1428 sc->xl_media == XL_MEDIAOPT_10FL) { 1429 if (bootverbose) 1430 device_printf(dev, "found 10baseFL\n"); 1431 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1432 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1433 0, NULL); 1434 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1435 ifmedia_add(&sc->ifmedia, 1436 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1437 } else { 1438 if (bootverbose) 1439 device_printf(dev, "found AUI\n"); 1440 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1441 } 1442 } 1443 1444 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1445 if (bootverbose) 1446 device_printf(dev, "found BNC\n"); 1447 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1448 } 1449 1450 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1451 if (bootverbose) 1452 device_printf(dev, "found 100baseFX\n"); 1453 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1454 } 1455 1456 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1457 xl_choose_media(sc, &media); 1458 1459 if (sc->xl_miibus == NULL) 1460 ifmedia_set(&sc->ifmedia, media); 1461 1462 done: 1463 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1464 XL_SEL_WIN(0); 1465 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1466 } 1467 1468 /* 1469 * Call MI attach routine. 1470 */ 1471 ether_ifattach(ifp, eaddr); 1472 1473 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1474 NULL, xl_intr, sc, &sc->xl_intrhand); 1475 if (error) { 1476 device_printf(dev, "couldn't set up irq\n"); 1477 ether_ifdetach(ifp); 1478 goto fail; 1479 } 1480 1481 fail: 1482 if (error) 1483 xl_detach(dev); 1484 1485 return (error); 1486 } 1487 1488 /* 1489 * Choose a default media. 1490 * XXX This is a leaf function only called by xl_attach() and 1491 * acquires/releases the non-recursible driver mutex to 1492 * satisfy lock assertions. 1493 */ 1494 static void 1495 xl_choose_media(struct xl_softc *sc, int *media) 1496 { 1497 1498 XL_LOCK(sc); 1499 1500 switch (sc->xl_xcvr) { 1501 case XL_XCVR_10BT: 1502 *media = IFM_ETHER|IFM_10_T; 1503 xl_setmode(sc, *media); 1504 break; 1505 case XL_XCVR_AUI: 1506 if (sc->xl_type == XL_TYPE_905B && 1507 sc->xl_media == XL_MEDIAOPT_10FL) { 1508 *media = IFM_ETHER|IFM_10_FL; 1509 xl_setmode(sc, *media); 1510 } else { 1511 *media = IFM_ETHER|IFM_10_5; 1512 xl_setmode(sc, *media); 1513 } 1514 break; 1515 case XL_XCVR_COAX: 1516 *media = IFM_ETHER|IFM_10_2; 1517 xl_setmode(sc, *media); 1518 break; 1519 case XL_XCVR_AUTO: 1520 case XL_XCVR_100BTX: 1521 case XL_XCVR_MII: 1522 /* Chosen by miibus */ 1523 break; 1524 case XL_XCVR_100BFX: 1525 *media = IFM_ETHER|IFM_100_FX; 1526 break; 1527 default: 1528 device_printf(sc->xl_dev, "unknown XCVR type: %d\n", 1529 sc->xl_xcvr); 1530 /* 1531 * This will probably be wrong, but it prevents 1532 * the ifmedia code from panicking. 1533 */ 1534 *media = IFM_ETHER|IFM_10_T; 1535 break; 1536 } 1537 1538 XL_UNLOCK(sc); 1539 } 1540 1541 /* 1542 * Shutdown hardware and free up resources. This can be called any 1543 * time after the mutex has been initialized. It is called in both 1544 * the error case in attach and the normal detach case so it needs 1545 * to be careful about only freeing resources that have actually been 1546 * allocated. 1547 */ 1548 static int 1549 xl_detach(device_t dev) 1550 { 1551 struct xl_softc *sc; 1552 if_t ifp; 1553 int rid, res; 1554 1555 sc = device_get_softc(dev); 1556 ifp = sc->xl_ifp; 1557 1558 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1559 1560 #ifdef DEVICE_POLLING 1561 if (ifp && if_getcapenable(ifp) & IFCAP_POLLING) 1562 ether_poll_deregister(ifp); 1563 #endif 1564 1565 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1566 rid = XL_PCI_LOMEM; 1567 res = SYS_RES_MEMORY; 1568 } else { 1569 rid = XL_PCI_LOIO; 1570 res = SYS_RES_IOPORT; 1571 } 1572 1573 /* These should only be active if attach succeeded */ 1574 if (device_is_attached(dev)) { 1575 XL_LOCK(sc); 1576 xl_stop(sc); 1577 XL_UNLOCK(sc); 1578 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1579 callout_drain(&sc->xl_tick_callout); 1580 ether_ifdetach(ifp); 1581 } 1582 if (sc->xl_miibus) 1583 device_delete_child(dev, sc->xl_miibus); 1584 bus_generic_detach(dev); 1585 ifmedia_removeall(&sc->ifmedia); 1586 1587 if (sc->xl_intrhand) 1588 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1589 if (sc->xl_irq) 1590 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1591 if (sc->xl_fres != NULL) 1592 bus_release_resource(dev, SYS_RES_MEMORY, 1593 XL_PCI_FUNCMEM, sc->xl_fres); 1594 if (sc->xl_res) 1595 bus_release_resource(dev, res, rid, sc->xl_res); 1596 1597 if (ifp) 1598 if_free(ifp); 1599 1600 if (sc->xl_mtag) { 1601 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1602 bus_dma_tag_destroy(sc->xl_mtag); 1603 } 1604 if (sc->xl_ldata.xl_rx_tag) { 1605 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1606 sc->xl_ldata.xl_rx_dmamap); 1607 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1608 sc->xl_ldata.xl_rx_dmamap); 1609 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1610 } 1611 if (sc->xl_ldata.xl_tx_tag) { 1612 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1613 sc->xl_ldata.xl_tx_dmamap); 1614 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1615 sc->xl_ldata.xl_tx_dmamap); 1616 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1617 } 1618 1619 mtx_destroy(&sc->xl_mtx); 1620 1621 return (0); 1622 } 1623 1624 /* 1625 * Initialize the transmit descriptors. 1626 */ 1627 static int 1628 xl_list_tx_init(struct xl_softc *sc) 1629 { 1630 struct xl_chain_data *cd; 1631 struct xl_list_data *ld; 1632 int error, i; 1633 1634 XL_LOCK_ASSERT(sc); 1635 1636 cd = &sc->xl_cdata; 1637 ld = &sc->xl_ldata; 1638 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1639 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1640 error = bus_dmamap_create(sc->xl_mtag, 0, 1641 &cd->xl_tx_chain[i].xl_map); 1642 if (error) 1643 return (error); 1644 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1645 i * sizeof(struct xl_list); 1646 if (i == (XL_TX_LIST_CNT - 1)) 1647 cd->xl_tx_chain[i].xl_next = NULL; 1648 else 1649 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1650 } 1651 1652 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1653 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1654 1655 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1656 return (0); 1657 } 1658 1659 /* 1660 * Initialize the transmit descriptors. 1661 */ 1662 static int 1663 xl_list_tx_init_90xB(struct xl_softc *sc) 1664 { 1665 struct xl_chain_data *cd; 1666 struct xl_list_data *ld; 1667 int error, i; 1668 1669 XL_LOCK_ASSERT(sc); 1670 1671 cd = &sc->xl_cdata; 1672 ld = &sc->xl_ldata; 1673 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1674 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1675 error = bus_dmamap_create(sc->xl_mtag, 0, 1676 &cd->xl_tx_chain[i].xl_map); 1677 if (error) 1678 return (error); 1679 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1680 i * sizeof(struct xl_list); 1681 if (i == (XL_TX_LIST_CNT - 1)) 1682 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1683 else 1684 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1685 if (i == 0) 1686 cd->xl_tx_chain[i].xl_prev = 1687 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1688 else 1689 cd->xl_tx_chain[i].xl_prev = 1690 &cd->xl_tx_chain[i - 1]; 1691 } 1692 1693 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1694 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1695 1696 cd->xl_tx_prod = 1; 1697 cd->xl_tx_cons = 1; 1698 cd->xl_tx_cnt = 0; 1699 1700 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1701 return (0); 1702 } 1703 1704 /* 1705 * Initialize the RX descriptors and allocate mbufs for them. Note that 1706 * we arrange the descriptors in a closed ring, so that the last descriptor 1707 * points back to the first. 1708 */ 1709 static int 1710 xl_list_rx_init(struct xl_softc *sc) 1711 { 1712 struct xl_chain_data *cd; 1713 struct xl_list_data *ld; 1714 int error, i, next; 1715 u_int32_t nextptr; 1716 1717 XL_LOCK_ASSERT(sc); 1718 1719 cd = &sc->xl_cdata; 1720 ld = &sc->xl_ldata; 1721 1722 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1723 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1724 error = bus_dmamap_create(sc->xl_mtag, 0, 1725 &cd->xl_rx_chain[i].xl_map); 1726 if (error) 1727 return (error); 1728 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1729 if (error) 1730 return (error); 1731 if (i == (XL_RX_LIST_CNT - 1)) 1732 next = 0; 1733 else 1734 next = i + 1; 1735 nextptr = ld->xl_rx_dmaaddr + 1736 next * sizeof(struct xl_list_onefrag); 1737 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1738 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1739 } 1740 1741 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1742 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1743 1744 return (0); 1745 } 1746 1747 /* 1748 * Initialize an RX descriptor and attach an MBUF cluster. 1749 * If we fail to do so, we need to leave the old mbuf and 1750 * the old DMA map untouched so that it can be reused. 1751 */ 1752 static int 1753 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1754 { 1755 struct mbuf *m_new = NULL; 1756 bus_dmamap_t map; 1757 bus_dma_segment_t segs[1]; 1758 int error, nseg; 1759 1760 XL_LOCK_ASSERT(sc); 1761 1762 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1763 if (m_new == NULL) 1764 return (ENOBUFS); 1765 1766 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1767 1768 /* Force longword alignment for packet payload. */ 1769 m_adj(m_new, ETHER_ALIGN); 1770 1771 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, 1772 segs, &nseg, BUS_DMA_NOWAIT); 1773 if (error) { 1774 m_freem(m_new); 1775 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", 1776 error); 1777 return (error); 1778 } 1779 KASSERT(nseg == 1, 1780 ("%s: too many DMA segments (%d)", __func__, nseg)); 1781 1782 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1783 map = c->xl_map; 1784 c->xl_map = sc->xl_tmpmap; 1785 sc->xl_tmpmap = map; 1786 c->xl_mbuf = m_new; 1787 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1788 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); 1789 c->xl_ptr->xl_status = 0; 1790 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1791 return (0); 1792 } 1793 1794 static int 1795 xl_rx_resync(struct xl_softc *sc) 1796 { 1797 struct xl_chain_onefrag *pos; 1798 int i; 1799 1800 XL_LOCK_ASSERT(sc); 1801 1802 pos = sc->xl_cdata.xl_rx_head; 1803 1804 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1805 if (pos->xl_ptr->xl_status) 1806 break; 1807 pos = pos->xl_next; 1808 } 1809 1810 if (i == XL_RX_LIST_CNT) 1811 return (0); 1812 1813 sc->xl_cdata.xl_rx_head = pos; 1814 1815 return (EAGAIN); 1816 } 1817 1818 /* 1819 * A frame has been uploaded: pass the resulting mbuf chain up to 1820 * the higher level protocols. 1821 */ 1822 static int 1823 xl_rxeof(struct xl_softc *sc) 1824 { 1825 struct mbuf *m; 1826 if_t ifp = sc->xl_ifp; 1827 struct xl_chain_onefrag *cur_rx; 1828 int total_len; 1829 int rx_npkts = 0; 1830 u_int32_t rxstat; 1831 1832 XL_LOCK_ASSERT(sc); 1833 again: 1834 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1835 BUS_DMASYNC_POSTREAD); 1836 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1837 #ifdef DEVICE_POLLING 1838 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1839 if (sc->rxcycles <= 0) 1840 break; 1841 sc->rxcycles--; 1842 } 1843 #endif 1844 cur_rx = sc->xl_cdata.xl_rx_head; 1845 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1846 total_len = rxstat & XL_RXSTAT_LENMASK; 1847 rx_npkts++; 1848 1849 /* 1850 * Since we have told the chip to allow large frames, 1851 * we need to trap giant frame errors in software. We allow 1852 * a little more than the normal frame size to account for 1853 * frames with VLAN tags. 1854 */ 1855 if (total_len > XL_MAX_FRAMELEN) 1856 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1857 1858 /* 1859 * If an error occurs, update stats, clear the 1860 * status word and leave the mbuf cluster in place: 1861 * it should simply get re-used next time this descriptor 1862 * comes up in the ring. 1863 */ 1864 if (rxstat & XL_RXSTAT_UP_ERROR) { 1865 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1866 cur_rx->xl_ptr->xl_status = 0; 1867 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1868 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1869 continue; 1870 } 1871 1872 /* 1873 * If the error bit was not set, the upload complete 1874 * bit should be set which means we have a valid packet. 1875 * If not, something truly strange has happened. 1876 */ 1877 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1878 device_printf(sc->xl_dev, 1879 "bad receive status -- packet dropped\n"); 1880 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1881 cur_rx->xl_ptr->xl_status = 0; 1882 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1883 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1884 continue; 1885 } 1886 1887 /* No errors; receive the packet. */ 1888 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 1889 BUS_DMASYNC_POSTREAD); 1890 m = cur_rx->xl_mbuf; 1891 1892 /* 1893 * Try to conjure up a new mbuf cluster. If that 1894 * fails, it means we have an out of memory condition and 1895 * should leave the buffer in place and continue. This will 1896 * result in a lost packet, but there's little else we 1897 * can do in this situation. 1898 */ 1899 if (xl_newbuf(sc, cur_rx)) { 1900 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1901 cur_rx->xl_ptr->xl_status = 0; 1902 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1903 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1904 continue; 1905 } 1906 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1907 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1908 1909 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1910 m->m_pkthdr.rcvif = ifp; 1911 m->m_pkthdr.len = m->m_len = total_len; 1912 1913 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 1914 /* Do IP checksum checking. */ 1915 if (rxstat & XL_RXSTAT_IPCKOK) 1916 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1917 if (!(rxstat & XL_RXSTAT_IPCKERR)) 1918 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1919 if ((rxstat & XL_RXSTAT_TCPCOK && 1920 !(rxstat & XL_RXSTAT_TCPCKERR)) || 1921 (rxstat & XL_RXSTAT_UDPCKOK && 1922 !(rxstat & XL_RXSTAT_UDPCKERR))) { 1923 m->m_pkthdr.csum_flags |= 1924 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1925 m->m_pkthdr.csum_data = 0xffff; 1926 } 1927 } 1928 1929 XL_UNLOCK(sc); 1930 if_input(ifp, m); 1931 XL_LOCK(sc); 1932 1933 /* 1934 * If we are running from the taskqueue, the interface 1935 * might have been stopped while we were passing the last 1936 * packet up the network stack. 1937 */ 1938 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 1939 return (rx_npkts); 1940 } 1941 1942 /* 1943 * Handle the 'end of channel' condition. When the upload 1944 * engine hits the end of the RX ring, it will stall. This 1945 * is our cue to flush the RX ring, reload the uplist pointer 1946 * register and unstall the engine. 1947 * XXX This is actually a little goofy. With the ThunderLAN 1948 * chip, you get an interrupt when the receiver hits the end 1949 * of the receive ring, which tells you exactly when you 1950 * you need to reload the ring pointer. Here we have to 1951 * fake it. I'm mad at myself for not being clever enough 1952 * to avoid the use of a goto here. 1953 */ 1954 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 1955 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 1956 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 1957 xl_wait(sc); 1958 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 1959 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 1960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 1961 goto again; 1962 } 1963 return (rx_npkts); 1964 } 1965 1966 /* 1967 * Taskqueue wrapper for xl_rxeof(). 1968 */ 1969 static void 1970 xl_rxeof_task(void *arg, int pending) 1971 { 1972 struct xl_softc *sc = (struct xl_softc *)arg; 1973 1974 XL_LOCK(sc); 1975 if (if_getdrvflags(sc->xl_ifp) & IFF_DRV_RUNNING) 1976 xl_rxeof(sc); 1977 XL_UNLOCK(sc); 1978 } 1979 1980 /* 1981 * A frame was downloaded to the chip. It's safe for us to clean up 1982 * the list buffers. 1983 */ 1984 static void 1985 xl_txeof(struct xl_softc *sc) 1986 { 1987 struct xl_chain *cur_tx; 1988 if_t ifp = sc->xl_ifp; 1989 1990 XL_LOCK_ASSERT(sc); 1991 1992 /* 1993 * Go through our tx list and free mbufs for those 1994 * frames that have been uploaded. Note: the 3c905B 1995 * sets a special bit in the status word to let us 1996 * know that a frame has been downloaded, but the 1997 * original 3c900/3c905 adapters don't do that. 1998 * Consequently, we have to use a different test if 1999 * xl_type != XL_TYPE_905B. 2000 */ 2001 while (sc->xl_cdata.xl_tx_head != NULL) { 2002 cur_tx = sc->xl_cdata.xl_tx_head; 2003 2004 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2005 break; 2006 2007 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2008 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2009 BUS_DMASYNC_POSTWRITE); 2010 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2011 m_freem(cur_tx->xl_mbuf); 2012 cur_tx->xl_mbuf = NULL; 2013 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2014 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2015 2016 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2017 sc->xl_cdata.xl_tx_free = cur_tx; 2018 } 2019 2020 if (sc->xl_cdata.xl_tx_head == NULL) { 2021 sc->xl_wdog_timer = 0; 2022 sc->xl_cdata.xl_tx_tail = NULL; 2023 } else { 2024 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2025 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2026 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2027 sc->xl_cdata.xl_tx_head->xl_phys); 2028 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2029 } 2030 } 2031 } 2032 2033 static void 2034 xl_txeof_90xB(struct xl_softc *sc) 2035 { 2036 struct xl_chain *cur_tx = NULL; 2037 if_t ifp = sc->xl_ifp; 2038 int idx; 2039 2040 XL_LOCK_ASSERT(sc); 2041 2042 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2043 BUS_DMASYNC_POSTREAD); 2044 idx = sc->xl_cdata.xl_tx_cons; 2045 while (idx != sc->xl_cdata.xl_tx_prod) { 2046 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2047 2048 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2049 XL_TXSTAT_DL_COMPLETE)) 2050 break; 2051 2052 if (cur_tx->xl_mbuf != NULL) { 2053 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2054 BUS_DMASYNC_POSTWRITE); 2055 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2056 m_freem(cur_tx->xl_mbuf); 2057 cur_tx->xl_mbuf = NULL; 2058 } 2059 2060 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2061 2062 sc->xl_cdata.xl_tx_cnt--; 2063 XL_INC(idx, XL_TX_LIST_CNT); 2064 } 2065 2066 if (sc->xl_cdata.xl_tx_cnt == 0) 2067 sc->xl_wdog_timer = 0; 2068 sc->xl_cdata.xl_tx_cons = idx; 2069 2070 if (cur_tx != NULL) 2071 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2072 } 2073 2074 /* 2075 * TX 'end of channel' interrupt handler. Actually, we should 2076 * only get a 'TX complete' interrupt if there's a transmit error, 2077 * so this is really TX error handler. 2078 */ 2079 static void 2080 xl_txeoc(struct xl_softc *sc) 2081 { 2082 u_int8_t txstat; 2083 2084 XL_LOCK_ASSERT(sc); 2085 2086 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2087 if (txstat & XL_TXSTATUS_UNDERRUN || 2088 txstat & XL_TXSTATUS_JABBER || 2089 txstat & XL_TXSTATUS_RECLAIM) { 2090 device_printf(sc->xl_dev, 2091 "transmission error: 0x%02x\n", txstat); 2092 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2093 xl_wait(sc); 2094 if (sc->xl_type == XL_TYPE_905B) { 2095 if (sc->xl_cdata.xl_tx_cnt) { 2096 int i; 2097 struct xl_chain *c; 2098 2099 i = sc->xl_cdata.xl_tx_cons; 2100 c = &sc->xl_cdata.xl_tx_chain[i]; 2101 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2102 c->xl_phys); 2103 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2104 sc->xl_wdog_timer = 5; 2105 } 2106 } else { 2107 if (sc->xl_cdata.xl_tx_head != NULL) { 2108 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2109 sc->xl_cdata.xl_tx_head->xl_phys); 2110 sc->xl_wdog_timer = 5; 2111 } 2112 } 2113 /* 2114 * Remember to set this for the 2115 * first generation 3c90X chips. 2116 */ 2117 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2118 if (txstat & XL_TXSTATUS_UNDERRUN && 2119 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2120 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2121 device_printf(sc->xl_dev, 2122 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2123 } 2124 CSR_WRITE_2(sc, XL_COMMAND, 2125 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2126 if (sc->xl_type == XL_TYPE_905B) { 2127 CSR_WRITE_2(sc, XL_COMMAND, 2128 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2129 } 2130 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2131 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2132 } else { 2133 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2134 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2135 } 2136 /* 2137 * Write an arbitrary byte to the TX_STATUS register 2138 * to clear this interrupt/error and advance to the next. 2139 */ 2140 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2141 } 2142 } 2143 2144 static void 2145 xl_intr(void *arg) 2146 { 2147 struct xl_softc *sc = arg; 2148 if_t ifp = sc->xl_ifp; 2149 u_int16_t status; 2150 2151 XL_LOCK(sc); 2152 2153 #ifdef DEVICE_POLLING 2154 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2155 XL_UNLOCK(sc); 2156 return; 2157 } 2158 #endif 2159 2160 for (;;) { 2161 status = CSR_READ_2(sc, XL_STATUS); 2162 if ((status & XL_INTRS) == 0 || status == 0xFFFF) 2163 break; 2164 CSR_WRITE_2(sc, XL_COMMAND, 2165 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2166 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2167 break; 2168 2169 if (status & XL_STAT_UP_COMPLETE) { 2170 if (xl_rxeof(sc) == 0) { 2171 while (xl_rx_resync(sc)) 2172 xl_rxeof(sc); 2173 } 2174 } 2175 2176 if (status & XL_STAT_DOWN_COMPLETE) { 2177 if (sc->xl_type == XL_TYPE_905B) 2178 xl_txeof_90xB(sc); 2179 else 2180 xl_txeof(sc); 2181 } 2182 2183 if (status & XL_STAT_TX_COMPLETE) { 2184 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2185 xl_txeoc(sc); 2186 } 2187 2188 if (status & XL_STAT_ADFAIL) { 2189 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2190 xl_init_locked(sc); 2191 break; 2192 } 2193 2194 if (status & XL_STAT_STATSOFLOW) 2195 xl_stats_update(sc); 2196 } 2197 2198 if (!if_sendq_empty(ifp) && 2199 if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2200 if (sc->xl_type == XL_TYPE_905B) 2201 xl_start_90xB_locked(ifp); 2202 else 2203 xl_start_locked(ifp); 2204 } 2205 2206 XL_UNLOCK(sc); 2207 } 2208 2209 #ifdef DEVICE_POLLING 2210 static int 2211 xl_poll(if_t ifp, enum poll_cmd cmd, int count) 2212 { 2213 struct xl_softc *sc = if_getsoftc(ifp); 2214 int rx_npkts = 0; 2215 2216 XL_LOCK(sc); 2217 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2218 rx_npkts = xl_poll_locked(ifp, cmd, count); 2219 XL_UNLOCK(sc); 2220 return (rx_npkts); 2221 } 2222 2223 static int 2224 xl_poll_locked(if_t ifp, enum poll_cmd cmd, int count) 2225 { 2226 struct xl_softc *sc = if_getsoftc(ifp); 2227 int rx_npkts; 2228 2229 XL_LOCK_ASSERT(sc); 2230 2231 sc->rxcycles = count; 2232 rx_npkts = xl_rxeof(sc); 2233 if (sc->xl_type == XL_TYPE_905B) 2234 xl_txeof_90xB(sc); 2235 else 2236 xl_txeof(sc); 2237 2238 if (!if_sendq_empty(ifp)) { 2239 if (sc->xl_type == XL_TYPE_905B) 2240 xl_start_90xB_locked(ifp); 2241 else 2242 xl_start_locked(ifp); 2243 } 2244 2245 if (cmd == POLL_AND_CHECK_STATUS) { 2246 u_int16_t status; 2247 2248 status = CSR_READ_2(sc, XL_STATUS); 2249 if (status & XL_INTRS && status != 0xFFFF) { 2250 CSR_WRITE_2(sc, XL_COMMAND, 2251 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2252 2253 if (status & XL_STAT_TX_COMPLETE) { 2254 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2255 xl_txeoc(sc); 2256 } 2257 2258 if (status & XL_STAT_ADFAIL) { 2259 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2260 xl_init_locked(sc); 2261 } 2262 2263 if (status & XL_STAT_STATSOFLOW) 2264 xl_stats_update(sc); 2265 } 2266 } 2267 return (rx_npkts); 2268 } 2269 #endif /* DEVICE_POLLING */ 2270 2271 static void 2272 xl_tick(void *xsc) 2273 { 2274 struct xl_softc *sc = xsc; 2275 struct mii_data *mii; 2276 2277 XL_LOCK_ASSERT(sc); 2278 2279 if (sc->xl_miibus != NULL) { 2280 mii = device_get_softc(sc->xl_miibus); 2281 mii_tick(mii); 2282 } 2283 2284 xl_stats_update(sc); 2285 if (xl_watchdog(sc) == EJUSTRETURN) 2286 return; 2287 2288 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc); 2289 } 2290 2291 static void 2292 xl_stats_update(struct xl_softc *sc) 2293 { 2294 if_t ifp = sc->xl_ifp; 2295 struct xl_stats xl_stats; 2296 u_int8_t *p; 2297 int i; 2298 2299 XL_LOCK_ASSERT(sc); 2300 2301 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2302 2303 p = (u_int8_t *)&xl_stats; 2304 2305 /* Read all the stats registers. */ 2306 XL_SEL_WIN(6); 2307 2308 for (i = 0; i < 16; i++) 2309 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2310 2311 if_inc_counter(ifp, IFCOUNTER_IERRORS, xl_stats.xl_rx_overrun); 2312 2313 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2314 xl_stats.xl_tx_multi_collision + 2315 xl_stats.xl_tx_single_collision + 2316 xl_stats.xl_tx_late_collision); 2317 2318 /* 2319 * Boomerang and cyclone chips have an extra stats counter 2320 * in window 4 (BadSSD). We have to read this too in order 2321 * to clear out all the stats registers and avoid a statsoflow 2322 * interrupt. 2323 */ 2324 XL_SEL_WIN(4); 2325 CSR_READ_1(sc, XL_W4_BADSSD); 2326 XL_SEL_WIN(7); 2327 } 2328 2329 /* 2330 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2331 * pointers to the fragment pointers. 2332 */ 2333 static int 2334 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) 2335 { 2336 struct mbuf *m_new; 2337 if_t ifp = sc->xl_ifp; 2338 int error, i, nseg, total_len; 2339 u_int32_t status; 2340 2341 XL_LOCK_ASSERT(sc); 2342 2343 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, 2344 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2345 2346 if (error && error != EFBIG) { 2347 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2348 return (error); 2349 } 2350 2351 /* 2352 * Handle special case: we used up all 63 fragments, 2353 * but we have more mbufs left in the chain. Copy the 2354 * data into an mbuf cluster. Note that we don't 2355 * bother clearing the values in the other fragment 2356 * pointers/counters; it wouldn't gain us anything, 2357 * and would waste cycles. 2358 */ 2359 if (error) { 2360 m_new = m_collapse(*m_head, M_NOWAIT, XL_MAXFRAGS); 2361 if (m_new == NULL) { 2362 m_freem(*m_head); 2363 *m_head = NULL; 2364 return (ENOBUFS); 2365 } 2366 *m_head = m_new; 2367 2368 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, 2369 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2370 if (error) { 2371 m_freem(*m_head); 2372 *m_head = NULL; 2373 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2374 return (error); 2375 } 2376 } 2377 2378 KASSERT(nseg <= XL_MAXFRAGS, 2379 ("%s: too many DMA segments (%d)", __func__, nseg)); 2380 if (nseg == 0) { 2381 m_freem(*m_head); 2382 *m_head = NULL; 2383 return (EIO); 2384 } 2385 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2386 2387 total_len = 0; 2388 for (i = 0; i < nseg; i++) { 2389 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, 2390 ("segment size too large")); 2391 c->xl_ptr->xl_frag[i].xl_addr = 2392 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); 2393 c->xl_ptr->xl_frag[i].xl_len = 2394 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); 2395 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; 2396 } 2397 c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG); 2398 2399 if (sc->xl_type == XL_TYPE_905B) { 2400 status = XL_TXSTAT_RND_DEFEAT; 2401 2402 #ifndef XL905B_TXCSUM_BROKEN 2403 if ((*m_head)->m_pkthdr.csum_flags) { 2404 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2405 status |= XL_TXSTAT_IPCKSUM; 2406 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2407 status |= XL_TXSTAT_TCPCKSUM; 2408 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2409 status |= XL_TXSTAT_UDPCKSUM; 2410 } 2411 #endif 2412 } else 2413 status = total_len; 2414 c->xl_ptr->xl_status = htole32(status); 2415 c->xl_ptr->xl_next = 0; 2416 2417 c->xl_mbuf = *m_head; 2418 return (0); 2419 } 2420 2421 /* 2422 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2423 * to the mbuf data regions directly in the transmit lists. We also save a 2424 * copy of the pointers since the transmit list fragment pointers are 2425 * physical addresses. 2426 */ 2427 2428 static void 2429 xl_start(if_t ifp) 2430 { 2431 struct xl_softc *sc = if_getsoftc(ifp); 2432 2433 XL_LOCK(sc); 2434 2435 if (sc->xl_type == XL_TYPE_905B) 2436 xl_start_90xB_locked(ifp); 2437 else 2438 xl_start_locked(ifp); 2439 2440 XL_UNLOCK(sc); 2441 } 2442 2443 static void 2444 xl_start_locked(if_t ifp) 2445 { 2446 struct xl_softc *sc = if_getsoftc(ifp); 2447 struct mbuf *m_head; 2448 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2449 struct xl_chain *prev_tx; 2450 int error; 2451 2452 XL_LOCK_ASSERT(sc); 2453 2454 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2455 IFF_DRV_RUNNING) 2456 return; 2457 /* 2458 * Check for an available queue slot. If there are none, 2459 * punt. 2460 */ 2461 if (sc->xl_cdata.xl_tx_free == NULL) { 2462 xl_txeoc(sc); 2463 xl_txeof(sc); 2464 if (sc->xl_cdata.xl_tx_free == NULL) { 2465 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2466 return; 2467 } 2468 } 2469 2470 start_tx = sc->xl_cdata.xl_tx_free; 2471 2472 for (; !if_sendq_empty(ifp) && 2473 sc->xl_cdata.xl_tx_free != NULL;) { 2474 m_head = if_dequeue(ifp); 2475 if (m_head == NULL) 2476 break; 2477 2478 /* Pick a descriptor off the free list. */ 2479 prev_tx = cur_tx; 2480 cur_tx = sc->xl_cdata.xl_tx_free; 2481 2482 /* Pack the data into the descriptor. */ 2483 error = xl_encap(sc, cur_tx, &m_head); 2484 if (error) { 2485 cur_tx = prev_tx; 2486 if (m_head == NULL) 2487 break; 2488 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2489 if_sendq_prepend(ifp, m_head); 2490 break; 2491 } 2492 2493 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2494 cur_tx->xl_next = NULL; 2495 2496 /* Chain it together. */ 2497 if (prev != NULL) { 2498 prev->xl_next = cur_tx; 2499 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2500 } 2501 prev = cur_tx; 2502 2503 /* 2504 * If there's a BPF listener, bounce a copy of this frame 2505 * to him. 2506 */ 2507 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2508 } 2509 2510 /* 2511 * If there are no packets queued, bail. 2512 */ 2513 if (cur_tx == NULL) 2514 return; 2515 2516 /* 2517 * Place the request for the upload interrupt 2518 * in the last descriptor in the chain. This way, if 2519 * we're chaining several packets at once, we'll only 2520 * get an interrupt once for the whole chain rather than 2521 * once for each packet. 2522 */ 2523 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2524 2525 /* 2526 * Queue the packets. If the TX channel is clear, update 2527 * the downlist pointer register. 2528 */ 2529 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2530 xl_wait(sc); 2531 2532 if (sc->xl_cdata.xl_tx_head != NULL) { 2533 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2534 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2535 htole32(start_tx->xl_phys); 2536 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &= 2537 htole32(~XL_TXSTAT_DL_INTR); 2538 sc->xl_cdata.xl_tx_tail = cur_tx; 2539 } else { 2540 sc->xl_cdata.xl_tx_head = start_tx; 2541 sc->xl_cdata.xl_tx_tail = cur_tx; 2542 } 2543 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2544 BUS_DMASYNC_PREWRITE); 2545 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2546 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2547 2548 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2549 2550 XL_SEL_WIN(7); 2551 2552 /* 2553 * Set a timeout in case the chip goes out to lunch. 2554 */ 2555 sc->xl_wdog_timer = 5; 2556 2557 /* 2558 * XXX Under certain conditions, usually on slower machines 2559 * where interrupts may be dropped, it's possible for the 2560 * adapter to chew up all the buffers in the receive ring 2561 * and stall, without us being able to do anything about it. 2562 * To guard against this, we need to make a pass over the 2563 * RX queue to make sure there aren't any packets pending. 2564 * Doing it here means we can flush the receive ring at the 2565 * same time the chip is DMAing the transmit descriptors we 2566 * just gave it. 2567 * 2568 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2569 * nature of their chips in all their marketing literature; 2570 * we may as well take advantage of it. :) 2571 */ 2572 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2573 } 2574 2575 static void 2576 xl_start_90xB_locked(if_t ifp) 2577 { 2578 struct xl_softc *sc = if_getsoftc(ifp); 2579 struct mbuf *m_head; 2580 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2581 struct xl_chain *prev_tx; 2582 int error, idx; 2583 2584 XL_LOCK_ASSERT(sc); 2585 2586 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2587 IFF_DRV_RUNNING) 2588 return; 2589 2590 idx = sc->xl_cdata.xl_tx_prod; 2591 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2592 2593 for (; !if_sendq_empty(ifp) && 2594 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { 2595 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2596 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2597 break; 2598 } 2599 2600 m_head = if_dequeue(ifp); 2601 if (m_head == NULL) 2602 break; 2603 2604 prev_tx = cur_tx; 2605 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2606 2607 /* Pack the data into the descriptor. */ 2608 error = xl_encap(sc, cur_tx, &m_head); 2609 if (error) { 2610 cur_tx = prev_tx; 2611 if (m_head == NULL) 2612 break; 2613 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2614 if_sendq_prepend(ifp, m_head); 2615 break; 2616 } 2617 2618 /* Chain it together. */ 2619 if (prev != NULL) 2620 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2621 prev = cur_tx; 2622 2623 /* 2624 * If there's a BPF listener, bounce a copy of this frame 2625 * to him. 2626 */ 2627 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2628 2629 XL_INC(idx, XL_TX_LIST_CNT); 2630 sc->xl_cdata.xl_tx_cnt++; 2631 } 2632 2633 /* 2634 * If there are no packets queued, bail. 2635 */ 2636 if (cur_tx == NULL) 2637 return; 2638 2639 /* 2640 * Place the request for the upload interrupt 2641 * in the last descriptor in the chain. This way, if 2642 * we're chaining several packets at once, we'll only 2643 * get an interrupt once for the whole chain rather than 2644 * once for each packet. 2645 */ 2646 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2647 2648 /* Start transmission */ 2649 sc->xl_cdata.xl_tx_prod = idx; 2650 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2651 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2652 BUS_DMASYNC_PREWRITE); 2653 2654 /* 2655 * Set a timeout in case the chip goes out to lunch. 2656 */ 2657 sc->xl_wdog_timer = 5; 2658 } 2659 2660 static void 2661 xl_init(void *xsc) 2662 { 2663 struct xl_softc *sc = xsc; 2664 2665 XL_LOCK(sc); 2666 xl_init_locked(sc); 2667 XL_UNLOCK(sc); 2668 } 2669 2670 static void 2671 xl_init_locked(struct xl_softc *sc) 2672 { 2673 if_t ifp = sc->xl_ifp; 2674 int error, i; 2675 struct mii_data *mii = NULL; 2676 2677 XL_LOCK_ASSERT(sc); 2678 2679 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2680 return; 2681 /* 2682 * Cancel pending I/O and free all RX/TX buffers. 2683 */ 2684 xl_stop(sc); 2685 2686 /* Reset the chip to a known state. */ 2687 xl_reset(sc); 2688 2689 if (sc->xl_miibus == NULL) { 2690 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2691 xl_wait(sc); 2692 } 2693 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2694 xl_wait(sc); 2695 DELAY(10000); 2696 2697 if (sc->xl_miibus != NULL) 2698 mii = device_get_softc(sc->xl_miibus); 2699 2700 /* 2701 * Clear WOL status and disable all WOL feature as WOL 2702 * would interfere Rx operation under normal environments. 2703 */ 2704 if ((sc->xl_flags & XL_FLAG_WOL) != 0) { 2705 XL_SEL_WIN(7); 2706 CSR_READ_2(sc, XL_W7_BM_PME); 2707 CSR_WRITE_2(sc, XL_W7_BM_PME, 0); 2708 } 2709 /* Init our MAC address */ 2710 XL_SEL_WIN(2); 2711 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2712 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2713 if_getlladdr(sc->xl_ifp)[i]); 2714 } 2715 2716 /* Clear the station mask. */ 2717 for (i = 0; i < 3; i++) 2718 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2719 #ifdef notdef 2720 /* Reset TX and RX. */ 2721 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2722 xl_wait(sc); 2723 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2724 xl_wait(sc); 2725 #endif 2726 /* Init circular RX list. */ 2727 error = xl_list_rx_init(sc); 2728 if (error) { 2729 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n", 2730 error); 2731 xl_stop(sc); 2732 return; 2733 } 2734 2735 /* Init TX descriptors. */ 2736 if (sc->xl_type == XL_TYPE_905B) 2737 error = xl_list_tx_init_90xB(sc); 2738 else 2739 error = xl_list_tx_init(sc); 2740 if (error) { 2741 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n", 2742 error); 2743 xl_stop(sc); 2744 return; 2745 } 2746 2747 /* 2748 * Set the TX freethresh value. 2749 * Note that this has no effect on 3c905B "cyclone" 2750 * cards but is required for 3c900/3c905 "boomerang" 2751 * cards in order to enable the download engine. 2752 */ 2753 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2754 2755 /* Set the TX start threshold for best performance. */ 2756 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2757 2758 /* 2759 * If this is a 3c905B, also set the tx reclaim threshold. 2760 * This helps cut down on the number of tx reclaim errors 2761 * that could happen on a busy network. The chip multiplies 2762 * the register value by 16 to obtain the actual threshold 2763 * in bytes, so we divide by 16 when setting the value here. 2764 * The existing threshold value can be examined by reading 2765 * the register at offset 9 in window 5. 2766 */ 2767 if (sc->xl_type == XL_TYPE_905B) { 2768 CSR_WRITE_2(sc, XL_COMMAND, 2769 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2770 } 2771 2772 /* Set RX filter bits. */ 2773 xl_rxfilter(sc); 2774 2775 /* 2776 * Load the address of the RX list. We have to 2777 * stall the upload engine before we can manipulate 2778 * the uplist pointer register, then unstall it when 2779 * we're finished. We also have to wait for the 2780 * stall command to complete before proceeding. 2781 * Note that we have to do this after any RX resets 2782 * have completed since the uplist register is cleared 2783 * by a reset. 2784 */ 2785 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2786 xl_wait(sc); 2787 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2788 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2789 xl_wait(sc); 2790 2791 if (sc->xl_type == XL_TYPE_905B) { 2792 /* Set polling interval */ 2793 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2794 /* Load the address of the TX list */ 2795 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2796 xl_wait(sc); 2797 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2798 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2799 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2800 xl_wait(sc); 2801 } 2802 2803 /* 2804 * If the coax transceiver is on, make sure to enable 2805 * the DC-DC converter. 2806 */ 2807 XL_SEL_WIN(3); 2808 if (sc->xl_xcvr == XL_XCVR_COAX) 2809 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2810 else 2811 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2812 2813 /* 2814 * increase packet size to allow reception of 802.1q or ISL packets. 2815 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2816 * control register. For 3c90xB/C chips, use the RX packet size 2817 * register. 2818 */ 2819 2820 if (sc->xl_type == XL_TYPE_905B) 2821 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2822 else { 2823 u_int8_t macctl; 2824 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2825 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2826 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2827 } 2828 2829 /* Clear out the stats counters. */ 2830 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2831 xl_stats_update(sc); 2832 XL_SEL_WIN(4); 2833 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2834 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2835 2836 /* 2837 * Enable interrupts. 2838 */ 2839 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2840 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2841 #ifdef DEVICE_POLLING 2842 /* Disable interrupts if we are polling. */ 2843 if (if_getcapenable(ifp) & IFCAP_POLLING) 2844 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2845 else 2846 #endif 2847 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2848 if (sc->xl_flags & XL_FLAG_FUNCREG) 2849 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2850 2851 /* Set the RX early threshold */ 2852 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2853 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2854 2855 /* Enable receiver and transmitter. */ 2856 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2857 xl_wait(sc); 2858 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2859 xl_wait(sc); 2860 2861 /* XXX Downcall to miibus. */ 2862 if (mii != NULL) 2863 mii_mediachg(mii); 2864 2865 /* Select window 7 for normal operations. */ 2866 XL_SEL_WIN(7); 2867 2868 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2869 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2870 2871 sc->xl_wdog_timer = 0; 2872 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc); 2873 } 2874 2875 /* 2876 * Set media options. 2877 */ 2878 static int 2879 xl_ifmedia_upd(if_t ifp) 2880 { 2881 struct xl_softc *sc = if_getsoftc(ifp); 2882 struct ifmedia *ifm = NULL; 2883 struct mii_data *mii = NULL; 2884 2885 XL_LOCK(sc); 2886 2887 if (sc->xl_miibus != NULL) 2888 mii = device_get_softc(sc->xl_miibus); 2889 if (mii == NULL) 2890 ifm = &sc->ifmedia; 2891 else 2892 ifm = &mii->mii_media; 2893 2894 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2895 case IFM_100_FX: 2896 case IFM_10_FL: 2897 case IFM_10_2: 2898 case IFM_10_5: 2899 xl_setmode(sc, ifm->ifm_media); 2900 XL_UNLOCK(sc); 2901 return (0); 2902 } 2903 2904 if (sc->xl_media & XL_MEDIAOPT_MII || 2905 sc->xl_media & XL_MEDIAOPT_BTX || 2906 sc->xl_media & XL_MEDIAOPT_BT4) { 2907 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2908 xl_init_locked(sc); 2909 } else { 2910 xl_setmode(sc, ifm->ifm_media); 2911 } 2912 2913 XL_UNLOCK(sc); 2914 2915 return (0); 2916 } 2917 2918 /* 2919 * Report current media status. 2920 */ 2921 static void 2922 xl_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2923 { 2924 struct xl_softc *sc = if_getsoftc(ifp); 2925 u_int32_t icfg; 2926 u_int16_t status = 0; 2927 struct mii_data *mii = NULL; 2928 2929 XL_LOCK(sc); 2930 2931 if (sc->xl_miibus != NULL) 2932 mii = device_get_softc(sc->xl_miibus); 2933 2934 XL_SEL_WIN(4); 2935 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 2936 2937 XL_SEL_WIN(3); 2938 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2939 icfg >>= XL_ICFG_CONNECTOR_BITS; 2940 2941 ifmr->ifm_active = IFM_ETHER; 2942 ifmr->ifm_status = IFM_AVALID; 2943 2944 if ((status & XL_MEDIASTAT_CARRIER) == 0) 2945 ifmr->ifm_status |= IFM_ACTIVE; 2946 2947 switch (icfg) { 2948 case XL_XCVR_10BT: 2949 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2950 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2951 ifmr->ifm_active |= IFM_FDX; 2952 else 2953 ifmr->ifm_active |= IFM_HDX; 2954 break; 2955 case XL_XCVR_AUI: 2956 if (sc->xl_type == XL_TYPE_905B && 2957 sc->xl_media == XL_MEDIAOPT_10FL) { 2958 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 2959 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2960 ifmr->ifm_active |= IFM_FDX; 2961 else 2962 ifmr->ifm_active |= IFM_HDX; 2963 } else 2964 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2965 break; 2966 case XL_XCVR_COAX: 2967 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 2968 break; 2969 /* 2970 * XXX MII and BTX/AUTO should be separate cases. 2971 */ 2972 2973 case XL_XCVR_100BTX: 2974 case XL_XCVR_AUTO: 2975 case XL_XCVR_MII: 2976 if (mii != NULL) { 2977 mii_pollstat(mii); 2978 ifmr->ifm_active = mii->mii_media_active; 2979 ifmr->ifm_status = mii->mii_media_status; 2980 } 2981 break; 2982 case XL_XCVR_100BFX: 2983 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 2984 break; 2985 default: 2986 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 2987 break; 2988 } 2989 2990 XL_UNLOCK(sc); 2991 } 2992 2993 static int 2994 xl_ioctl(if_t ifp, u_long command, caddr_t data) 2995 { 2996 struct xl_softc *sc = if_getsoftc(ifp); 2997 struct ifreq *ifr = (struct ifreq *) data; 2998 int error = 0, mask; 2999 struct mii_data *mii = NULL; 3000 3001 switch (command) { 3002 case SIOCSIFFLAGS: 3003 XL_LOCK(sc); 3004 if (if_getflags(ifp) & IFF_UP) { 3005 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 3006 (if_getflags(ifp) ^ sc->xl_if_flags) & 3007 (IFF_PROMISC | IFF_ALLMULTI)) 3008 xl_rxfilter(sc); 3009 else 3010 xl_init_locked(sc); 3011 } else { 3012 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3013 xl_stop(sc); 3014 } 3015 sc->xl_if_flags = if_getflags(ifp); 3016 XL_UNLOCK(sc); 3017 break; 3018 case SIOCADDMULTI: 3019 case SIOCDELMULTI: 3020 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3021 XL_LOCK(sc); 3022 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3023 xl_rxfilter(sc); 3024 XL_UNLOCK(sc); 3025 break; 3026 case SIOCGIFMEDIA: 3027 case SIOCSIFMEDIA: 3028 if (sc->xl_miibus != NULL) 3029 mii = device_get_softc(sc->xl_miibus); 3030 if (mii == NULL) 3031 error = ifmedia_ioctl(ifp, ifr, 3032 &sc->ifmedia, command); 3033 else 3034 error = ifmedia_ioctl(ifp, ifr, 3035 &mii->mii_media, command); 3036 break; 3037 case SIOCSIFCAP: 3038 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3039 #ifdef DEVICE_POLLING 3040 if ((mask & IFCAP_POLLING) != 0 && 3041 (if_getcapabilities(ifp) & IFCAP_POLLING) != 0) { 3042 if_togglecapenable(ifp, IFCAP_POLLING); 3043 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0) { 3044 error = ether_poll_register(xl_poll, ifp); 3045 if (error) 3046 break; 3047 XL_LOCK(sc); 3048 /* Disable interrupts */ 3049 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3050 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 3051 XL_UNLOCK(sc); 3052 } else { 3053 error = ether_poll_deregister(ifp); 3054 /* Enable interrupts. */ 3055 XL_LOCK(sc); 3056 CSR_WRITE_2(sc, XL_COMMAND, 3057 XL_CMD_INTR_ACK | 0xFF); 3058 CSR_WRITE_2(sc, XL_COMMAND, 3059 XL_CMD_INTR_ENB | XL_INTRS); 3060 if (sc->xl_flags & XL_FLAG_FUNCREG) 3061 bus_space_write_4(sc->xl_ftag, 3062 sc->xl_fhandle, 4, 0x8000); 3063 XL_UNLOCK(sc); 3064 } 3065 } 3066 #endif /* DEVICE_POLLING */ 3067 XL_LOCK(sc); 3068 if ((mask & IFCAP_TXCSUM) != 0 && 3069 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3070 if_togglecapenable(ifp, IFCAP_TXCSUM); 3071 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3072 if_sethwassistbits(ifp, XL905B_CSUM_FEATURES, 0); 3073 else 3074 if_sethwassistbits(ifp, 0, XL905B_CSUM_FEATURES); 3075 } 3076 if ((mask & IFCAP_RXCSUM) != 0 && 3077 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 3078 if_togglecapenable(ifp, IFCAP_RXCSUM); 3079 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3080 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 3081 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3082 XL_UNLOCK(sc); 3083 break; 3084 default: 3085 error = ether_ioctl(ifp, command, data); 3086 break; 3087 } 3088 3089 return (error); 3090 } 3091 3092 static int 3093 xl_watchdog(struct xl_softc *sc) 3094 { 3095 if_t ifp = sc->xl_ifp; 3096 u_int16_t status = 0; 3097 int misintr; 3098 3099 XL_LOCK_ASSERT(sc); 3100 3101 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) 3102 return (0); 3103 3104 xl_rxeof(sc); 3105 xl_txeoc(sc); 3106 misintr = 0; 3107 if (sc->xl_type == XL_TYPE_905B) { 3108 xl_txeof_90xB(sc); 3109 if (sc->xl_cdata.xl_tx_cnt == 0) 3110 misintr++; 3111 } else { 3112 xl_txeof(sc); 3113 if (sc->xl_cdata.xl_tx_head == NULL) 3114 misintr++; 3115 } 3116 if (misintr != 0) { 3117 device_printf(sc->xl_dev, 3118 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 3119 return (0); 3120 } 3121 3122 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3123 XL_SEL_WIN(4); 3124 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3125 device_printf(sc->xl_dev, "watchdog timeout\n"); 3126 3127 if (status & XL_MEDIASTAT_CARRIER) 3128 device_printf(sc->xl_dev, 3129 "no carrier - transceiver cable problem?\n"); 3130 3131 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3132 xl_init_locked(sc); 3133 3134 if (!if_sendq_empty(ifp)) { 3135 if (sc->xl_type == XL_TYPE_905B) 3136 xl_start_90xB_locked(ifp); 3137 else 3138 xl_start_locked(ifp); 3139 } 3140 3141 return (EJUSTRETURN); 3142 } 3143 3144 /* 3145 * Stop the adapter and free any mbufs allocated to the 3146 * RX and TX lists. 3147 */ 3148 static void 3149 xl_stop(struct xl_softc *sc) 3150 { 3151 int i; 3152 if_t ifp = sc->xl_ifp; 3153 3154 XL_LOCK_ASSERT(sc); 3155 3156 sc->xl_wdog_timer = 0; 3157 3158 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3159 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3160 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3161 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3162 xl_wait(sc); 3163 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3164 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3165 DELAY(800); 3166 3167 #ifdef foo 3168 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3169 xl_wait(sc); 3170 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3171 xl_wait(sc); 3172 #endif 3173 3174 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3175 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3176 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3177 if (sc->xl_flags & XL_FLAG_FUNCREG) 3178 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3179 3180 /* Stop the stats updater. */ 3181 callout_stop(&sc->xl_tick_callout); 3182 3183 /* 3184 * Free data in the RX lists. 3185 */ 3186 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3187 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3188 bus_dmamap_unload(sc->xl_mtag, 3189 sc->xl_cdata.xl_rx_chain[i].xl_map); 3190 bus_dmamap_destroy(sc->xl_mtag, 3191 sc->xl_cdata.xl_rx_chain[i].xl_map); 3192 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3193 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3194 } 3195 } 3196 if (sc->xl_ldata.xl_rx_list != NULL) 3197 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3198 /* 3199 * Free the TX list buffers. 3200 */ 3201 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3202 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3203 bus_dmamap_unload(sc->xl_mtag, 3204 sc->xl_cdata.xl_tx_chain[i].xl_map); 3205 bus_dmamap_destroy(sc->xl_mtag, 3206 sc->xl_cdata.xl_tx_chain[i].xl_map); 3207 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3208 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3209 } 3210 } 3211 if (sc->xl_ldata.xl_tx_list != NULL) 3212 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3213 3214 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 3215 } 3216 3217 /* 3218 * Stop all chip I/O so that the kernel's probe routines don't 3219 * get confused by errant DMAs when rebooting. 3220 */ 3221 static int 3222 xl_shutdown(device_t dev) 3223 { 3224 3225 return (xl_suspend(dev)); 3226 } 3227 3228 static int 3229 xl_suspend(device_t dev) 3230 { 3231 struct xl_softc *sc; 3232 3233 sc = device_get_softc(dev); 3234 3235 XL_LOCK(sc); 3236 xl_stop(sc); 3237 xl_setwol(sc); 3238 XL_UNLOCK(sc); 3239 3240 return (0); 3241 } 3242 3243 static int 3244 xl_resume(device_t dev) 3245 { 3246 struct xl_softc *sc; 3247 if_t ifp; 3248 3249 sc = device_get_softc(dev); 3250 ifp = sc->xl_ifp; 3251 3252 XL_LOCK(sc); 3253 3254 if (if_getflags(ifp) & IFF_UP) { 3255 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3256 xl_init_locked(sc); 3257 } 3258 3259 XL_UNLOCK(sc); 3260 3261 return (0); 3262 } 3263 3264 static void 3265 xl_setwol(struct xl_softc *sc) 3266 { 3267 if_t ifp; 3268 u_int16_t cfg, pmstat; 3269 3270 if ((sc->xl_flags & XL_FLAG_WOL) == 0) 3271 return; 3272 3273 ifp = sc->xl_ifp; 3274 XL_SEL_WIN(7); 3275 /* Clear any pending PME events. */ 3276 CSR_READ_2(sc, XL_W7_BM_PME); 3277 cfg = 0; 3278 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3279 cfg |= XL_BM_PME_MAGIC; 3280 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg); 3281 /* Enable RX. */ 3282 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3283 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 3284 /* Request PME. */ 3285 pmstat = pci_read_config(sc->xl_dev, 3286 sc->xl_pmcap + PCIR_POWER_STATUS, 2); 3287 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3288 pmstat |= PCIM_PSTAT_PMEENABLE; 3289 else 3290 pmstat &= ~PCIM_PSTAT_PMEENABLE; 3291 pci_write_config(sc->xl_dev, 3292 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2); 3293 } 3294