xref: /freebsd/sys/dev/xl/if_xl.c (revision 62cfcf62f627e5093fb37026a6d8c98e4d2ef04c)
1 /*-
2  * SPDX-License-Identifier: BSD-4-Clause
3  *
4  * Copyright (c) 1997, 1998, 1999
5  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *	This product includes software developed by Bill Paul.
18  * 4. Neither the name of the author nor the names of any co-contributors
19  *    may be used to endorse or promote products derived from this software
20  *    without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32  * THE POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
37 
38 /*
39  * 3Com 3c90x Etherlink XL PCI NIC driver
40  *
41  * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
42  * bus-master chips (3c90x cards and embedded controllers) including
43  * the following:
44  *
45  * 3Com 3c900-TPO	10Mbps/RJ-45
46  * 3Com 3c900-COMBO	10Mbps/RJ-45,AUI,BNC
47  * 3Com 3c905-TX	10/100Mbps/RJ-45
48  * 3Com 3c905-T4	10/100Mbps/RJ-45
49  * 3Com 3c900B-TPO	10Mbps/RJ-45
50  * 3Com 3c900B-COMBO	10Mbps/RJ-45,AUI,BNC
51  * 3Com 3c900B-TPC	10Mbps/RJ-45,BNC
52  * 3Com 3c900B-FL	10Mbps/Fiber-optic
53  * 3Com 3c905B-COMBO	10/100Mbps/RJ-45,AUI,BNC
54  * 3Com 3c905B-TX	10/100Mbps/RJ-45
55  * 3Com 3c905B-FL/FX	10/100Mbps/Fiber-optic
56  * 3Com 3c905C-TX	10/100Mbps/RJ-45 (Tornado ASIC)
57  * 3Com 3c980-TX	10/100Mbps server adapter (Hurricane ASIC)
58  * 3Com 3c980C-TX	10/100Mbps server adapter (Tornado ASIC)
59  * 3Com 3cSOHO100-TX	10/100Mbps/RJ-45 (Hurricane ASIC)
60  * 3Com 3c450-TX	10/100Mbps/RJ-45 (Tornado ASIC)
61  * 3Com 3c555		10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
62  * 3Com 3c556		10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
63  * 3Com 3c556B		10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
64  * 3Com 3c575TX		10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65  * 3Com 3c575B		10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66  * 3Com 3c575C		10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67  * 3Com 3cxfem656	10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
68  * 3Com 3cxfem656b	10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
69  * 3Com 3cxfem656c	10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
70  * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
71  * Dell on-board 3c920 10/100Mbps/RJ-45
72  * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
73  * Dell Latitude laptop docking station embedded 3c905-TX
74  *
75  * Written by Bill Paul <wpaul@ctr.columbia.edu>
76  * Electrical Engineering Department
77  * Columbia University, New York City
78  */
79 /*
80  * The 3c90x series chips use a bus-master DMA interface for transferring
81  * packets to and from the controller chip. Some of the "vortex" cards
82  * (3c59x) also supported a bus master mode, however for those chips
83  * you could only DMA packets to/from a contiguous memory buffer. For
84  * transmission this would mean copying the contents of the queued mbuf
85  * chain into an mbuf cluster and then DMAing the cluster. This extra
86  * copy would sort of defeat the purpose of the bus master support for
87  * any packet that doesn't fit into a single mbuf.
88  *
89  * By contrast, the 3c90x cards support a fragment-based bus master
90  * mode where mbuf chains can be encapsulated using TX descriptors.
91  * This is similar to other PCI chips such as the Texas Instruments
92  * ThunderLAN and the Intel 82557/82558.
93  *
94  * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
95  * bus master chips because they maintain the old PIO interface for
96  * backwards compatibility, but starting with the 3c905B and the
97  * "cyclone" chips, the compatibility interface has been dropped.
98  * Since using bus master DMA is a big win, we use this driver to
99  * support the PCI "boomerang" chips even though they work with the
100  * "vortex" driver in order to obtain better performance.
101  */
102 
103 #ifdef HAVE_KERNEL_OPTION_HEADERS
104 #include "opt_device_polling.h"
105 #endif
106 
107 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/sockio.h>
110 #include <sys/endian.h>
111 #include <sys/kernel.h>
112 #include <sys/malloc.h>
113 #include <sys/mbuf.h>
114 #include <sys/module.h>
115 #include <sys/socket.h>
116 #include <sys/taskqueue.h>
117 
118 #include <net/if.h>
119 #include <net/if_var.h>
120 #include <net/if_arp.h>
121 #include <net/ethernet.h>
122 #include <net/if_dl.h>
123 #include <net/if_media.h>
124 #include <net/if_types.h>
125 
126 #include <net/bpf.h>
127 
128 #include <machine/bus.h>
129 #include <machine/resource.h>
130 #include <sys/bus.h>
131 #include <sys/rman.h>
132 
133 #include <dev/mii/mii.h>
134 #include <dev/mii/mii_bitbang.h>
135 #include <dev/mii/miivar.h>
136 
137 #include <dev/pci/pcireg.h>
138 #include <dev/pci/pcivar.h>
139 
140 MODULE_DEPEND(xl, pci, 1, 1, 1);
141 MODULE_DEPEND(xl, ether, 1, 1, 1);
142 MODULE_DEPEND(xl, miibus, 1, 1, 1);
143 
144 /* "device miibus" required.  See GENERIC if you get errors here. */
145 #include "miibus_if.h"
146 
147 #include <dev/xl/if_xlreg.h>
148 
149 /*
150  * TX Checksumming is disabled by default for two reasons:
151  * - TX Checksumming will occasionally produce corrupt packets
152  * - TX Checksumming seems to reduce performance
153  *
154  * Only 905B/C cards were reported to have this problem, it is possible
155  * that later chips _may_ be immune.
156  */
157 #define	XL905B_TXCSUM_BROKEN	1
158 
159 #ifdef XL905B_TXCSUM_BROKEN
160 #define XL905B_CSUM_FEATURES	0
161 #else
162 #define XL905B_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
163 #endif
164 
165 /*
166  * Various supported device vendors/types and their names.
167  */
168 static const struct xl_type xl_devs[] = {
169 	{ TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
170 		"3Com 3c900-TPO Etherlink XL" },
171 	{ TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
172 		"3Com 3c900-COMBO Etherlink XL" },
173 	{ TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
174 		"3Com 3c905-TX Fast Etherlink XL" },
175 	{ TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
176 		"3Com 3c905-T4 Fast Etherlink XL" },
177 	{ TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
178 		"3Com 3c900B-TPO Etherlink XL" },
179 	{ TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
180 		"3Com 3c900B-COMBO Etherlink XL" },
181 	{ TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
182 		"3Com 3c900B-TPC Etherlink XL" },
183 	{ TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
184 		"3Com 3c900B-FL Etherlink XL" },
185 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
186 		"3Com 3c905B-TX Fast Etherlink XL" },
187 	{ TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
188 		"3Com 3c905B-T4 Fast Etherlink XL" },
189 	{ TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
190 		"3Com 3c905B-FX/SC Fast Etherlink XL" },
191 	{ TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
192 		"3Com 3c905B-COMBO Fast Etherlink XL" },
193 	{ TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
194 		"3Com 3c905C-TX Fast Etherlink XL" },
195 	{ TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
196 		"3Com 3c920B-EMB Integrated Fast Etherlink XL" },
197 	{ TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
198 		"3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
199 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
200 		"3Com 3c980 Fast Etherlink XL" },
201 	{ TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
202 		"3Com 3c980C Fast Etherlink XL" },
203 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
204 		"3Com 3cSOHO100-TX OfficeConnect" },
205 	{ TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
206 		"3Com 3c450-TX HomeConnect" },
207 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_555,
208 		"3Com 3c555 Fast Etherlink XL" },
209 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_556,
210 		"3Com 3c556 Fast Etherlink XL" },
211 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
212 		"3Com 3c556B Fast Etherlink XL" },
213 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
214 		"3Com 3c575TX Fast Etherlink XL" },
215 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
216 		"3Com 3c575B Fast Etherlink XL" },
217 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
218 		"3Com 3c575C Fast Etherlink XL" },
219 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_656,
220 		"3Com 3c656 Fast Etherlink XL" },
221 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
222 		"3Com 3c656B Fast Etherlink XL" },
223 	{ TC_VENDORID, TC_DEVICEID_TORNADO_656C,
224 		"3Com 3c656C Fast Etherlink XL" },
225 	{ 0, 0, NULL }
226 };
227 
228 static int xl_probe(device_t);
229 static int xl_attach(device_t);
230 static int xl_detach(device_t);
231 
232 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
233 static void xl_tick(void *);
234 static void xl_stats_update(struct xl_softc *);
235 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **);
236 static int xl_rxeof(struct xl_softc *);
237 static void xl_rxeof_task(void *, int);
238 static int xl_rx_resync(struct xl_softc *);
239 static void xl_txeof(struct xl_softc *);
240 static void xl_txeof_90xB(struct xl_softc *);
241 static void xl_txeoc(struct xl_softc *);
242 static void xl_intr(void *);
243 static void xl_start(struct ifnet *);
244 static void xl_start_locked(struct ifnet *);
245 static void xl_start_90xB_locked(struct ifnet *);
246 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
247 static void xl_init(void *);
248 static void xl_init_locked(struct xl_softc *);
249 static void xl_stop(struct xl_softc *);
250 static int xl_watchdog(struct xl_softc *);
251 static int xl_shutdown(device_t);
252 static int xl_suspend(device_t);
253 static int xl_resume(device_t);
254 static void xl_setwol(struct xl_softc *);
255 
256 #ifdef DEVICE_POLLING
257 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
258 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
259 #endif
260 
261 static int xl_ifmedia_upd(struct ifnet *);
262 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
263 
264 static int xl_eeprom_wait(struct xl_softc *);
265 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
266 
267 static void xl_rxfilter(struct xl_softc *);
268 static void xl_rxfilter_90x(struct xl_softc *);
269 static void xl_rxfilter_90xB(struct xl_softc *);
270 static void xl_setcfg(struct xl_softc *);
271 static void xl_setmode(struct xl_softc *, int);
272 static void xl_reset(struct xl_softc *);
273 static int xl_list_rx_init(struct xl_softc *);
274 static int xl_list_tx_init(struct xl_softc *);
275 static int xl_list_tx_init_90xB(struct xl_softc *);
276 static void xl_wait(struct xl_softc *);
277 static void xl_mediacheck(struct xl_softc *);
278 static void xl_choose_media(struct xl_softc *sc, int *media);
279 static void xl_choose_xcvr(struct xl_softc *, int);
280 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
281 #ifdef notdef
282 static void xl_testpacket(struct xl_softc *);
283 #endif
284 
285 static int xl_miibus_readreg(device_t, int, int);
286 static int xl_miibus_writereg(device_t, int, int, int);
287 static void xl_miibus_statchg(device_t);
288 static void xl_miibus_mediainit(device_t);
289 
290 /*
291  * MII bit-bang glue
292  */
293 static uint32_t xl_mii_bitbang_read(device_t);
294 static void xl_mii_bitbang_write(device_t, uint32_t);
295 
296 static const struct mii_bitbang_ops xl_mii_bitbang_ops = {
297 	xl_mii_bitbang_read,
298 	xl_mii_bitbang_write,
299 	{
300 		XL_MII_DATA,		/* MII_BIT_MDO */
301 		XL_MII_DATA,		/* MII_BIT_MDI */
302 		XL_MII_CLK,		/* MII_BIT_MDC */
303 		XL_MII_DIR,		/* MII_BIT_DIR_HOST_PHY */
304 		0,			/* MII_BIT_DIR_PHY_HOST */
305 	}
306 };
307 
308 static device_method_t xl_methods[] = {
309 	/* Device interface */
310 	DEVMETHOD(device_probe,		xl_probe),
311 	DEVMETHOD(device_attach,	xl_attach),
312 	DEVMETHOD(device_detach,	xl_detach),
313 	DEVMETHOD(device_shutdown,	xl_shutdown),
314 	DEVMETHOD(device_suspend,	xl_suspend),
315 	DEVMETHOD(device_resume,	xl_resume),
316 
317 	/* MII interface */
318 	DEVMETHOD(miibus_readreg,	xl_miibus_readreg),
319 	DEVMETHOD(miibus_writereg,	xl_miibus_writereg),
320 	DEVMETHOD(miibus_statchg,	xl_miibus_statchg),
321 	DEVMETHOD(miibus_mediainit,	xl_miibus_mediainit),
322 
323 	DEVMETHOD_END
324 };
325 
326 static driver_t xl_driver = {
327 	"xl",
328 	xl_methods,
329 	sizeof(struct xl_softc)
330 };
331 
332 static devclass_t xl_devclass;
333 
334 DRIVER_MODULE_ORDERED(xl, pci, xl_driver, xl_devclass, NULL, NULL,
335     SI_ORDER_ANY);
336 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, NULL, NULL);
337 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, xl, xl_devs,
338     nitems(xl_devs) - 1);
339 
340 static void
341 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
342 {
343 	u_int32_t *paddr;
344 
345 	paddr = arg;
346 	*paddr = segs->ds_addr;
347 }
348 
349 /*
350  * Murphy's law says that it's possible the chip can wedge and
351  * the 'command in progress' bit may never clear. Hence, we wait
352  * only a finite amount of time to avoid getting caught in an
353  * infinite loop. Normally this delay routine would be a macro,
354  * but it isn't called during normal operation so we can afford
355  * to make it a function.  Suppress warning when card gone.
356  */
357 static void
358 xl_wait(struct xl_softc *sc)
359 {
360 	int			i;
361 
362 	for (i = 0; i < XL_TIMEOUT; i++) {
363 		if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
364 			break;
365 	}
366 
367 	if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev))
368 		device_printf(sc->xl_dev, "command never completed!\n");
369 }
370 
371 /*
372  * MII access routines are provided for adapters with external
373  * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
374  * autoneg logic that's faked up to look like a PHY (3c905B-TX).
375  * Note: if you don't perform the MDIO operations just right,
376  * it's possible to end up with code that works correctly with
377  * some chips/CPUs/processor speeds/bus speeds/etc but not
378  * with others.
379  */
380 
381 /*
382  * Read the MII serial port for the MII bit-bang module.
383  */
384 static uint32_t
385 xl_mii_bitbang_read(device_t dev)
386 {
387 	struct xl_softc		*sc;
388 	uint32_t		val;
389 
390 	sc = device_get_softc(dev);
391 
392 	/* We're already in window 4. */
393 	val = CSR_READ_2(sc, XL_W4_PHY_MGMT);
394 	CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
395 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
396 
397 	return (val);
398 }
399 
400 /*
401  * Write the MII serial port for the MII bit-bang module.
402  */
403 static void
404 xl_mii_bitbang_write(device_t dev, uint32_t val)
405 {
406 	struct xl_softc		*sc;
407 
408 	sc = device_get_softc(dev);
409 
410 	/* We're already in window 4. */
411 	CSR_WRITE_2(sc, XL_W4_PHY_MGMT,	val);
412 	CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
413 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
414 }
415 
416 static int
417 xl_miibus_readreg(device_t dev, int phy, int reg)
418 {
419 	struct xl_softc		*sc;
420 
421 	sc = device_get_softc(dev);
422 
423 	/* Select the window 4. */
424 	XL_SEL_WIN(4);
425 
426 	return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg));
427 }
428 
429 static int
430 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
431 {
432 	struct xl_softc		*sc;
433 
434 	sc = device_get_softc(dev);
435 
436 	/* Select the window 4. */
437 	XL_SEL_WIN(4);
438 
439 	mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data);
440 
441 	return (0);
442 }
443 
444 static void
445 xl_miibus_statchg(device_t dev)
446 {
447 	struct xl_softc		*sc;
448 	struct mii_data		*mii;
449 	uint8_t			macctl;
450 
451 	sc = device_get_softc(dev);
452 	mii = device_get_softc(sc->xl_miibus);
453 
454 	xl_setcfg(sc);
455 
456 	/* Set ASIC's duplex mode to match the PHY. */
457 	XL_SEL_WIN(3);
458 	macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
459 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
460 		macctl |= XL_MACCTRL_DUPLEX;
461 		if (sc->xl_type == XL_TYPE_905B) {
462 			if ((IFM_OPTIONS(mii->mii_media_active) &
463 			    IFM_ETH_RXPAUSE) != 0)
464 				macctl |= XL_MACCTRL_FLOW_CONTROL_ENB;
465 			else
466 				macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
467 		}
468 	} else {
469 		macctl &= ~XL_MACCTRL_DUPLEX;
470 		if (sc->xl_type == XL_TYPE_905B)
471 			macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
472 	}
473 	CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
474 }
475 
476 /*
477  * Special support for the 3c905B-COMBO. This card has 10/100 support
478  * plus BNC and AUI ports. This means we will have both an miibus attached
479  * plus some non-MII media settings. In order to allow this, we have to
480  * add the extra media to the miibus's ifmedia struct, but we can't do
481  * that during xl_attach() because the miibus hasn't been attached yet.
482  * So instead, we wait until the miibus probe/attach is done, at which
483  * point we will get a callback telling is that it's safe to add our
484  * extra media.
485  */
486 static void
487 xl_miibus_mediainit(device_t dev)
488 {
489 	struct xl_softc		*sc;
490 	struct mii_data		*mii;
491 	struct ifmedia		*ifm;
492 
493 	sc = device_get_softc(dev);
494 	mii = device_get_softc(sc->xl_miibus);
495 	ifm = &mii->mii_media;
496 
497 	if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
498 		/*
499 		 * Check for a 10baseFL board in disguise.
500 		 */
501 		if (sc->xl_type == XL_TYPE_905B &&
502 		    sc->xl_media == XL_MEDIAOPT_10FL) {
503 			if (bootverbose)
504 				device_printf(sc->xl_dev, "found 10baseFL\n");
505 			ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
506 			ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
507 			    NULL);
508 			if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
509 				ifmedia_add(ifm,
510 				    IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
511 		} else {
512 			if (bootverbose)
513 				device_printf(sc->xl_dev, "found AUI\n");
514 			ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
515 		}
516 	}
517 
518 	if (sc->xl_media & XL_MEDIAOPT_BNC) {
519 		if (bootverbose)
520 			device_printf(sc->xl_dev, "found BNC\n");
521 		ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
522 	}
523 }
524 
525 /*
526  * The EEPROM is slow: give it time to come ready after issuing
527  * it a command.
528  */
529 static int
530 xl_eeprom_wait(struct xl_softc *sc)
531 {
532 	int			i;
533 
534 	for (i = 0; i < 100; i++) {
535 		if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
536 			DELAY(162);
537 		else
538 			break;
539 	}
540 
541 	if (i == 100) {
542 		device_printf(sc->xl_dev, "eeprom failed to come ready\n");
543 		return (1);
544 	}
545 
546 	return (0);
547 }
548 
549 /*
550  * Read a sequence of words from the EEPROM. Note that ethernet address
551  * data is stored in the EEPROM in network byte order.
552  */
553 static int
554 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
555 {
556 	int			err = 0, i;
557 	u_int16_t		word = 0, *ptr;
558 
559 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
560 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
561 	/*
562 	 * XXX: WARNING! DANGER!
563 	 * It's easy to accidentally overwrite the rom content!
564 	 * Note: the 3c575 uses 8bit EEPROM offsets.
565 	 */
566 	XL_SEL_WIN(0);
567 
568 	if (xl_eeprom_wait(sc))
569 		return (1);
570 
571 	if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
572 		off += 0x30;
573 
574 	for (i = 0; i < cnt; i++) {
575 		if (sc->xl_flags & XL_FLAG_8BITROM)
576 			CSR_WRITE_2(sc, XL_W0_EE_CMD,
577 			    XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
578 		else
579 			CSR_WRITE_2(sc, XL_W0_EE_CMD,
580 			    XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
581 		err = xl_eeprom_wait(sc);
582 		if (err)
583 			break;
584 		word = CSR_READ_2(sc, XL_W0_EE_DATA);
585 		ptr = (u_int16_t *)(dest + (i * 2));
586 		if (swap)
587 			*ptr = ntohs(word);
588 		else
589 			*ptr = word;
590 	}
591 
592 	return (err ? 1 : 0);
593 }
594 
595 static void
596 xl_rxfilter(struct xl_softc *sc)
597 {
598 
599 	if (sc->xl_type == XL_TYPE_905B)
600 		xl_rxfilter_90xB(sc);
601 	else
602 		xl_rxfilter_90x(sc);
603 }
604 
605 /*
606  * NICs older than the 3c905B have only one multicast option, which
607  * is to enable reception of all multicast frames.
608  */
609 static u_int
610 xl_check_maddr_90x(void *arg, struct sockaddr_dl *sdl, u_int cnt)
611 {
612 	uint8_t *rxfilt = arg;
613 
614 	*rxfilt |= XL_RXFILTER_ALLMULTI;
615 
616 	return (1);
617 }
618 
619 static void
620 xl_rxfilter_90x(struct xl_softc *sc)
621 {
622 	struct ifnet		*ifp;
623 	u_int8_t		rxfilt;
624 
625 	XL_LOCK_ASSERT(sc);
626 
627 	ifp = sc->xl_ifp;
628 
629 	XL_SEL_WIN(5);
630 	rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
631 	rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
632 	    XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL);
633 
634 	/* Set the individual bit to receive frames for this host only. */
635 	rxfilt |= XL_RXFILTER_INDIVIDUAL;
636 	/* Set capture broadcast bit to capture broadcast frames. */
637 	if (ifp->if_flags & IFF_BROADCAST)
638 		rxfilt |= XL_RXFILTER_BROADCAST;
639 
640 	/* If we want promiscuous mode, set the allframes bit. */
641 	if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
642 		if (ifp->if_flags & IFF_PROMISC)
643 			rxfilt |= XL_RXFILTER_ALLFRAMES;
644 		if (ifp->if_flags & IFF_ALLMULTI)
645 			rxfilt |= XL_RXFILTER_ALLMULTI;
646 	} else
647 		if_foreach_llmaddr(sc->xl_ifp, xl_check_maddr_90x, &rxfilt);
648 
649 	CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
650 	XL_SEL_WIN(7);
651 }
652 
653 /*
654  * 3c905B adapters have a hash filter that we can program.
655  * Note: the 3c905B currently only supports a 64-bit
656  * hash table, which means we really only need 6 bits,
657  * but the manual indicates that future chip revisions
658  * will have a 256-bit hash table, hence the routine
659  * is set up to calculate 8 bits of position info in
660  * case we need it some day.
661  * Note II, The Sequel: _CURRENT_ versions of the
662  * 3c905B have a 256 bit hash table. This means we have
663  * to use all 8 bits regardless.  On older cards, the
664  * upper 2 bits will be ignored. Grrrr....
665  */
666 static u_int
667 xl_check_maddr_90xB(void *arg, struct sockaddr_dl *sdl, u_int count)
668 {
669 	struct xl_softc *sc = arg;
670 	uint16_t h;
671 
672 	h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF;
673 	CSR_WRITE_2(sc, XL_COMMAND, h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
674 
675 	return (1);
676 }
677 
678 static void
679 xl_rxfilter_90xB(struct xl_softc *sc)
680 {
681 	struct ifnet		*ifp;
682 	int			i;
683 	u_int8_t		rxfilt;
684 
685 	XL_LOCK_ASSERT(sc);
686 
687 	ifp = sc->xl_ifp;
688 
689 	XL_SEL_WIN(5);
690 	rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
691 	rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
692 	    XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL |
693 	    XL_RXFILTER_MULTIHASH);
694 
695 	/* Set the individual bit to receive frames for this host only. */
696 	rxfilt |= XL_RXFILTER_INDIVIDUAL;
697 	/* Set capture broadcast bit to capture broadcast frames. */
698 	if (ifp->if_flags & IFF_BROADCAST)
699 		rxfilt |= XL_RXFILTER_BROADCAST;
700 
701 	/* If we want promiscuous mode, set the allframes bit. */
702 	if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
703 		if (ifp->if_flags & IFF_PROMISC)
704 			rxfilt |= XL_RXFILTER_ALLFRAMES;
705 		if (ifp->if_flags & IFF_ALLMULTI)
706 			rxfilt |= XL_RXFILTER_ALLMULTI;
707 	} else {
708 		/* First, zot all the existing hash bits. */
709 		for (i = 0; i < XL_HASHFILT_SIZE; i++)
710 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
711 
712 		/* Now program new ones. */
713 		if (if_foreach_llmaddr(sc->xl_ifp, xl_check_maddr_90xB, sc) > 0)
714 			rxfilt |= XL_RXFILTER_MULTIHASH;
715 	}
716 
717 	CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
718 	XL_SEL_WIN(7);
719 }
720 
721 static void
722 xl_setcfg(struct xl_softc *sc)
723 {
724 	u_int32_t		icfg;
725 
726 	/*XL_LOCK_ASSERT(sc);*/
727 
728 	XL_SEL_WIN(3);
729 	icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
730 	icfg &= ~XL_ICFG_CONNECTOR_MASK;
731 	if (sc->xl_media & XL_MEDIAOPT_MII ||
732 		sc->xl_media & XL_MEDIAOPT_BT4)
733 		icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
734 	if (sc->xl_media & XL_MEDIAOPT_BTX)
735 		icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
736 
737 	CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
738 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
739 }
740 
741 static void
742 xl_setmode(struct xl_softc *sc, int media)
743 {
744 	u_int32_t		icfg;
745 	u_int16_t		mediastat;
746 	char			*pmsg = "", *dmsg = "";
747 
748 	XL_LOCK_ASSERT(sc);
749 
750 	XL_SEL_WIN(4);
751 	mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
752 	XL_SEL_WIN(3);
753 	icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
754 
755 	if (sc->xl_media & XL_MEDIAOPT_BT) {
756 		if (IFM_SUBTYPE(media) == IFM_10_T) {
757 			pmsg = "10baseT transceiver";
758 			sc->xl_xcvr = XL_XCVR_10BT;
759 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
760 			icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
761 			mediastat |= XL_MEDIASTAT_LINKBEAT |
762 			    XL_MEDIASTAT_JABGUARD;
763 			mediastat &= ~XL_MEDIASTAT_SQEENB;
764 		}
765 	}
766 
767 	if (sc->xl_media & XL_MEDIAOPT_BFX) {
768 		if (IFM_SUBTYPE(media) == IFM_100_FX) {
769 			pmsg = "100baseFX port";
770 			sc->xl_xcvr = XL_XCVR_100BFX;
771 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
772 			icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
773 			mediastat |= XL_MEDIASTAT_LINKBEAT;
774 			mediastat &= ~XL_MEDIASTAT_SQEENB;
775 		}
776 	}
777 
778 	if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
779 		if (IFM_SUBTYPE(media) == IFM_10_5) {
780 			pmsg = "AUI port";
781 			sc->xl_xcvr = XL_XCVR_AUI;
782 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
783 			icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
784 			mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
785 			    XL_MEDIASTAT_JABGUARD);
786 			mediastat |= ~XL_MEDIASTAT_SQEENB;
787 		}
788 		if (IFM_SUBTYPE(media) == IFM_10_FL) {
789 			pmsg = "10baseFL transceiver";
790 			sc->xl_xcvr = XL_XCVR_AUI;
791 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
792 			icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
793 			mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
794 			    XL_MEDIASTAT_JABGUARD);
795 			mediastat |= ~XL_MEDIASTAT_SQEENB;
796 		}
797 	}
798 
799 	if (sc->xl_media & XL_MEDIAOPT_BNC) {
800 		if (IFM_SUBTYPE(media) == IFM_10_2) {
801 			pmsg = "AUI port";
802 			sc->xl_xcvr = XL_XCVR_COAX;
803 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
804 			icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
805 			mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
806 			    XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
807 		}
808 	}
809 
810 	if ((media & IFM_GMASK) == IFM_FDX ||
811 			IFM_SUBTYPE(media) == IFM_100_FX) {
812 		dmsg = "full";
813 		XL_SEL_WIN(3);
814 		CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
815 	} else {
816 		dmsg = "half";
817 		XL_SEL_WIN(3);
818 		CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
819 			(CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
820 	}
821 
822 	if (IFM_SUBTYPE(media) == IFM_10_2)
823 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
824 	else
825 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
826 
827 	CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
828 	XL_SEL_WIN(4);
829 	CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
830 
831 	DELAY(800);
832 	XL_SEL_WIN(7);
833 
834 	device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
835 }
836 
837 static void
838 xl_reset(struct xl_softc *sc)
839 {
840 	int			i;
841 
842 	XL_LOCK_ASSERT(sc);
843 
844 	XL_SEL_WIN(0);
845 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
846 	    ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
847 	     XL_RESETOPT_DISADVFD:0));
848 
849 	/*
850 	 * If we're using memory mapped register mode, pause briefly
851 	 * after issuing the reset command before trying to access any
852 	 * other registers. With my 3c575C CardBus card, failing to do
853 	 * this results in the system locking up while trying to poll
854 	 * the command busy bit in the status register.
855 	 */
856 	if (sc->xl_flags & XL_FLAG_USE_MMIO)
857 		DELAY(100000);
858 
859 	for (i = 0; i < XL_TIMEOUT; i++) {
860 		DELAY(10);
861 		if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
862 			break;
863 	}
864 
865 	if (i == XL_TIMEOUT)
866 		device_printf(sc->xl_dev, "reset didn't complete\n");
867 
868 	/* Reset TX and RX. */
869 	/* Note: the RX reset takes an absurd amount of time
870 	 * on newer versions of the Tornado chips such as those
871 	 * on the 3c905CX and newer 3c908C cards. We wait an
872 	 * extra amount of time so that xl_wait() doesn't complain
873 	 * and annoy the users.
874 	 */
875 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
876 	DELAY(100000);
877 	xl_wait(sc);
878 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
879 	xl_wait(sc);
880 
881 	if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
882 	    sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
883 		XL_SEL_WIN(2);
884 		CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
885 		    CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
886 		    ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
887 		    XL_RESETOPT_INVERT_LED : 0) |
888 		    ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
889 		    XL_RESETOPT_INVERT_MII : 0));
890 	}
891 
892 	/* Wait a little while for the chip to get its brains in order. */
893 	DELAY(100000);
894 }
895 
896 /*
897  * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
898  * IDs against our list and return a device name if we find a match.
899  */
900 static int
901 xl_probe(device_t dev)
902 {
903 	const struct xl_type	*t;
904 
905 	t = xl_devs;
906 
907 	while (t->xl_name != NULL) {
908 		if ((pci_get_vendor(dev) == t->xl_vid) &&
909 		    (pci_get_device(dev) == t->xl_did)) {
910 			device_set_desc(dev, t->xl_name);
911 			return (BUS_PROBE_DEFAULT);
912 		}
913 		t++;
914 	}
915 
916 	return (ENXIO);
917 }
918 
919 /*
920  * This routine is a kludge to work around possible hardware faults
921  * or manufacturing defects that can cause the media options register
922  * (or reset options register, as it's called for the first generation
923  * 3c90x adapters) to return an incorrect result. I have encountered
924  * one Dell Latitude laptop docking station with an integrated 3c905-TX
925  * which doesn't have any of the 'mediaopt' bits set. This screws up
926  * the attach routine pretty badly because it doesn't know what media
927  * to look for. If we find ourselves in this predicament, this routine
928  * will try to guess the media options values and warn the user of a
929  * possible manufacturing defect with his adapter/system/whatever.
930  */
931 static void
932 xl_mediacheck(struct xl_softc *sc)
933 {
934 
935 	/*
936 	 * If some of the media options bits are set, assume they are
937 	 * correct. If not, try to figure it out down below.
938 	 * XXX I should check for 10baseFL, but I don't have an adapter
939 	 * to test with.
940 	 */
941 	if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
942 		/*
943 		 * Check the XCVR value. If it's not in the normal range
944 		 * of values, we need to fake it up here.
945 		 */
946 		if (sc->xl_xcvr <= XL_XCVR_AUTO)
947 			return;
948 		else {
949 			device_printf(sc->xl_dev,
950 			    "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
951 			device_printf(sc->xl_dev,
952 			    "choosing new default based on card type\n");
953 		}
954 	} else {
955 		if (sc->xl_type == XL_TYPE_905B &&
956 		    sc->xl_media & XL_MEDIAOPT_10FL)
957 			return;
958 		device_printf(sc->xl_dev,
959 "WARNING: no media options bits set in the media options register!!\n");
960 		device_printf(sc->xl_dev,
961 "this could be a manufacturing defect in your adapter or system\n");
962 		device_printf(sc->xl_dev,
963 "attempting to guess media type; you should probably consult your vendor\n");
964 	}
965 
966 	xl_choose_xcvr(sc, 1);
967 }
968 
969 static void
970 xl_choose_xcvr(struct xl_softc *sc, int verbose)
971 {
972 	u_int16_t		devid;
973 
974 	/*
975 	 * Read the device ID from the EEPROM.
976 	 * This is what's loaded into the PCI device ID register, so it has
977 	 * to be correct otherwise we wouldn't have gotten this far.
978 	 */
979 	xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
980 
981 	switch (devid) {
982 	case TC_DEVICEID_BOOMERANG_10BT:	/* 3c900-TPO */
983 	case TC_DEVICEID_KRAKATOA_10BT:		/* 3c900B-TPO */
984 		sc->xl_media = XL_MEDIAOPT_BT;
985 		sc->xl_xcvr = XL_XCVR_10BT;
986 		if (verbose)
987 			device_printf(sc->xl_dev,
988 			    "guessing 10BaseT transceiver\n");
989 		break;
990 	case TC_DEVICEID_BOOMERANG_10BT_COMBO:	/* 3c900-COMBO */
991 	case TC_DEVICEID_KRAKATOA_10BT_COMBO:	/* 3c900B-COMBO */
992 		sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
993 		sc->xl_xcvr = XL_XCVR_10BT;
994 		if (verbose)
995 			device_printf(sc->xl_dev,
996 			    "guessing COMBO (AUI/BNC/TP)\n");
997 		break;
998 	case TC_DEVICEID_KRAKATOA_10BT_TPC:	/* 3c900B-TPC */
999 		sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1000 		sc->xl_xcvr = XL_XCVR_10BT;
1001 		if (verbose)
1002 			device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
1003 		break;
1004 	case TC_DEVICEID_CYCLONE_10FL:		/* 3c900B-FL */
1005 		sc->xl_media = XL_MEDIAOPT_10FL;
1006 		sc->xl_xcvr = XL_XCVR_AUI;
1007 		if (verbose)
1008 			device_printf(sc->xl_dev, "guessing 10baseFL\n");
1009 		break;
1010 	case TC_DEVICEID_BOOMERANG_10_100BT:	/* 3c905-TX */
1011 	case TC_DEVICEID_HURRICANE_555:		/* 3c555 */
1012 	case TC_DEVICEID_HURRICANE_556:		/* 3c556 */
1013 	case TC_DEVICEID_HURRICANE_556B:	/* 3c556B */
1014 	case TC_DEVICEID_HURRICANE_575A:	/* 3c575TX */
1015 	case TC_DEVICEID_HURRICANE_575B:	/* 3c575B */
1016 	case TC_DEVICEID_HURRICANE_575C:	/* 3c575C */
1017 	case TC_DEVICEID_HURRICANE_656:		/* 3c656 */
1018 	case TC_DEVICEID_HURRICANE_656B:	/* 3c656B */
1019 	case TC_DEVICEID_TORNADO_656C:		/* 3c656C */
1020 	case TC_DEVICEID_TORNADO_10_100BT_920B:	/* 3c920B-EMB */
1021 	case TC_DEVICEID_TORNADO_10_100BT_920B_WNM:	/* 3c920B-EMB-WNM */
1022 		sc->xl_media = XL_MEDIAOPT_MII;
1023 		sc->xl_xcvr = XL_XCVR_MII;
1024 		if (verbose)
1025 			device_printf(sc->xl_dev, "guessing MII\n");
1026 		break;
1027 	case TC_DEVICEID_BOOMERANG_100BT4:	/* 3c905-T4 */
1028 	case TC_DEVICEID_CYCLONE_10_100BT4:	/* 3c905B-T4 */
1029 		sc->xl_media = XL_MEDIAOPT_BT4;
1030 		sc->xl_xcvr = XL_XCVR_MII;
1031 		if (verbose)
1032 			device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1033 		break;
1034 	case TC_DEVICEID_HURRICANE_10_100BT:	/* 3c905B-TX */
1035 	case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1036 	case TC_DEVICEID_TORNADO_10_100BT_SERV:	/* 3c980C-TX */
1037 	case TC_DEVICEID_HURRICANE_SOHO100TX:	/* 3cSOHO100-TX */
1038 	case TC_DEVICEID_TORNADO_10_100BT:	/* 3c905C-TX */
1039 	case TC_DEVICEID_TORNADO_HOMECONNECT:	/* 3c450-TX */
1040 		sc->xl_media = XL_MEDIAOPT_BTX;
1041 		sc->xl_xcvr = XL_XCVR_AUTO;
1042 		if (verbose)
1043 			device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1044 		break;
1045 	case TC_DEVICEID_CYCLONE_10_100_COMBO:	/* 3c905B-COMBO */
1046 		sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1047 		sc->xl_xcvr = XL_XCVR_AUTO;
1048 		if (verbose)
1049 			device_printf(sc->xl_dev,
1050 			    "guessing 10/100 plus BNC/AUI\n");
1051 		break;
1052 	default:
1053 		device_printf(sc->xl_dev,
1054 		    "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1055 		sc->xl_media = XL_MEDIAOPT_BT;
1056 		break;
1057 	}
1058 }
1059 
1060 /*
1061  * Attach the interface. Allocate softc structures, do ifmedia
1062  * setup and ethernet/BPF attach.
1063  */
1064 static int
1065 xl_attach(device_t dev)
1066 {
1067 	u_char			eaddr[ETHER_ADDR_LEN];
1068 	u_int16_t		sinfo2, xcvr[2];
1069 	struct xl_softc		*sc;
1070 	struct ifnet		*ifp;
1071 	int			media, pmcap;
1072 	int			error = 0, phy, rid, res, unit;
1073 	uint16_t		did;
1074 
1075 	sc = device_get_softc(dev);
1076 	sc->xl_dev = dev;
1077 
1078 	unit = device_get_unit(dev);
1079 
1080 	mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1081 	    MTX_DEF);
1082 	ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1083 
1084 	did = pci_get_device(dev);
1085 
1086 	sc->xl_flags = 0;
1087 	if (did == TC_DEVICEID_HURRICANE_555)
1088 		sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1089 	if (did == TC_DEVICEID_HURRICANE_556 ||
1090 	    did == TC_DEVICEID_HURRICANE_556B)
1091 		sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1092 		    XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1093 		    XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1094 	if (did == TC_DEVICEID_HURRICANE_555 ||
1095 	    did == TC_DEVICEID_HURRICANE_556)
1096 		sc->xl_flags |= XL_FLAG_8BITROM;
1097 	if (did == TC_DEVICEID_HURRICANE_556B)
1098 		sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1099 
1100 	if (did == TC_DEVICEID_HURRICANE_575B ||
1101 	    did == TC_DEVICEID_HURRICANE_575C ||
1102 	    did == TC_DEVICEID_HURRICANE_656B ||
1103 	    did == TC_DEVICEID_TORNADO_656C)
1104 		sc->xl_flags |= XL_FLAG_FUNCREG;
1105 	if (did == TC_DEVICEID_HURRICANE_575A ||
1106 	    did == TC_DEVICEID_HURRICANE_575B ||
1107 	    did == TC_DEVICEID_HURRICANE_575C ||
1108 	    did == TC_DEVICEID_HURRICANE_656B ||
1109 	    did == TC_DEVICEID_TORNADO_656C)
1110 		sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1111 		  XL_FLAG_8BITROM;
1112 	if (did == TC_DEVICEID_HURRICANE_656)
1113 		sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1114 	if (did == TC_DEVICEID_HURRICANE_575B)
1115 		sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1116 	if (did == TC_DEVICEID_HURRICANE_575C)
1117 		sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1118 	if (did == TC_DEVICEID_TORNADO_656C)
1119 		sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1120 	if (did == TC_DEVICEID_HURRICANE_656 ||
1121 	    did == TC_DEVICEID_HURRICANE_656B)
1122 		sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1123 		    XL_FLAG_INVERT_LED_PWR;
1124 	if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1125 	    did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1126 		sc->xl_flags |= XL_FLAG_PHYOK;
1127 
1128 	switch (did) {
1129 	case TC_DEVICEID_BOOMERANG_10_100BT:	/* 3c905-TX */
1130 	case TC_DEVICEID_HURRICANE_575A:
1131 	case TC_DEVICEID_HURRICANE_575B:
1132 	case TC_DEVICEID_HURRICANE_575C:
1133 		sc->xl_flags |= XL_FLAG_NO_MMIO;
1134 		break;
1135 	default:
1136 		break;
1137 	}
1138 
1139 	/*
1140 	 * Map control/status registers.
1141 	 */
1142 	pci_enable_busmaster(dev);
1143 
1144 	if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1145 		rid = XL_PCI_LOMEM;
1146 		res = SYS_RES_MEMORY;
1147 
1148 		sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1149 	}
1150 
1151 	if (sc->xl_res != NULL) {
1152 		sc->xl_flags |= XL_FLAG_USE_MMIO;
1153 		if (bootverbose)
1154 			device_printf(dev, "using memory mapped I/O\n");
1155 	} else {
1156 		rid = XL_PCI_LOIO;
1157 		res = SYS_RES_IOPORT;
1158 		sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1159 		if (sc->xl_res == NULL) {
1160 			device_printf(dev, "couldn't map ports/memory\n");
1161 			error = ENXIO;
1162 			goto fail;
1163 		}
1164 		if (bootverbose)
1165 			device_printf(dev, "using port I/O\n");
1166 	}
1167 
1168 	sc->xl_btag = rman_get_bustag(sc->xl_res);
1169 	sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1170 
1171 	if (sc->xl_flags & XL_FLAG_FUNCREG) {
1172 		rid = XL_PCI_FUNCMEM;
1173 		sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1174 		    RF_ACTIVE);
1175 
1176 		if (sc->xl_fres == NULL) {
1177 			device_printf(dev, "couldn't map funcreg memory\n");
1178 			error = ENXIO;
1179 			goto fail;
1180 		}
1181 
1182 		sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1183 		sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1184 	}
1185 
1186 	/* Allocate interrupt */
1187 	rid = 0;
1188 	sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1189 	    RF_SHAREABLE | RF_ACTIVE);
1190 	if (sc->xl_irq == NULL) {
1191 		device_printf(dev, "couldn't map interrupt\n");
1192 		error = ENXIO;
1193 		goto fail;
1194 	}
1195 
1196 	/* Initialize interface name. */
1197 	ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1198 	if (ifp == NULL) {
1199 		device_printf(dev, "can not if_alloc()\n");
1200 		error = ENOSPC;
1201 		goto fail;
1202 	}
1203 	ifp->if_softc = sc;
1204 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1205 
1206 	/* Reset the adapter. */
1207 	XL_LOCK(sc);
1208 	xl_reset(sc);
1209 	XL_UNLOCK(sc);
1210 
1211 	/*
1212 	 * Get station address from the EEPROM.
1213 	 */
1214 	if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1215 		device_printf(dev, "failed to read station address\n");
1216 		error = ENXIO;
1217 		goto fail;
1218 	}
1219 
1220 	callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0);
1221 	NET_TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1222 
1223 	/*
1224 	 * Now allocate a tag for the DMA descriptor lists and a chunk
1225 	 * of DMA-able memory based on the tag.  Also obtain the DMA
1226 	 * addresses of the RX and TX ring, which we'll need later.
1227 	 * All of our lists are allocated as a contiguous block
1228 	 * of memory.
1229 	 */
1230 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1231 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1232 	    XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1233 	    &sc->xl_ldata.xl_rx_tag);
1234 	if (error) {
1235 		device_printf(dev, "failed to allocate rx dma tag\n");
1236 		goto fail;
1237 	}
1238 
1239 	error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1240 	    (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT |
1241 	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap);
1242 	if (error) {
1243 		device_printf(dev, "no memory for rx list buffers!\n");
1244 		bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1245 		sc->xl_ldata.xl_rx_tag = NULL;
1246 		goto fail;
1247 	}
1248 
1249 	error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1250 	    sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1251 	    XL_RX_LIST_SZ, xl_dma_map_addr,
1252 	    &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1253 	if (error) {
1254 		device_printf(dev, "cannot get dma address of the rx ring!\n");
1255 		bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1256 		    sc->xl_ldata.xl_rx_dmamap);
1257 		bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1258 		sc->xl_ldata.xl_rx_tag = NULL;
1259 		goto fail;
1260 	}
1261 
1262 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1263 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1264 	    XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1265 	    &sc->xl_ldata.xl_tx_tag);
1266 	if (error) {
1267 		device_printf(dev, "failed to allocate tx dma tag\n");
1268 		goto fail;
1269 	}
1270 
1271 	error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1272 	    (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT |
1273 	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap);
1274 	if (error) {
1275 		device_printf(dev, "no memory for list buffers!\n");
1276 		bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1277 		sc->xl_ldata.xl_tx_tag = NULL;
1278 		goto fail;
1279 	}
1280 
1281 	error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1282 	    sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1283 	    XL_TX_LIST_SZ, xl_dma_map_addr,
1284 	    &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1285 	if (error) {
1286 		device_printf(dev, "cannot get dma address of the tx ring!\n");
1287 		bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1288 		    sc->xl_ldata.xl_tx_dmamap);
1289 		bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1290 		sc->xl_ldata.xl_tx_tag = NULL;
1291 		goto fail;
1292 	}
1293 
1294 	/*
1295 	 * Allocate a DMA tag for the mapping of mbufs.
1296 	 */
1297 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1298 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1299 	    MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1300 	    NULL, &sc->xl_mtag);
1301 	if (error) {
1302 		device_printf(dev, "failed to allocate mbuf dma tag\n");
1303 		goto fail;
1304 	}
1305 
1306 	/* We need a spare DMA map for the RX ring. */
1307 	error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1308 	if (error)
1309 		goto fail;
1310 
1311 	/*
1312 	 * Figure out the card type. 3c905B adapters have the
1313 	 * 'supportsNoTxLength' bit set in the capabilities
1314 	 * word in the EEPROM.
1315 	 * Note: my 3c575C CardBus card lies. It returns a value
1316 	 * of 0x1578 for its capabilities word, which is somewhat
1317 	 * nonsensical. Another way to distinguish a 3c90x chip
1318 	 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1319 	 * bit. This will only be set for 3c90x boomerage chips.
1320 	 */
1321 	xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1322 	if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1323 	    !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1324 		sc->xl_type = XL_TYPE_905B;
1325 	else
1326 		sc->xl_type = XL_TYPE_90X;
1327 
1328 	/* Check availability of WOL. */
1329 	if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 &&
1330 	    pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) {
1331 		sc->xl_pmcap = pmcap;
1332 		sc->xl_flags |= XL_FLAG_WOL;
1333 		sinfo2 = 0;
1334 		xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0);
1335 		if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose)
1336 			device_printf(dev,
1337 			    "No auxiliary remote wakeup connector!\n");
1338 	}
1339 
1340 	/* Set the TX start threshold for best performance. */
1341 	sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1342 
1343 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1344 	ifp->if_ioctl = xl_ioctl;
1345 	ifp->if_capabilities = IFCAP_VLAN_MTU;
1346 	if (sc->xl_type == XL_TYPE_905B) {
1347 		ifp->if_hwassist = XL905B_CSUM_FEATURES;
1348 #ifdef XL905B_TXCSUM_BROKEN
1349 		ifp->if_capabilities |= IFCAP_RXCSUM;
1350 #else
1351 		ifp->if_capabilities |= IFCAP_HWCSUM;
1352 #endif
1353 	}
1354 	if ((sc->xl_flags & XL_FLAG_WOL) != 0)
1355 		ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1356 	ifp->if_capenable = ifp->if_capabilities;
1357 #ifdef DEVICE_POLLING
1358 	ifp->if_capabilities |= IFCAP_POLLING;
1359 #endif
1360 	ifp->if_start = xl_start;
1361 	ifp->if_init = xl_init;
1362 	IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1363 	ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1364 	IFQ_SET_READY(&ifp->if_snd);
1365 
1366 	/*
1367 	 * Now we have to see what sort of media we have.
1368 	 * This includes probing for an MII interace and a
1369 	 * possible PHY.
1370 	 */
1371 	XL_SEL_WIN(3);
1372 	sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1373 	if (bootverbose)
1374 		device_printf(dev, "media options word: %x\n", sc->xl_media);
1375 
1376 	xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1377 	sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1378 	sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1379 	sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1380 
1381 	xl_mediacheck(sc);
1382 
1383 	if (sc->xl_media & XL_MEDIAOPT_MII ||
1384 	    sc->xl_media & XL_MEDIAOPT_BTX ||
1385 	    sc->xl_media & XL_MEDIAOPT_BT4) {
1386 		if (bootverbose)
1387 			device_printf(dev, "found MII/AUTO\n");
1388 		xl_setcfg(sc);
1389 		/*
1390 		 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK.
1391 		 * This is to guard against problems with certain 3Com ASIC
1392 		 * revisions that incorrectly map the internal transceiver
1393 		 * control registers at all MII addresses.
1394 		 */
1395 		phy = MII_PHY_ANY;
1396 		if ((sc->xl_flags & XL_FLAG_PHYOK) == 0)
1397 			phy = 24;
1398 		error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd,
1399 		    xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
1400 		    sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0);
1401 		if (error != 0) {
1402 			device_printf(dev, "attaching PHYs failed\n");
1403 			goto fail;
1404 		}
1405 		goto done;
1406 	}
1407 
1408 	/*
1409 	 * Sanity check. If the user has selected "auto" and this isn't
1410 	 * a 10/100 card of some kind, we need to force the transceiver
1411 	 * type to something sane.
1412 	 */
1413 	if (sc->xl_xcvr == XL_XCVR_AUTO)
1414 		xl_choose_xcvr(sc, bootverbose);
1415 
1416 	/*
1417 	 * Do ifmedia setup.
1418 	 */
1419 	if (sc->xl_media & XL_MEDIAOPT_BT) {
1420 		if (bootverbose)
1421 			device_printf(dev, "found 10baseT\n");
1422 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1423 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1424 		if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1425 			ifmedia_add(&sc->ifmedia,
1426 			    IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1427 	}
1428 
1429 	if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1430 		/*
1431 		 * Check for a 10baseFL board in disguise.
1432 		 */
1433 		if (sc->xl_type == XL_TYPE_905B &&
1434 		    sc->xl_media == XL_MEDIAOPT_10FL) {
1435 			if (bootverbose)
1436 				device_printf(dev, "found 10baseFL\n");
1437 			ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1438 			ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1439 			    0, NULL);
1440 			if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1441 				ifmedia_add(&sc->ifmedia,
1442 				    IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1443 		} else {
1444 			if (bootverbose)
1445 				device_printf(dev, "found AUI\n");
1446 			ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1447 		}
1448 	}
1449 
1450 	if (sc->xl_media & XL_MEDIAOPT_BNC) {
1451 		if (bootverbose)
1452 			device_printf(dev, "found BNC\n");
1453 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1454 	}
1455 
1456 	if (sc->xl_media & XL_MEDIAOPT_BFX) {
1457 		if (bootverbose)
1458 			device_printf(dev, "found 100baseFX\n");
1459 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1460 	}
1461 
1462 	media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1463 	xl_choose_media(sc, &media);
1464 
1465 	if (sc->xl_miibus == NULL)
1466 		ifmedia_set(&sc->ifmedia, media);
1467 
1468 done:
1469 	if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1470 		XL_SEL_WIN(0);
1471 		CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1472 	}
1473 
1474 	/*
1475 	 * Call MI attach routine.
1476 	 */
1477 	ether_ifattach(ifp, eaddr);
1478 
1479 	error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1480 	    NULL, xl_intr, sc, &sc->xl_intrhand);
1481 	if (error) {
1482 		device_printf(dev, "couldn't set up irq\n");
1483 		ether_ifdetach(ifp);
1484 		goto fail;
1485 	}
1486 
1487 fail:
1488 	if (error)
1489 		xl_detach(dev);
1490 
1491 	return (error);
1492 }
1493 
1494 /*
1495  * Choose a default media.
1496  * XXX This is a leaf function only called by xl_attach() and
1497  *     acquires/releases the non-recursible driver mutex to
1498  *     satisfy lock assertions.
1499  */
1500 static void
1501 xl_choose_media(struct xl_softc *sc, int *media)
1502 {
1503 
1504 	XL_LOCK(sc);
1505 
1506 	switch (sc->xl_xcvr) {
1507 	case XL_XCVR_10BT:
1508 		*media = IFM_ETHER|IFM_10_T;
1509 		xl_setmode(sc, *media);
1510 		break;
1511 	case XL_XCVR_AUI:
1512 		if (sc->xl_type == XL_TYPE_905B &&
1513 		    sc->xl_media == XL_MEDIAOPT_10FL) {
1514 			*media = IFM_ETHER|IFM_10_FL;
1515 			xl_setmode(sc, *media);
1516 		} else {
1517 			*media = IFM_ETHER|IFM_10_5;
1518 			xl_setmode(sc, *media);
1519 		}
1520 		break;
1521 	case XL_XCVR_COAX:
1522 		*media = IFM_ETHER|IFM_10_2;
1523 		xl_setmode(sc, *media);
1524 		break;
1525 	case XL_XCVR_AUTO:
1526 	case XL_XCVR_100BTX:
1527 	case XL_XCVR_MII:
1528 		/* Chosen by miibus */
1529 		break;
1530 	case XL_XCVR_100BFX:
1531 		*media = IFM_ETHER|IFM_100_FX;
1532 		break;
1533 	default:
1534 		device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1535 		    sc->xl_xcvr);
1536 		/*
1537 		 * This will probably be wrong, but it prevents
1538 		 * the ifmedia code from panicking.
1539 		 */
1540 		*media = IFM_ETHER|IFM_10_T;
1541 		break;
1542 	}
1543 
1544 	XL_UNLOCK(sc);
1545 }
1546 
1547 /*
1548  * Shutdown hardware and free up resources. This can be called any
1549  * time after the mutex has been initialized. It is called in both
1550  * the error case in attach and the normal detach case so it needs
1551  * to be careful about only freeing resources that have actually been
1552  * allocated.
1553  */
1554 static int
1555 xl_detach(device_t dev)
1556 {
1557 	struct xl_softc		*sc;
1558 	struct ifnet		*ifp;
1559 	int			rid, res;
1560 
1561 	sc = device_get_softc(dev);
1562 	ifp = sc->xl_ifp;
1563 
1564 	KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1565 
1566 #ifdef DEVICE_POLLING
1567 	if (ifp && ifp->if_capenable & IFCAP_POLLING)
1568 		ether_poll_deregister(ifp);
1569 #endif
1570 
1571 	if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1572 		rid = XL_PCI_LOMEM;
1573 		res = SYS_RES_MEMORY;
1574 	} else {
1575 		rid = XL_PCI_LOIO;
1576 		res = SYS_RES_IOPORT;
1577 	}
1578 
1579 	/* These should only be active if attach succeeded */
1580 	if (device_is_attached(dev)) {
1581 		XL_LOCK(sc);
1582 		xl_stop(sc);
1583 		XL_UNLOCK(sc);
1584 		taskqueue_drain(taskqueue_swi, &sc->xl_task);
1585 		callout_drain(&sc->xl_tick_callout);
1586 		ether_ifdetach(ifp);
1587 	}
1588 	if (sc->xl_miibus)
1589 		device_delete_child(dev, sc->xl_miibus);
1590 	bus_generic_detach(dev);
1591 	ifmedia_removeall(&sc->ifmedia);
1592 
1593 	if (sc->xl_intrhand)
1594 		bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1595 	if (sc->xl_irq)
1596 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1597 	if (sc->xl_fres != NULL)
1598 		bus_release_resource(dev, SYS_RES_MEMORY,
1599 		    XL_PCI_FUNCMEM, sc->xl_fres);
1600 	if (sc->xl_res)
1601 		bus_release_resource(dev, res, rid, sc->xl_res);
1602 
1603 	if (ifp)
1604 		if_free(ifp);
1605 
1606 	if (sc->xl_mtag) {
1607 		bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1608 		bus_dma_tag_destroy(sc->xl_mtag);
1609 	}
1610 	if (sc->xl_ldata.xl_rx_tag) {
1611 		bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1612 		    sc->xl_ldata.xl_rx_dmamap);
1613 		bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1614 		    sc->xl_ldata.xl_rx_dmamap);
1615 		bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1616 	}
1617 	if (sc->xl_ldata.xl_tx_tag) {
1618 		bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1619 		    sc->xl_ldata.xl_tx_dmamap);
1620 		bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1621 		    sc->xl_ldata.xl_tx_dmamap);
1622 		bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1623 	}
1624 
1625 	mtx_destroy(&sc->xl_mtx);
1626 
1627 	return (0);
1628 }
1629 
1630 /*
1631  * Initialize the transmit descriptors.
1632  */
1633 static int
1634 xl_list_tx_init(struct xl_softc *sc)
1635 {
1636 	struct xl_chain_data	*cd;
1637 	struct xl_list_data	*ld;
1638 	int			error, i;
1639 
1640 	XL_LOCK_ASSERT(sc);
1641 
1642 	cd = &sc->xl_cdata;
1643 	ld = &sc->xl_ldata;
1644 	for (i = 0; i < XL_TX_LIST_CNT; i++) {
1645 		cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1646 		error = bus_dmamap_create(sc->xl_mtag, 0,
1647 		    &cd->xl_tx_chain[i].xl_map);
1648 		if (error)
1649 			return (error);
1650 		cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1651 		    i * sizeof(struct xl_list);
1652 		if (i == (XL_TX_LIST_CNT - 1))
1653 			cd->xl_tx_chain[i].xl_next = NULL;
1654 		else
1655 			cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1656 	}
1657 
1658 	cd->xl_tx_free = &cd->xl_tx_chain[0];
1659 	cd->xl_tx_tail = cd->xl_tx_head = NULL;
1660 
1661 	bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1662 	return (0);
1663 }
1664 
1665 /*
1666  * Initialize the transmit descriptors.
1667  */
1668 static int
1669 xl_list_tx_init_90xB(struct xl_softc *sc)
1670 {
1671 	struct xl_chain_data	*cd;
1672 	struct xl_list_data	*ld;
1673 	int			error, i;
1674 
1675 	XL_LOCK_ASSERT(sc);
1676 
1677 	cd = &sc->xl_cdata;
1678 	ld = &sc->xl_ldata;
1679 	for (i = 0; i < XL_TX_LIST_CNT; i++) {
1680 		cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1681 		error = bus_dmamap_create(sc->xl_mtag, 0,
1682 		    &cd->xl_tx_chain[i].xl_map);
1683 		if (error)
1684 			return (error);
1685 		cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1686 		    i * sizeof(struct xl_list);
1687 		if (i == (XL_TX_LIST_CNT - 1))
1688 			cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1689 		else
1690 			cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1691 		if (i == 0)
1692 			cd->xl_tx_chain[i].xl_prev =
1693 			    &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1694 		else
1695 			cd->xl_tx_chain[i].xl_prev =
1696 			    &cd->xl_tx_chain[i - 1];
1697 	}
1698 
1699 	bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1700 	ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1701 
1702 	cd->xl_tx_prod = 1;
1703 	cd->xl_tx_cons = 1;
1704 	cd->xl_tx_cnt = 0;
1705 
1706 	bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1707 	return (0);
1708 }
1709 
1710 /*
1711  * Initialize the RX descriptors and allocate mbufs for them. Note that
1712  * we arrange the descriptors in a closed ring, so that the last descriptor
1713  * points back to the first.
1714  */
1715 static int
1716 xl_list_rx_init(struct xl_softc *sc)
1717 {
1718 	struct xl_chain_data	*cd;
1719 	struct xl_list_data	*ld;
1720 	int			error, i, next;
1721 	u_int32_t		nextptr;
1722 
1723 	XL_LOCK_ASSERT(sc);
1724 
1725 	cd = &sc->xl_cdata;
1726 	ld = &sc->xl_ldata;
1727 
1728 	for (i = 0; i < XL_RX_LIST_CNT; i++) {
1729 		cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1730 		error = bus_dmamap_create(sc->xl_mtag, 0,
1731 		    &cd->xl_rx_chain[i].xl_map);
1732 		if (error)
1733 			return (error);
1734 		error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1735 		if (error)
1736 			return (error);
1737 		if (i == (XL_RX_LIST_CNT - 1))
1738 			next = 0;
1739 		else
1740 			next = i + 1;
1741 		nextptr = ld->xl_rx_dmaaddr +
1742 		    next * sizeof(struct xl_list_onefrag);
1743 		cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1744 		ld->xl_rx_list[i].xl_next = htole32(nextptr);
1745 	}
1746 
1747 	bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1748 	cd->xl_rx_head = &cd->xl_rx_chain[0];
1749 
1750 	return (0);
1751 }
1752 
1753 /*
1754  * Initialize an RX descriptor and attach an MBUF cluster.
1755  * If we fail to do so, we need to leave the old mbuf and
1756  * the old DMA map untouched so that it can be reused.
1757  */
1758 static int
1759 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1760 {
1761 	struct mbuf		*m_new = NULL;
1762 	bus_dmamap_t		map;
1763 	bus_dma_segment_t	segs[1];
1764 	int			error, nseg;
1765 
1766 	XL_LOCK_ASSERT(sc);
1767 
1768 	m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1769 	if (m_new == NULL)
1770 		return (ENOBUFS);
1771 
1772 	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1773 
1774 	/* Force longword alignment for packet payload. */
1775 	m_adj(m_new, ETHER_ALIGN);
1776 
1777 	error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new,
1778 	    segs, &nseg, BUS_DMA_NOWAIT);
1779 	if (error) {
1780 		m_freem(m_new);
1781 		device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1782 		    error);
1783 		return (error);
1784 	}
1785 	KASSERT(nseg == 1,
1786 	    ("%s: too many DMA segments (%d)", __func__, nseg));
1787 
1788 	bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1789 	map = c->xl_map;
1790 	c->xl_map = sc->xl_tmpmap;
1791 	sc->xl_tmpmap = map;
1792 	c->xl_mbuf = m_new;
1793 	c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1794 	c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr);
1795 	c->xl_ptr->xl_status = 0;
1796 	bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1797 	return (0);
1798 }
1799 
1800 static int
1801 xl_rx_resync(struct xl_softc *sc)
1802 {
1803 	struct xl_chain_onefrag	*pos;
1804 	int			i;
1805 
1806 	XL_LOCK_ASSERT(sc);
1807 
1808 	pos = sc->xl_cdata.xl_rx_head;
1809 
1810 	for (i = 0; i < XL_RX_LIST_CNT; i++) {
1811 		if (pos->xl_ptr->xl_status)
1812 			break;
1813 		pos = pos->xl_next;
1814 	}
1815 
1816 	if (i == XL_RX_LIST_CNT)
1817 		return (0);
1818 
1819 	sc->xl_cdata.xl_rx_head = pos;
1820 
1821 	return (EAGAIN);
1822 }
1823 
1824 /*
1825  * A frame has been uploaded: pass the resulting mbuf chain up to
1826  * the higher level protocols.
1827  */
1828 static int
1829 xl_rxeof(struct xl_softc *sc)
1830 {
1831 	struct mbuf		*m;
1832 	struct ifnet		*ifp = sc->xl_ifp;
1833 	struct xl_chain_onefrag	*cur_rx;
1834 	int			total_len;
1835 	int			rx_npkts = 0;
1836 	u_int32_t		rxstat;
1837 
1838 	XL_LOCK_ASSERT(sc);
1839 again:
1840 	bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1841 	    BUS_DMASYNC_POSTREAD);
1842 	while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1843 #ifdef DEVICE_POLLING
1844 		if (ifp->if_capenable & IFCAP_POLLING) {
1845 			if (sc->rxcycles <= 0)
1846 				break;
1847 			sc->rxcycles--;
1848 		}
1849 #endif
1850 		cur_rx = sc->xl_cdata.xl_rx_head;
1851 		sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1852 		total_len = rxstat & XL_RXSTAT_LENMASK;
1853 		rx_npkts++;
1854 
1855 		/*
1856 		 * Since we have told the chip to allow large frames,
1857 		 * we need to trap giant frame errors in software. We allow
1858 		 * a little more than the normal frame size to account for
1859 		 * frames with VLAN tags.
1860 		 */
1861 		if (total_len > XL_MAX_FRAMELEN)
1862 			rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1863 
1864 		/*
1865 		 * If an error occurs, update stats, clear the
1866 		 * status word and leave the mbuf cluster in place:
1867 		 * it should simply get re-used next time this descriptor
1868 		 * comes up in the ring.
1869 		 */
1870 		if (rxstat & XL_RXSTAT_UP_ERROR) {
1871 			if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1872 			cur_rx->xl_ptr->xl_status = 0;
1873 			bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1874 			    sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1875 			continue;
1876 		}
1877 
1878 		/*
1879 		 * If the error bit was not set, the upload complete
1880 		 * bit should be set which means we have a valid packet.
1881 		 * If not, something truly strange has happened.
1882 		 */
1883 		if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1884 			device_printf(sc->xl_dev,
1885 			    "bad receive status -- packet dropped\n");
1886 			if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1887 			cur_rx->xl_ptr->xl_status = 0;
1888 			bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1889 			    sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1890 			continue;
1891 		}
1892 
1893 		/* No errors; receive the packet. */
1894 		bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
1895 		    BUS_DMASYNC_POSTREAD);
1896 		m = cur_rx->xl_mbuf;
1897 
1898 		/*
1899 		 * Try to conjure up a new mbuf cluster. If that
1900 		 * fails, it means we have an out of memory condition and
1901 		 * should leave the buffer in place and continue. This will
1902 		 * result in a lost packet, but there's little else we
1903 		 * can do in this situation.
1904 		 */
1905 		if (xl_newbuf(sc, cur_rx)) {
1906 			if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1907 			cur_rx->xl_ptr->xl_status = 0;
1908 			bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1909 			    sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1910 			continue;
1911 		}
1912 		bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1913 		    sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1914 
1915 		if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1916 		m->m_pkthdr.rcvif = ifp;
1917 		m->m_pkthdr.len = m->m_len = total_len;
1918 
1919 		if (ifp->if_capenable & IFCAP_RXCSUM) {
1920 			/* Do IP checksum checking. */
1921 			if (rxstat & XL_RXSTAT_IPCKOK)
1922 				m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1923 			if (!(rxstat & XL_RXSTAT_IPCKERR))
1924 				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1925 			if ((rxstat & XL_RXSTAT_TCPCOK &&
1926 			     !(rxstat & XL_RXSTAT_TCPCKERR)) ||
1927 			    (rxstat & XL_RXSTAT_UDPCKOK &&
1928 			     !(rxstat & XL_RXSTAT_UDPCKERR))) {
1929 				m->m_pkthdr.csum_flags |=
1930 					CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1931 				m->m_pkthdr.csum_data = 0xffff;
1932 			}
1933 		}
1934 
1935 		XL_UNLOCK(sc);
1936 		(*ifp->if_input)(ifp, m);
1937 		XL_LOCK(sc);
1938 
1939 		/*
1940 		 * If we are running from the taskqueue, the interface
1941 		 * might have been stopped while we were passing the last
1942 		 * packet up the network stack.
1943 		 */
1944 		if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1945 			return (rx_npkts);
1946 	}
1947 
1948 	/*
1949 	 * Handle the 'end of channel' condition. When the upload
1950 	 * engine hits the end of the RX ring, it will stall. This
1951 	 * is our cue to flush the RX ring, reload the uplist pointer
1952 	 * register and unstall the engine.
1953 	 * XXX This is actually a little goofy. With the ThunderLAN
1954 	 * chip, you get an interrupt when the receiver hits the end
1955 	 * of the receive ring, which tells you exactly when you
1956 	 * you need to reload the ring pointer. Here we have to
1957 	 * fake it. I'm mad at myself for not being clever enough
1958 	 * to avoid the use of a goto here.
1959 	 */
1960 	if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1961 		CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1962 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1963 		xl_wait(sc);
1964 		CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
1965 		sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1966 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1967 		goto again;
1968 	}
1969 	return (rx_npkts);
1970 }
1971 
1972 /*
1973  * Taskqueue wrapper for xl_rxeof().
1974  */
1975 static void
1976 xl_rxeof_task(void *arg, int pending)
1977 {
1978 	struct xl_softc *sc = (struct xl_softc *)arg;
1979 
1980 	XL_LOCK(sc);
1981 	if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
1982 		xl_rxeof(sc);
1983 	XL_UNLOCK(sc);
1984 }
1985 
1986 /*
1987  * A frame was downloaded to the chip. It's safe for us to clean up
1988  * the list buffers.
1989  */
1990 static void
1991 xl_txeof(struct xl_softc *sc)
1992 {
1993 	struct xl_chain		*cur_tx;
1994 	struct ifnet		*ifp = sc->xl_ifp;
1995 
1996 	XL_LOCK_ASSERT(sc);
1997 
1998 	/*
1999 	 * Go through our tx list and free mbufs for those
2000 	 * frames that have been uploaded. Note: the 3c905B
2001 	 * sets a special bit in the status word to let us
2002 	 * know that a frame has been downloaded, but the
2003 	 * original 3c900/3c905 adapters don't do that.
2004 	 * Consequently, we have to use a different test if
2005 	 * xl_type != XL_TYPE_905B.
2006 	 */
2007 	while (sc->xl_cdata.xl_tx_head != NULL) {
2008 		cur_tx = sc->xl_cdata.xl_tx_head;
2009 
2010 		if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2011 			break;
2012 
2013 		sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2014 		bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2015 		    BUS_DMASYNC_POSTWRITE);
2016 		bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2017 		m_freem(cur_tx->xl_mbuf);
2018 		cur_tx->xl_mbuf = NULL;
2019 		if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2020 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2021 
2022 		cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2023 		sc->xl_cdata.xl_tx_free = cur_tx;
2024 	}
2025 
2026 	if (sc->xl_cdata.xl_tx_head == NULL) {
2027 		sc->xl_wdog_timer = 0;
2028 		sc->xl_cdata.xl_tx_tail = NULL;
2029 	} else {
2030 		if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2031 			!CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2032 			CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2033 				sc->xl_cdata.xl_tx_head->xl_phys);
2034 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2035 		}
2036 	}
2037 }
2038 
2039 static void
2040 xl_txeof_90xB(struct xl_softc *sc)
2041 {
2042 	struct xl_chain		*cur_tx = NULL;
2043 	struct ifnet		*ifp = sc->xl_ifp;
2044 	int			idx;
2045 
2046 	XL_LOCK_ASSERT(sc);
2047 
2048 	bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2049 	    BUS_DMASYNC_POSTREAD);
2050 	idx = sc->xl_cdata.xl_tx_cons;
2051 	while (idx != sc->xl_cdata.xl_tx_prod) {
2052 		cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2053 
2054 		if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2055 		      XL_TXSTAT_DL_COMPLETE))
2056 			break;
2057 
2058 		if (cur_tx->xl_mbuf != NULL) {
2059 			bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2060 			    BUS_DMASYNC_POSTWRITE);
2061 			bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2062 			m_freem(cur_tx->xl_mbuf);
2063 			cur_tx->xl_mbuf = NULL;
2064 		}
2065 
2066 		if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2067 
2068 		sc->xl_cdata.xl_tx_cnt--;
2069 		XL_INC(idx, XL_TX_LIST_CNT);
2070 	}
2071 
2072 	if (sc->xl_cdata.xl_tx_cnt == 0)
2073 		sc->xl_wdog_timer = 0;
2074 	sc->xl_cdata.xl_tx_cons = idx;
2075 
2076 	if (cur_tx != NULL)
2077 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2078 }
2079 
2080 /*
2081  * TX 'end of channel' interrupt handler. Actually, we should
2082  * only get a 'TX complete' interrupt if there's a transmit error,
2083  * so this is really TX error handler.
2084  */
2085 static void
2086 xl_txeoc(struct xl_softc *sc)
2087 {
2088 	u_int8_t		txstat;
2089 
2090 	XL_LOCK_ASSERT(sc);
2091 
2092 	while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2093 		if (txstat & XL_TXSTATUS_UNDERRUN ||
2094 			txstat & XL_TXSTATUS_JABBER ||
2095 			txstat & XL_TXSTATUS_RECLAIM) {
2096 			device_printf(sc->xl_dev,
2097 			    "transmission error: 0x%02x\n", txstat);
2098 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2099 			xl_wait(sc);
2100 			if (sc->xl_type == XL_TYPE_905B) {
2101 				if (sc->xl_cdata.xl_tx_cnt) {
2102 					int			i;
2103 					struct xl_chain		*c;
2104 
2105 					i = sc->xl_cdata.xl_tx_cons;
2106 					c = &sc->xl_cdata.xl_tx_chain[i];
2107 					CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2108 					    c->xl_phys);
2109 					CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2110 					sc->xl_wdog_timer = 5;
2111 				}
2112 			} else {
2113 				if (sc->xl_cdata.xl_tx_head != NULL) {
2114 					CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2115 					    sc->xl_cdata.xl_tx_head->xl_phys);
2116 					sc->xl_wdog_timer = 5;
2117 				}
2118 			}
2119 			/*
2120 			 * Remember to set this for the
2121 			 * first generation 3c90X chips.
2122 			 */
2123 			CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2124 			if (txstat & XL_TXSTATUS_UNDERRUN &&
2125 			    sc->xl_tx_thresh < XL_PACKET_SIZE) {
2126 				sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2127 				device_printf(sc->xl_dev,
2128 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2129 			}
2130 			CSR_WRITE_2(sc, XL_COMMAND,
2131 			    XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2132 			if (sc->xl_type == XL_TYPE_905B) {
2133 				CSR_WRITE_2(sc, XL_COMMAND,
2134 				XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2135 			}
2136 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2137 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2138 		} else {
2139 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2140 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2141 		}
2142 		/*
2143 		 * Write an arbitrary byte to the TX_STATUS register
2144 		 * to clear this interrupt/error and advance to the next.
2145 		 */
2146 		CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2147 	}
2148 }
2149 
2150 static void
2151 xl_intr(void *arg)
2152 {
2153 	struct xl_softc		*sc = arg;
2154 	struct ifnet		*ifp = sc->xl_ifp;
2155 	u_int16_t		status;
2156 
2157 	XL_LOCK(sc);
2158 
2159 #ifdef DEVICE_POLLING
2160 	if (ifp->if_capenable & IFCAP_POLLING) {
2161 		XL_UNLOCK(sc);
2162 		return;
2163 	}
2164 #endif
2165 
2166 	for (;;) {
2167 		status = CSR_READ_2(sc, XL_STATUS);
2168 		if ((status & XL_INTRS) == 0 || status == 0xFFFF)
2169 			break;
2170 		CSR_WRITE_2(sc, XL_COMMAND,
2171 		    XL_CMD_INTR_ACK|(status & XL_INTRS));
2172 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2173 			break;
2174 
2175 		if (status & XL_STAT_UP_COMPLETE) {
2176 			if (xl_rxeof(sc) == 0) {
2177 				while (xl_rx_resync(sc))
2178 					xl_rxeof(sc);
2179 			}
2180 		}
2181 
2182 		if (status & XL_STAT_DOWN_COMPLETE) {
2183 			if (sc->xl_type == XL_TYPE_905B)
2184 				xl_txeof_90xB(sc);
2185 			else
2186 				xl_txeof(sc);
2187 		}
2188 
2189 		if (status & XL_STAT_TX_COMPLETE) {
2190 			if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2191 			xl_txeoc(sc);
2192 		}
2193 
2194 		if (status & XL_STAT_ADFAIL) {
2195 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2196 			xl_init_locked(sc);
2197 			break;
2198 		}
2199 
2200 		if (status & XL_STAT_STATSOFLOW)
2201 			xl_stats_update(sc);
2202 	}
2203 
2204 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2205 	    ifp->if_drv_flags & IFF_DRV_RUNNING) {
2206 		if (sc->xl_type == XL_TYPE_905B)
2207 			xl_start_90xB_locked(ifp);
2208 		else
2209 			xl_start_locked(ifp);
2210 	}
2211 
2212 	XL_UNLOCK(sc);
2213 }
2214 
2215 #ifdef DEVICE_POLLING
2216 static int
2217 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2218 {
2219 	struct xl_softc *sc = ifp->if_softc;
2220 	int rx_npkts = 0;
2221 
2222 	XL_LOCK(sc);
2223 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2224 		rx_npkts = xl_poll_locked(ifp, cmd, count);
2225 	XL_UNLOCK(sc);
2226 	return (rx_npkts);
2227 }
2228 
2229 static int
2230 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2231 {
2232 	struct xl_softc *sc = ifp->if_softc;
2233 	int rx_npkts;
2234 
2235 	XL_LOCK_ASSERT(sc);
2236 
2237 	sc->rxcycles = count;
2238 	rx_npkts = xl_rxeof(sc);
2239 	if (sc->xl_type == XL_TYPE_905B)
2240 		xl_txeof_90xB(sc);
2241 	else
2242 		xl_txeof(sc);
2243 
2244 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2245 		if (sc->xl_type == XL_TYPE_905B)
2246 			xl_start_90xB_locked(ifp);
2247 		else
2248 			xl_start_locked(ifp);
2249 	}
2250 
2251 	if (cmd == POLL_AND_CHECK_STATUS) {
2252 		u_int16_t status;
2253 
2254 		status = CSR_READ_2(sc, XL_STATUS);
2255 		if (status & XL_INTRS && status != 0xFFFF) {
2256 			CSR_WRITE_2(sc, XL_COMMAND,
2257 			    XL_CMD_INTR_ACK|(status & XL_INTRS));
2258 
2259 			if (status & XL_STAT_TX_COMPLETE) {
2260 				if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2261 				xl_txeoc(sc);
2262 			}
2263 
2264 			if (status & XL_STAT_ADFAIL) {
2265 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2266 				xl_init_locked(sc);
2267 			}
2268 
2269 			if (status & XL_STAT_STATSOFLOW)
2270 				xl_stats_update(sc);
2271 		}
2272 	}
2273 	return (rx_npkts);
2274 }
2275 #endif /* DEVICE_POLLING */
2276 
2277 static void
2278 xl_tick(void *xsc)
2279 {
2280 	struct xl_softc *sc = xsc;
2281 	struct mii_data *mii;
2282 
2283 	XL_LOCK_ASSERT(sc);
2284 
2285 	if (sc->xl_miibus != NULL) {
2286 		mii = device_get_softc(sc->xl_miibus);
2287 		mii_tick(mii);
2288 	}
2289 
2290 	xl_stats_update(sc);
2291 	if (xl_watchdog(sc) == EJUSTRETURN)
2292 		return;
2293 
2294 	callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2295 }
2296 
2297 static void
2298 xl_stats_update(struct xl_softc *sc)
2299 {
2300 	struct ifnet		*ifp = sc->xl_ifp;
2301 	struct xl_stats		xl_stats;
2302 	u_int8_t		*p;
2303 	int			i;
2304 
2305 	XL_LOCK_ASSERT(sc);
2306 
2307 	bzero((char *)&xl_stats, sizeof(struct xl_stats));
2308 
2309 	p = (u_int8_t *)&xl_stats;
2310 
2311 	/* Read all the stats registers. */
2312 	XL_SEL_WIN(6);
2313 
2314 	for (i = 0; i < 16; i++)
2315 		*p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2316 
2317 	if_inc_counter(ifp, IFCOUNTER_IERRORS, xl_stats.xl_rx_overrun);
2318 
2319 	if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2320 	    xl_stats.xl_tx_multi_collision +
2321 	    xl_stats.xl_tx_single_collision +
2322 	    xl_stats.xl_tx_late_collision);
2323 
2324 	/*
2325 	 * Boomerang and cyclone chips have an extra stats counter
2326 	 * in window 4 (BadSSD). We have to read this too in order
2327 	 * to clear out all the stats registers and avoid a statsoflow
2328 	 * interrupt.
2329 	 */
2330 	XL_SEL_WIN(4);
2331 	CSR_READ_1(sc, XL_W4_BADSSD);
2332 	XL_SEL_WIN(7);
2333 }
2334 
2335 /*
2336  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2337  * pointers to the fragment pointers.
2338  */
2339 static int
2340 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head)
2341 {
2342 	struct mbuf		*m_new;
2343 	struct ifnet		*ifp = sc->xl_ifp;
2344 	int			error, i, nseg, total_len;
2345 	u_int32_t		status;
2346 
2347 	XL_LOCK_ASSERT(sc);
2348 
2349 	error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head,
2350 	    sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2351 
2352 	if (error && error != EFBIG) {
2353 		if_printf(ifp, "can't map mbuf (error %d)\n", error);
2354 		return (error);
2355 	}
2356 
2357 	/*
2358 	 * Handle special case: we used up all 63 fragments,
2359 	 * but we have more mbufs left in the chain. Copy the
2360 	 * data into an mbuf cluster. Note that we don't
2361 	 * bother clearing the values in the other fragment
2362 	 * pointers/counters; it wouldn't gain us anything,
2363 	 * and would waste cycles.
2364 	 */
2365 	if (error) {
2366 		m_new = m_collapse(*m_head, M_NOWAIT, XL_MAXFRAGS);
2367 		if (m_new == NULL) {
2368 			m_freem(*m_head);
2369 			*m_head = NULL;
2370 			return (ENOBUFS);
2371 		}
2372 		*m_head = m_new;
2373 
2374 		error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map,
2375 		    *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2376 		if (error) {
2377 			m_freem(*m_head);
2378 			*m_head = NULL;
2379 			if_printf(ifp, "can't map mbuf (error %d)\n", error);
2380 			return (error);
2381 		}
2382 	}
2383 
2384 	KASSERT(nseg <= XL_MAXFRAGS,
2385 	    ("%s: too many DMA segments (%d)", __func__, nseg));
2386 	if (nseg == 0) {
2387 		m_freem(*m_head);
2388 		*m_head = NULL;
2389 		return (EIO);
2390 	}
2391 	bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2392 
2393 	total_len = 0;
2394 	for (i = 0; i < nseg; i++) {
2395 		KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES,
2396 		    ("segment size too large"));
2397 		c->xl_ptr->xl_frag[i].xl_addr =
2398 		    htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr);
2399 		c->xl_ptr->xl_frag[i].xl_len =
2400 		    htole32(sc->xl_cdata.xl_tx_segs[i].ds_len);
2401 		total_len += sc->xl_cdata.xl_tx_segs[i].ds_len;
2402 	}
2403 	c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG);
2404 
2405 	if (sc->xl_type == XL_TYPE_905B) {
2406 		status = XL_TXSTAT_RND_DEFEAT;
2407 
2408 #ifndef XL905B_TXCSUM_BROKEN
2409 		if ((*m_head)->m_pkthdr.csum_flags) {
2410 			if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
2411 				status |= XL_TXSTAT_IPCKSUM;
2412 			if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
2413 				status |= XL_TXSTAT_TCPCKSUM;
2414 			if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
2415 				status |= XL_TXSTAT_UDPCKSUM;
2416 		}
2417 #endif
2418 	} else
2419 		status = total_len;
2420 	c->xl_ptr->xl_status = htole32(status);
2421 	c->xl_ptr->xl_next = 0;
2422 
2423 	c->xl_mbuf = *m_head;
2424 	return (0);
2425 }
2426 
2427 /*
2428  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2429  * to the mbuf data regions directly in the transmit lists. We also save a
2430  * copy of the pointers since the transmit list fragment pointers are
2431  * physical addresses.
2432  */
2433 
2434 static void
2435 xl_start(struct ifnet *ifp)
2436 {
2437 	struct xl_softc		*sc = ifp->if_softc;
2438 
2439 	XL_LOCK(sc);
2440 
2441 	if (sc->xl_type == XL_TYPE_905B)
2442 		xl_start_90xB_locked(ifp);
2443 	else
2444 		xl_start_locked(ifp);
2445 
2446 	XL_UNLOCK(sc);
2447 }
2448 
2449 static void
2450 xl_start_locked(struct ifnet *ifp)
2451 {
2452 	struct xl_softc		*sc = ifp->if_softc;
2453 	struct mbuf		*m_head;
2454 	struct xl_chain		*prev = NULL, *cur_tx = NULL, *start_tx;
2455 	struct xl_chain		*prev_tx;
2456 	int			error;
2457 
2458 	XL_LOCK_ASSERT(sc);
2459 
2460 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2461 	    IFF_DRV_RUNNING)
2462 		return;
2463 	/*
2464 	 * Check for an available queue slot. If there are none,
2465 	 * punt.
2466 	 */
2467 	if (sc->xl_cdata.xl_tx_free == NULL) {
2468 		xl_txeoc(sc);
2469 		xl_txeof(sc);
2470 		if (sc->xl_cdata.xl_tx_free == NULL) {
2471 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2472 			return;
2473 		}
2474 	}
2475 
2476 	start_tx = sc->xl_cdata.xl_tx_free;
2477 
2478 	for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2479 	    sc->xl_cdata.xl_tx_free != NULL;) {
2480 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2481 		if (m_head == NULL)
2482 			break;
2483 
2484 		/* Pick a descriptor off the free list. */
2485 		prev_tx = cur_tx;
2486 		cur_tx = sc->xl_cdata.xl_tx_free;
2487 
2488 		/* Pack the data into the descriptor. */
2489 		error = xl_encap(sc, cur_tx, &m_head);
2490 		if (error) {
2491 			cur_tx = prev_tx;
2492 			if (m_head == NULL)
2493 				break;
2494 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2495 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2496 			break;
2497 		}
2498 
2499 		sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2500 		cur_tx->xl_next = NULL;
2501 
2502 		/* Chain it together. */
2503 		if (prev != NULL) {
2504 			prev->xl_next = cur_tx;
2505 			prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2506 		}
2507 		prev = cur_tx;
2508 
2509 		/*
2510 		 * If there's a BPF listener, bounce a copy of this frame
2511 		 * to him.
2512 		 */
2513 		BPF_MTAP(ifp, cur_tx->xl_mbuf);
2514 	}
2515 
2516 	/*
2517 	 * If there are no packets queued, bail.
2518 	 */
2519 	if (cur_tx == NULL)
2520 		return;
2521 
2522 	/*
2523 	 * Place the request for the upload interrupt
2524 	 * in the last descriptor in the chain. This way, if
2525 	 * we're chaining several packets at once, we'll only
2526 	 * get an interrupt once for the whole chain rather than
2527 	 * once for each packet.
2528 	 */
2529 	cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2530 
2531 	/*
2532 	 * Queue the packets. If the TX channel is clear, update
2533 	 * the downlist pointer register.
2534 	 */
2535 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2536 	xl_wait(sc);
2537 
2538 	if (sc->xl_cdata.xl_tx_head != NULL) {
2539 		sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2540 		sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2541 		    htole32(start_tx->xl_phys);
2542 		sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2543 		    htole32(~XL_TXSTAT_DL_INTR);
2544 		sc->xl_cdata.xl_tx_tail = cur_tx;
2545 	} else {
2546 		sc->xl_cdata.xl_tx_head = start_tx;
2547 		sc->xl_cdata.xl_tx_tail = cur_tx;
2548 	}
2549 	bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2550 	    BUS_DMASYNC_PREWRITE);
2551 	if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2552 		CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2553 
2554 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2555 
2556 	XL_SEL_WIN(7);
2557 
2558 	/*
2559 	 * Set a timeout in case the chip goes out to lunch.
2560 	 */
2561 	sc->xl_wdog_timer = 5;
2562 
2563 	/*
2564 	 * XXX Under certain conditions, usually on slower machines
2565 	 * where interrupts may be dropped, it's possible for the
2566 	 * adapter to chew up all the buffers in the receive ring
2567 	 * and stall, without us being able to do anything about it.
2568 	 * To guard against this, we need to make a pass over the
2569 	 * RX queue to make sure there aren't any packets pending.
2570 	 * Doing it here means we can flush the receive ring at the
2571 	 * same time the chip is DMAing the transmit descriptors we
2572 	 * just gave it.
2573 	 *
2574 	 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2575 	 * nature of their chips in all their marketing literature;
2576 	 * we may as well take advantage of it. :)
2577 	 */
2578 	taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2579 }
2580 
2581 static void
2582 xl_start_90xB_locked(struct ifnet *ifp)
2583 {
2584 	struct xl_softc		*sc = ifp->if_softc;
2585 	struct mbuf		*m_head;
2586 	struct xl_chain		*prev = NULL, *cur_tx = NULL, *start_tx;
2587 	struct xl_chain		*prev_tx;
2588 	int			error, idx;
2589 
2590 	XL_LOCK_ASSERT(sc);
2591 
2592 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2593 	    IFF_DRV_RUNNING)
2594 		return;
2595 
2596 	idx = sc->xl_cdata.xl_tx_prod;
2597 	start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2598 
2599 	for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2600 	    sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) {
2601 		if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2602 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2603 			break;
2604 		}
2605 
2606 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2607 		if (m_head == NULL)
2608 			break;
2609 
2610 		prev_tx = cur_tx;
2611 		cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2612 
2613 		/* Pack the data into the descriptor. */
2614 		error = xl_encap(sc, cur_tx, &m_head);
2615 		if (error) {
2616 			cur_tx = prev_tx;
2617 			if (m_head == NULL)
2618 				break;
2619 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2620 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2621 			break;
2622 		}
2623 
2624 		/* Chain it together. */
2625 		if (prev != NULL)
2626 			prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2627 		prev = cur_tx;
2628 
2629 		/*
2630 		 * If there's a BPF listener, bounce a copy of this frame
2631 		 * to him.
2632 		 */
2633 		BPF_MTAP(ifp, cur_tx->xl_mbuf);
2634 
2635 		XL_INC(idx, XL_TX_LIST_CNT);
2636 		sc->xl_cdata.xl_tx_cnt++;
2637 	}
2638 
2639 	/*
2640 	 * If there are no packets queued, bail.
2641 	 */
2642 	if (cur_tx == NULL)
2643 		return;
2644 
2645 	/*
2646 	 * Place the request for the upload interrupt
2647 	 * in the last descriptor in the chain. This way, if
2648 	 * we're chaining several packets at once, we'll only
2649 	 * get an interrupt once for the whole chain rather than
2650 	 * once for each packet.
2651 	 */
2652 	cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2653 
2654 	/* Start transmission */
2655 	sc->xl_cdata.xl_tx_prod = idx;
2656 	start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2657 	bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2658 	    BUS_DMASYNC_PREWRITE);
2659 
2660 	/*
2661 	 * Set a timeout in case the chip goes out to lunch.
2662 	 */
2663 	sc->xl_wdog_timer = 5;
2664 }
2665 
2666 static void
2667 xl_init(void *xsc)
2668 {
2669 	struct xl_softc		*sc = xsc;
2670 
2671 	XL_LOCK(sc);
2672 	xl_init_locked(sc);
2673 	XL_UNLOCK(sc);
2674 }
2675 
2676 static void
2677 xl_init_locked(struct xl_softc *sc)
2678 {
2679 	struct ifnet		*ifp = sc->xl_ifp;
2680 	int			error, i;
2681 	struct mii_data		*mii = NULL;
2682 
2683 	XL_LOCK_ASSERT(sc);
2684 
2685 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2686 		return;
2687 	/*
2688 	 * Cancel pending I/O and free all RX/TX buffers.
2689 	 */
2690 	xl_stop(sc);
2691 
2692 	/* Reset the chip to a known state. */
2693 	xl_reset(sc);
2694 
2695 	if (sc->xl_miibus == NULL) {
2696 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2697 		xl_wait(sc);
2698 	}
2699 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2700 	xl_wait(sc);
2701 	DELAY(10000);
2702 
2703 	if (sc->xl_miibus != NULL)
2704 		mii = device_get_softc(sc->xl_miibus);
2705 
2706 	/*
2707 	 * Clear WOL status and disable all WOL feature as WOL
2708 	 * would interfere Rx operation under normal environments.
2709 	 */
2710 	if ((sc->xl_flags & XL_FLAG_WOL) != 0) {
2711 		XL_SEL_WIN(7);
2712 		CSR_READ_2(sc, XL_W7_BM_PME);
2713 		CSR_WRITE_2(sc, XL_W7_BM_PME, 0);
2714 	}
2715 	/* Init our MAC address */
2716 	XL_SEL_WIN(2);
2717 	for (i = 0; i < ETHER_ADDR_LEN; i++) {
2718 		CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2719 				IF_LLADDR(sc->xl_ifp)[i]);
2720 	}
2721 
2722 	/* Clear the station mask. */
2723 	for (i = 0; i < 3; i++)
2724 		CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2725 #ifdef notdef
2726 	/* Reset TX and RX. */
2727 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2728 	xl_wait(sc);
2729 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2730 	xl_wait(sc);
2731 #endif
2732 	/* Init circular RX list. */
2733 	error = xl_list_rx_init(sc);
2734 	if (error) {
2735 		device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2736 		    error);
2737 		xl_stop(sc);
2738 		return;
2739 	}
2740 
2741 	/* Init TX descriptors. */
2742 	if (sc->xl_type == XL_TYPE_905B)
2743 		error = xl_list_tx_init_90xB(sc);
2744 	else
2745 		error = xl_list_tx_init(sc);
2746 	if (error) {
2747 		device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2748 		    error);
2749 		xl_stop(sc);
2750 		return;
2751 	}
2752 
2753 	/*
2754 	 * Set the TX freethresh value.
2755 	 * Note that this has no effect on 3c905B "cyclone"
2756 	 * cards but is required for 3c900/3c905 "boomerang"
2757 	 * cards in order to enable the download engine.
2758 	 */
2759 	CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2760 
2761 	/* Set the TX start threshold for best performance. */
2762 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2763 
2764 	/*
2765 	 * If this is a 3c905B, also set the tx reclaim threshold.
2766 	 * This helps cut down on the number of tx reclaim errors
2767 	 * that could happen on a busy network. The chip multiplies
2768 	 * the register value by 16 to obtain the actual threshold
2769 	 * in bytes, so we divide by 16 when setting the value here.
2770 	 * The existing threshold value can be examined by reading
2771 	 * the register at offset 9 in window 5.
2772 	 */
2773 	if (sc->xl_type == XL_TYPE_905B) {
2774 		CSR_WRITE_2(sc, XL_COMMAND,
2775 		    XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2776 	}
2777 
2778 	/* Set RX filter bits. */
2779 	xl_rxfilter(sc);
2780 
2781 	/*
2782 	 * Load the address of the RX list. We have to
2783 	 * stall the upload engine before we can manipulate
2784 	 * the uplist pointer register, then unstall it when
2785 	 * we're finished. We also have to wait for the
2786 	 * stall command to complete before proceeding.
2787 	 * Note that we have to do this after any RX resets
2788 	 * have completed since the uplist register is cleared
2789 	 * by a reset.
2790 	 */
2791 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2792 	xl_wait(sc);
2793 	CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2794 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2795 	xl_wait(sc);
2796 
2797 	if (sc->xl_type == XL_TYPE_905B) {
2798 		/* Set polling interval */
2799 		CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2800 		/* Load the address of the TX list */
2801 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2802 		xl_wait(sc);
2803 		CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2804 		    sc->xl_cdata.xl_tx_chain[0].xl_phys);
2805 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2806 		xl_wait(sc);
2807 	}
2808 
2809 	/*
2810 	 * If the coax transceiver is on, make sure to enable
2811 	 * the DC-DC converter.
2812 	 */
2813 	XL_SEL_WIN(3);
2814 	if (sc->xl_xcvr == XL_XCVR_COAX)
2815 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2816 	else
2817 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2818 
2819 	/*
2820 	 * increase packet size to allow reception of 802.1q or ISL packets.
2821 	 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2822 	 * control register. For 3c90xB/C chips, use the RX packet size
2823 	 * register.
2824 	 */
2825 
2826 	if (sc->xl_type == XL_TYPE_905B)
2827 		CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2828 	else {
2829 		u_int8_t macctl;
2830 		macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2831 		macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2832 		CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2833 	}
2834 
2835 	/* Clear out the stats counters. */
2836 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2837 	xl_stats_update(sc);
2838 	XL_SEL_WIN(4);
2839 	CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2840 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2841 
2842 	/*
2843 	 * Enable interrupts.
2844 	 */
2845 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2846 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2847 #ifdef DEVICE_POLLING
2848 	/* Disable interrupts if we are polling. */
2849 	if (ifp->if_capenable & IFCAP_POLLING)
2850 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2851 	else
2852 #endif
2853 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2854 	if (sc->xl_flags & XL_FLAG_FUNCREG)
2855 	    bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2856 
2857 	/* Set the RX early threshold */
2858 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2859 	CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2860 
2861 	/* Enable receiver and transmitter. */
2862 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2863 	xl_wait(sc);
2864 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2865 	xl_wait(sc);
2866 
2867 	/* XXX Downcall to miibus. */
2868 	if (mii != NULL)
2869 		mii_mediachg(mii);
2870 
2871 	/* Select window 7 for normal operations. */
2872 	XL_SEL_WIN(7);
2873 
2874 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
2875 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2876 
2877 	sc->xl_wdog_timer = 0;
2878 	callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2879 }
2880 
2881 /*
2882  * Set media options.
2883  */
2884 static int
2885 xl_ifmedia_upd(struct ifnet *ifp)
2886 {
2887 	struct xl_softc		*sc = ifp->if_softc;
2888 	struct ifmedia		*ifm = NULL;
2889 	struct mii_data		*mii = NULL;
2890 
2891 	XL_LOCK(sc);
2892 
2893 	if (sc->xl_miibus != NULL)
2894 		mii = device_get_softc(sc->xl_miibus);
2895 	if (mii == NULL)
2896 		ifm = &sc->ifmedia;
2897 	else
2898 		ifm = &mii->mii_media;
2899 
2900 	switch (IFM_SUBTYPE(ifm->ifm_media)) {
2901 	case IFM_100_FX:
2902 	case IFM_10_FL:
2903 	case IFM_10_2:
2904 	case IFM_10_5:
2905 		xl_setmode(sc, ifm->ifm_media);
2906 		XL_UNLOCK(sc);
2907 		return (0);
2908 	}
2909 
2910 	if (sc->xl_media & XL_MEDIAOPT_MII ||
2911 	    sc->xl_media & XL_MEDIAOPT_BTX ||
2912 	    sc->xl_media & XL_MEDIAOPT_BT4) {
2913 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2914 		xl_init_locked(sc);
2915 	} else {
2916 		xl_setmode(sc, ifm->ifm_media);
2917 	}
2918 
2919 	XL_UNLOCK(sc);
2920 
2921 	return (0);
2922 }
2923 
2924 /*
2925  * Report current media status.
2926  */
2927 static void
2928 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2929 {
2930 	struct xl_softc		*sc = ifp->if_softc;
2931 	u_int32_t		icfg;
2932 	u_int16_t		status = 0;
2933 	struct mii_data		*mii = NULL;
2934 
2935 	XL_LOCK(sc);
2936 
2937 	if (sc->xl_miibus != NULL)
2938 		mii = device_get_softc(sc->xl_miibus);
2939 
2940 	XL_SEL_WIN(4);
2941 	status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2942 
2943 	XL_SEL_WIN(3);
2944 	icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2945 	icfg >>= XL_ICFG_CONNECTOR_BITS;
2946 
2947 	ifmr->ifm_active = IFM_ETHER;
2948 	ifmr->ifm_status = IFM_AVALID;
2949 
2950 	if ((status & XL_MEDIASTAT_CARRIER) == 0)
2951 		ifmr->ifm_status |= IFM_ACTIVE;
2952 
2953 	switch (icfg) {
2954 	case XL_XCVR_10BT:
2955 		ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2956 		if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2957 			ifmr->ifm_active |= IFM_FDX;
2958 		else
2959 			ifmr->ifm_active |= IFM_HDX;
2960 		break;
2961 	case XL_XCVR_AUI:
2962 		if (sc->xl_type == XL_TYPE_905B &&
2963 		    sc->xl_media == XL_MEDIAOPT_10FL) {
2964 			ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
2965 			if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2966 				ifmr->ifm_active |= IFM_FDX;
2967 			else
2968 				ifmr->ifm_active |= IFM_HDX;
2969 		} else
2970 			ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2971 		break;
2972 	case XL_XCVR_COAX:
2973 		ifmr->ifm_active = IFM_ETHER|IFM_10_2;
2974 		break;
2975 	/*
2976 	 * XXX MII and BTX/AUTO should be separate cases.
2977 	 */
2978 
2979 	case XL_XCVR_100BTX:
2980 	case XL_XCVR_AUTO:
2981 	case XL_XCVR_MII:
2982 		if (mii != NULL) {
2983 			mii_pollstat(mii);
2984 			ifmr->ifm_active = mii->mii_media_active;
2985 			ifmr->ifm_status = mii->mii_media_status;
2986 		}
2987 		break;
2988 	case XL_XCVR_100BFX:
2989 		ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
2990 		break;
2991 	default:
2992 		if_printf(ifp, "unknown XCVR type: %d\n", icfg);
2993 		break;
2994 	}
2995 
2996 	XL_UNLOCK(sc);
2997 }
2998 
2999 static int
3000 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3001 {
3002 	struct xl_softc		*sc = ifp->if_softc;
3003 	struct ifreq		*ifr = (struct ifreq *) data;
3004 	int			error = 0, mask;
3005 	struct mii_data		*mii = NULL;
3006 
3007 	switch (command) {
3008 	case SIOCSIFFLAGS:
3009 		XL_LOCK(sc);
3010 		if (ifp->if_flags & IFF_UP) {
3011 			if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3012 			    (ifp->if_flags ^ sc->xl_if_flags) &
3013 			    (IFF_PROMISC | IFF_ALLMULTI))
3014 				xl_rxfilter(sc);
3015 			else
3016 				xl_init_locked(sc);
3017 		} else {
3018 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3019 				xl_stop(sc);
3020 		}
3021 		sc->xl_if_flags = ifp->if_flags;
3022 		XL_UNLOCK(sc);
3023 		break;
3024 	case SIOCADDMULTI:
3025 	case SIOCDELMULTI:
3026 		/* XXX Downcall from if_addmulti() possibly with locks held. */
3027 		XL_LOCK(sc);
3028 		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3029 			xl_rxfilter(sc);
3030 		XL_UNLOCK(sc);
3031 		break;
3032 	case SIOCGIFMEDIA:
3033 	case SIOCSIFMEDIA:
3034 		if (sc->xl_miibus != NULL)
3035 			mii = device_get_softc(sc->xl_miibus);
3036 		if (mii == NULL)
3037 			error = ifmedia_ioctl(ifp, ifr,
3038 			    &sc->ifmedia, command);
3039 		else
3040 			error = ifmedia_ioctl(ifp, ifr,
3041 			    &mii->mii_media, command);
3042 		break;
3043 	case SIOCSIFCAP:
3044 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3045 #ifdef DEVICE_POLLING
3046 		if ((mask & IFCAP_POLLING) != 0 &&
3047 		    (ifp->if_capabilities & IFCAP_POLLING) != 0) {
3048 			ifp->if_capenable ^= IFCAP_POLLING;
3049 			if ((ifp->if_capenable & IFCAP_POLLING) != 0) {
3050 				error = ether_poll_register(xl_poll, ifp);
3051 				if (error)
3052 					break;
3053 				XL_LOCK(sc);
3054 				/* Disable interrupts */
3055 				CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3056 				ifp->if_capenable |= IFCAP_POLLING;
3057 				XL_UNLOCK(sc);
3058 			} else {
3059 				error = ether_poll_deregister(ifp);
3060 				/* Enable interrupts. */
3061 				XL_LOCK(sc);
3062 				CSR_WRITE_2(sc, XL_COMMAND,
3063 				    XL_CMD_INTR_ACK | 0xFF);
3064 				CSR_WRITE_2(sc, XL_COMMAND,
3065 				    XL_CMD_INTR_ENB | XL_INTRS);
3066 				if (sc->xl_flags & XL_FLAG_FUNCREG)
3067 					bus_space_write_4(sc->xl_ftag,
3068 					    sc->xl_fhandle, 4, 0x8000);
3069 				XL_UNLOCK(sc);
3070 			}
3071 		}
3072 #endif /* DEVICE_POLLING */
3073 		XL_LOCK(sc);
3074 		if ((mask & IFCAP_TXCSUM) != 0 &&
3075 		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3076 			ifp->if_capenable ^= IFCAP_TXCSUM;
3077 			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3078 				ifp->if_hwassist |= XL905B_CSUM_FEATURES;
3079 			else
3080 				ifp->if_hwassist &= ~XL905B_CSUM_FEATURES;
3081 		}
3082 		if ((mask & IFCAP_RXCSUM) != 0 &&
3083 		    (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3084 			ifp->if_capenable ^= IFCAP_RXCSUM;
3085 		if ((mask & IFCAP_WOL_MAGIC) != 0 &&
3086 		    (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
3087 			ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3088 		XL_UNLOCK(sc);
3089 		break;
3090 	default:
3091 		error = ether_ioctl(ifp, command, data);
3092 		break;
3093 	}
3094 
3095 	return (error);
3096 }
3097 
3098 static int
3099 xl_watchdog(struct xl_softc *sc)
3100 {
3101 	struct ifnet		*ifp = sc->xl_ifp;
3102 	u_int16_t		status = 0;
3103 	int			misintr;
3104 
3105 	XL_LOCK_ASSERT(sc);
3106 
3107 	if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3108 		return (0);
3109 
3110 	xl_rxeof(sc);
3111 	xl_txeoc(sc);
3112 	misintr = 0;
3113 	if (sc->xl_type == XL_TYPE_905B) {
3114 		xl_txeof_90xB(sc);
3115 		if (sc->xl_cdata.xl_tx_cnt == 0)
3116 			misintr++;
3117 	} else {
3118 		xl_txeof(sc);
3119 		if (sc->xl_cdata.xl_tx_head == NULL)
3120 			misintr++;
3121 	}
3122 	if (misintr != 0) {
3123 		device_printf(sc->xl_dev,
3124 		    "watchdog timeout (missed Tx interrupts) -- recovering\n");
3125 		return (0);
3126 	}
3127 
3128 	if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3129 	XL_SEL_WIN(4);
3130 	status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3131 	device_printf(sc->xl_dev, "watchdog timeout\n");
3132 
3133 	if (status & XL_MEDIASTAT_CARRIER)
3134 		device_printf(sc->xl_dev,
3135 		    "no carrier - transceiver cable problem?\n");
3136 
3137 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3138 	xl_init_locked(sc);
3139 
3140 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3141 		if (sc->xl_type == XL_TYPE_905B)
3142 			xl_start_90xB_locked(ifp);
3143 		else
3144 			xl_start_locked(ifp);
3145 	}
3146 
3147 	return (EJUSTRETURN);
3148 }
3149 
3150 /*
3151  * Stop the adapter and free any mbufs allocated to the
3152  * RX and TX lists.
3153  */
3154 static void
3155 xl_stop(struct xl_softc *sc)
3156 {
3157 	int			i;
3158 	struct ifnet		*ifp = sc->xl_ifp;
3159 
3160 	XL_LOCK_ASSERT(sc);
3161 
3162 	sc->xl_wdog_timer = 0;
3163 
3164 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3165 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3166 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3167 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3168 	xl_wait(sc);
3169 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3170 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3171 	DELAY(800);
3172 
3173 #ifdef foo
3174 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3175 	xl_wait(sc);
3176 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3177 	xl_wait(sc);
3178 #endif
3179 
3180 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3181 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3182 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3183 	if (sc->xl_flags & XL_FLAG_FUNCREG)
3184 		bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3185 
3186 	/* Stop the stats updater. */
3187 	callout_stop(&sc->xl_tick_callout);
3188 
3189 	/*
3190 	 * Free data in the RX lists.
3191 	 */
3192 	for (i = 0; i < XL_RX_LIST_CNT; i++) {
3193 		if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3194 			bus_dmamap_unload(sc->xl_mtag,
3195 			    sc->xl_cdata.xl_rx_chain[i].xl_map);
3196 			bus_dmamap_destroy(sc->xl_mtag,
3197 			    sc->xl_cdata.xl_rx_chain[i].xl_map);
3198 			m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3199 			sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3200 		}
3201 	}
3202 	if (sc->xl_ldata.xl_rx_list != NULL)
3203 		bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3204 	/*
3205 	 * Free the TX list buffers.
3206 	 */
3207 	for (i = 0; i < XL_TX_LIST_CNT; i++) {
3208 		if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3209 			bus_dmamap_unload(sc->xl_mtag,
3210 			    sc->xl_cdata.xl_tx_chain[i].xl_map);
3211 			bus_dmamap_destroy(sc->xl_mtag,
3212 			    sc->xl_cdata.xl_tx_chain[i].xl_map);
3213 			m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3214 			sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3215 		}
3216 	}
3217 	if (sc->xl_ldata.xl_tx_list != NULL)
3218 		bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3219 
3220 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3221 }
3222 
3223 /*
3224  * Stop all chip I/O so that the kernel's probe routines don't
3225  * get confused by errant DMAs when rebooting.
3226  */
3227 static int
3228 xl_shutdown(device_t dev)
3229 {
3230 
3231 	return (xl_suspend(dev));
3232 }
3233 
3234 static int
3235 xl_suspend(device_t dev)
3236 {
3237 	struct xl_softc		*sc;
3238 
3239 	sc = device_get_softc(dev);
3240 
3241 	XL_LOCK(sc);
3242 	xl_stop(sc);
3243 	xl_setwol(sc);
3244 	XL_UNLOCK(sc);
3245 
3246 	return (0);
3247 }
3248 
3249 static int
3250 xl_resume(device_t dev)
3251 {
3252 	struct xl_softc		*sc;
3253 	struct ifnet		*ifp;
3254 
3255 	sc = device_get_softc(dev);
3256 	ifp = sc->xl_ifp;
3257 
3258 	XL_LOCK(sc);
3259 
3260 	if (ifp->if_flags & IFF_UP) {
3261 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3262 		xl_init_locked(sc);
3263 	}
3264 
3265 	XL_UNLOCK(sc);
3266 
3267 	return (0);
3268 }
3269 
3270 static void
3271 xl_setwol(struct xl_softc *sc)
3272 {
3273 	struct ifnet		*ifp;
3274 	u_int16_t		cfg, pmstat;
3275 
3276 	if ((sc->xl_flags & XL_FLAG_WOL) == 0)
3277 		return;
3278 
3279 	ifp = sc->xl_ifp;
3280 	XL_SEL_WIN(7);
3281 	/* Clear any pending PME events. */
3282 	CSR_READ_2(sc, XL_W7_BM_PME);
3283 	cfg = 0;
3284 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3285 		cfg |= XL_BM_PME_MAGIC;
3286 	CSR_WRITE_2(sc, XL_W7_BM_PME, cfg);
3287 	/* Enable RX. */
3288 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3289 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3290 	/* Request PME. */
3291 	pmstat = pci_read_config(sc->xl_dev,
3292 	    sc->xl_pmcap + PCIR_POWER_STATUS, 2);
3293 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3294 		pmstat |= PCIM_PSTAT_PMEENABLE;
3295 	else
3296 		pmstat &= ~PCIM_PSTAT_PMEENABLE;
3297 	pci_write_config(sc->xl_dev,
3298 	    sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2);
3299 }
3300