1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 /* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 */ 100 101 #ifdef HAVE_KERNEL_OPTION_HEADERS 102 #include "opt_device_polling.h" 103 #endif 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/sockio.h> 108 #include <sys/endian.h> 109 #include <sys/mbuf.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/taskqueue.h> 114 115 #include <net/if.h> 116 #include <net/if_arp.h> 117 #include <net/ethernet.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 #include <net/if_types.h> 121 122 #include <net/bpf.h> 123 124 #include <machine/bus.h> 125 #include <machine/resource.h> 126 #include <sys/bus.h> 127 #include <sys/rman.h> 128 129 #include <dev/mii/mii.h> 130 #include <dev/mii/miivar.h> 131 132 #include <dev/pci/pcireg.h> 133 #include <dev/pci/pcivar.h> 134 135 MODULE_DEPEND(xl, pci, 1, 1, 1); 136 MODULE_DEPEND(xl, ether, 1, 1, 1); 137 MODULE_DEPEND(xl, miibus, 1, 1, 1); 138 139 /* "device miibus" required. See GENERIC if you get errors here. */ 140 #include "miibus_if.h" 141 142 #include <dev/xl/if_xlreg.h> 143 144 /* 145 * TX Checksumming is disabled by default for two reasons: 146 * - TX Checksumming will occasionally produce corrupt packets 147 * - TX Checksumming seems to reduce performance 148 * 149 * Only 905B/C cards were reported to have this problem, it is possible 150 * that later chips _may_ be immune. 151 */ 152 #define XL905B_TXCSUM_BROKEN 1 153 154 #ifdef XL905B_TXCSUM_BROKEN 155 #define XL905B_CSUM_FEATURES 0 156 #else 157 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 #endif 159 160 /* 161 * Various supported device vendors/types and their names. 162 */ 163 static const struct xl_type xl_devs[] = { 164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 165 "3Com 3c900-TPO Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 167 "3Com 3c900-COMBO Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 169 "3Com 3c905-TX Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 171 "3Com 3c905-T4 Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 173 "3Com 3c900B-TPO Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 175 "3Com 3c900B-COMBO Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 177 "3Com 3c900B-TPC Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 179 "3Com 3c900B-FL Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 181 "3Com 3c905B-TX Fast Etherlink XL" }, 182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 183 "3Com 3c905B-T4 Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 185 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 187 "3Com 3c905B-COMBO Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 189 "3Com 3c905C-TX Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 191 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 193 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 195 "3Com 3c980 Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 197 "3Com 3c980C Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 199 "3Com 3cSOHO100-TX OfficeConnect" }, 200 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 201 "3Com 3c450-TX HomeConnect" }, 202 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 203 "3Com 3c555 Fast Etherlink XL" }, 204 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 205 "3Com 3c556 Fast Etherlink XL" }, 206 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 207 "3Com 3c556B Fast Etherlink XL" }, 208 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 209 "3Com 3c575TX Fast Etherlink XL" }, 210 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 211 "3Com 3c575B Fast Etherlink XL" }, 212 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 213 "3Com 3c575C Fast Etherlink XL" }, 214 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 215 "3Com 3c656 Fast Etherlink XL" }, 216 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 217 "3Com 3c656B Fast Etherlink XL" }, 218 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 219 "3Com 3c656C Fast Etherlink XL" }, 220 { 0, 0, NULL } 221 }; 222 223 static int xl_probe(device_t); 224 static int xl_attach(device_t); 225 static int xl_detach(device_t); 226 227 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 228 static void xl_stats_update(void *); 229 static void xl_stats_update_locked(struct xl_softc *); 230 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); 231 static int xl_rxeof(struct xl_softc *); 232 static void xl_rxeof_task(void *, int); 233 static int xl_rx_resync(struct xl_softc *); 234 static void xl_txeof(struct xl_softc *); 235 static void xl_txeof_90xB(struct xl_softc *); 236 static void xl_txeoc(struct xl_softc *); 237 static void xl_intr(void *); 238 static void xl_start(struct ifnet *); 239 static void xl_start_locked(struct ifnet *); 240 static void xl_start_90xB_locked(struct ifnet *); 241 static int xl_ioctl(struct ifnet *, u_long, caddr_t); 242 static void xl_init(void *); 243 static void xl_init_locked(struct xl_softc *); 244 static void xl_stop(struct xl_softc *); 245 static int xl_watchdog(struct xl_softc *); 246 static int xl_shutdown(device_t); 247 static int xl_suspend(device_t); 248 static int xl_resume(device_t); 249 static void xl_setwol(struct xl_softc *); 250 251 #ifdef DEVICE_POLLING 252 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 253 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 254 #endif 255 256 static int xl_ifmedia_upd(struct ifnet *); 257 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 258 259 static int xl_eeprom_wait(struct xl_softc *); 260 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 261 static void xl_mii_sync(struct xl_softc *); 262 static void xl_mii_send(struct xl_softc *, u_int32_t, int); 263 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *); 264 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *); 265 266 static void xl_setcfg(struct xl_softc *); 267 static void xl_setmode(struct xl_softc *, int); 268 static void xl_setmulti(struct xl_softc *); 269 static void xl_setmulti_hash(struct xl_softc *); 270 static void xl_reset(struct xl_softc *); 271 static int xl_list_rx_init(struct xl_softc *); 272 static int xl_list_tx_init(struct xl_softc *); 273 static int xl_list_tx_init_90xB(struct xl_softc *); 274 static void xl_wait(struct xl_softc *); 275 static void xl_mediacheck(struct xl_softc *); 276 static void xl_choose_media(struct xl_softc *sc, int *media); 277 static void xl_choose_xcvr(struct xl_softc *, int); 278 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 279 #ifdef notdef 280 static void xl_testpacket(struct xl_softc *); 281 #endif 282 283 static int xl_miibus_readreg(device_t, int, int); 284 static int xl_miibus_writereg(device_t, int, int, int); 285 static void xl_miibus_statchg(device_t); 286 static void xl_miibus_mediainit(device_t); 287 288 static device_method_t xl_methods[] = { 289 /* Device interface */ 290 DEVMETHOD(device_probe, xl_probe), 291 DEVMETHOD(device_attach, xl_attach), 292 DEVMETHOD(device_detach, xl_detach), 293 DEVMETHOD(device_shutdown, xl_shutdown), 294 DEVMETHOD(device_suspend, xl_suspend), 295 DEVMETHOD(device_resume, xl_resume), 296 297 /* bus interface */ 298 DEVMETHOD(bus_print_child, bus_generic_print_child), 299 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 300 301 /* MII interface */ 302 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 303 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 304 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 305 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 306 307 { 0, 0 } 308 }; 309 310 static driver_t xl_driver = { 311 "xl", 312 xl_methods, 313 sizeof(struct xl_softc) 314 }; 315 316 static devclass_t xl_devclass; 317 318 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0); 319 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 320 321 static void 322 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 323 { 324 u_int32_t *paddr; 325 326 paddr = arg; 327 *paddr = segs->ds_addr; 328 } 329 330 /* 331 * Murphy's law says that it's possible the chip can wedge and 332 * the 'command in progress' bit may never clear. Hence, we wait 333 * only a finite amount of time to avoid getting caught in an 334 * infinite loop. Normally this delay routine would be a macro, 335 * but it isn't called during normal operation so we can afford 336 * to make it a function. 337 */ 338 static void 339 xl_wait(struct xl_softc *sc) 340 { 341 register int i; 342 343 for (i = 0; i < XL_TIMEOUT; i++) { 344 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 345 break; 346 } 347 348 if (i == XL_TIMEOUT) 349 device_printf(sc->xl_dev, "command never completed!\n"); 350 } 351 352 /* 353 * MII access routines are provided for adapters with external 354 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 355 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 356 * Note: if you don't perform the MDIO operations just right, 357 * it's possible to end up with code that works correctly with 358 * some chips/CPUs/processor speeds/bus speeds/etc but not 359 * with others. 360 */ 361 #define MII_SET(x) \ 362 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 363 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 364 365 #define MII_CLR(x) \ 366 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 367 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 368 369 /* 370 * Sync the PHYs by setting data bit and strobing the clock 32 times. 371 */ 372 static void 373 xl_mii_sync(struct xl_softc *sc) 374 { 375 register int i; 376 377 XL_SEL_WIN(4); 378 MII_SET(XL_MII_DIR|XL_MII_DATA); 379 380 for (i = 0; i < 32; i++) { 381 MII_SET(XL_MII_CLK); 382 MII_SET(XL_MII_DATA); 383 MII_SET(XL_MII_DATA); 384 MII_CLR(XL_MII_CLK); 385 MII_SET(XL_MII_DATA); 386 MII_SET(XL_MII_DATA); 387 } 388 } 389 390 /* 391 * Clock a series of bits through the MII. 392 */ 393 static void 394 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 395 { 396 int i; 397 398 XL_SEL_WIN(4); 399 MII_CLR(XL_MII_CLK); 400 401 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 402 if (bits & i) { 403 MII_SET(XL_MII_DATA); 404 } else { 405 MII_CLR(XL_MII_DATA); 406 } 407 MII_CLR(XL_MII_CLK); 408 MII_SET(XL_MII_CLK); 409 } 410 } 411 412 /* 413 * Read an PHY register through the MII. 414 */ 415 static int 416 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 417 { 418 int i, ack; 419 420 /* Set up frame for RX. */ 421 frame->mii_stdelim = XL_MII_STARTDELIM; 422 frame->mii_opcode = XL_MII_READOP; 423 frame->mii_turnaround = 0; 424 frame->mii_data = 0; 425 426 /* Select register window 4. */ 427 XL_SEL_WIN(4); 428 429 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 430 /* Turn on data xmit. */ 431 MII_SET(XL_MII_DIR); 432 433 xl_mii_sync(sc); 434 435 /* Send command/address info. */ 436 xl_mii_send(sc, frame->mii_stdelim, 2); 437 xl_mii_send(sc, frame->mii_opcode, 2); 438 xl_mii_send(sc, frame->mii_phyaddr, 5); 439 xl_mii_send(sc, frame->mii_regaddr, 5); 440 441 /* Idle bit */ 442 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 443 MII_SET(XL_MII_CLK); 444 445 /* Turn off xmit. */ 446 MII_CLR(XL_MII_DIR); 447 448 /* Check for ack */ 449 MII_CLR(XL_MII_CLK); 450 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 451 MII_SET(XL_MII_CLK); 452 453 /* 454 * Now try reading data bits. If the ack failed, we still 455 * need to clock through 16 cycles to keep the PHY(s) in sync. 456 */ 457 if (ack) { 458 for (i = 0; i < 16; i++) { 459 MII_CLR(XL_MII_CLK); 460 MII_SET(XL_MII_CLK); 461 } 462 goto fail; 463 } 464 465 for (i = 0x8000; i; i >>= 1) { 466 MII_CLR(XL_MII_CLK); 467 if (!ack) { 468 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 469 frame->mii_data |= i; 470 } 471 MII_SET(XL_MII_CLK); 472 } 473 474 fail: 475 MII_CLR(XL_MII_CLK); 476 MII_SET(XL_MII_CLK); 477 478 return (ack ? 1 : 0); 479 } 480 481 /* 482 * Write to a PHY register through the MII. 483 */ 484 static int 485 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 486 { 487 488 /* Set up frame for TX. */ 489 frame->mii_stdelim = XL_MII_STARTDELIM; 490 frame->mii_opcode = XL_MII_WRITEOP; 491 frame->mii_turnaround = XL_MII_TURNAROUND; 492 493 /* Select the window 4. */ 494 XL_SEL_WIN(4); 495 496 /* Turn on data output. */ 497 MII_SET(XL_MII_DIR); 498 499 xl_mii_sync(sc); 500 501 xl_mii_send(sc, frame->mii_stdelim, 2); 502 xl_mii_send(sc, frame->mii_opcode, 2); 503 xl_mii_send(sc, frame->mii_phyaddr, 5); 504 xl_mii_send(sc, frame->mii_regaddr, 5); 505 xl_mii_send(sc, frame->mii_turnaround, 2); 506 xl_mii_send(sc, frame->mii_data, 16); 507 508 /* Idle bit. */ 509 MII_SET(XL_MII_CLK); 510 MII_CLR(XL_MII_CLK); 511 512 /* Turn off xmit. */ 513 MII_CLR(XL_MII_DIR); 514 515 return (0); 516 } 517 518 static int 519 xl_miibus_readreg(device_t dev, int phy, int reg) 520 { 521 struct xl_softc *sc; 522 struct xl_mii_frame frame; 523 524 sc = device_get_softc(dev); 525 526 /* 527 * Pretend that PHYs are only available at MII address 24. 528 * This is to guard against problems with certain 3Com ASIC 529 * revisions that incorrectly map the internal transceiver 530 * control registers at all MII addresses. This can cause 531 * the miibus code to attach the same PHY several times over. 532 */ 533 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) 534 return (0); 535 536 bzero((char *)&frame, sizeof(frame)); 537 frame.mii_phyaddr = phy; 538 frame.mii_regaddr = reg; 539 540 xl_mii_readreg(sc, &frame); 541 542 return (frame.mii_data); 543 } 544 545 static int 546 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 547 { 548 struct xl_softc *sc; 549 struct xl_mii_frame frame; 550 551 sc = device_get_softc(dev); 552 553 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) 554 return (0); 555 556 bzero((char *)&frame, sizeof(frame)); 557 frame.mii_phyaddr = phy; 558 frame.mii_regaddr = reg; 559 frame.mii_data = data; 560 561 xl_mii_writereg(sc, &frame); 562 563 return (0); 564 } 565 566 static void 567 xl_miibus_statchg(device_t dev) 568 { 569 struct xl_softc *sc; 570 struct mii_data *mii; 571 572 sc = device_get_softc(dev); 573 mii = device_get_softc(sc->xl_miibus); 574 575 xl_setcfg(sc); 576 577 /* Set ASIC's duplex mode to match the PHY. */ 578 XL_SEL_WIN(3); 579 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 580 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 581 else 582 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 583 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 584 } 585 586 /* 587 * Special support for the 3c905B-COMBO. This card has 10/100 support 588 * plus BNC and AUI ports. This means we will have both an miibus attached 589 * plus some non-MII media settings. In order to allow this, we have to 590 * add the extra media to the miibus's ifmedia struct, but we can't do 591 * that during xl_attach() because the miibus hasn't been attached yet. 592 * So instead, we wait until the miibus probe/attach is done, at which 593 * point we will get a callback telling is that it's safe to add our 594 * extra media. 595 */ 596 static void 597 xl_miibus_mediainit(device_t dev) 598 { 599 struct xl_softc *sc; 600 struct mii_data *mii; 601 struct ifmedia *ifm; 602 603 sc = device_get_softc(dev); 604 mii = device_get_softc(sc->xl_miibus); 605 ifm = &mii->mii_media; 606 607 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 608 /* 609 * Check for a 10baseFL board in disguise. 610 */ 611 if (sc->xl_type == XL_TYPE_905B && 612 sc->xl_media == XL_MEDIAOPT_10FL) { 613 if (bootverbose) 614 device_printf(sc->xl_dev, "found 10baseFL\n"); 615 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 616 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 617 NULL); 618 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 619 ifmedia_add(ifm, 620 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 621 } else { 622 if (bootverbose) 623 device_printf(sc->xl_dev, "found AUI\n"); 624 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 625 } 626 } 627 628 if (sc->xl_media & XL_MEDIAOPT_BNC) { 629 if (bootverbose) 630 device_printf(sc->xl_dev, "found BNC\n"); 631 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 632 } 633 } 634 635 /* 636 * The EEPROM is slow: give it time to come ready after issuing 637 * it a command. 638 */ 639 static int 640 xl_eeprom_wait(struct xl_softc *sc) 641 { 642 int i; 643 644 for (i = 0; i < 100; i++) { 645 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 646 DELAY(162); 647 else 648 break; 649 } 650 651 if (i == 100) { 652 device_printf(sc->xl_dev, "eeprom failed to come ready\n"); 653 return (1); 654 } 655 656 return (0); 657 } 658 659 /* 660 * Read a sequence of words from the EEPROM. Note that ethernet address 661 * data is stored in the EEPROM in network byte order. 662 */ 663 static int 664 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 665 { 666 int err = 0, i; 667 u_int16_t word = 0, *ptr; 668 669 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 670 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 671 /* 672 * XXX: WARNING! DANGER! 673 * It's easy to accidentally overwrite the rom content! 674 * Note: the 3c575 uses 8bit EEPROM offsets. 675 */ 676 XL_SEL_WIN(0); 677 678 if (xl_eeprom_wait(sc)) 679 return (1); 680 681 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 682 off += 0x30; 683 684 for (i = 0; i < cnt; i++) { 685 if (sc->xl_flags & XL_FLAG_8BITROM) 686 CSR_WRITE_2(sc, XL_W0_EE_CMD, 687 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 688 else 689 CSR_WRITE_2(sc, XL_W0_EE_CMD, 690 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 691 err = xl_eeprom_wait(sc); 692 if (err) 693 break; 694 word = CSR_READ_2(sc, XL_W0_EE_DATA); 695 ptr = (u_int16_t *)(dest + (i * 2)); 696 if (swap) 697 *ptr = ntohs(word); 698 else 699 *ptr = word; 700 } 701 702 return (err ? 1 : 0); 703 } 704 705 /* 706 * NICs older than the 3c905B have only one multicast option, which 707 * is to enable reception of all multicast frames. 708 */ 709 static void 710 xl_setmulti(struct xl_softc *sc) 711 { 712 struct ifnet *ifp = sc->xl_ifp; 713 struct ifmultiaddr *ifma; 714 u_int8_t rxfilt; 715 int mcnt = 0; 716 717 XL_LOCK_ASSERT(sc); 718 719 XL_SEL_WIN(5); 720 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 721 722 if (ifp->if_flags & IFF_ALLMULTI) { 723 rxfilt |= XL_RXFILTER_ALLMULTI; 724 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 725 return; 726 } 727 728 if_maddr_rlock(ifp); 729 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 730 mcnt++; 731 if_maddr_runlock(ifp); 732 733 if (mcnt) 734 rxfilt |= XL_RXFILTER_ALLMULTI; 735 else 736 rxfilt &= ~XL_RXFILTER_ALLMULTI; 737 738 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 739 } 740 741 /* 742 * 3c905B adapters have a hash filter that we can program. 743 */ 744 static void 745 xl_setmulti_hash(struct xl_softc *sc) 746 { 747 struct ifnet *ifp = sc->xl_ifp; 748 int h = 0, i; 749 struct ifmultiaddr *ifma; 750 u_int8_t rxfilt; 751 int mcnt = 0; 752 753 XL_LOCK_ASSERT(sc); 754 755 XL_SEL_WIN(5); 756 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 757 758 if (ifp->if_flags & IFF_ALLMULTI) { 759 rxfilt |= XL_RXFILTER_ALLMULTI; 760 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 761 return; 762 } else 763 rxfilt &= ~XL_RXFILTER_ALLMULTI; 764 765 /* first, zot all the existing hash bits */ 766 for (i = 0; i < XL_HASHFILT_SIZE; i++) 767 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 768 769 /* now program new ones */ 770 if_maddr_rlock(ifp); 771 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 772 if (ifma->ifma_addr->sa_family != AF_LINK) 773 continue; 774 /* 775 * Note: the 3c905B currently only supports a 64-bit hash 776 * table, which means we really only need 6 bits, but the 777 * manual indicates that future chip revisions will have a 778 * 256-bit hash table, hence the routine is set up to 779 * calculate 8 bits of position info in case we need it some 780 * day. 781 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have 782 * a 256 bit hash table. This means we have to use all 8 bits 783 * regardless. On older cards, the upper 2 bits will be 784 * ignored. Grrrr.... 785 */ 786 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 787 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 788 CSR_WRITE_2(sc, XL_COMMAND, 789 h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 790 mcnt++; 791 } 792 if_maddr_runlock(ifp); 793 794 if (mcnt) 795 rxfilt |= XL_RXFILTER_MULTIHASH; 796 else 797 rxfilt &= ~XL_RXFILTER_MULTIHASH; 798 799 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 800 } 801 802 static void 803 xl_setcfg(struct xl_softc *sc) 804 { 805 u_int32_t icfg; 806 807 /*XL_LOCK_ASSERT(sc);*/ 808 809 XL_SEL_WIN(3); 810 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 811 icfg &= ~XL_ICFG_CONNECTOR_MASK; 812 if (sc->xl_media & XL_MEDIAOPT_MII || 813 sc->xl_media & XL_MEDIAOPT_BT4) 814 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 815 if (sc->xl_media & XL_MEDIAOPT_BTX) 816 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 817 818 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 819 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 820 } 821 822 static void 823 xl_setmode(struct xl_softc *sc, int media) 824 { 825 u_int32_t icfg; 826 u_int16_t mediastat; 827 char *pmsg = "", *dmsg = ""; 828 829 XL_LOCK_ASSERT(sc); 830 831 XL_SEL_WIN(4); 832 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 833 XL_SEL_WIN(3); 834 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 835 836 if (sc->xl_media & XL_MEDIAOPT_BT) { 837 if (IFM_SUBTYPE(media) == IFM_10_T) { 838 pmsg = "10baseT transceiver"; 839 sc->xl_xcvr = XL_XCVR_10BT; 840 icfg &= ~XL_ICFG_CONNECTOR_MASK; 841 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 842 mediastat |= XL_MEDIASTAT_LINKBEAT | 843 XL_MEDIASTAT_JABGUARD; 844 mediastat &= ~XL_MEDIASTAT_SQEENB; 845 } 846 } 847 848 if (sc->xl_media & XL_MEDIAOPT_BFX) { 849 if (IFM_SUBTYPE(media) == IFM_100_FX) { 850 pmsg = "100baseFX port"; 851 sc->xl_xcvr = XL_XCVR_100BFX; 852 icfg &= ~XL_ICFG_CONNECTOR_MASK; 853 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 854 mediastat |= XL_MEDIASTAT_LINKBEAT; 855 mediastat &= ~XL_MEDIASTAT_SQEENB; 856 } 857 } 858 859 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 860 if (IFM_SUBTYPE(media) == IFM_10_5) { 861 pmsg = "AUI port"; 862 sc->xl_xcvr = XL_XCVR_AUI; 863 icfg &= ~XL_ICFG_CONNECTOR_MASK; 864 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 865 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 866 XL_MEDIASTAT_JABGUARD); 867 mediastat |= ~XL_MEDIASTAT_SQEENB; 868 } 869 if (IFM_SUBTYPE(media) == IFM_10_FL) { 870 pmsg = "10baseFL transceiver"; 871 sc->xl_xcvr = XL_XCVR_AUI; 872 icfg &= ~XL_ICFG_CONNECTOR_MASK; 873 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 874 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 875 XL_MEDIASTAT_JABGUARD); 876 mediastat |= ~XL_MEDIASTAT_SQEENB; 877 } 878 } 879 880 if (sc->xl_media & XL_MEDIAOPT_BNC) { 881 if (IFM_SUBTYPE(media) == IFM_10_2) { 882 pmsg = "AUI port"; 883 sc->xl_xcvr = XL_XCVR_COAX; 884 icfg &= ~XL_ICFG_CONNECTOR_MASK; 885 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 886 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 887 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 888 } 889 } 890 891 if ((media & IFM_GMASK) == IFM_FDX || 892 IFM_SUBTYPE(media) == IFM_100_FX) { 893 dmsg = "full"; 894 XL_SEL_WIN(3); 895 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 896 } else { 897 dmsg = "half"; 898 XL_SEL_WIN(3); 899 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 900 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 901 } 902 903 if (IFM_SUBTYPE(media) == IFM_10_2) 904 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 905 else 906 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 907 908 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 909 XL_SEL_WIN(4); 910 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 911 912 DELAY(800); 913 XL_SEL_WIN(7); 914 915 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg); 916 } 917 918 static void 919 xl_reset(struct xl_softc *sc) 920 { 921 register int i; 922 923 XL_LOCK_ASSERT(sc); 924 925 XL_SEL_WIN(0); 926 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 927 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 928 XL_RESETOPT_DISADVFD:0)); 929 930 /* 931 * If we're using memory mapped register mode, pause briefly 932 * after issuing the reset command before trying to access any 933 * other registers. With my 3c575C CardBus card, failing to do 934 * this results in the system locking up while trying to poll 935 * the command busy bit in the status register. 936 */ 937 if (sc->xl_flags & XL_FLAG_USE_MMIO) 938 DELAY(100000); 939 940 for (i = 0; i < XL_TIMEOUT; i++) { 941 DELAY(10); 942 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 943 break; 944 } 945 946 if (i == XL_TIMEOUT) 947 device_printf(sc->xl_dev, "reset didn't complete\n"); 948 949 /* Reset TX and RX. */ 950 /* Note: the RX reset takes an absurd amount of time 951 * on newer versions of the Tornado chips such as those 952 * on the 3c905CX and newer 3c908C cards. We wait an 953 * extra amount of time so that xl_wait() doesn't complain 954 * and annoy the users. 955 */ 956 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 957 DELAY(100000); 958 xl_wait(sc); 959 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 960 xl_wait(sc); 961 962 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 963 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 964 XL_SEL_WIN(2); 965 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 966 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 967 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 968 XL_RESETOPT_INVERT_LED : 0) | 969 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 970 XL_RESETOPT_INVERT_MII : 0)); 971 } 972 973 /* Wait a little while for the chip to get its brains in order. */ 974 DELAY(100000); 975 } 976 977 /* 978 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 979 * IDs against our list and return a device name if we find a match. 980 */ 981 static int 982 xl_probe(device_t dev) 983 { 984 const struct xl_type *t; 985 986 t = xl_devs; 987 988 while (t->xl_name != NULL) { 989 if ((pci_get_vendor(dev) == t->xl_vid) && 990 (pci_get_device(dev) == t->xl_did)) { 991 device_set_desc(dev, t->xl_name); 992 return (BUS_PROBE_DEFAULT); 993 } 994 t++; 995 } 996 997 return (ENXIO); 998 } 999 1000 /* 1001 * This routine is a kludge to work around possible hardware faults 1002 * or manufacturing defects that can cause the media options register 1003 * (or reset options register, as it's called for the first generation 1004 * 3c90x adapters) to return an incorrect result. I have encountered 1005 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1006 * which doesn't have any of the 'mediaopt' bits set. This screws up 1007 * the attach routine pretty badly because it doesn't know what media 1008 * to look for. If we find ourselves in this predicament, this routine 1009 * will try to guess the media options values and warn the user of a 1010 * possible manufacturing defect with his adapter/system/whatever. 1011 */ 1012 static void 1013 xl_mediacheck(struct xl_softc *sc) 1014 { 1015 1016 /* 1017 * If some of the media options bits are set, assume they are 1018 * correct. If not, try to figure it out down below. 1019 * XXX I should check for 10baseFL, but I don't have an adapter 1020 * to test with. 1021 */ 1022 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1023 /* 1024 * Check the XCVR value. If it's not in the normal range 1025 * of values, we need to fake it up here. 1026 */ 1027 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1028 return; 1029 else { 1030 device_printf(sc->xl_dev, 1031 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 1032 device_printf(sc->xl_dev, 1033 "choosing new default based on card type\n"); 1034 } 1035 } else { 1036 if (sc->xl_type == XL_TYPE_905B && 1037 sc->xl_media & XL_MEDIAOPT_10FL) 1038 return; 1039 device_printf(sc->xl_dev, 1040 "WARNING: no media options bits set in the media options register!!\n"); 1041 device_printf(sc->xl_dev, 1042 "this could be a manufacturing defect in your adapter or system\n"); 1043 device_printf(sc->xl_dev, 1044 "attempting to guess media type; you should probably consult your vendor\n"); 1045 } 1046 1047 xl_choose_xcvr(sc, 1); 1048 } 1049 1050 static void 1051 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1052 { 1053 u_int16_t devid; 1054 1055 /* 1056 * Read the device ID from the EEPROM. 1057 * This is what's loaded into the PCI device ID register, so it has 1058 * to be correct otherwise we wouldn't have gotten this far. 1059 */ 1060 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1061 1062 switch (devid) { 1063 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1064 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1065 sc->xl_media = XL_MEDIAOPT_BT; 1066 sc->xl_xcvr = XL_XCVR_10BT; 1067 if (verbose) 1068 device_printf(sc->xl_dev, 1069 "guessing 10BaseT transceiver\n"); 1070 break; 1071 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1072 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1073 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1074 sc->xl_xcvr = XL_XCVR_10BT; 1075 if (verbose) 1076 device_printf(sc->xl_dev, 1077 "guessing COMBO (AUI/BNC/TP)\n"); 1078 break; 1079 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1080 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1081 sc->xl_xcvr = XL_XCVR_10BT; 1082 if (verbose) 1083 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n"); 1084 break; 1085 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1086 sc->xl_media = XL_MEDIAOPT_10FL; 1087 sc->xl_xcvr = XL_XCVR_AUI; 1088 if (verbose) 1089 device_printf(sc->xl_dev, "guessing 10baseFL\n"); 1090 break; 1091 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1092 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1093 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1094 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1095 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1096 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1097 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1098 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1099 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1100 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1101 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1102 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1103 sc->xl_media = XL_MEDIAOPT_MII; 1104 sc->xl_xcvr = XL_XCVR_MII; 1105 if (verbose) 1106 device_printf(sc->xl_dev, "guessing MII\n"); 1107 break; 1108 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1109 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1110 sc->xl_media = XL_MEDIAOPT_BT4; 1111 sc->xl_xcvr = XL_XCVR_MII; 1112 if (verbose) 1113 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n"); 1114 break; 1115 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1116 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1117 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1118 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1119 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1120 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1121 sc->xl_media = XL_MEDIAOPT_BTX; 1122 sc->xl_xcvr = XL_XCVR_AUTO; 1123 if (verbose) 1124 device_printf(sc->xl_dev, "guessing 10/100 internal\n"); 1125 break; 1126 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1127 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1128 sc->xl_xcvr = XL_XCVR_AUTO; 1129 if (verbose) 1130 device_printf(sc->xl_dev, 1131 "guessing 10/100 plus BNC/AUI\n"); 1132 break; 1133 default: 1134 device_printf(sc->xl_dev, 1135 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1136 sc->xl_media = XL_MEDIAOPT_BT; 1137 break; 1138 } 1139 } 1140 1141 /* 1142 * Attach the interface. Allocate softc structures, do ifmedia 1143 * setup and ethernet/BPF attach. 1144 */ 1145 static int 1146 xl_attach(device_t dev) 1147 { 1148 u_char eaddr[ETHER_ADDR_LEN]; 1149 u_int16_t sinfo2, xcvr[2]; 1150 struct xl_softc *sc; 1151 struct ifnet *ifp; 1152 int media, pmcap; 1153 int unit, error = 0, rid, res; 1154 uint16_t did; 1155 1156 sc = device_get_softc(dev); 1157 sc->xl_dev = dev; 1158 1159 unit = device_get_unit(dev); 1160 1161 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1162 MTX_DEF); 1163 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1164 1165 did = pci_get_device(dev); 1166 1167 sc->xl_flags = 0; 1168 if (did == TC_DEVICEID_HURRICANE_555) 1169 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1170 if (did == TC_DEVICEID_HURRICANE_556 || 1171 did == TC_DEVICEID_HURRICANE_556B) 1172 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1173 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1174 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1175 if (did == TC_DEVICEID_HURRICANE_555 || 1176 did == TC_DEVICEID_HURRICANE_556) 1177 sc->xl_flags |= XL_FLAG_8BITROM; 1178 if (did == TC_DEVICEID_HURRICANE_556B) 1179 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1180 1181 if (did == TC_DEVICEID_HURRICANE_575B || 1182 did == TC_DEVICEID_HURRICANE_575C || 1183 did == TC_DEVICEID_HURRICANE_656B || 1184 did == TC_DEVICEID_TORNADO_656C) 1185 sc->xl_flags |= XL_FLAG_FUNCREG; 1186 if (did == TC_DEVICEID_HURRICANE_575A || 1187 did == TC_DEVICEID_HURRICANE_575B || 1188 did == TC_DEVICEID_HURRICANE_575C || 1189 did == TC_DEVICEID_HURRICANE_656B || 1190 did == TC_DEVICEID_TORNADO_656C) 1191 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1192 XL_FLAG_8BITROM; 1193 if (did == TC_DEVICEID_HURRICANE_656) 1194 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1195 if (did == TC_DEVICEID_HURRICANE_575B) 1196 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1197 if (did == TC_DEVICEID_HURRICANE_575C) 1198 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1199 if (did == TC_DEVICEID_TORNADO_656C) 1200 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1201 if (did == TC_DEVICEID_HURRICANE_656 || 1202 did == TC_DEVICEID_HURRICANE_656B) 1203 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1204 XL_FLAG_INVERT_LED_PWR; 1205 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1206 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1207 sc->xl_flags |= XL_FLAG_PHYOK; 1208 1209 switch (did) { 1210 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1211 case TC_DEVICEID_HURRICANE_575A: 1212 case TC_DEVICEID_HURRICANE_575B: 1213 case TC_DEVICEID_HURRICANE_575C: 1214 sc->xl_flags |= XL_FLAG_NO_MMIO; 1215 break; 1216 default: 1217 break; 1218 } 1219 1220 /* 1221 * Map control/status registers. 1222 */ 1223 pci_enable_busmaster(dev); 1224 1225 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1226 rid = XL_PCI_LOMEM; 1227 res = SYS_RES_MEMORY; 1228 1229 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1230 } 1231 1232 if (sc->xl_res != NULL) { 1233 sc->xl_flags |= XL_FLAG_USE_MMIO; 1234 if (bootverbose) 1235 device_printf(dev, "using memory mapped I/O\n"); 1236 } else { 1237 rid = XL_PCI_LOIO; 1238 res = SYS_RES_IOPORT; 1239 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1240 if (sc->xl_res == NULL) { 1241 device_printf(dev, "couldn't map ports/memory\n"); 1242 error = ENXIO; 1243 goto fail; 1244 } 1245 if (bootverbose) 1246 device_printf(dev, "using port I/O\n"); 1247 } 1248 1249 sc->xl_btag = rman_get_bustag(sc->xl_res); 1250 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1251 1252 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1253 rid = XL_PCI_FUNCMEM; 1254 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1255 RF_ACTIVE); 1256 1257 if (sc->xl_fres == NULL) { 1258 device_printf(dev, "couldn't map funcreg memory\n"); 1259 error = ENXIO; 1260 goto fail; 1261 } 1262 1263 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1264 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1265 } 1266 1267 /* Allocate interrupt */ 1268 rid = 0; 1269 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1270 RF_SHAREABLE | RF_ACTIVE); 1271 if (sc->xl_irq == NULL) { 1272 device_printf(dev, "couldn't map interrupt\n"); 1273 error = ENXIO; 1274 goto fail; 1275 } 1276 1277 /* Initialize interface name. */ 1278 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1279 if (ifp == NULL) { 1280 device_printf(dev, "can not if_alloc()\n"); 1281 error = ENOSPC; 1282 goto fail; 1283 } 1284 ifp->if_softc = sc; 1285 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1286 1287 /* Reset the adapter. */ 1288 XL_LOCK(sc); 1289 xl_reset(sc); 1290 XL_UNLOCK(sc); 1291 1292 /* 1293 * Get station address from the EEPROM. 1294 */ 1295 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1296 device_printf(dev, "failed to read station address\n"); 1297 error = ENXIO; 1298 goto fail; 1299 } 1300 1301 callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0); 1302 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1303 1304 /* 1305 * Now allocate a tag for the DMA descriptor lists and a chunk 1306 * of DMA-able memory based on the tag. Also obtain the DMA 1307 * addresses of the RX and TX ring, which we'll need later. 1308 * All of our lists are allocated as a contiguous block 1309 * of memory. 1310 */ 1311 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1312 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1313 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1314 &sc->xl_ldata.xl_rx_tag); 1315 if (error) { 1316 device_printf(dev, "failed to allocate rx dma tag\n"); 1317 goto fail; 1318 } 1319 1320 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1321 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1322 &sc->xl_ldata.xl_rx_dmamap); 1323 if (error) { 1324 device_printf(dev, "no memory for rx list buffers!\n"); 1325 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1326 sc->xl_ldata.xl_rx_tag = NULL; 1327 goto fail; 1328 } 1329 1330 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1331 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1332 XL_RX_LIST_SZ, xl_dma_map_addr, 1333 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1334 if (error) { 1335 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1336 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1337 sc->xl_ldata.xl_rx_dmamap); 1338 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1339 sc->xl_ldata.xl_rx_tag = NULL; 1340 goto fail; 1341 } 1342 1343 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1344 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1345 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1346 &sc->xl_ldata.xl_tx_tag); 1347 if (error) { 1348 device_printf(dev, "failed to allocate tx dma tag\n"); 1349 goto fail; 1350 } 1351 1352 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1353 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1354 &sc->xl_ldata.xl_tx_dmamap); 1355 if (error) { 1356 device_printf(dev, "no memory for list buffers!\n"); 1357 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1358 sc->xl_ldata.xl_tx_tag = NULL; 1359 goto fail; 1360 } 1361 1362 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1363 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1364 XL_TX_LIST_SZ, xl_dma_map_addr, 1365 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1366 if (error) { 1367 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1368 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1369 sc->xl_ldata.xl_tx_dmamap); 1370 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1371 sc->xl_ldata.xl_tx_tag = NULL; 1372 goto fail; 1373 } 1374 1375 /* 1376 * Allocate a DMA tag for the mapping of mbufs. 1377 */ 1378 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1379 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1380 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1381 NULL, &sc->xl_mtag); 1382 if (error) { 1383 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1384 goto fail; 1385 } 1386 1387 /* We need a spare DMA map for the RX ring. */ 1388 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1389 if (error) 1390 goto fail; 1391 1392 /* 1393 * Figure out the card type. 3c905B adapters have the 1394 * 'supportsNoTxLength' bit set in the capabilities 1395 * word in the EEPROM. 1396 * Note: my 3c575C CardBus card lies. It returns a value 1397 * of 0x1578 for its capabilities word, which is somewhat 1398 * nonsensical. Another way to distinguish a 3c90x chip 1399 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1400 * bit. This will only be set for 3c90x boomerage chips. 1401 */ 1402 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1403 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1404 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1405 sc->xl_type = XL_TYPE_905B; 1406 else 1407 sc->xl_type = XL_TYPE_90X; 1408 1409 /* Check availability of WOL. */ 1410 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 && 1411 pci_find_extcap(dev, PCIY_PMG, &pmcap) == 0) { 1412 sc->xl_pmcap = pmcap; 1413 sc->xl_flags |= XL_FLAG_WOL; 1414 sinfo2 = 0; 1415 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0); 1416 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose) 1417 device_printf(dev, 1418 "No auxiliary remote wakeup connector!\n"); 1419 } 1420 1421 /* Set the TX start threshold for best performance. */ 1422 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1423 1424 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1425 ifp->if_ioctl = xl_ioctl; 1426 ifp->if_capabilities = IFCAP_VLAN_MTU; 1427 if (sc->xl_type == XL_TYPE_905B) { 1428 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1429 #ifdef XL905B_TXCSUM_BROKEN 1430 ifp->if_capabilities |= IFCAP_RXCSUM; 1431 #else 1432 ifp->if_capabilities |= IFCAP_HWCSUM; 1433 #endif 1434 } 1435 if ((sc->xl_flags & XL_FLAG_WOL) != 0) 1436 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1437 ifp->if_capenable = ifp->if_capabilities; 1438 #ifdef DEVICE_POLLING 1439 ifp->if_capabilities |= IFCAP_POLLING; 1440 #endif 1441 ifp->if_start = xl_start; 1442 ifp->if_init = xl_init; 1443 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1444 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1; 1445 IFQ_SET_READY(&ifp->if_snd); 1446 1447 /* 1448 * Now we have to see what sort of media we have. 1449 * This includes probing for an MII interace and a 1450 * possible PHY. 1451 */ 1452 XL_SEL_WIN(3); 1453 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1454 if (bootverbose) 1455 device_printf(dev, "media options word: %x\n", sc->xl_media); 1456 1457 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1458 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1459 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1460 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1461 1462 xl_mediacheck(sc); 1463 1464 if (sc->xl_media & XL_MEDIAOPT_MII || 1465 sc->xl_media & XL_MEDIAOPT_BTX || 1466 sc->xl_media & XL_MEDIAOPT_BT4) { 1467 if (bootverbose) 1468 device_printf(dev, "found MII/AUTO\n"); 1469 xl_setcfg(sc); 1470 if (mii_phy_probe(dev, &sc->xl_miibus, 1471 xl_ifmedia_upd, xl_ifmedia_sts)) { 1472 device_printf(dev, "no PHY found!\n"); 1473 error = ENXIO; 1474 goto fail; 1475 } 1476 goto done; 1477 } 1478 1479 /* 1480 * Sanity check. If the user has selected "auto" and this isn't 1481 * a 10/100 card of some kind, we need to force the transceiver 1482 * type to something sane. 1483 */ 1484 if (sc->xl_xcvr == XL_XCVR_AUTO) 1485 xl_choose_xcvr(sc, bootverbose); 1486 1487 /* 1488 * Do ifmedia setup. 1489 */ 1490 if (sc->xl_media & XL_MEDIAOPT_BT) { 1491 if (bootverbose) 1492 device_printf(dev, "found 10baseT\n"); 1493 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1494 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1495 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1496 ifmedia_add(&sc->ifmedia, 1497 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1498 } 1499 1500 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1501 /* 1502 * Check for a 10baseFL board in disguise. 1503 */ 1504 if (sc->xl_type == XL_TYPE_905B && 1505 sc->xl_media == XL_MEDIAOPT_10FL) { 1506 if (bootverbose) 1507 device_printf(dev, "found 10baseFL\n"); 1508 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1509 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1510 0, NULL); 1511 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1512 ifmedia_add(&sc->ifmedia, 1513 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1514 } else { 1515 if (bootverbose) 1516 device_printf(dev, "found AUI\n"); 1517 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1518 } 1519 } 1520 1521 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1522 if (bootverbose) 1523 device_printf(dev, "found BNC\n"); 1524 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1525 } 1526 1527 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1528 if (bootverbose) 1529 device_printf(dev, "found 100baseFX\n"); 1530 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1531 } 1532 1533 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1534 xl_choose_media(sc, &media); 1535 1536 if (sc->xl_miibus == NULL) 1537 ifmedia_set(&sc->ifmedia, media); 1538 1539 done: 1540 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1541 XL_SEL_WIN(0); 1542 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1543 } 1544 1545 /* 1546 * Call MI attach routine. 1547 */ 1548 ether_ifattach(ifp, eaddr); 1549 1550 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1551 NULL, xl_intr, sc, &sc->xl_intrhand); 1552 if (error) { 1553 device_printf(dev, "couldn't set up irq\n"); 1554 ether_ifdetach(ifp); 1555 goto fail; 1556 } 1557 1558 fail: 1559 if (error) 1560 xl_detach(dev); 1561 1562 return (error); 1563 } 1564 1565 /* 1566 * Choose a default media. 1567 * XXX This is a leaf function only called by xl_attach() and 1568 * acquires/releases the non-recursible driver mutex to 1569 * satisfy lock assertions. 1570 */ 1571 static void 1572 xl_choose_media(struct xl_softc *sc, int *media) 1573 { 1574 1575 XL_LOCK(sc); 1576 1577 switch (sc->xl_xcvr) { 1578 case XL_XCVR_10BT: 1579 *media = IFM_ETHER|IFM_10_T; 1580 xl_setmode(sc, *media); 1581 break; 1582 case XL_XCVR_AUI: 1583 if (sc->xl_type == XL_TYPE_905B && 1584 sc->xl_media == XL_MEDIAOPT_10FL) { 1585 *media = IFM_ETHER|IFM_10_FL; 1586 xl_setmode(sc, *media); 1587 } else { 1588 *media = IFM_ETHER|IFM_10_5; 1589 xl_setmode(sc, *media); 1590 } 1591 break; 1592 case XL_XCVR_COAX: 1593 *media = IFM_ETHER|IFM_10_2; 1594 xl_setmode(sc, *media); 1595 break; 1596 case XL_XCVR_AUTO: 1597 case XL_XCVR_100BTX: 1598 case XL_XCVR_MII: 1599 /* Chosen by miibus */ 1600 break; 1601 case XL_XCVR_100BFX: 1602 *media = IFM_ETHER|IFM_100_FX; 1603 break; 1604 default: 1605 device_printf(sc->xl_dev, "unknown XCVR type: %d\n", 1606 sc->xl_xcvr); 1607 /* 1608 * This will probably be wrong, but it prevents 1609 * the ifmedia code from panicking. 1610 */ 1611 *media = IFM_ETHER|IFM_10_T; 1612 break; 1613 } 1614 1615 XL_UNLOCK(sc); 1616 } 1617 1618 /* 1619 * Shutdown hardware and free up resources. This can be called any 1620 * time after the mutex has been initialized. It is called in both 1621 * the error case in attach and the normal detach case so it needs 1622 * to be careful about only freeing resources that have actually been 1623 * allocated. 1624 */ 1625 static int 1626 xl_detach(device_t dev) 1627 { 1628 struct xl_softc *sc; 1629 struct ifnet *ifp; 1630 int rid, res; 1631 1632 sc = device_get_softc(dev); 1633 ifp = sc->xl_ifp; 1634 1635 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1636 1637 #ifdef DEVICE_POLLING 1638 if (ifp && ifp->if_capenable & IFCAP_POLLING) 1639 ether_poll_deregister(ifp); 1640 #endif 1641 1642 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1643 rid = XL_PCI_LOMEM; 1644 res = SYS_RES_MEMORY; 1645 } else { 1646 rid = XL_PCI_LOIO; 1647 res = SYS_RES_IOPORT; 1648 } 1649 1650 /* These should only be active if attach succeeded */ 1651 if (device_is_attached(dev)) { 1652 XL_LOCK(sc); 1653 xl_stop(sc); 1654 XL_UNLOCK(sc); 1655 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1656 callout_drain(&sc->xl_stat_callout); 1657 ether_ifdetach(ifp); 1658 } 1659 if (sc->xl_miibus) 1660 device_delete_child(dev, sc->xl_miibus); 1661 bus_generic_detach(dev); 1662 ifmedia_removeall(&sc->ifmedia); 1663 1664 if (sc->xl_intrhand) 1665 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1666 if (sc->xl_irq) 1667 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1668 if (sc->xl_fres != NULL) 1669 bus_release_resource(dev, SYS_RES_MEMORY, 1670 XL_PCI_FUNCMEM, sc->xl_fres); 1671 if (sc->xl_res) 1672 bus_release_resource(dev, res, rid, sc->xl_res); 1673 1674 if (ifp) 1675 if_free(ifp); 1676 1677 if (sc->xl_mtag) { 1678 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1679 bus_dma_tag_destroy(sc->xl_mtag); 1680 } 1681 if (sc->xl_ldata.xl_rx_tag) { 1682 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1683 sc->xl_ldata.xl_rx_dmamap); 1684 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1685 sc->xl_ldata.xl_rx_dmamap); 1686 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1687 } 1688 if (sc->xl_ldata.xl_tx_tag) { 1689 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1690 sc->xl_ldata.xl_tx_dmamap); 1691 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1692 sc->xl_ldata.xl_tx_dmamap); 1693 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1694 } 1695 1696 mtx_destroy(&sc->xl_mtx); 1697 1698 return (0); 1699 } 1700 1701 /* 1702 * Initialize the transmit descriptors. 1703 */ 1704 static int 1705 xl_list_tx_init(struct xl_softc *sc) 1706 { 1707 struct xl_chain_data *cd; 1708 struct xl_list_data *ld; 1709 int error, i; 1710 1711 XL_LOCK_ASSERT(sc); 1712 1713 cd = &sc->xl_cdata; 1714 ld = &sc->xl_ldata; 1715 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1716 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1717 error = bus_dmamap_create(sc->xl_mtag, 0, 1718 &cd->xl_tx_chain[i].xl_map); 1719 if (error) 1720 return (error); 1721 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1722 i * sizeof(struct xl_list); 1723 if (i == (XL_TX_LIST_CNT - 1)) 1724 cd->xl_tx_chain[i].xl_next = NULL; 1725 else 1726 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1727 } 1728 1729 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1730 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1731 1732 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1733 return (0); 1734 } 1735 1736 /* 1737 * Initialize the transmit descriptors. 1738 */ 1739 static int 1740 xl_list_tx_init_90xB(struct xl_softc *sc) 1741 { 1742 struct xl_chain_data *cd; 1743 struct xl_list_data *ld; 1744 int error, i; 1745 1746 XL_LOCK_ASSERT(sc); 1747 1748 cd = &sc->xl_cdata; 1749 ld = &sc->xl_ldata; 1750 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1751 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1752 error = bus_dmamap_create(sc->xl_mtag, 0, 1753 &cd->xl_tx_chain[i].xl_map); 1754 if (error) 1755 return (error); 1756 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1757 i * sizeof(struct xl_list); 1758 if (i == (XL_TX_LIST_CNT - 1)) 1759 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1760 else 1761 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1762 if (i == 0) 1763 cd->xl_tx_chain[i].xl_prev = 1764 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1765 else 1766 cd->xl_tx_chain[i].xl_prev = 1767 &cd->xl_tx_chain[i - 1]; 1768 } 1769 1770 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1771 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1772 1773 cd->xl_tx_prod = 1; 1774 cd->xl_tx_cons = 1; 1775 cd->xl_tx_cnt = 0; 1776 1777 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1778 return (0); 1779 } 1780 1781 /* 1782 * Initialize the RX descriptors and allocate mbufs for them. Note that 1783 * we arrange the descriptors in a closed ring, so that the last descriptor 1784 * points back to the first. 1785 */ 1786 static int 1787 xl_list_rx_init(struct xl_softc *sc) 1788 { 1789 struct xl_chain_data *cd; 1790 struct xl_list_data *ld; 1791 int error, i, next; 1792 u_int32_t nextptr; 1793 1794 XL_LOCK_ASSERT(sc); 1795 1796 cd = &sc->xl_cdata; 1797 ld = &sc->xl_ldata; 1798 1799 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1800 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1801 error = bus_dmamap_create(sc->xl_mtag, 0, 1802 &cd->xl_rx_chain[i].xl_map); 1803 if (error) 1804 return (error); 1805 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1806 if (error) 1807 return (error); 1808 if (i == (XL_RX_LIST_CNT - 1)) 1809 next = 0; 1810 else 1811 next = i + 1; 1812 nextptr = ld->xl_rx_dmaaddr + 1813 next * sizeof(struct xl_list_onefrag); 1814 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1815 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1816 } 1817 1818 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1819 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1820 1821 return (0); 1822 } 1823 1824 /* 1825 * Initialize an RX descriptor and attach an MBUF cluster. 1826 * If we fail to do so, we need to leave the old mbuf and 1827 * the old DMA map untouched so that it can be reused. 1828 */ 1829 static int 1830 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1831 { 1832 struct mbuf *m_new = NULL; 1833 bus_dmamap_t map; 1834 bus_dma_segment_t segs[1]; 1835 int error, nseg; 1836 1837 XL_LOCK_ASSERT(sc); 1838 1839 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1840 if (m_new == NULL) 1841 return (ENOBUFS); 1842 1843 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1844 1845 /* Force longword alignment for packet payload. */ 1846 m_adj(m_new, ETHER_ALIGN); 1847 1848 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, 1849 segs, &nseg, BUS_DMA_NOWAIT); 1850 if (error) { 1851 m_freem(m_new); 1852 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", 1853 error); 1854 return (error); 1855 } 1856 KASSERT(nseg == 1, 1857 ("%s: too many DMA segments (%d)", __func__, nseg)); 1858 1859 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1860 map = c->xl_map; 1861 c->xl_map = sc->xl_tmpmap; 1862 sc->xl_tmpmap = map; 1863 c->xl_mbuf = m_new; 1864 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1865 c->xl_ptr->xl_status = 0; 1866 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); 1867 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1868 return (0); 1869 } 1870 1871 static int 1872 xl_rx_resync(struct xl_softc *sc) 1873 { 1874 struct xl_chain_onefrag *pos; 1875 int i; 1876 1877 XL_LOCK_ASSERT(sc); 1878 1879 pos = sc->xl_cdata.xl_rx_head; 1880 1881 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1882 if (pos->xl_ptr->xl_status) 1883 break; 1884 pos = pos->xl_next; 1885 } 1886 1887 if (i == XL_RX_LIST_CNT) 1888 return (0); 1889 1890 sc->xl_cdata.xl_rx_head = pos; 1891 1892 return (EAGAIN); 1893 } 1894 1895 /* 1896 * A frame has been uploaded: pass the resulting mbuf chain up to 1897 * the higher level protocols. 1898 */ 1899 static int 1900 xl_rxeof(struct xl_softc *sc) 1901 { 1902 struct mbuf *m; 1903 struct ifnet *ifp = sc->xl_ifp; 1904 struct xl_chain_onefrag *cur_rx; 1905 int total_len = 0; 1906 int rx_npkts = 0; 1907 u_int32_t rxstat; 1908 1909 XL_LOCK_ASSERT(sc); 1910 again: 1911 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1912 BUS_DMASYNC_POSTREAD); 1913 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1914 #ifdef DEVICE_POLLING 1915 if (ifp->if_capenable & IFCAP_POLLING) { 1916 if (sc->rxcycles <= 0) 1917 break; 1918 sc->rxcycles--; 1919 } 1920 #endif 1921 cur_rx = sc->xl_cdata.xl_rx_head; 1922 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1923 total_len = rxstat & XL_RXSTAT_LENMASK; 1924 1925 /* 1926 * Since we have told the chip to allow large frames, 1927 * we need to trap giant frame errors in software. We allow 1928 * a little more than the normal frame size to account for 1929 * frames with VLAN tags. 1930 */ 1931 if (total_len > XL_MAX_FRAMELEN) 1932 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1933 1934 /* 1935 * If an error occurs, update stats, clear the 1936 * status word and leave the mbuf cluster in place: 1937 * it should simply get re-used next time this descriptor 1938 * comes up in the ring. 1939 */ 1940 if (rxstat & XL_RXSTAT_UP_ERROR) { 1941 ifp->if_ierrors++; 1942 cur_rx->xl_ptr->xl_status = 0; 1943 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1944 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1945 continue; 1946 } 1947 1948 /* 1949 * If the error bit was not set, the upload complete 1950 * bit should be set which means we have a valid packet. 1951 * If not, something truly strange has happened. 1952 */ 1953 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1954 device_printf(sc->xl_dev, 1955 "bad receive status -- packet dropped\n"); 1956 ifp->if_ierrors++; 1957 cur_rx->xl_ptr->xl_status = 0; 1958 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1959 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1960 continue; 1961 } 1962 1963 /* No errors; receive the packet. */ 1964 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 1965 BUS_DMASYNC_POSTREAD); 1966 m = cur_rx->xl_mbuf; 1967 1968 /* 1969 * Try to conjure up a new mbuf cluster. If that 1970 * fails, it means we have an out of memory condition and 1971 * should leave the buffer in place and continue. This will 1972 * result in a lost packet, but there's little else we 1973 * can do in this situation. 1974 */ 1975 if (xl_newbuf(sc, cur_rx)) { 1976 ifp->if_ierrors++; 1977 cur_rx->xl_ptr->xl_status = 0; 1978 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1979 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1980 continue; 1981 } 1982 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1983 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1984 1985 ifp->if_ipackets++; 1986 m->m_pkthdr.rcvif = ifp; 1987 m->m_pkthdr.len = m->m_len = total_len; 1988 1989 if (ifp->if_capenable & IFCAP_RXCSUM) { 1990 /* Do IP checksum checking. */ 1991 if (rxstat & XL_RXSTAT_IPCKOK) 1992 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1993 if (!(rxstat & XL_RXSTAT_IPCKERR)) 1994 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1995 if ((rxstat & XL_RXSTAT_TCPCOK && 1996 !(rxstat & XL_RXSTAT_TCPCKERR)) || 1997 (rxstat & XL_RXSTAT_UDPCKOK && 1998 !(rxstat & XL_RXSTAT_UDPCKERR))) { 1999 m->m_pkthdr.csum_flags |= 2000 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2001 m->m_pkthdr.csum_data = 0xffff; 2002 } 2003 } 2004 2005 XL_UNLOCK(sc); 2006 (*ifp->if_input)(ifp, m); 2007 XL_LOCK(sc); 2008 rx_npkts++; 2009 2010 /* 2011 * If we are running from the taskqueue, the interface 2012 * might have been stopped while we were passing the last 2013 * packet up the network stack. 2014 */ 2015 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 2016 return (rx_npkts); 2017 } 2018 2019 /* 2020 * Handle the 'end of channel' condition. When the upload 2021 * engine hits the end of the RX ring, it will stall. This 2022 * is our cue to flush the RX ring, reload the uplist pointer 2023 * register and unstall the engine. 2024 * XXX This is actually a little goofy. With the ThunderLAN 2025 * chip, you get an interrupt when the receiver hits the end 2026 * of the receive ring, which tells you exactly when you 2027 * you need to reload the ring pointer. Here we have to 2028 * fake it. I'm mad at myself for not being clever enough 2029 * to avoid the use of a goto here. 2030 */ 2031 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2032 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2033 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2034 xl_wait(sc); 2035 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2036 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2037 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2038 goto again; 2039 } 2040 return (rx_npkts); 2041 } 2042 2043 /* 2044 * Taskqueue wrapper for xl_rxeof(). 2045 */ 2046 static void 2047 xl_rxeof_task(void *arg, int pending) 2048 { 2049 struct xl_softc *sc = (struct xl_softc *)arg; 2050 2051 XL_LOCK(sc); 2052 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING) 2053 xl_rxeof(sc); 2054 XL_UNLOCK(sc); 2055 } 2056 2057 /* 2058 * A frame was downloaded to the chip. It's safe for us to clean up 2059 * the list buffers. 2060 */ 2061 static void 2062 xl_txeof(struct xl_softc *sc) 2063 { 2064 struct xl_chain *cur_tx; 2065 struct ifnet *ifp = sc->xl_ifp; 2066 2067 XL_LOCK_ASSERT(sc); 2068 2069 /* 2070 * Go through our tx list and free mbufs for those 2071 * frames that have been uploaded. Note: the 3c905B 2072 * sets a special bit in the status word to let us 2073 * know that a frame has been downloaded, but the 2074 * original 3c900/3c905 adapters don't do that. 2075 * Consequently, we have to use a different test if 2076 * xl_type != XL_TYPE_905B. 2077 */ 2078 while (sc->xl_cdata.xl_tx_head != NULL) { 2079 cur_tx = sc->xl_cdata.xl_tx_head; 2080 2081 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2082 break; 2083 2084 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2085 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2086 BUS_DMASYNC_POSTWRITE); 2087 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2088 m_freem(cur_tx->xl_mbuf); 2089 cur_tx->xl_mbuf = NULL; 2090 ifp->if_opackets++; 2091 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2092 2093 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2094 sc->xl_cdata.xl_tx_free = cur_tx; 2095 } 2096 2097 if (sc->xl_cdata.xl_tx_head == NULL) { 2098 sc->xl_wdog_timer = 0; 2099 sc->xl_cdata.xl_tx_tail = NULL; 2100 } else { 2101 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2102 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2103 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2104 sc->xl_cdata.xl_tx_head->xl_phys); 2105 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2106 } 2107 } 2108 } 2109 2110 static void 2111 xl_txeof_90xB(struct xl_softc *sc) 2112 { 2113 struct xl_chain *cur_tx = NULL; 2114 struct ifnet *ifp = sc->xl_ifp; 2115 int idx; 2116 2117 XL_LOCK_ASSERT(sc); 2118 2119 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2120 BUS_DMASYNC_POSTREAD); 2121 idx = sc->xl_cdata.xl_tx_cons; 2122 while (idx != sc->xl_cdata.xl_tx_prod) { 2123 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2124 2125 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2126 XL_TXSTAT_DL_COMPLETE)) 2127 break; 2128 2129 if (cur_tx->xl_mbuf != NULL) { 2130 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2131 BUS_DMASYNC_POSTWRITE); 2132 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2133 m_freem(cur_tx->xl_mbuf); 2134 cur_tx->xl_mbuf = NULL; 2135 } 2136 2137 ifp->if_opackets++; 2138 2139 sc->xl_cdata.xl_tx_cnt--; 2140 XL_INC(idx, XL_TX_LIST_CNT); 2141 } 2142 2143 if (sc->xl_cdata.xl_tx_cnt == 0) 2144 sc->xl_wdog_timer = 0; 2145 sc->xl_cdata.xl_tx_cons = idx; 2146 2147 if (cur_tx != NULL) 2148 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2149 } 2150 2151 /* 2152 * TX 'end of channel' interrupt handler. Actually, we should 2153 * only get a 'TX complete' interrupt if there's a transmit error, 2154 * so this is really TX error handler. 2155 */ 2156 static void 2157 xl_txeoc(struct xl_softc *sc) 2158 { 2159 u_int8_t txstat; 2160 2161 XL_LOCK_ASSERT(sc); 2162 2163 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2164 if (txstat & XL_TXSTATUS_UNDERRUN || 2165 txstat & XL_TXSTATUS_JABBER || 2166 txstat & XL_TXSTATUS_RECLAIM) { 2167 device_printf(sc->xl_dev, 2168 "transmission error: %x\n", txstat); 2169 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2170 xl_wait(sc); 2171 if (sc->xl_type == XL_TYPE_905B) { 2172 if (sc->xl_cdata.xl_tx_cnt) { 2173 int i; 2174 struct xl_chain *c; 2175 2176 i = sc->xl_cdata.xl_tx_cons; 2177 c = &sc->xl_cdata.xl_tx_chain[i]; 2178 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2179 c->xl_phys); 2180 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2181 } 2182 } else { 2183 if (sc->xl_cdata.xl_tx_head != NULL) 2184 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2185 sc->xl_cdata.xl_tx_head->xl_phys); 2186 } 2187 /* 2188 * Remember to set this for the 2189 * first generation 3c90X chips. 2190 */ 2191 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2192 if (txstat & XL_TXSTATUS_UNDERRUN && 2193 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2194 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2195 device_printf(sc->xl_dev, 2196 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2197 } 2198 CSR_WRITE_2(sc, XL_COMMAND, 2199 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2200 if (sc->xl_type == XL_TYPE_905B) { 2201 CSR_WRITE_2(sc, XL_COMMAND, 2202 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2203 } 2204 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2205 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2206 } else { 2207 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2208 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2209 } 2210 /* 2211 * Write an arbitrary byte to the TX_STATUS register 2212 * to clear this interrupt/error and advance to the next. 2213 */ 2214 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2215 } 2216 } 2217 2218 static void 2219 xl_intr(void *arg) 2220 { 2221 struct xl_softc *sc = arg; 2222 struct ifnet *ifp = sc->xl_ifp; 2223 u_int16_t status; 2224 2225 XL_LOCK(sc); 2226 2227 #ifdef DEVICE_POLLING 2228 if (ifp->if_capenable & IFCAP_POLLING) { 2229 XL_UNLOCK(sc); 2230 return; 2231 } 2232 #endif 2233 2234 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && 2235 status != 0xFFFF) { 2236 CSR_WRITE_2(sc, XL_COMMAND, 2237 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2238 2239 if (status & XL_STAT_UP_COMPLETE) { 2240 int curpkts; 2241 2242 curpkts = ifp->if_ipackets; 2243 xl_rxeof(sc); 2244 if (curpkts == ifp->if_ipackets) { 2245 while (xl_rx_resync(sc)) 2246 xl_rxeof(sc); 2247 } 2248 } 2249 2250 if (status & XL_STAT_DOWN_COMPLETE) { 2251 if (sc->xl_type == XL_TYPE_905B) 2252 xl_txeof_90xB(sc); 2253 else 2254 xl_txeof(sc); 2255 } 2256 2257 if (status & XL_STAT_TX_COMPLETE) { 2258 ifp->if_oerrors++; 2259 xl_txeoc(sc); 2260 } 2261 2262 if (status & XL_STAT_ADFAIL) { 2263 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2264 xl_init_locked(sc); 2265 } 2266 2267 if (status & XL_STAT_STATSOFLOW) { 2268 sc->xl_stats_no_timeout = 1; 2269 xl_stats_update_locked(sc); 2270 sc->xl_stats_no_timeout = 0; 2271 } 2272 } 2273 2274 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2275 if (sc->xl_type == XL_TYPE_905B) 2276 xl_start_90xB_locked(ifp); 2277 else 2278 xl_start_locked(ifp); 2279 } 2280 2281 XL_UNLOCK(sc); 2282 } 2283 2284 #ifdef DEVICE_POLLING 2285 static int 2286 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2287 { 2288 struct xl_softc *sc = ifp->if_softc; 2289 int rx_npkts = 0; 2290 2291 XL_LOCK(sc); 2292 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2293 rx_npkts = xl_poll_locked(ifp, cmd, count); 2294 XL_UNLOCK(sc); 2295 return (rx_npkts); 2296 } 2297 2298 static int 2299 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2300 { 2301 struct xl_softc *sc = ifp->if_softc; 2302 int rx_npkts; 2303 2304 XL_LOCK_ASSERT(sc); 2305 2306 sc->rxcycles = count; 2307 rx_npkts = xl_rxeof(sc); 2308 if (sc->xl_type == XL_TYPE_905B) 2309 xl_txeof_90xB(sc); 2310 else 2311 xl_txeof(sc); 2312 2313 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2314 if (sc->xl_type == XL_TYPE_905B) 2315 xl_start_90xB_locked(ifp); 2316 else 2317 xl_start_locked(ifp); 2318 } 2319 2320 if (cmd == POLL_AND_CHECK_STATUS) { 2321 u_int16_t status; 2322 2323 status = CSR_READ_2(sc, XL_STATUS); 2324 if (status & XL_INTRS && status != 0xFFFF) { 2325 CSR_WRITE_2(sc, XL_COMMAND, 2326 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2327 2328 if (status & XL_STAT_TX_COMPLETE) { 2329 ifp->if_oerrors++; 2330 xl_txeoc(sc); 2331 } 2332 2333 if (status & XL_STAT_ADFAIL) { 2334 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2335 xl_init_locked(sc); 2336 } 2337 2338 if (status & XL_STAT_STATSOFLOW) { 2339 sc->xl_stats_no_timeout = 1; 2340 xl_stats_update_locked(sc); 2341 sc->xl_stats_no_timeout = 0; 2342 } 2343 } 2344 } 2345 return (rx_npkts); 2346 } 2347 #endif /* DEVICE_POLLING */ 2348 2349 /* 2350 * XXX: This is an entry point for callout which needs to take the lock. 2351 */ 2352 static void 2353 xl_stats_update(void *xsc) 2354 { 2355 struct xl_softc *sc = xsc; 2356 2357 XL_LOCK_ASSERT(sc); 2358 2359 if (xl_watchdog(sc) == EJUSTRETURN) 2360 return; 2361 2362 xl_stats_update_locked(sc); 2363 } 2364 2365 static void 2366 xl_stats_update_locked(struct xl_softc *sc) 2367 { 2368 struct ifnet *ifp = sc->xl_ifp; 2369 struct xl_stats xl_stats; 2370 u_int8_t *p; 2371 int i; 2372 struct mii_data *mii = NULL; 2373 2374 XL_LOCK_ASSERT(sc); 2375 2376 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2377 2378 if (sc->xl_miibus != NULL) 2379 mii = device_get_softc(sc->xl_miibus); 2380 2381 p = (u_int8_t *)&xl_stats; 2382 2383 /* Read all the stats registers. */ 2384 XL_SEL_WIN(6); 2385 2386 for (i = 0; i < 16; i++) 2387 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2388 2389 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2390 2391 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2392 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision; 2393 2394 /* 2395 * Boomerang and cyclone chips have an extra stats counter 2396 * in window 4 (BadSSD). We have to read this too in order 2397 * to clear out all the stats registers and avoid a statsoflow 2398 * interrupt. 2399 */ 2400 XL_SEL_WIN(4); 2401 CSR_READ_1(sc, XL_W4_BADSSD); 2402 2403 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2404 mii_tick(mii); 2405 2406 XL_SEL_WIN(7); 2407 2408 if (!sc->xl_stats_no_timeout) 2409 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2410 } 2411 2412 /* 2413 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2414 * pointers to the fragment pointers. 2415 */ 2416 static int 2417 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) 2418 { 2419 struct mbuf *m_new; 2420 struct ifnet *ifp = sc->xl_ifp; 2421 int error, i, nseg, total_len; 2422 u_int32_t status; 2423 2424 XL_LOCK_ASSERT(sc); 2425 2426 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, 2427 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2428 2429 if (error && error != EFBIG) { 2430 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2431 return (error); 2432 } 2433 2434 /* 2435 * Handle special case: we used up all 63 fragments, 2436 * but we have more mbufs left in the chain. Copy the 2437 * data into an mbuf cluster. Note that we don't 2438 * bother clearing the values in the other fragment 2439 * pointers/counters; it wouldn't gain us anything, 2440 * and would waste cycles. 2441 */ 2442 if (error) { 2443 m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS); 2444 if (m_new == NULL) { 2445 m_freem(*m_head); 2446 *m_head = NULL; 2447 return (ENOBUFS); 2448 } 2449 *m_head = m_new; 2450 2451 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, 2452 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2453 if (error) { 2454 m_freem(*m_head); 2455 *m_head = NULL; 2456 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2457 return (error); 2458 } 2459 } 2460 2461 KASSERT(nseg <= XL_MAXFRAGS, 2462 ("%s: too many DMA segments (%d)", __func__, nseg)); 2463 if (nseg == 0) { 2464 m_freem(*m_head); 2465 *m_head = NULL; 2466 return (EIO); 2467 } 2468 2469 total_len = 0; 2470 for (i = 0; i < nseg; i++) { 2471 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, 2472 ("segment size too large")); 2473 c->xl_ptr->xl_frag[i].xl_addr = 2474 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); 2475 c->xl_ptr->xl_frag[i].xl_len = 2476 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); 2477 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; 2478 } 2479 c->xl_ptr->xl_frag[nseg - 1].xl_len = 2480 htole32(sc->xl_cdata.xl_tx_segs[nseg - 1].ds_len | XL_LAST_FRAG); 2481 c->xl_ptr->xl_status = htole32(total_len); 2482 c->xl_ptr->xl_next = 0; 2483 2484 if (sc->xl_type == XL_TYPE_905B) { 2485 status = XL_TXSTAT_RND_DEFEAT; 2486 2487 #ifndef XL905B_TXCSUM_BROKEN 2488 if ((*m_head)->m_pkthdr.csum_flags) { 2489 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2490 status |= XL_TXSTAT_IPCKSUM; 2491 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2492 status |= XL_TXSTAT_TCPCKSUM; 2493 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2494 status |= XL_TXSTAT_UDPCKSUM; 2495 } 2496 #endif 2497 c->xl_ptr->xl_status = htole32(status); 2498 } 2499 2500 c->xl_mbuf = *m_head; 2501 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2502 return (0); 2503 } 2504 2505 /* 2506 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2507 * to the mbuf data regions directly in the transmit lists. We also save a 2508 * copy of the pointers since the transmit list fragment pointers are 2509 * physical addresses. 2510 */ 2511 2512 static void 2513 xl_start(struct ifnet *ifp) 2514 { 2515 struct xl_softc *sc = ifp->if_softc; 2516 2517 XL_LOCK(sc); 2518 2519 if (sc->xl_type == XL_TYPE_905B) 2520 xl_start_90xB_locked(ifp); 2521 else 2522 xl_start_locked(ifp); 2523 2524 XL_UNLOCK(sc); 2525 } 2526 2527 static void 2528 xl_start_locked(struct ifnet *ifp) 2529 { 2530 struct xl_softc *sc = ifp->if_softc; 2531 struct mbuf *m_head = NULL; 2532 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2533 u_int32_t status; 2534 int error; 2535 2536 XL_LOCK_ASSERT(sc); 2537 2538 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2539 IFF_DRV_RUNNING) 2540 return; 2541 /* 2542 * Check for an available queue slot. If there are none, 2543 * punt. 2544 */ 2545 if (sc->xl_cdata.xl_tx_free == NULL) { 2546 xl_txeoc(sc); 2547 xl_txeof(sc); 2548 if (sc->xl_cdata.xl_tx_free == NULL) { 2549 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2550 return; 2551 } 2552 } 2553 2554 start_tx = sc->xl_cdata.xl_tx_free; 2555 2556 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2557 sc->xl_cdata.xl_tx_free != NULL;) { 2558 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2559 if (m_head == NULL) 2560 break; 2561 2562 /* Pick a descriptor off the free list. */ 2563 cur_tx = sc->xl_cdata.xl_tx_free; 2564 2565 /* Pack the data into the descriptor. */ 2566 error = xl_encap(sc, cur_tx, &m_head); 2567 if (error) { 2568 if (m_head == NULL) 2569 break; 2570 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2571 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2572 break; 2573 } 2574 2575 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2576 cur_tx->xl_next = NULL; 2577 2578 /* Chain it together. */ 2579 if (prev != NULL) { 2580 prev->xl_next = cur_tx; 2581 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2582 } 2583 prev = cur_tx; 2584 2585 /* 2586 * If there's a BPF listener, bounce a copy of this frame 2587 * to him. 2588 */ 2589 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2590 } 2591 2592 /* 2593 * If there are no packets queued, bail. 2594 */ 2595 if (cur_tx == NULL) 2596 return; 2597 2598 /* 2599 * Place the request for the upload interrupt 2600 * in the last descriptor in the chain. This way, if 2601 * we're chaining several packets at once, we'll only 2602 * get an interrupt once for the whole chain rather than 2603 * once for each packet. 2604 */ 2605 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2606 XL_TXSTAT_DL_INTR); 2607 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2608 BUS_DMASYNC_PREWRITE); 2609 2610 /* 2611 * Queue the packets. If the TX channel is clear, update 2612 * the downlist pointer register. 2613 */ 2614 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2615 xl_wait(sc); 2616 2617 if (sc->xl_cdata.xl_tx_head != NULL) { 2618 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2619 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2620 htole32(start_tx->xl_phys); 2621 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2622 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2623 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2624 sc->xl_cdata.xl_tx_tail = cur_tx; 2625 } else { 2626 sc->xl_cdata.xl_tx_head = start_tx; 2627 sc->xl_cdata.xl_tx_tail = cur_tx; 2628 } 2629 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2630 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2631 2632 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2633 2634 XL_SEL_WIN(7); 2635 2636 /* 2637 * Set a timeout in case the chip goes out to lunch. 2638 */ 2639 sc->xl_wdog_timer = 5; 2640 2641 /* 2642 * XXX Under certain conditions, usually on slower machines 2643 * where interrupts may be dropped, it's possible for the 2644 * adapter to chew up all the buffers in the receive ring 2645 * and stall, without us being able to do anything about it. 2646 * To guard against this, we need to make a pass over the 2647 * RX queue to make sure there aren't any packets pending. 2648 * Doing it here means we can flush the receive ring at the 2649 * same time the chip is DMAing the transmit descriptors we 2650 * just gave it. 2651 * 2652 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2653 * nature of their chips in all their marketing literature; 2654 * we may as well take advantage of it. :) 2655 */ 2656 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2657 } 2658 2659 static void 2660 xl_start_90xB_locked(struct ifnet *ifp) 2661 { 2662 struct xl_softc *sc = ifp->if_softc; 2663 struct mbuf *m_head = NULL; 2664 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2665 int error, idx; 2666 2667 XL_LOCK_ASSERT(sc); 2668 2669 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2670 IFF_DRV_RUNNING) 2671 return; 2672 2673 idx = sc->xl_cdata.xl_tx_prod; 2674 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2675 2676 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2677 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { 2678 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2679 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2680 break; 2681 } 2682 2683 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2684 if (m_head == NULL) 2685 break; 2686 2687 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2688 2689 /* Pack the data into the descriptor. */ 2690 error = xl_encap(sc, cur_tx, &m_head); 2691 if (error) { 2692 if (m_head == NULL) 2693 break; 2694 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2695 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2696 break; 2697 } 2698 2699 /* Chain it together. */ 2700 if (prev != NULL) 2701 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2702 prev = cur_tx; 2703 2704 /* 2705 * If there's a BPF listener, bounce a copy of this frame 2706 * to him. 2707 */ 2708 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2709 2710 XL_INC(idx, XL_TX_LIST_CNT); 2711 sc->xl_cdata.xl_tx_cnt++; 2712 } 2713 2714 /* 2715 * If there are no packets queued, bail. 2716 */ 2717 if (cur_tx == NULL) 2718 return; 2719 2720 /* 2721 * Place the request for the upload interrupt 2722 * in the last descriptor in the chain. This way, if 2723 * we're chaining several packets at once, we'll only 2724 * get an interrupt once for the whole chain rather than 2725 * once for each packet. 2726 */ 2727 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2728 XL_TXSTAT_DL_INTR); 2729 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2730 BUS_DMASYNC_PREWRITE); 2731 2732 /* Start transmission */ 2733 sc->xl_cdata.xl_tx_prod = idx; 2734 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2735 2736 /* 2737 * Set a timeout in case the chip goes out to lunch. 2738 */ 2739 sc->xl_wdog_timer = 5; 2740 } 2741 2742 static void 2743 xl_init(void *xsc) 2744 { 2745 struct xl_softc *sc = xsc; 2746 2747 XL_LOCK(sc); 2748 xl_init_locked(sc); 2749 XL_UNLOCK(sc); 2750 } 2751 2752 static void 2753 xl_init_locked(struct xl_softc *sc) 2754 { 2755 struct ifnet *ifp = sc->xl_ifp; 2756 int error, i; 2757 u_int16_t rxfilt = 0; 2758 struct mii_data *mii = NULL; 2759 2760 XL_LOCK_ASSERT(sc); 2761 2762 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2763 return; 2764 /* 2765 * Cancel pending I/O and free all RX/TX buffers. 2766 */ 2767 xl_stop(sc); 2768 2769 /* Reset the chip to a known state. */ 2770 xl_reset(sc); 2771 2772 if (sc->xl_miibus == NULL) { 2773 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2774 xl_wait(sc); 2775 } 2776 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2777 xl_wait(sc); 2778 DELAY(10000); 2779 2780 if (sc->xl_miibus != NULL) 2781 mii = device_get_softc(sc->xl_miibus); 2782 2783 /* 2784 * Clear WOL status and disable all WOL feature as WOL 2785 * would interfere Rx operation under normal environments. 2786 */ 2787 if ((sc->xl_flags & XL_FLAG_WOL) != 0) { 2788 XL_SEL_WIN(7); 2789 CSR_READ_2(sc, XL_W7_BM_PME); 2790 CSR_WRITE_2(sc, XL_W7_BM_PME, 0); 2791 } 2792 /* Init our MAC address */ 2793 XL_SEL_WIN(2); 2794 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2795 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2796 IF_LLADDR(sc->xl_ifp)[i]); 2797 } 2798 2799 /* Clear the station mask. */ 2800 for (i = 0; i < 3; i++) 2801 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2802 #ifdef notdef 2803 /* Reset TX and RX. */ 2804 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2805 xl_wait(sc); 2806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2807 xl_wait(sc); 2808 #endif 2809 /* Init circular RX list. */ 2810 error = xl_list_rx_init(sc); 2811 if (error) { 2812 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n", 2813 error); 2814 xl_stop(sc); 2815 return; 2816 } 2817 2818 /* Init TX descriptors. */ 2819 if (sc->xl_type == XL_TYPE_905B) 2820 error = xl_list_tx_init_90xB(sc); 2821 else 2822 error = xl_list_tx_init(sc); 2823 if (error) { 2824 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n", 2825 error); 2826 xl_stop(sc); 2827 return; 2828 } 2829 2830 /* 2831 * Set the TX freethresh value. 2832 * Note that this has no effect on 3c905B "cyclone" 2833 * cards but is required for 3c900/3c905 "boomerang" 2834 * cards in order to enable the download engine. 2835 */ 2836 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2837 2838 /* Set the TX start threshold for best performance. */ 2839 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2840 2841 /* 2842 * If this is a 3c905B, also set the tx reclaim threshold. 2843 * This helps cut down on the number of tx reclaim errors 2844 * that could happen on a busy network. The chip multiplies 2845 * the register value by 16 to obtain the actual threshold 2846 * in bytes, so we divide by 16 when setting the value here. 2847 * The existing threshold value can be examined by reading 2848 * the register at offset 9 in window 5. 2849 */ 2850 if (sc->xl_type == XL_TYPE_905B) { 2851 CSR_WRITE_2(sc, XL_COMMAND, 2852 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2853 } 2854 2855 /* Set RX filter bits. */ 2856 XL_SEL_WIN(5); 2857 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2858 2859 /* Set the individual bit to receive frames for this host only. */ 2860 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2861 2862 /* If we want promiscuous mode, set the allframes bit. */ 2863 if (ifp->if_flags & IFF_PROMISC) { 2864 rxfilt |= XL_RXFILTER_ALLFRAMES; 2865 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2866 } else { 2867 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2868 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2869 } 2870 2871 /* 2872 * Set capture broadcast bit to capture broadcast frames. 2873 */ 2874 if (ifp->if_flags & IFF_BROADCAST) { 2875 rxfilt |= XL_RXFILTER_BROADCAST; 2876 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2877 } else { 2878 rxfilt &= ~XL_RXFILTER_BROADCAST; 2879 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2880 } 2881 2882 /* 2883 * Program the multicast filter, if necessary. 2884 */ 2885 if (sc->xl_type == XL_TYPE_905B) 2886 xl_setmulti_hash(sc); 2887 else 2888 xl_setmulti(sc); 2889 2890 /* 2891 * Load the address of the RX list. We have to 2892 * stall the upload engine before we can manipulate 2893 * the uplist pointer register, then unstall it when 2894 * we're finished. We also have to wait for the 2895 * stall command to complete before proceeding. 2896 * Note that we have to do this after any RX resets 2897 * have completed since the uplist register is cleared 2898 * by a reset. 2899 */ 2900 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2901 xl_wait(sc); 2902 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2903 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2904 xl_wait(sc); 2905 2906 if (sc->xl_type == XL_TYPE_905B) { 2907 /* Set polling interval */ 2908 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2909 /* Load the address of the TX list */ 2910 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2911 xl_wait(sc); 2912 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2913 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2914 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2915 xl_wait(sc); 2916 } 2917 2918 /* 2919 * If the coax transceiver is on, make sure to enable 2920 * the DC-DC converter. 2921 */ 2922 XL_SEL_WIN(3); 2923 if (sc->xl_xcvr == XL_XCVR_COAX) 2924 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2925 else 2926 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2927 2928 /* 2929 * increase packet size to allow reception of 802.1q or ISL packets. 2930 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2931 * control register. For 3c90xB/C chips, use the RX packet size 2932 * register. 2933 */ 2934 2935 if (sc->xl_type == XL_TYPE_905B) 2936 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2937 else { 2938 u_int8_t macctl; 2939 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2940 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2941 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2942 } 2943 2944 /* Clear out the stats counters. */ 2945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2946 sc->xl_stats_no_timeout = 1; 2947 xl_stats_update_locked(sc); 2948 sc->xl_stats_no_timeout = 0; 2949 XL_SEL_WIN(4); 2950 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2951 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2952 2953 /* 2954 * Enable interrupts. 2955 */ 2956 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2957 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2958 #ifdef DEVICE_POLLING 2959 /* Disable interrupts if we are polling. */ 2960 if (ifp->if_capenable & IFCAP_POLLING) 2961 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2962 else 2963 #endif 2964 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2965 if (sc->xl_flags & XL_FLAG_FUNCREG) 2966 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2967 2968 /* Set the RX early threshold */ 2969 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2970 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2971 2972 /* Enable receiver and transmitter. */ 2973 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2974 xl_wait(sc); 2975 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2976 xl_wait(sc); 2977 2978 /* XXX Downcall to miibus. */ 2979 if (mii != NULL) 2980 mii_mediachg(mii); 2981 2982 /* Select window 7 for normal operations. */ 2983 XL_SEL_WIN(7); 2984 2985 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2986 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2987 2988 sc->xl_wdog_timer = 0; 2989 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2990 } 2991 2992 /* 2993 * Set media options. 2994 */ 2995 static int 2996 xl_ifmedia_upd(struct ifnet *ifp) 2997 { 2998 struct xl_softc *sc = ifp->if_softc; 2999 struct ifmedia *ifm = NULL; 3000 struct mii_data *mii = NULL; 3001 3002 XL_LOCK(sc); 3003 3004 if (sc->xl_miibus != NULL) 3005 mii = device_get_softc(sc->xl_miibus); 3006 if (mii == NULL) 3007 ifm = &sc->ifmedia; 3008 else 3009 ifm = &mii->mii_media; 3010 3011 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3012 case IFM_100_FX: 3013 case IFM_10_FL: 3014 case IFM_10_2: 3015 case IFM_10_5: 3016 xl_setmode(sc, ifm->ifm_media); 3017 XL_UNLOCK(sc); 3018 return (0); 3019 } 3020 3021 if (sc->xl_media & XL_MEDIAOPT_MII || 3022 sc->xl_media & XL_MEDIAOPT_BTX || 3023 sc->xl_media & XL_MEDIAOPT_BT4) { 3024 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3025 xl_init_locked(sc); 3026 } else { 3027 xl_setmode(sc, ifm->ifm_media); 3028 } 3029 3030 XL_UNLOCK(sc); 3031 3032 return (0); 3033 } 3034 3035 /* 3036 * Report current media status. 3037 */ 3038 static void 3039 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3040 { 3041 struct xl_softc *sc = ifp->if_softc; 3042 u_int32_t icfg; 3043 u_int16_t status = 0; 3044 struct mii_data *mii = NULL; 3045 3046 XL_LOCK(sc); 3047 3048 if (sc->xl_miibus != NULL) 3049 mii = device_get_softc(sc->xl_miibus); 3050 3051 XL_SEL_WIN(4); 3052 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3053 3054 XL_SEL_WIN(3); 3055 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3056 icfg >>= XL_ICFG_CONNECTOR_BITS; 3057 3058 ifmr->ifm_active = IFM_ETHER; 3059 ifmr->ifm_status = IFM_AVALID; 3060 3061 if ((status & XL_MEDIASTAT_CARRIER) == 0) 3062 ifmr->ifm_status |= IFM_ACTIVE; 3063 3064 switch (icfg) { 3065 case XL_XCVR_10BT: 3066 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3067 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3068 ifmr->ifm_active |= IFM_FDX; 3069 else 3070 ifmr->ifm_active |= IFM_HDX; 3071 break; 3072 case XL_XCVR_AUI: 3073 if (sc->xl_type == XL_TYPE_905B && 3074 sc->xl_media == XL_MEDIAOPT_10FL) { 3075 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3076 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3077 ifmr->ifm_active |= IFM_FDX; 3078 else 3079 ifmr->ifm_active |= IFM_HDX; 3080 } else 3081 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3082 break; 3083 case XL_XCVR_COAX: 3084 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3085 break; 3086 /* 3087 * XXX MII and BTX/AUTO should be separate cases. 3088 */ 3089 3090 case XL_XCVR_100BTX: 3091 case XL_XCVR_AUTO: 3092 case XL_XCVR_MII: 3093 if (mii != NULL) { 3094 mii_pollstat(mii); 3095 ifmr->ifm_active = mii->mii_media_active; 3096 ifmr->ifm_status = mii->mii_media_status; 3097 } 3098 break; 3099 case XL_XCVR_100BFX: 3100 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3101 break; 3102 default: 3103 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3104 break; 3105 } 3106 3107 XL_UNLOCK(sc); 3108 } 3109 3110 static int 3111 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3112 { 3113 struct xl_softc *sc = ifp->if_softc; 3114 struct ifreq *ifr = (struct ifreq *) data; 3115 int error = 0, mask; 3116 struct mii_data *mii = NULL; 3117 u_int8_t rxfilt; 3118 3119 switch (command) { 3120 case SIOCSIFFLAGS: 3121 XL_LOCK(sc); 3122 3123 XL_SEL_WIN(5); 3124 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3125 if (ifp->if_flags & IFF_UP) { 3126 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3127 ifp->if_flags & IFF_PROMISC && 3128 !(sc->xl_if_flags & IFF_PROMISC)) { 3129 rxfilt |= XL_RXFILTER_ALLFRAMES; 3130 CSR_WRITE_2(sc, XL_COMMAND, 3131 XL_CMD_RX_SET_FILT|rxfilt); 3132 XL_SEL_WIN(7); 3133 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3134 !(ifp->if_flags & IFF_PROMISC) && 3135 sc->xl_if_flags & IFF_PROMISC) { 3136 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3137 CSR_WRITE_2(sc, XL_COMMAND, 3138 XL_CMD_RX_SET_FILT|rxfilt); 3139 XL_SEL_WIN(7); 3140 } else 3141 xl_init_locked(sc); 3142 } else { 3143 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3144 xl_stop(sc); 3145 } 3146 sc->xl_if_flags = ifp->if_flags; 3147 XL_UNLOCK(sc); 3148 error = 0; 3149 break; 3150 case SIOCADDMULTI: 3151 case SIOCDELMULTI: 3152 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3153 XL_LOCK(sc); 3154 if (sc->xl_type == XL_TYPE_905B) 3155 xl_setmulti_hash(sc); 3156 else 3157 xl_setmulti(sc); 3158 XL_UNLOCK(sc); 3159 error = 0; 3160 break; 3161 case SIOCGIFMEDIA: 3162 case SIOCSIFMEDIA: 3163 if (sc->xl_miibus != NULL) 3164 mii = device_get_softc(sc->xl_miibus); 3165 if (mii == NULL) 3166 error = ifmedia_ioctl(ifp, ifr, 3167 &sc->ifmedia, command); 3168 else 3169 error = ifmedia_ioctl(ifp, ifr, 3170 &mii->mii_media, command); 3171 break; 3172 case SIOCSIFCAP: 3173 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3174 #ifdef DEVICE_POLLING 3175 if ((mask & IFCAP_POLLING) != 0 && 3176 (ifp->if_capabilities & IFCAP_POLLING) != 0) { 3177 ifp->if_capenable ^= IFCAP_POLLING; 3178 if ((ifp->if_capenable & IFCAP_POLLING) != 0) { 3179 error = ether_poll_register(xl_poll, ifp); 3180 if (error) 3181 break; 3182 XL_LOCK(sc); 3183 /* Disable interrupts */ 3184 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3185 ifp->if_capenable |= IFCAP_POLLING; 3186 XL_UNLOCK(sc); 3187 } else { 3188 error = ether_poll_deregister(ifp); 3189 /* Enable interrupts. */ 3190 XL_LOCK(sc); 3191 CSR_WRITE_2(sc, XL_COMMAND, 3192 XL_CMD_INTR_ACK | 0xFF); 3193 CSR_WRITE_2(sc, XL_COMMAND, 3194 XL_CMD_INTR_ENB | XL_INTRS); 3195 if (sc->xl_flags & XL_FLAG_FUNCREG) 3196 bus_space_write_4(sc->xl_ftag, 3197 sc->xl_fhandle, 4, 0x8000); 3198 XL_UNLOCK(sc); 3199 } 3200 } 3201 #endif /* DEVICE_POLLING */ 3202 XL_LOCK(sc); 3203 if ((mask & IFCAP_TXCSUM) != 0 && 3204 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3205 ifp->if_capenable ^= IFCAP_TXCSUM; 3206 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3207 ifp->if_hwassist |= XL905B_CSUM_FEATURES; 3208 else 3209 ifp->if_hwassist &= ~XL905B_CSUM_FEATURES; 3210 } 3211 if ((mask & IFCAP_RXCSUM) != 0 && 3212 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3213 ifp->if_capenable ^= IFCAP_RXCSUM; 3214 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3215 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3216 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3217 XL_UNLOCK(sc); 3218 break; 3219 default: 3220 error = ether_ioctl(ifp, command, data); 3221 break; 3222 } 3223 3224 return (error); 3225 } 3226 3227 static int 3228 xl_watchdog(struct xl_softc *sc) 3229 { 3230 struct ifnet *ifp = sc->xl_ifp; 3231 u_int16_t status = 0; 3232 int misintr; 3233 3234 XL_LOCK_ASSERT(sc); 3235 3236 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) 3237 return (0); 3238 3239 xl_rxeof(sc); 3240 xl_txeoc(sc); 3241 misintr = 0; 3242 if (sc->xl_type == XL_TYPE_905B) { 3243 xl_txeof_90xB(sc); 3244 if (sc->xl_cdata.xl_tx_cnt == 0) 3245 misintr++; 3246 } else { 3247 xl_txeof(sc); 3248 if (sc->xl_cdata.xl_tx_head == NULL) 3249 misintr++; 3250 } 3251 if (misintr != 0) { 3252 device_printf(sc->xl_dev, 3253 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 3254 return (0); 3255 } 3256 3257 ifp->if_oerrors++; 3258 XL_SEL_WIN(4); 3259 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3260 device_printf(sc->xl_dev, "watchdog timeout\n"); 3261 3262 if (status & XL_MEDIASTAT_CARRIER) 3263 device_printf(sc->xl_dev, 3264 "no carrier - transceiver cable problem?\n"); 3265 3266 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3267 xl_init_locked(sc); 3268 3269 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 3270 if (sc->xl_type == XL_TYPE_905B) 3271 xl_start_90xB_locked(ifp); 3272 else 3273 xl_start_locked(ifp); 3274 } 3275 3276 return (EJUSTRETURN); 3277 } 3278 3279 /* 3280 * Stop the adapter and free any mbufs allocated to the 3281 * RX and TX lists. 3282 */ 3283 static void 3284 xl_stop(struct xl_softc *sc) 3285 { 3286 register int i; 3287 struct ifnet *ifp = sc->xl_ifp; 3288 3289 XL_LOCK_ASSERT(sc); 3290 3291 sc->xl_wdog_timer = 0; 3292 3293 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3294 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3295 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3296 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3297 xl_wait(sc); 3298 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3299 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3300 DELAY(800); 3301 3302 #ifdef foo 3303 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3304 xl_wait(sc); 3305 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3306 xl_wait(sc); 3307 #endif 3308 3309 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3310 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3311 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3312 if (sc->xl_flags & XL_FLAG_FUNCREG) 3313 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3314 3315 /* Stop the stats updater. */ 3316 callout_stop(&sc->xl_stat_callout); 3317 3318 /* 3319 * Free data in the RX lists. 3320 */ 3321 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3322 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3323 bus_dmamap_unload(sc->xl_mtag, 3324 sc->xl_cdata.xl_rx_chain[i].xl_map); 3325 bus_dmamap_destroy(sc->xl_mtag, 3326 sc->xl_cdata.xl_rx_chain[i].xl_map); 3327 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3328 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3329 } 3330 } 3331 if (sc->xl_ldata.xl_rx_list != NULL) 3332 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3333 /* 3334 * Free the TX list buffers. 3335 */ 3336 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3337 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3338 bus_dmamap_unload(sc->xl_mtag, 3339 sc->xl_cdata.xl_tx_chain[i].xl_map); 3340 bus_dmamap_destroy(sc->xl_mtag, 3341 sc->xl_cdata.xl_tx_chain[i].xl_map); 3342 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3343 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3344 } 3345 } 3346 if (sc->xl_ldata.xl_tx_list != NULL) 3347 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3348 3349 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3350 } 3351 3352 /* 3353 * Stop all chip I/O so that the kernel's probe routines don't 3354 * get confused by errant DMAs when rebooting. 3355 */ 3356 static int 3357 xl_shutdown(device_t dev) 3358 { 3359 3360 return (xl_suspend(dev)); 3361 } 3362 3363 static int 3364 xl_suspend(device_t dev) 3365 { 3366 struct xl_softc *sc; 3367 3368 sc = device_get_softc(dev); 3369 3370 XL_LOCK(sc); 3371 xl_stop(sc); 3372 xl_setwol(sc); 3373 XL_UNLOCK(sc); 3374 3375 return (0); 3376 } 3377 3378 static int 3379 xl_resume(device_t dev) 3380 { 3381 struct xl_softc *sc; 3382 struct ifnet *ifp; 3383 3384 sc = device_get_softc(dev); 3385 ifp = sc->xl_ifp; 3386 3387 XL_LOCK(sc); 3388 3389 if (ifp->if_flags & IFF_UP) { 3390 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3391 xl_init_locked(sc); 3392 } 3393 3394 XL_UNLOCK(sc); 3395 3396 return (0); 3397 } 3398 3399 static void 3400 xl_setwol(struct xl_softc *sc) 3401 { 3402 struct ifnet *ifp; 3403 u_int16_t cfg, pmstat; 3404 3405 if ((sc->xl_flags & XL_FLAG_WOL) == 0) 3406 return; 3407 3408 ifp = sc->xl_ifp; 3409 XL_SEL_WIN(7); 3410 /* Clear any pending PME events. */ 3411 CSR_READ_2(sc, XL_W7_BM_PME); 3412 cfg = 0; 3413 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3414 cfg |= XL_BM_PME_MAGIC; 3415 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg); 3416 /* Enable RX. */ 3417 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3418 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 3419 /* Request PME. */ 3420 pmstat = pci_read_config(sc->xl_dev, 3421 sc->xl_pmcap + PCIR_POWER_STATUS, 2); 3422 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3423 pmstat |= PCIM_PSTAT_PMEENABLE; 3424 else 3425 pmstat &= ~PCIM_PSTAT_PMEENABLE; 3426 pci_write_config(sc->xl_dev, 3427 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2); 3428 } 3429