xref: /freebsd/sys/dev/xl/if_xl.c (revision 396c556d77189a5c474d35cec6f44a762e310b7d)
1 /*-
2  * SPDX-License-Identifier: BSD-4-Clause
3  *
4  * Copyright (c) 1997, 1998, 1999
5  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *	This product includes software developed by Bill Paul.
18  * 4. Neither the name of the author nor the names of any co-contributors
19  *    may be used to endorse or promote products derived from this software
20  *    without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32  * THE POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
37 
38 /*
39  * 3Com 3c90x Etherlink XL PCI NIC driver
40  *
41  * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
42  * bus-master chips (3c90x cards and embedded controllers) including
43  * the following:
44  *
45  * 3Com 3c900-TPO	10Mbps/RJ-45
46  * 3Com 3c900-COMBO	10Mbps/RJ-45,AUI,BNC
47  * 3Com 3c905-TX	10/100Mbps/RJ-45
48  * 3Com 3c905-T4	10/100Mbps/RJ-45
49  * 3Com 3c900B-TPO	10Mbps/RJ-45
50  * 3Com 3c900B-COMBO	10Mbps/RJ-45,AUI,BNC
51  * 3Com 3c900B-TPC	10Mbps/RJ-45,BNC
52  * 3Com 3c900B-FL	10Mbps/Fiber-optic
53  * 3Com 3c905B-COMBO	10/100Mbps/RJ-45,AUI,BNC
54  * 3Com 3c905B-TX	10/100Mbps/RJ-45
55  * 3Com 3c905B-FL/FX	10/100Mbps/Fiber-optic
56  * 3Com 3c905C-TX	10/100Mbps/RJ-45 (Tornado ASIC)
57  * 3Com 3c980-TX	10/100Mbps server adapter (Hurricane ASIC)
58  * 3Com 3c980C-TX	10/100Mbps server adapter (Tornado ASIC)
59  * 3Com 3cSOHO100-TX	10/100Mbps/RJ-45 (Hurricane ASIC)
60  * 3Com 3c450-TX	10/100Mbps/RJ-45 (Tornado ASIC)
61  * 3Com 3c555		10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
62  * 3Com 3c556		10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
63  * 3Com 3c556B		10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
64  * 3Com 3c575TX		10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65  * 3Com 3c575B		10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66  * 3Com 3c575C		10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67  * 3Com 3cxfem656	10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
68  * 3Com 3cxfem656b	10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
69  * 3Com 3cxfem656c	10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
70  * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
71  * Dell on-board 3c920 10/100Mbps/RJ-45
72  * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
73  * Dell Latitude laptop docking station embedded 3c905-TX
74  *
75  * Written by Bill Paul <wpaul@ctr.columbia.edu>
76  * Electrical Engineering Department
77  * Columbia University, New York City
78  */
79 /*
80  * The 3c90x series chips use a bus-master DMA interface for transferring
81  * packets to and from the controller chip. Some of the "vortex" cards
82  * (3c59x) also supported a bus master mode, however for those chips
83  * you could only DMA packets to/from a contiguous memory buffer. For
84  * transmission this would mean copying the contents of the queued mbuf
85  * chain into an mbuf cluster and then DMAing the cluster. This extra
86  * copy would sort of defeat the purpose of the bus master support for
87  * any packet that doesn't fit into a single mbuf.
88  *
89  * By contrast, the 3c90x cards support a fragment-based bus master
90  * mode where mbuf chains can be encapsulated using TX descriptors.
91  * This is similar to other PCI chips such as the Texas Instruments
92  * ThunderLAN and the Intel 82557/82558.
93  *
94  * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
95  * bus master chips because they maintain the old PIO interface for
96  * backwards compatibility, but starting with the 3c905B and the
97  * "cyclone" chips, the compatibility interface has been dropped.
98  * Since using bus master DMA is a big win, we use this driver to
99  * support the PCI "boomerang" chips even though they work with the
100  * "vortex" driver in order to obtain better performance.
101  */
102 
103 #ifdef HAVE_KERNEL_OPTION_HEADERS
104 #include "opt_device_polling.h"
105 #endif
106 
107 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/sockio.h>
110 #include <sys/endian.h>
111 #include <sys/kernel.h>
112 #include <sys/malloc.h>
113 #include <sys/mbuf.h>
114 #include <sys/module.h>
115 #include <sys/socket.h>
116 #include <sys/taskqueue.h>
117 
118 #include <net/if.h>
119 #include <net/if_var.h>
120 #include <net/if_arp.h>
121 #include <net/ethernet.h>
122 #include <net/if_dl.h>
123 #include <net/if_media.h>
124 #include <net/if_types.h>
125 
126 #include <net/bpf.h>
127 
128 #include <machine/bus.h>
129 #include <machine/resource.h>
130 #include <sys/bus.h>
131 #include <sys/rman.h>
132 
133 #include <dev/mii/mii.h>
134 #include <dev/mii/mii_bitbang.h>
135 #include <dev/mii/miivar.h>
136 
137 #include <dev/pci/pcireg.h>
138 #include <dev/pci/pcivar.h>
139 
140 MODULE_DEPEND(xl, pci, 1, 1, 1);
141 MODULE_DEPEND(xl, ether, 1, 1, 1);
142 MODULE_DEPEND(xl, miibus, 1, 1, 1);
143 
144 /* "device miibus" required.  See GENERIC if you get errors here. */
145 #include "miibus_if.h"
146 
147 #include <dev/xl/if_xlreg.h>
148 
149 /*
150  * TX Checksumming is disabled by default for two reasons:
151  * - TX Checksumming will occasionally produce corrupt packets
152  * - TX Checksumming seems to reduce performance
153  *
154  * Only 905B/C cards were reported to have this problem, it is possible
155  * that later chips _may_ be immune.
156  */
157 #define	XL905B_TXCSUM_BROKEN	1
158 
159 #ifdef XL905B_TXCSUM_BROKEN
160 #define XL905B_CSUM_FEATURES	0
161 #else
162 #define XL905B_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
163 #endif
164 
165 /*
166  * Various supported device vendors/types and their names.
167  */
168 static const struct xl_type xl_devs[] = {
169 	{ TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
170 		"3Com 3c900-TPO Etherlink XL" },
171 	{ TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
172 		"3Com 3c900-COMBO Etherlink XL" },
173 	{ TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
174 		"3Com 3c905-TX Fast Etherlink XL" },
175 	{ TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
176 		"3Com 3c905-T4 Fast Etherlink XL" },
177 	{ TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
178 		"3Com 3c900B-TPO Etherlink XL" },
179 	{ TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
180 		"3Com 3c900B-COMBO Etherlink XL" },
181 	{ TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
182 		"3Com 3c900B-TPC Etherlink XL" },
183 	{ TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
184 		"3Com 3c900B-FL Etherlink XL" },
185 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
186 		"3Com 3c905B-TX Fast Etherlink XL" },
187 	{ TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
188 		"3Com 3c905B-T4 Fast Etherlink XL" },
189 	{ TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
190 		"3Com 3c905B-FX/SC Fast Etherlink XL" },
191 	{ TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
192 		"3Com 3c905B-COMBO Fast Etherlink XL" },
193 	{ TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
194 		"3Com 3c905C-TX Fast Etherlink XL" },
195 	{ TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
196 		"3Com 3c920B-EMB Integrated Fast Etherlink XL" },
197 	{ TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
198 		"3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
199 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
200 		"3Com 3c980 Fast Etherlink XL" },
201 	{ TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
202 		"3Com 3c980C Fast Etherlink XL" },
203 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
204 		"3Com 3cSOHO100-TX OfficeConnect" },
205 	{ TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
206 		"3Com 3c450-TX HomeConnect" },
207 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_555,
208 		"3Com 3c555 Fast Etherlink XL" },
209 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_556,
210 		"3Com 3c556 Fast Etherlink XL" },
211 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
212 		"3Com 3c556B Fast Etherlink XL" },
213 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
214 		"3Com 3c575TX Fast Etherlink XL" },
215 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
216 		"3Com 3c575B Fast Etherlink XL" },
217 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
218 		"3Com 3c575C Fast Etherlink XL" },
219 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_656,
220 		"3Com 3c656 Fast Etherlink XL" },
221 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
222 		"3Com 3c656B Fast Etherlink XL" },
223 	{ TC_VENDORID, TC_DEVICEID_TORNADO_656C,
224 		"3Com 3c656C Fast Etherlink XL" },
225 	{ 0, 0, NULL }
226 };
227 
228 static int xl_probe(device_t);
229 static int xl_attach(device_t);
230 static int xl_detach(device_t);
231 
232 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
233 static void xl_tick(void *);
234 static void xl_stats_update(struct xl_softc *);
235 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **);
236 static int xl_rxeof(struct xl_softc *);
237 static void xl_rxeof_task(void *, int);
238 static int xl_rx_resync(struct xl_softc *);
239 static void xl_txeof(struct xl_softc *);
240 static void xl_txeof_90xB(struct xl_softc *);
241 static void xl_txeoc(struct xl_softc *);
242 static void xl_intr(void *);
243 static void xl_start(struct ifnet *);
244 static void xl_start_locked(struct ifnet *);
245 static void xl_start_90xB_locked(struct ifnet *);
246 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
247 static void xl_init(void *);
248 static void xl_init_locked(struct xl_softc *);
249 static void xl_stop(struct xl_softc *);
250 static int xl_watchdog(struct xl_softc *);
251 static int xl_shutdown(device_t);
252 static int xl_suspend(device_t);
253 static int xl_resume(device_t);
254 static void xl_setwol(struct xl_softc *);
255 
256 #ifdef DEVICE_POLLING
257 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
258 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
259 #endif
260 
261 static int xl_ifmedia_upd(struct ifnet *);
262 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
263 
264 static int xl_eeprom_wait(struct xl_softc *);
265 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
266 
267 static void xl_rxfilter(struct xl_softc *);
268 static void xl_rxfilter_90x(struct xl_softc *);
269 static void xl_rxfilter_90xB(struct xl_softc *);
270 static void xl_setcfg(struct xl_softc *);
271 static void xl_setmode(struct xl_softc *, int);
272 static void xl_reset(struct xl_softc *);
273 static int xl_list_rx_init(struct xl_softc *);
274 static int xl_list_tx_init(struct xl_softc *);
275 static int xl_list_tx_init_90xB(struct xl_softc *);
276 static void xl_wait(struct xl_softc *);
277 static void xl_mediacheck(struct xl_softc *);
278 static void xl_choose_media(struct xl_softc *sc, int *media);
279 static void xl_choose_xcvr(struct xl_softc *, int);
280 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
281 #ifdef notdef
282 static void xl_testpacket(struct xl_softc *);
283 #endif
284 
285 static int xl_miibus_readreg(device_t, int, int);
286 static int xl_miibus_writereg(device_t, int, int, int);
287 static void xl_miibus_statchg(device_t);
288 static void xl_miibus_mediainit(device_t);
289 
290 /*
291  * MII bit-bang glue
292  */
293 static uint32_t xl_mii_bitbang_read(device_t);
294 static void xl_mii_bitbang_write(device_t, uint32_t);
295 
296 static const struct mii_bitbang_ops xl_mii_bitbang_ops = {
297 	xl_mii_bitbang_read,
298 	xl_mii_bitbang_write,
299 	{
300 		XL_MII_DATA,		/* MII_BIT_MDO */
301 		XL_MII_DATA,		/* MII_BIT_MDI */
302 		XL_MII_CLK,		/* MII_BIT_MDC */
303 		XL_MII_DIR,		/* MII_BIT_DIR_HOST_PHY */
304 		0,			/* MII_BIT_DIR_PHY_HOST */
305 	}
306 };
307 
308 static device_method_t xl_methods[] = {
309 	/* Device interface */
310 	DEVMETHOD(device_probe,		xl_probe),
311 	DEVMETHOD(device_attach,	xl_attach),
312 	DEVMETHOD(device_detach,	xl_detach),
313 	DEVMETHOD(device_shutdown,	xl_shutdown),
314 	DEVMETHOD(device_suspend,	xl_suspend),
315 	DEVMETHOD(device_resume,	xl_resume),
316 
317 	/* MII interface */
318 	DEVMETHOD(miibus_readreg,	xl_miibus_readreg),
319 	DEVMETHOD(miibus_writereg,	xl_miibus_writereg),
320 	DEVMETHOD(miibus_statchg,	xl_miibus_statchg),
321 	DEVMETHOD(miibus_mediainit,	xl_miibus_mediainit),
322 
323 	DEVMETHOD_END
324 };
325 
326 static driver_t xl_driver = {
327 	"xl",
328 	xl_methods,
329 	sizeof(struct xl_softc)
330 };
331 
332 static devclass_t xl_devclass;
333 
334 DRIVER_MODULE_ORDERED(xl, pci, xl_driver, xl_devclass, NULL, NULL,
335     SI_ORDER_ANY);
336 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, NULL, NULL);
337 
338 static void
339 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
340 {
341 	u_int32_t *paddr;
342 
343 	paddr = arg;
344 	*paddr = segs->ds_addr;
345 }
346 
347 /*
348  * Murphy's law says that it's possible the chip can wedge and
349  * the 'command in progress' bit may never clear. Hence, we wait
350  * only a finite amount of time to avoid getting caught in an
351  * infinite loop. Normally this delay routine would be a macro,
352  * but it isn't called during normal operation so we can afford
353  * to make it a function.  Suppress warning when card gone.
354  */
355 static void
356 xl_wait(struct xl_softc *sc)
357 {
358 	int			i;
359 
360 	for (i = 0; i < XL_TIMEOUT; i++) {
361 		if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
362 			break;
363 	}
364 
365 	if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev))
366 		device_printf(sc->xl_dev, "command never completed!\n");
367 }
368 
369 /*
370  * MII access routines are provided for adapters with external
371  * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
372  * autoneg logic that's faked up to look like a PHY (3c905B-TX).
373  * Note: if you don't perform the MDIO operations just right,
374  * it's possible to end up with code that works correctly with
375  * some chips/CPUs/processor speeds/bus speeds/etc but not
376  * with others.
377  */
378 
379 /*
380  * Read the MII serial port for the MII bit-bang module.
381  */
382 static uint32_t
383 xl_mii_bitbang_read(device_t dev)
384 {
385 	struct xl_softc		*sc;
386 	uint32_t		val;
387 
388 	sc = device_get_softc(dev);
389 
390 	/* We're already in window 4. */
391 	val = CSR_READ_2(sc, XL_W4_PHY_MGMT);
392 	CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
393 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
394 
395 	return (val);
396 }
397 
398 /*
399  * Write the MII serial port for the MII bit-bang module.
400  */
401 static void
402 xl_mii_bitbang_write(device_t dev, uint32_t val)
403 {
404 	struct xl_softc		*sc;
405 
406 	sc = device_get_softc(dev);
407 
408 	/* We're already in window 4. */
409 	CSR_WRITE_2(sc, XL_W4_PHY_MGMT,	val);
410 	CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
411 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
412 }
413 
414 static int
415 xl_miibus_readreg(device_t dev, int phy, int reg)
416 {
417 	struct xl_softc		*sc;
418 
419 	sc = device_get_softc(dev);
420 
421 	/* Select the window 4. */
422 	XL_SEL_WIN(4);
423 
424 	return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg));
425 }
426 
427 static int
428 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
429 {
430 	struct xl_softc		*sc;
431 
432 	sc = device_get_softc(dev);
433 
434 	/* Select the window 4. */
435 	XL_SEL_WIN(4);
436 
437 	mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data);
438 
439 	return (0);
440 }
441 
442 static void
443 xl_miibus_statchg(device_t dev)
444 {
445 	struct xl_softc		*sc;
446 	struct mii_data		*mii;
447 	uint8_t			macctl;
448 
449 	sc = device_get_softc(dev);
450 	mii = device_get_softc(sc->xl_miibus);
451 
452 	xl_setcfg(sc);
453 
454 	/* Set ASIC's duplex mode to match the PHY. */
455 	XL_SEL_WIN(3);
456 	macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
457 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
458 		macctl |= XL_MACCTRL_DUPLEX;
459 		if (sc->xl_type == XL_TYPE_905B) {
460 			if ((IFM_OPTIONS(mii->mii_media_active) &
461 			    IFM_ETH_RXPAUSE) != 0)
462 				macctl |= XL_MACCTRL_FLOW_CONTROL_ENB;
463 			else
464 				macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
465 		}
466 	} else {
467 		macctl &= ~XL_MACCTRL_DUPLEX;
468 		if (sc->xl_type == XL_TYPE_905B)
469 			macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
470 	}
471 	CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
472 }
473 
474 /*
475  * Special support for the 3c905B-COMBO. This card has 10/100 support
476  * plus BNC and AUI ports. This means we will have both an miibus attached
477  * plus some non-MII media settings. In order to allow this, we have to
478  * add the extra media to the miibus's ifmedia struct, but we can't do
479  * that during xl_attach() because the miibus hasn't been attached yet.
480  * So instead, we wait until the miibus probe/attach is done, at which
481  * point we will get a callback telling is that it's safe to add our
482  * extra media.
483  */
484 static void
485 xl_miibus_mediainit(device_t dev)
486 {
487 	struct xl_softc		*sc;
488 	struct mii_data		*mii;
489 	struct ifmedia		*ifm;
490 
491 	sc = device_get_softc(dev);
492 	mii = device_get_softc(sc->xl_miibus);
493 	ifm = &mii->mii_media;
494 
495 	if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
496 		/*
497 		 * Check for a 10baseFL board in disguise.
498 		 */
499 		if (sc->xl_type == XL_TYPE_905B &&
500 		    sc->xl_media == XL_MEDIAOPT_10FL) {
501 			if (bootverbose)
502 				device_printf(sc->xl_dev, "found 10baseFL\n");
503 			ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
504 			ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
505 			    NULL);
506 			if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
507 				ifmedia_add(ifm,
508 				    IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
509 		} else {
510 			if (bootverbose)
511 				device_printf(sc->xl_dev, "found AUI\n");
512 			ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
513 		}
514 	}
515 
516 	if (sc->xl_media & XL_MEDIAOPT_BNC) {
517 		if (bootverbose)
518 			device_printf(sc->xl_dev, "found BNC\n");
519 		ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
520 	}
521 }
522 
523 /*
524  * The EEPROM is slow: give it time to come ready after issuing
525  * it a command.
526  */
527 static int
528 xl_eeprom_wait(struct xl_softc *sc)
529 {
530 	int			i;
531 
532 	for (i = 0; i < 100; i++) {
533 		if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
534 			DELAY(162);
535 		else
536 			break;
537 	}
538 
539 	if (i == 100) {
540 		device_printf(sc->xl_dev, "eeprom failed to come ready\n");
541 		return (1);
542 	}
543 
544 	return (0);
545 }
546 
547 /*
548  * Read a sequence of words from the EEPROM. Note that ethernet address
549  * data is stored in the EEPROM in network byte order.
550  */
551 static int
552 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
553 {
554 	int			err = 0, i;
555 	u_int16_t		word = 0, *ptr;
556 
557 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
558 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
559 	/*
560 	 * XXX: WARNING! DANGER!
561 	 * It's easy to accidentally overwrite the rom content!
562 	 * Note: the 3c575 uses 8bit EEPROM offsets.
563 	 */
564 	XL_SEL_WIN(0);
565 
566 	if (xl_eeprom_wait(sc))
567 		return (1);
568 
569 	if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
570 		off += 0x30;
571 
572 	for (i = 0; i < cnt; i++) {
573 		if (sc->xl_flags & XL_FLAG_8BITROM)
574 			CSR_WRITE_2(sc, XL_W0_EE_CMD,
575 			    XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
576 		else
577 			CSR_WRITE_2(sc, XL_W0_EE_CMD,
578 			    XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
579 		err = xl_eeprom_wait(sc);
580 		if (err)
581 			break;
582 		word = CSR_READ_2(sc, XL_W0_EE_DATA);
583 		ptr = (u_int16_t *)(dest + (i * 2));
584 		if (swap)
585 			*ptr = ntohs(word);
586 		else
587 			*ptr = word;
588 	}
589 
590 	return (err ? 1 : 0);
591 }
592 
593 static void
594 xl_rxfilter(struct xl_softc *sc)
595 {
596 
597 	if (sc->xl_type == XL_TYPE_905B)
598 		xl_rxfilter_90xB(sc);
599 	else
600 		xl_rxfilter_90x(sc);
601 }
602 
603 /*
604  * NICs older than the 3c905B have only one multicast option, which
605  * is to enable reception of all multicast frames.
606  */
607 static void
608 xl_rxfilter_90x(struct xl_softc *sc)
609 {
610 	struct ifnet		*ifp;
611 	struct ifmultiaddr	*ifma;
612 	u_int8_t		rxfilt;
613 
614 	XL_LOCK_ASSERT(sc);
615 
616 	ifp = sc->xl_ifp;
617 
618 	XL_SEL_WIN(5);
619 	rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
620 	rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
621 	    XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL);
622 
623 	/* Set the individual bit to receive frames for this host only. */
624 	rxfilt |= XL_RXFILTER_INDIVIDUAL;
625 	/* Set capture broadcast bit to capture broadcast frames. */
626 	if (ifp->if_flags & IFF_BROADCAST)
627 		rxfilt |= XL_RXFILTER_BROADCAST;
628 
629 	/* If we want promiscuous mode, set the allframes bit. */
630 	if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
631 		if (ifp->if_flags & IFF_PROMISC)
632 			rxfilt |= XL_RXFILTER_ALLFRAMES;
633 		if (ifp->if_flags & IFF_ALLMULTI)
634 			rxfilt |= XL_RXFILTER_ALLMULTI;
635 	} else {
636 		if_maddr_rlock(ifp);
637 		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
638 			if (ifma->ifma_addr->sa_family != AF_LINK)
639 				continue;
640 			rxfilt |= XL_RXFILTER_ALLMULTI;
641 			break;
642 		}
643 		if_maddr_runlock(ifp);
644 	}
645 
646 	CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
647 	XL_SEL_WIN(7);
648 }
649 
650 /*
651  * 3c905B adapters have a hash filter that we can program.
652  */
653 static void
654 xl_rxfilter_90xB(struct xl_softc *sc)
655 {
656 	struct ifnet		*ifp;
657 	struct ifmultiaddr	*ifma;
658 	int			i, mcnt;
659 	u_int16_t		h;
660 	u_int8_t		rxfilt;
661 
662 	XL_LOCK_ASSERT(sc);
663 
664 	ifp = sc->xl_ifp;
665 
666 	XL_SEL_WIN(5);
667 	rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
668 	rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
669 	    XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL |
670 	    XL_RXFILTER_MULTIHASH);
671 
672 	/* Set the individual bit to receive frames for this host only. */
673 	rxfilt |= XL_RXFILTER_INDIVIDUAL;
674 	/* Set capture broadcast bit to capture broadcast frames. */
675 	if (ifp->if_flags & IFF_BROADCAST)
676 		rxfilt |= XL_RXFILTER_BROADCAST;
677 
678 	/* If we want promiscuous mode, set the allframes bit. */
679 	if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
680 		if (ifp->if_flags & IFF_PROMISC)
681 			rxfilt |= XL_RXFILTER_ALLFRAMES;
682 		if (ifp->if_flags & IFF_ALLMULTI)
683 			rxfilt |= XL_RXFILTER_ALLMULTI;
684 	} else {
685 		/* First, zot all the existing hash bits. */
686 		for (i = 0; i < XL_HASHFILT_SIZE; i++)
687 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
688 
689 		/* Now program new ones. */
690 		mcnt = 0;
691 		if_maddr_rlock(ifp);
692 		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
693 			if (ifma->ifma_addr->sa_family != AF_LINK)
694 				continue;
695 			/*
696 			 * Note: the 3c905B currently only supports a 64-bit
697 			 * hash table, which means we really only need 6 bits,
698 			 * but the manual indicates that future chip revisions
699 			 * will have a 256-bit hash table, hence the routine
700 			 * is set up to calculate 8 bits of position info in
701 			 * case we need it some day.
702 			 * Note II, The Sequel: _CURRENT_ versions of the
703 			 * 3c905B have a 256 bit hash table. This means we have
704 			 * to use all 8 bits regardless.  On older cards, the
705 			 * upper 2 bits will be ignored. Grrrr....
706 			 */
707 			h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
708 			    ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
709 			CSR_WRITE_2(sc, XL_COMMAND,
710 			    h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
711 			mcnt++;
712 		}
713 		if_maddr_runlock(ifp);
714 		if (mcnt > 0)
715 			rxfilt |= XL_RXFILTER_MULTIHASH;
716 	}
717 
718 	CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
719 	XL_SEL_WIN(7);
720 }
721 
722 static void
723 xl_setcfg(struct xl_softc *sc)
724 {
725 	u_int32_t		icfg;
726 
727 	/*XL_LOCK_ASSERT(sc);*/
728 
729 	XL_SEL_WIN(3);
730 	icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
731 	icfg &= ~XL_ICFG_CONNECTOR_MASK;
732 	if (sc->xl_media & XL_MEDIAOPT_MII ||
733 		sc->xl_media & XL_MEDIAOPT_BT4)
734 		icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
735 	if (sc->xl_media & XL_MEDIAOPT_BTX)
736 		icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
737 
738 	CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
739 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
740 }
741 
742 static void
743 xl_setmode(struct xl_softc *sc, int media)
744 {
745 	u_int32_t		icfg;
746 	u_int16_t		mediastat;
747 	char			*pmsg = "", *dmsg = "";
748 
749 	XL_LOCK_ASSERT(sc);
750 
751 	XL_SEL_WIN(4);
752 	mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
753 	XL_SEL_WIN(3);
754 	icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
755 
756 	if (sc->xl_media & XL_MEDIAOPT_BT) {
757 		if (IFM_SUBTYPE(media) == IFM_10_T) {
758 			pmsg = "10baseT transceiver";
759 			sc->xl_xcvr = XL_XCVR_10BT;
760 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
761 			icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
762 			mediastat |= XL_MEDIASTAT_LINKBEAT |
763 			    XL_MEDIASTAT_JABGUARD;
764 			mediastat &= ~XL_MEDIASTAT_SQEENB;
765 		}
766 	}
767 
768 	if (sc->xl_media & XL_MEDIAOPT_BFX) {
769 		if (IFM_SUBTYPE(media) == IFM_100_FX) {
770 			pmsg = "100baseFX port";
771 			sc->xl_xcvr = XL_XCVR_100BFX;
772 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
773 			icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
774 			mediastat |= XL_MEDIASTAT_LINKBEAT;
775 			mediastat &= ~XL_MEDIASTAT_SQEENB;
776 		}
777 	}
778 
779 	if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
780 		if (IFM_SUBTYPE(media) == IFM_10_5) {
781 			pmsg = "AUI port";
782 			sc->xl_xcvr = XL_XCVR_AUI;
783 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
784 			icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
785 			mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
786 			    XL_MEDIASTAT_JABGUARD);
787 			mediastat |= ~XL_MEDIASTAT_SQEENB;
788 		}
789 		if (IFM_SUBTYPE(media) == IFM_10_FL) {
790 			pmsg = "10baseFL transceiver";
791 			sc->xl_xcvr = XL_XCVR_AUI;
792 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
793 			icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
794 			mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
795 			    XL_MEDIASTAT_JABGUARD);
796 			mediastat |= ~XL_MEDIASTAT_SQEENB;
797 		}
798 	}
799 
800 	if (sc->xl_media & XL_MEDIAOPT_BNC) {
801 		if (IFM_SUBTYPE(media) == IFM_10_2) {
802 			pmsg = "AUI port";
803 			sc->xl_xcvr = XL_XCVR_COAX;
804 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
805 			icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
806 			mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
807 			    XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
808 		}
809 	}
810 
811 	if ((media & IFM_GMASK) == IFM_FDX ||
812 			IFM_SUBTYPE(media) == IFM_100_FX) {
813 		dmsg = "full";
814 		XL_SEL_WIN(3);
815 		CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
816 	} else {
817 		dmsg = "half";
818 		XL_SEL_WIN(3);
819 		CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
820 			(CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
821 	}
822 
823 	if (IFM_SUBTYPE(media) == IFM_10_2)
824 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
825 	else
826 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
827 
828 	CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
829 	XL_SEL_WIN(4);
830 	CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
831 
832 	DELAY(800);
833 	XL_SEL_WIN(7);
834 
835 	device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
836 }
837 
838 static void
839 xl_reset(struct xl_softc *sc)
840 {
841 	int			i;
842 
843 	XL_LOCK_ASSERT(sc);
844 
845 	XL_SEL_WIN(0);
846 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
847 	    ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
848 	     XL_RESETOPT_DISADVFD:0));
849 
850 	/*
851 	 * If we're using memory mapped register mode, pause briefly
852 	 * after issuing the reset command before trying to access any
853 	 * other registers. With my 3c575C CardBus card, failing to do
854 	 * this results in the system locking up while trying to poll
855 	 * the command busy bit in the status register.
856 	 */
857 	if (sc->xl_flags & XL_FLAG_USE_MMIO)
858 		DELAY(100000);
859 
860 	for (i = 0; i < XL_TIMEOUT; i++) {
861 		DELAY(10);
862 		if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
863 			break;
864 	}
865 
866 	if (i == XL_TIMEOUT)
867 		device_printf(sc->xl_dev, "reset didn't complete\n");
868 
869 	/* Reset TX and RX. */
870 	/* Note: the RX reset takes an absurd amount of time
871 	 * on newer versions of the Tornado chips such as those
872 	 * on the 3c905CX and newer 3c908C cards. We wait an
873 	 * extra amount of time so that xl_wait() doesn't complain
874 	 * and annoy the users.
875 	 */
876 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
877 	DELAY(100000);
878 	xl_wait(sc);
879 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
880 	xl_wait(sc);
881 
882 	if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
883 	    sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
884 		XL_SEL_WIN(2);
885 		CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
886 		    CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
887 		    ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
888 		    XL_RESETOPT_INVERT_LED : 0) |
889 		    ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
890 		    XL_RESETOPT_INVERT_MII : 0));
891 	}
892 
893 	/* Wait a little while for the chip to get its brains in order. */
894 	DELAY(100000);
895 }
896 
897 /*
898  * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
899  * IDs against our list and return a device name if we find a match.
900  */
901 static int
902 xl_probe(device_t dev)
903 {
904 	const struct xl_type	*t;
905 
906 	t = xl_devs;
907 
908 	while (t->xl_name != NULL) {
909 		if ((pci_get_vendor(dev) == t->xl_vid) &&
910 		    (pci_get_device(dev) == t->xl_did)) {
911 			device_set_desc(dev, t->xl_name);
912 			return (BUS_PROBE_DEFAULT);
913 		}
914 		t++;
915 	}
916 
917 	return (ENXIO);
918 }
919 
920 /*
921  * This routine is a kludge to work around possible hardware faults
922  * or manufacturing defects that can cause the media options register
923  * (or reset options register, as it's called for the first generation
924  * 3c90x adapters) to return an incorrect result. I have encountered
925  * one Dell Latitude laptop docking station with an integrated 3c905-TX
926  * which doesn't have any of the 'mediaopt' bits set. This screws up
927  * the attach routine pretty badly because it doesn't know what media
928  * to look for. If we find ourselves in this predicament, this routine
929  * will try to guess the media options values and warn the user of a
930  * possible manufacturing defect with his adapter/system/whatever.
931  */
932 static void
933 xl_mediacheck(struct xl_softc *sc)
934 {
935 
936 	/*
937 	 * If some of the media options bits are set, assume they are
938 	 * correct. If not, try to figure it out down below.
939 	 * XXX I should check for 10baseFL, but I don't have an adapter
940 	 * to test with.
941 	 */
942 	if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
943 		/*
944 		 * Check the XCVR value. If it's not in the normal range
945 		 * of values, we need to fake it up here.
946 		 */
947 		if (sc->xl_xcvr <= XL_XCVR_AUTO)
948 			return;
949 		else {
950 			device_printf(sc->xl_dev,
951 			    "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
952 			device_printf(sc->xl_dev,
953 			    "choosing new default based on card type\n");
954 		}
955 	} else {
956 		if (sc->xl_type == XL_TYPE_905B &&
957 		    sc->xl_media & XL_MEDIAOPT_10FL)
958 			return;
959 		device_printf(sc->xl_dev,
960 "WARNING: no media options bits set in the media options register!!\n");
961 		device_printf(sc->xl_dev,
962 "this could be a manufacturing defect in your adapter or system\n");
963 		device_printf(sc->xl_dev,
964 "attempting to guess media type; you should probably consult your vendor\n");
965 	}
966 
967 	xl_choose_xcvr(sc, 1);
968 }
969 
970 static void
971 xl_choose_xcvr(struct xl_softc *sc, int verbose)
972 {
973 	u_int16_t		devid;
974 
975 	/*
976 	 * Read the device ID from the EEPROM.
977 	 * This is what's loaded into the PCI device ID register, so it has
978 	 * to be correct otherwise we wouldn't have gotten this far.
979 	 */
980 	xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
981 
982 	switch (devid) {
983 	case TC_DEVICEID_BOOMERANG_10BT:	/* 3c900-TPO */
984 	case TC_DEVICEID_KRAKATOA_10BT:		/* 3c900B-TPO */
985 		sc->xl_media = XL_MEDIAOPT_BT;
986 		sc->xl_xcvr = XL_XCVR_10BT;
987 		if (verbose)
988 			device_printf(sc->xl_dev,
989 			    "guessing 10BaseT transceiver\n");
990 		break;
991 	case TC_DEVICEID_BOOMERANG_10BT_COMBO:	/* 3c900-COMBO */
992 	case TC_DEVICEID_KRAKATOA_10BT_COMBO:	/* 3c900B-COMBO */
993 		sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
994 		sc->xl_xcvr = XL_XCVR_10BT;
995 		if (verbose)
996 			device_printf(sc->xl_dev,
997 			    "guessing COMBO (AUI/BNC/TP)\n");
998 		break;
999 	case TC_DEVICEID_KRAKATOA_10BT_TPC:	/* 3c900B-TPC */
1000 		sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1001 		sc->xl_xcvr = XL_XCVR_10BT;
1002 		if (verbose)
1003 			device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
1004 		break;
1005 	case TC_DEVICEID_CYCLONE_10FL:		/* 3c900B-FL */
1006 		sc->xl_media = XL_MEDIAOPT_10FL;
1007 		sc->xl_xcvr = XL_XCVR_AUI;
1008 		if (verbose)
1009 			device_printf(sc->xl_dev, "guessing 10baseFL\n");
1010 		break;
1011 	case TC_DEVICEID_BOOMERANG_10_100BT:	/* 3c905-TX */
1012 	case TC_DEVICEID_HURRICANE_555:		/* 3c555 */
1013 	case TC_DEVICEID_HURRICANE_556:		/* 3c556 */
1014 	case TC_DEVICEID_HURRICANE_556B:	/* 3c556B */
1015 	case TC_DEVICEID_HURRICANE_575A:	/* 3c575TX */
1016 	case TC_DEVICEID_HURRICANE_575B:	/* 3c575B */
1017 	case TC_DEVICEID_HURRICANE_575C:	/* 3c575C */
1018 	case TC_DEVICEID_HURRICANE_656:		/* 3c656 */
1019 	case TC_DEVICEID_HURRICANE_656B:	/* 3c656B */
1020 	case TC_DEVICEID_TORNADO_656C:		/* 3c656C */
1021 	case TC_DEVICEID_TORNADO_10_100BT_920B:	/* 3c920B-EMB */
1022 	case TC_DEVICEID_TORNADO_10_100BT_920B_WNM:	/* 3c920B-EMB-WNM */
1023 		sc->xl_media = XL_MEDIAOPT_MII;
1024 		sc->xl_xcvr = XL_XCVR_MII;
1025 		if (verbose)
1026 			device_printf(sc->xl_dev, "guessing MII\n");
1027 		break;
1028 	case TC_DEVICEID_BOOMERANG_100BT4:	/* 3c905-T4 */
1029 	case TC_DEVICEID_CYCLONE_10_100BT4:	/* 3c905B-T4 */
1030 		sc->xl_media = XL_MEDIAOPT_BT4;
1031 		sc->xl_xcvr = XL_XCVR_MII;
1032 		if (verbose)
1033 			device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1034 		break;
1035 	case TC_DEVICEID_HURRICANE_10_100BT:	/* 3c905B-TX */
1036 	case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1037 	case TC_DEVICEID_TORNADO_10_100BT_SERV:	/* 3c980C-TX */
1038 	case TC_DEVICEID_HURRICANE_SOHO100TX:	/* 3cSOHO100-TX */
1039 	case TC_DEVICEID_TORNADO_10_100BT:	/* 3c905C-TX */
1040 	case TC_DEVICEID_TORNADO_HOMECONNECT:	/* 3c450-TX */
1041 		sc->xl_media = XL_MEDIAOPT_BTX;
1042 		sc->xl_xcvr = XL_XCVR_AUTO;
1043 		if (verbose)
1044 			device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1045 		break;
1046 	case TC_DEVICEID_CYCLONE_10_100_COMBO:	/* 3c905B-COMBO */
1047 		sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1048 		sc->xl_xcvr = XL_XCVR_AUTO;
1049 		if (verbose)
1050 			device_printf(sc->xl_dev,
1051 			    "guessing 10/100 plus BNC/AUI\n");
1052 		break;
1053 	default:
1054 		device_printf(sc->xl_dev,
1055 		    "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1056 		sc->xl_media = XL_MEDIAOPT_BT;
1057 		break;
1058 	}
1059 }
1060 
1061 /*
1062  * Attach the interface. Allocate softc structures, do ifmedia
1063  * setup and ethernet/BPF attach.
1064  */
1065 static int
1066 xl_attach(device_t dev)
1067 {
1068 	u_char			eaddr[ETHER_ADDR_LEN];
1069 	u_int16_t		sinfo2, xcvr[2];
1070 	struct xl_softc		*sc;
1071 	struct ifnet		*ifp;
1072 	int			media, pmcap;
1073 	int			error = 0, phy, rid, res, unit;
1074 	uint16_t		did;
1075 
1076 	sc = device_get_softc(dev);
1077 	sc->xl_dev = dev;
1078 
1079 	unit = device_get_unit(dev);
1080 
1081 	mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1082 	    MTX_DEF);
1083 	ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1084 
1085 	did = pci_get_device(dev);
1086 
1087 	sc->xl_flags = 0;
1088 	if (did == TC_DEVICEID_HURRICANE_555)
1089 		sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1090 	if (did == TC_DEVICEID_HURRICANE_556 ||
1091 	    did == TC_DEVICEID_HURRICANE_556B)
1092 		sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1093 		    XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1094 		    XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1095 	if (did == TC_DEVICEID_HURRICANE_555 ||
1096 	    did == TC_DEVICEID_HURRICANE_556)
1097 		sc->xl_flags |= XL_FLAG_8BITROM;
1098 	if (did == TC_DEVICEID_HURRICANE_556B)
1099 		sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1100 
1101 	if (did == TC_DEVICEID_HURRICANE_575B ||
1102 	    did == TC_DEVICEID_HURRICANE_575C ||
1103 	    did == TC_DEVICEID_HURRICANE_656B ||
1104 	    did == TC_DEVICEID_TORNADO_656C)
1105 		sc->xl_flags |= XL_FLAG_FUNCREG;
1106 	if (did == TC_DEVICEID_HURRICANE_575A ||
1107 	    did == TC_DEVICEID_HURRICANE_575B ||
1108 	    did == TC_DEVICEID_HURRICANE_575C ||
1109 	    did == TC_DEVICEID_HURRICANE_656B ||
1110 	    did == TC_DEVICEID_TORNADO_656C)
1111 		sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1112 		  XL_FLAG_8BITROM;
1113 	if (did == TC_DEVICEID_HURRICANE_656)
1114 		sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1115 	if (did == TC_DEVICEID_HURRICANE_575B)
1116 		sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1117 	if (did == TC_DEVICEID_HURRICANE_575C)
1118 		sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1119 	if (did == TC_DEVICEID_TORNADO_656C)
1120 		sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1121 	if (did == TC_DEVICEID_HURRICANE_656 ||
1122 	    did == TC_DEVICEID_HURRICANE_656B)
1123 		sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1124 		    XL_FLAG_INVERT_LED_PWR;
1125 	if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1126 	    did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1127 		sc->xl_flags |= XL_FLAG_PHYOK;
1128 
1129 	switch (did) {
1130 	case TC_DEVICEID_BOOMERANG_10_100BT:	/* 3c905-TX */
1131 	case TC_DEVICEID_HURRICANE_575A:
1132 	case TC_DEVICEID_HURRICANE_575B:
1133 	case TC_DEVICEID_HURRICANE_575C:
1134 		sc->xl_flags |= XL_FLAG_NO_MMIO;
1135 		break;
1136 	default:
1137 		break;
1138 	}
1139 
1140 	/*
1141 	 * Map control/status registers.
1142 	 */
1143 	pci_enable_busmaster(dev);
1144 
1145 	if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1146 		rid = XL_PCI_LOMEM;
1147 		res = SYS_RES_MEMORY;
1148 
1149 		sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1150 	}
1151 
1152 	if (sc->xl_res != NULL) {
1153 		sc->xl_flags |= XL_FLAG_USE_MMIO;
1154 		if (bootverbose)
1155 			device_printf(dev, "using memory mapped I/O\n");
1156 	} else {
1157 		rid = XL_PCI_LOIO;
1158 		res = SYS_RES_IOPORT;
1159 		sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1160 		if (sc->xl_res == NULL) {
1161 			device_printf(dev, "couldn't map ports/memory\n");
1162 			error = ENXIO;
1163 			goto fail;
1164 		}
1165 		if (bootverbose)
1166 			device_printf(dev, "using port I/O\n");
1167 	}
1168 
1169 	sc->xl_btag = rman_get_bustag(sc->xl_res);
1170 	sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1171 
1172 	if (sc->xl_flags & XL_FLAG_FUNCREG) {
1173 		rid = XL_PCI_FUNCMEM;
1174 		sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1175 		    RF_ACTIVE);
1176 
1177 		if (sc->xl_fres == NULL) {
1178 			device_printf(dev, "couldn't map funcreg memory\n");
1179 			error = ENXIO;
1180 			goto fail;
1181 		}
1182 
1183 		sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1184 		sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1185 	}
1186 
1187 	/* Allocate interrupt */
1188 	rid = 0;
1189 	sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1190 	    RF_SHAREABLE | RF_ACTIVE);
1191 	if (sc->xl_irq == NULL) {
1192 		device_printf(dev, "couldn't map interrupt\n");
1193 		error = ENXIO;
1194 		goto fail;
1195 	}
1196 
1197 	/* Initialize interface name. */
1198 	ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1199 	if (ifp == NULL) {
1200 		device_printf(dev, "can not if_alloc()\n");
1201 		error = ENOSPC;
1202 		goto fail;
1203 	}
1204 	ifp->if_softc = sc;
1205 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1206 
1207 	/* Reset the adapter. */
1208 	XL_LOCK(sc);
1209 	xl_reset(sc);
1210 	XL_UNLOCK(sc);
1211 
1212 	/*
1213 	 * Get station address from the EEPROM.
1214 	 */
1215 	if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1216 		device_printf(dev, "failed to read station address\n");
1217 		error = ENXIO;
1218 		goto fail;
1219 	}
1220 
1221 	callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0);
1222 	TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1223 
1224 	/*
1225 	 * Now allocate a tag for the DMA descriptor lists and a chunk
1226 	 * of DMA-able memory based on the tag.  Also obtain the DMA
1227 	 * addresses of the RX and TX ring, which we'll need later.
1228 	 * All of our lists are allocated as a contiguous block
1229 	 * of memory.
1230 	 */
1231 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1232 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1233 	    XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1234 	    &sc->xl_ldata.xl_rx_tag);
1235 	if (error) {
1236 		device_printf(dev, "failed to allocate rx dma tag\n");
1237 		goto fail;
1238 	}
1239 
1240 	error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1241 	    (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT |
1242 	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap);
1243 	if (error) {
1244 		device_printf(dev, "no memory for rx list buffers!\n");
1245 		bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1246 		sc->xl_ldata.xl_rx_tag = NULL;
1247 		goto fail;
1248 	}
1249 
1250 	error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1251 	    sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1252 	    XL_RX_LIST_SZ, xl_dma_map_addr,
1253 	    &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1254 	if (error) {
1255 		device_printf(dev, "cannot get dma address of the rx ring!\n");
1256 		bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1257 		    sc->xl_ldata.xl_rx_dmamap);
1258 		bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1259 		sc->xl_ldata.xl_rx_tag = NULL;
1260 		goto fail;
1261 	}
1262 
1263 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1264 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1265 	    XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1266 	    &sc->xl_ldata.xl_tx_tag);
1267 	if (error) {
1268 		device_printf(dev, "failed to allocate tx dma tag\n");
1269 		goto fail;
1270 	}
1271 
1272 	error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1273 	    (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT |
1274 	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap);
1275 	if (error) {
1276 		device_printf(dev, "no memory for list buffers!\n");
1277 		bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1278 		sc->xl_ldata.xl_tx_tag = NULL;
1279 		goto fail;
1280 	}
1281 
1282 	error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1283 	    sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1284 	    XL_TX_LIST_SZ, xl_dma_map_addr,
1285 	    &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1286 	if (error) {
1287 		device_printf(dev, "cannot get dma address of the tx ring!\n");
1288 		bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1289 		    sc->xl_ldata.xl_tx_dmamap);
1290 		bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1291 		sc->xl_ldata.xl_tx_tag = NULL;
1292 		goto fail;
1293 	}
1294 
1295 	/*
1296 	 * Allocate a DMA tag for the mapping of mbufs.
1297 	 */
1298 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1299 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1300 	    MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1301 	    NULL, &sc->xl_mtag);
1302 	if (error) {
1303 		device_printf(dev, "failed to allocate mbuf dma tag\n");
1304 		goto fail;
1305 	}
1306 
1307 	/* We need a spare DMA map for the RX ring. */
1308 	error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1309 	if (error)
1310 		goto fail;
1311 
1312 	/*
1313 	 * Figure out the card type. 3c905B adapters have the
1314 	 * 'supportsNoTxLength' bit set in the capabilities
1315 	 * word in the EEPROM.
1316 	 * Note: my 3c575C CardBus card lies. It returns a value
1317 	 * of 0x1578 for its capabilities word, which is somewhat
1318 	 * nonsensical. Another way to distinguish a 3c90x chip
1319 	 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1320 	 * bit. This will only be set for 3c90x boomerage chips.
1321 	 */
1322 	xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1323 	if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1324 	    !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1325 		sc->xl_type = XL_TYPE_905B;
1326 	else
1327 		sc->xl_type = XL_TYPE_90X;
1328 
1329 	/* Check availability of WOL. */
1330 	if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 &&
1331 	    pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) {
1332 		sc->xl_pmcap = pmcap;
1333 		sc->xl_flags |= XL_FLAG_WOL;
1334 		sinfo2 = 0;
1335 		xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0);
1336 		if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose)
1337 			device_printf(dev,
1338 			    "No auxiliary remote wakeup connector!\n");
1339 	}
1340 
1341 	/* Set the TX start threshold for best performance. */
1342 	sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1343 
1344 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1345 	ifp->if_ioctl = xl_ioctl;
1346 	ifp->if_capabilities = IFCAP_VLAN_MTU;
1347 	if (sc->xl_type == XL_TYPE_905B) {
1348 		ifp->if_hwassist = XL905B_CSUM_FEATURES;
1349 #ifdef XL905B_TXCSUM_BROKEN
1350 		ifp->if_capabilities |= IFCAP_RXCSUM;
1351 #else
1352 		ifp->if_capabilities |= IFCAP_HWCSUM;
1353 #endif
1354 	}
1355 	if ((sc->xl_flags & XL_FLAG_WOL) != 0)
1356 		ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1357 	ifp->if_capenable = ifp->if_capabilities;
1358 #ifdef DEVICE_POLLING
1359 	ifp->if_capabilities |= IFCAP_POLLING;
1360 #endif
1361 	ifp->if_start = xl_start;
1362 	ifp->if_init = xl_init;
1363 	IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1364 	ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1365 	IFQ_SET_READY(&ifp->if_snd);
1366 
1367 	/*
1368 	 * Now we have to see what sort of media we have.
1369 	 * This includes probing for an MII interace and a
1370 	 * possible PHY.
1371 	 */
1372 	XL_SEL_WIN(3);
1373 	sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1374 	if (bootverbose)
1375 		device_printf(dev, "media options word: %x\n", sc->xl_media);
1376 
1377 	xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1378 	sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1379 	sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1380 	sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1381 
1382 	xl_mediacheck(sc);
1383 
1384 	if (sc->xl_media & XL_MEDIAOPT_MII ||
1385 	    sc->xl_media & XL_MEDIAOPT_BTX ||
1386 	    sc->xl_media & XL_MEDIAOPT_BT4) {
1387 		if (bootverbose)
1388 			device_printf(dev, "found MII/AUTO\n");
1389 		xl_setcfg(sc);
1390 		/*
1391 		 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK.
1392 		 * This is to guard against problems with certain 3Com ASIC
1393 		 * revisions that incorrectly map the internal transceiver
1394 		 * control registers at all MII addresses.
1395 		 */
1396 		phy = MII_PHY_ANY;
1397 		if ((sc->xl_flags & XL_FLAG_PHYOK) == 0)
1398 			phy = 24;
1399 		error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd,
1400 		    xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
1401 		    sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0);
1402 		if (error != 0) {
1403 			device_printf(dev, "attaching PHYs failed\n");
1404 			goto fail;
1405 		}
1406 		goto done;
1407 	}
1408 
1409 	/*
1410 	 * Sanity check. If the user has selected "auto" and this isn't
1411 	 * a 10/100 card of some kind, we need to force the transceiver
1412 	 * type to something sane.
1413 	 */
1414 	if (sc->xl_xcvr == XL_XCVR_AUTO)
1415 		xl_choose_xcvr(sc, bootverbose);
1416 
1417 	/*
1418 	 * Do ifmedia setup.
1419 	 */
1420 	if (sc->xl_media & XL_MEDIAOPT_BT) {
1421 		if (bootverbose)
1422 			device_printf(dev, "found 10baseT\n");
1423 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1424 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1425 		if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1426 			ifmedia_add(&sc->ifmedia,
1427 			    IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1428 	}
1429 
1430 	if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1431 		/*
1432 		 * Check for a 10baseFL board in disguise.
1433 		 */
1434 		if (sc->xl_type == XL_TYPE_905B &&
1435 		    sc->xl_media == XL_MEDIAOPT_10FL) {
1436 			if (bootverbose)
1437 				device_printf(dev, "found 10baseFL\n");
1438 			ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1439 			ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1440 			    0, NULL);
1441 			if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1442 				ifmedia_add(&sc->ifmedia,
1443 				    IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1444 		} else {
1445 			if (bootverbose)
1446 				device_printf(dev, "found AUI\n");
1447 			ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1448 		}
1449 	}
1450 
1451 	if (sc->xl_media & XL_MEDIAOPT_BNC) {
1452 		if (bootverbose)
1453 			device_printf(dev, "found BNC\n");
1454 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1455 	}
1456 
1457 	if (sc->xl_media & XL_MEDIAOPT_BFX) {
1458 		if (bootverbose)
1459 			device_printf(dev, "found 100baseFX\n");
1460 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1461 	}
1462 
1463 	media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1464 	xl_choose_media(sc, &media);
1465 
1466 	if (sc->xl_miibus == NULL)
1467 		ifmedia_set(&sc->ifmedia, media);
1468 
1469 done:
1470 	if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1471 		XL_SEL_WIN(0);
1472 		CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1473 	}
1474 
1475 	/*
1476 	 * Call MI attach routine.
1477 	 */
1478 	ether_ifattach(ifp, eaddr);
1479 
1480 	error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1481 	    NULL, xl_intr, sc, &sc->xl_intrhand);
1482 	if (error) {
1483 		device_printf(dev, "couldn't set up irq\n");
1484 		ether_ifdetach(ifp);
1485 		goto fail;
1486 	}
1487 
1488 fail:
1489 	if (error)
1490 		xl_detach(dev);
1491 
1492 	return (error);
1493 }
1494 
1495 /*
1496  * Choose a default media.
1497  * XXX This is a leaf function only called by xl_attach() and
1498  *     acquires/releases the non-recursible driver mutex to
1499  *     satisfy lock assertions.
1500  */
1501 static void
1502 xl_choose_media(struct xl_softc *sc, int *media)
1503 {
1504 
1505 	XL_LOCK(sc);
1506 
1507 	switch (sc->xl_xcvr) {
1508 	case XL_XCVR_10BT:
1509 		*media = IFM_ETHER|IFM_10_T;
1510 		xl_setmode(sc, *media);
1511 		break;
1512 	case XL_XCVR_AUI:
1513 		if (sc->xl_type == XL_TYPE_905B &&
1514 		    sc->xl_media == XL_MEDIAOPT_10FL) {
1515 			*media = IFM_ETHER|IFM_10_FL;
1516 			xl_setmode(sc, *media);
1517 		} else {
1518 			*media = IFM_ETHER|IFM_10_5;
1519 			xl_setmode(sc, *media);
1520 		}
1521 		break;
1522 	case XL_XCVR_COAX:
1523 		*media = IFM_ETHER|IFM_10_2;
1524 		xl_setmode(sc, *media);
1525 		break;
1526 	case XL_XCVR_AUTO:
1527 	case XL_XCVR_100BTX:
1528 	case XL_XCVR_MII:
1529 		/* Chosen by miibus */
1530 		break;
1531 	case XL_XCVR_100BFX:
1532 		*media = IFM_ETHER|IFM_100_FX;
1533 		break;
1534 	default:
1535 		device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1536 		    sc->xl_xcvr);
1537 		/*
1538 		 * This will probably be wrong, but it prevents
1539 		 * the ifmedia code from panicking.
1540 		 */
1541 		*media = IFM_ETHER|IFM_10_T;
1542 		break;
1543 	}
1544 
1545 	XL_UNLOCK(sc);
1546 }
1547 
1548 /*
1549  * Shutdown hardware and free up resources. This can be called any
1550  * time after the mutex has been initialized. It is called in both
1551  * the error case in attach and the normal detach case so it needs
1552  * to be careful about only freeing resources that have actually been
1553  * allocated.
1554  */
1555 static int
1556 xl_detach(device_t dev)
1557 {
1558 	struct xl_softc		*sc;
1559 	struct ifnet		*ifp;
1560 	int			rid, res;
1561 
1562 	sc = device_get_softc(dev);
1563 	ifp = sc->xl_ifp;
1564 
1565 	KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1566 
1567 #ifdef DEVICE_POLLING
1568 	if (ifp && ifp->if_capenable & IFCAP_POLLING)
1569 		ether_poll_deregister(ifp);
1570 #endif
1571 
1572 	if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1573 		rid = XL_PCI_LOMEM;
1574 		res = SYS_RES_MEMORY;
1575 	} else {
1576 		rid = XL_PCI_LOIO;
1577 		res = SYS_RES_IOPORT;
1578 	}
1579 
1580 	/* These should only be active if attach succeeded */
1581 	if (device_is_attached(dev)) {
1582 		XL_LOCK(sc);
1583 		xl_stop(sc);
1584 		XL_UNLOCK(sc);
1585 		taskqueue_drain(taskqueue_swi, &sc->xl_task);
1586 		callout_drain(&sc->xl_tick_callout);
1587 		ether_ifdetach(ifp);
1588 	}
1589 	if (sc->xl_miibus)
1590 		device_delete_child(dev, sc->xl_miibus);
1591 	bus_generic_detach(dev);
1592 	ifmedia_removeall(&sc->ifmedia);
1593 
1594 	if (sc->xl_intrhand)
1595 		bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1596 	if (sc->xl_irq)
1597 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1598 	if (sc->xl_fres != NULL)
1599 		bus_release_resource(dev, SYS_RES_MEMORY,
1600 		    XL_PCI_FUNCMEM, sc->xl_fres);
1601 	if (sc->xl_res)
1602 		bus_release_resource(dev, res, rid, sc->xl_res);
1603 
1604 	if (ifp)
1605 		if_free(ifp);
1606 
1607 	if (sc->xl_mtag) {
1608 		bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1609 		bus_dma_tag_destroy(sc->xl_mtag);
1610 	}
1611 	if (sc->xl_ldata.xl_rx_tag) {
1612 		bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1613 		    sc->xl_ldata.xl_rx_dmamap);
1614 		bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1615 		    sc->xl_ldata.xl_rx_dmamap);
1616 		bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1617 	}
1618 	if (sc->xl_ldata.xl_tx_tag) {
1619 		bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1620 		    sc->xl_ldata.xl_tx_dmamap);
1621 		bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1622 		    sc->xl_ldata.xl_tx_dmamap);
1623 		bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1624 	}
1625 
1626 	mtx_destroy(&sc->xl_mtx);
1627 
1628 	return (0);
1629 }
1630 
1631 /*
1632  * Initialize the transmit descriptors.
1633  */
1634 static int
1635 xl_list_tx_init(struct xl_softc *sc)
1636 {
1637 	struct xl_chain_data	*cd;
1638 	struct xl_list_data	*ld;
1639 	int			error, i;
1640 
1641 	XL_LOCK_ASSERT(sc);
1642 
1643 	cd = &sc->xl_cdata;
1644 	ld = &sc->xl_ldata;
1645 	for (i = 0; i < XL_TX_LIST_CNT; i++) {
1646 		cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1647 		error = bus_dmamap_create(sc->xl_mtag, 0,
1648 		    &cd->xl_tx_chain[i].xl_map);
1649 		if (error)
1650 			return (error);
1651 		cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1652 		    i * sizeof(struct xl_list);
1653 		if (i == (XL_TX_LIST_CNT - 1))
1654 			cd->xl_tx_chain[i].xl_next = NULL;
1655 		else
1656 			cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1657 	}
1658 
1659 	cd->xl_tx_free = &cd->xl_tx_chain[0];
1660 	cd->xl_tx_tail = cd->xl_tx_head = NULL;
1661 
1662 	bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1663 	return (0);
1664 }
1665 
1666 /*
1667  * Initialize the transmit descriptors.
1668  */
1669 static int
1670 xl_list_tx_init_90xB(struct xl_softc *sc)
1671 {
1672 	struct xl_chain_data	*cd;
1673 	struct xl_list_data	*ld;
1674 	int			error, i;
1675 
1676 	XL_LOCK_ASSERT(sc);
1677 
1678 	cd = &sc->xl_cdata;
1679 	ld = &sc->xl_ldata;
1680 	for (i = 0; i < XL_TX_LIST_CNT; i++) {
1681 		cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1682 		error = bus_dmamap_create(sc->xl_mtag, 0,
1683 		    &cd->xl_tx_chain[i].xl_map);
1684 		if (error)
1685 			return (error);
1686 		cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1687 		    i * sizeof(struct xl_list);
1688 		if (i == (XL_TX_LIST_CNT - 1))
1689 			cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1690 		else
1691 			cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1692 		if (i == 0)
1693 			cd->xl_tx_chain[i].xl_prev =
1694 			    &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1695 		else
1696 			cd->xl_tx_chain[i].xl_prev =
1697 			    &cd->xl_tx_chain[i - 1];
1698 	}
1699 
1700 	bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1701 	ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1702 
1703 	cd->xl_tx_prod = 1;
1704 	cd->xl_tx_cons = 1;
1705 	cd->xl_tx_cnt = 0;
1706 
1707 	bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1708 	return (0);
1709 }
1710 
1711 /*
1712  * Initialize the RX descriptors and allocate mbufs for them. Note that
1713  * we arrange the descriptors in a closed ring, so that the last descriptor
1714  * points back to the first.
1715  */
1716 static int
1717 xl_list_rx_init(struct xl_softc *sc)
1718 {
1719 	struct xl_chain_data	*cd;
1720 	struct xl_list_data	*ld;
1721 	int			error, i, next;
1722 	u_int32_t		nextptr;
1723 
1724 	XL_LOCK_ASSERT(sc);
1725 
1726 	cd = &sc->xl_cdata;
1727 	ld = &sc->xl_ldata;
1728 
1729 	for (i = 0; i < XL_RX_LIST_CNT; i++) {
1730 		cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1731 		error = bus_dmamap_create(sc->xl_mtag, 0,
1732 		    &cd->xl_rx_chain[i].xl_map);
1733 		if (error)
1734 			return (error);
1735 		error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1736 		if (error)
1737 			return (error);
1738 		if (i == (XL_RX_LIST_CNT - 1))
1739 			next = 0;
1740 		else
1741 			next = i + 1;
1742 		nextptr = ld->xl_rx_dmaaddr +
1743 		    next * sizeof(struct xl_list_onefrag);
1744 		cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1745 		ld->xl_rx_list[i].xl_next = htole32(nextptr);
1746 	}
1747 
1748 	bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1749 	cd->xl_rx_head = &cd->xl_rx_chain[0];
1750 
1751 	return (0);
1752 }
1753 
1754 /*
1755  * Initialize an RX descriptor and attach an MBUF cluster.
1756  * If we fail to do so, we need to leave the old mbuf and
1757  * the old DMA map untouched so that it can be reused.
1758  */
1759 static int
1760 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1761 {
1762 	struct mbuf		*m_new = NULL;
1763 	bus_dmamap_t		map;
1764 	bus_dma_segment_t	segs[1];
1765 	int			error, nseg;
1766 
1767 	XL_LOCK_ASSERT(sc);
1768 
1769 	m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1770 	if (m_new == NULL)
1771 		return (ENOBUFS);
1772 
1773 	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1774 
1775 	/* Force longword alignment for packet payload. */
1776 	m_adj(m_new, ETHER_ALIGN);
1777 
1778 	error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new,
1779 	    segs, &nseg, BUS_DMA_NOWAIT);
1780 	if (error) {
1781 		m_freem(m_new);
1782 		device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1783 		    error);
1784 		return (error);
1785 	}
1786 	KASSERT(nseg == 1,
1787 	    ("%s: too many DMA segments (%d)", __func__, nseg));
1788 
1789 	bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1790 	map = c->xl_map;
1791 	c->xl_map = sc->xl_tmpmap;
1792 	sc->xl_tmpmap = map;
1793 	c->xl_mbuf = m_new;
1794 	c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1795 	c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr);
1796 	c->xl_ptr->xl_status = 0;
1797 	bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1798 	return (0);
1799 }
1800 
1801 static int
1802 xl_rx_resync(struct xl_softc *sc)
1803 {
1804 	struct xl_chain_onefrag	*pos;
1805 	int			i;
1806 
1807 	XL_LOCK_ASSERT(sc);
1808 
1809 	pos = sc->xl_cdata.xl_rx_head;
1810 
1811 	for (i = 0; i < XL_RX_LIST_CNT; i++) {
1812 		if (pos->xl_ptr->xl_status)
1813 			break;
1814 		pos = pos->xl_next;
1815 	}
1816 
1817 	if (i == XL_RX_LIST_CNT)
1818 		return (0);
1819 
1820 	sc->xl_cdata.xl_rx_head = pos;
1821 
1822 	return (EAGAIN);
1823 }
1824 
1825 /*
1826  * A frame has been uploaded: pass the resulting mbuf chain up to
1827  * the higher level protocols.
1828  */
1829 static int
1830 xl_rxeof(struct xl_softc *sc)
1831 {
1832 	struct mbuf		*m;
1833 	struct ifnet		*ifp = sc->xl_ifp;
1834 	struct xl_chain_onefrag	*cur_rx;
1835 	int			total_len;
1836 	int			rx_npkts = 0;
1837 	u_int32_t		rxstat;
1838 
1839 	XL_LOCK_ASSERT(sc);
1840 again:
1841 	bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1842 	    BUS_DMASYNC_POSTREAD);
1843 	while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1844 #ifdef DEVICE_POLLING
1845 		if (ifp->if_capenable & IFCAP_POLLING) {
1846 			if (sc->rxcycles <= 0)
1847 				break;
1848 			sc->rxcycles--;
1849 		}
1850 #endif
1851 		cur_rx = sc->xl_cdata.xl_rx_head;
1852 		sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1853 		total_len = rxstat & XL_RXSTAT_LENMASK;
1854 		rx_npkts++;
1855 
1856 		/*
1857 		 * Since we have told the chip to allow large frames,
1858 		 * we need to trap giant frame errors in software. We allow
1859 		 * a little more than the normal frame size to account for
1860 		 * frames with VLAN tags.
1861 		 */
1862 		if (total_len > XL_MAX_FRAMELEN)
1863 			rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1864 
1865 		/*
1866 		 * If an error occurs, update stats, clear the
1867 		 * status word and leave the mbuf cluster in place:
1868 		 * it should simply get re-used next time this descriptor
1869 		 * comes up in the ring.
1870 		 */
1871 		if (rxstat & XL_RXSTAT_UP_ERROR) {
1872 			if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1873 			cur_rx->xl_ptr->xl_status = 0;
1874 			bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1875 			    sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1876 			continue;
1877 		}
1878 
1879 		/*
1880 		 * If the error bit was not set, the upload complete
1881 		 * bit should be set which means we have a valid packet.
1882 		 * If not, something truly strange has happened.
1883 		 */
1884 		if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1885 			device_printf(sc->xl_dev,
1886 			    "bad receive status -- packet dropped\n");
1887 			if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1888 			cur_rx->xl_ptr->xl_status = 0;
1889 			bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1890 			    sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1891 			continue;
1892 		}
1893 
1894 		/* No errors; receive the packet. */
1895 		bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
1896 		    BUS_DMASYNC_POSTREAD);
1897 		m = cur_rx->xl_mbuf;
1898 
1899 		/*
1900 		 * Try to conjure up a new mbuf cluster. If that
1901 		 * fails, it means we have an out of memory condition and
1902 		 * should leave the buffer in place and continue. This will
1903 		 * result in a lost packet, but there's little else we
1904 		 * can do in this situation.
1905 		 */
1906 		if (xl_newbuf(sc, cur_rx)) {
1907 			if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1908 			cur_rx->xl_ptr->xl_status = 0;
1909 			bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1910 			    sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1911 			continue;
1912 		}
1913 		bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1914 		    sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1915 
1916 		if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1917 		m->m_pkthdr.rcvif = ifp;
1918 		m->m_pkthdr.len = m->m_len = total_len;
1919 
1920 		if (ifp->if_capenable & IFCAP_RXCSUM) {
1921 			/* Do IP checksum checking. */
1922 			if (rxstat & XL_RXSTAT_IPCKOK)
1923 				m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1924 			if (!(rxstat & XL_RXSTAT_IPCKERR))
1925 				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1926 			if ((rxstat & XL_RXSTAT_TCPCOK &&
1927 			     !(rxstat & XL_RXSTAT_TCPCKERR)) ||
1928 			    (rxstat & XL_RXSTAT_UDPCKOK &&
1929 			     !(rxstat & XL_RXSTAT_UDPCKERR))) {
1930 				m->m_pkthdr.csum_flags |=
1931 					CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1932 				m->m_pkthdr.csum_data = 0xffff;
1933 			}
1934 		}
1935 
1936 		XL_UNLOCK(sc);
1937 		(*ifp->if_input)(ifp, m);
1938 		XL_LOCK(sc);
1939 
1940 		/*
1941 		 * If we are running from the taskqueue, the interface
1942 		 * might have been stopped while we were passing the last
1943 		 * packet up the network stack.
1944 		 */
1945 		if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1946 			return (rx_npkts);
1947 	}
1948 
1949 	/*
1950 	 * Handle the 'end of channel' condition. When the upload
1951 	 * engine hits the end of the RX ring, it will stall. This
1952 	 * is our cue to flush the RX ring, reload the uplist pointer
1953 	 * register and unstall the engine.
1954 	 * XXX This is actually a little goofy. With the ThunderLAN
1955 	 * chip, you get an interrupt when the receiver hits the end
1956 	 * of the receive ring, which tells you exactly when you
1957 	 * you need to reload the ring pointer. Here we have to
1958 	 * fake it. I'm mad at myself for not being clever enough
1959 	 * to avoid the use of a goto here.
1960 	 */
1961 	if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1962 		CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1963 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1964 		xl_wait(sc);
1965 		CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
1966 		sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1967 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1968 		goto again;
1969 	}
1970 	return (rx_npkts);
1971 }
1972 
1973 /*
1974  * Taskqueue wrapper for xl_rxeof().
1975  */
1976 static void
1977 xl_rxeof_task(void *arg, int pending)
1978 {
1979 	struct xl_softc *sc = (struct xl_softc *)arg;
1980 
1981 	XL_LOCK(sc);
1982 	if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
1983 		xl_rxeof(sc);
1984 	XL_UNLOCK(sc);
1985 }
1986 
1987 /*
1988  * A frame was downloaded to the chip. It's safe for us to clean up
1989  * the list buffers.
1990  */
1991 static void
1992 xl_txeof(struct xl_softc *sc)
1993 {
1994 	struct xl_chain		*cur_tx;
1995 	struct ifnet		*ifp = sc->xl_ifp;
1996 
1997 	XL_LOCK_ASSERT(sc);
1998 
1999 	/*
2000 	 * Go through our tx list and free mbufs for those
2001 	 * frames that have been uploaded. Note: the 3c905B
2002 	 * sets a special bit in the status word to let us
2003 	 * know that a frame has been downloaded, but the
2004 	 * original 3c900/3c905 adapters don't do that.
2005 	 * Consequently, we have to use a different test if
2006 	 * xl_type != XL_TYPE_905B.
2007 	 */
2008 	while (sc->xl_cdata.xl_tx_head != NULL) {
2009 		cur_tx = sc->xl_cdata.xl_tx_head;
2010 
2011 		if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2012 			break;
2013 
2014 		sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2015 		bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2016 		    BUS_DMASYNC_POSTWRITE);
2017 		bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2018 		m_freem(cur_tx->xl_mbuf);
2019 		cur_tx->xl_mbuf = NULL;
2020 		if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2021 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2022 
2023 		cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2024 		sc->xl_cdata.xl_tx_free = cur_tx;
2025 	}
2026 
2027 	if (sc->xl_cdata.xl_tx_head == NULL) {
2028 		sc->xl_wdog_timer = 0;
2029 		sc->xl_cdata.xl_tx_tail = NULL;
2030 	} else {
2031 		if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2032 			!CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2033 			CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2034 				sc->xl_cdata.xl_tx_head->xl_phys);
2035 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2036 		}
2037 	}
2038 }
2039 
2040 static void
2041 xl_txeof_90xB(struct xl_softc *sc)
2042 {
2043 	struct xl_chain		*cur_tx = NULL;
2044 	struct ifnet		*ifp = sc->xl_ifp;
2045 	int			idx;
2046 
2047 	XL_LOCK_ASSERT(sc);
2048 
2049 	bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2050 	    BUS_DMASYNC_POSTREAD);
2051 	idx = sc->xl_cdata.xl_tx_cons;
2052 	while (idx != sc->xl_cdata.xl_tx_prod) {
2053 		cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2054 
2055 		if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2056 		      XL_TXSTAT_DL_COMPLETE))
2057 			break;
2058 
2059 		if (cur_tx->xl_mbuf != NULL) {
2060 			bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2061 			    BUS_DMASYNC_POSTWRITE);
2062 			bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2063 			m_freem(cur_tx->xl_mbuf);
2064 			cur_tx->xl_mbuf = NULL;
2065 		}
2066 
2067 		if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2068 
2069 		sc->xl_cdata.xl_tx_cnt--;
2070 		XL_INC(idx, XL_TX_LIST_CNT);
2071 	}
2072 
2073 	if (sc->xl_cdata.xl_tx_cnt == 0)
2074 		sc->xl_wdog_timer = 0;
2075 	sc->xl_cdata.xl_tx_cons = idx;
2076 
2077 	if (cur_tx != NULL)
2078 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2079 }
2080 
2081 /*
2082  * TX 'end of channel' interrupt handler. Actually, we should
2083  * only get a 'TX complete' interrupt if there's a transmit error,
2084  * so this is really TX error handler.
2085  */
2086 static void
2087 xl_txeoc(struct xl_softc *sc)
2088 {
2089 	u_int8_t		txstat;
2090 
2091 	XL_LOCK_ASSERT(sc);
2092 
2093 	while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2094 		if (txstat & XL_TXSTATUS_UNDERRUN ||
2095 			txstat & XL_TXSTATUS_JABBER ||
2096 			txstat & XL_TXSTATUS_RECLAIM) {
2097 			device_printf(sc->xl_dev,
2098 			    "transmission error: 0x%02x\n", txstat);
2099 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2100 			xl_wait(sc);
2101 			if (sc->xl_type == XL_TYPE_905B) {
2102 				if (sc->xl_cdata.xl_tx_cnt) {
2103 					int			i;
2104 					struct xl_chain		*c;
2105 
2106 					i = sc->xl_cdata.xl_tx_cons;
2107 					c = &sc->xl_cdata.xl_tx_chain[i];
2108 					CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2109 					    c->xl_phys);
2110 					CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2111 					sc->xl_wdog_timer = 5;
2112 				}
2113 			} else {
2114 				if (sc->xl_cdata.xl_tx_head != NULL) {
2115 					CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2116 					    sc->xl_cdata.xl_tx_head->xl_phys);
2117 					sc->xl_wdog_timer = 5;
2118 				}
2119 			}
2120 			/*
2121 			 * Remember to set this for the
2122 			 * first generation 3c90X chips.
2123 			 */
2124 			CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2125 			if (txstat & XL_TXSTATUS_UNDERRUN &&
2126 			    sc->xl_tx_thresh < XL_PACKET_SIZE) {
2127 				sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2128 				device_printf(sc->xl_dev,
2129 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2130 			}
2131 			CSR_WRITE_2(sc, XL_COMMAND,
2132 			    XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2133 			if (sc->xl_type == XL_TYPE_905B) {
2134 				CSR_WRITE_2(sc, XL_COMMAND,
2135 				XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2136 			}
2137 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2138 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2139 		} else {
2140 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2141 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2142 		}
2143 		/*
2144 		 * Write an arbitrary byte to the TX_STATUS register
2145 		 * to clear this interrupt/error and advance to the next.
2146 		 */
2147 		CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2148 	}
2149 }
2150 
2151 static void
2152 xl_intr(void *arg)
2153 {
2154 	struct xl_softc		*sc = arg;
2155 	struct ifnet		*ifp = sc->xl_ifp;
2156 	u_int16_t		status;
2157 
2158 	XL_LOCK(sc);
2159 
2160 #ifdef DEVICE_POLLING
2161 	if (ifp->if_capenable & IFCAP_POLLING) {
2162 		XL_UNLOCK(sc);
2163 		return;
2164 	}
2165 #endif
2166 
2167 	for (;;) {
2168 		status = CSR_READ_2(sc, XL_STATUS);
2169 		if ((status & XL_INTRS) == 0 || status == 0xFFFF)
2170 			break;
2171 		CSR_WRITE_2(sc, XL_COMMAND,
2172 		    XL_CMD_INTR_ACK|(status & XL_INTRS));
2173 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2174 			break;
2175 
2176 		if (status & XL_STAT_UP_COMPLETE) {
2177 			if (xl_rxeof(sc) == 0) {
2178 				while (xl_rx_resync(sc))
2179 					xl_rxeof(sc);
2180 			}
2181 		}
2182 
2183 		if (status & XL_STAT_DOWN_COMPLETE) {
2184 			if (sc->xl_type == XL_TYPE_905B)
2185 				xl_txeof_90xB(sc);
2186 			else
2187 				xl_txeof(sc);
2188 		}
2189 
2190 		if (status & XL_STAT_TX_COMPLETE) {
2191 			if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2192 			xl_txeoc(sc);
2193 		}
2194 
2195 		if (status & XL_STAT_ADFAIL) {
2196 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2197 			xl_init_locked(sc);
2198 			break;
2199 		}
2200 
2201 		if (status & XL_STAT_STATSOFLOW)
2202 			xl_stats_update(sc);
2203 	}
2204 
2205 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2206 	    ifp->if_drv_flags & IFF_DRV_RUNNING) {
2207 		if (sc->xl_type == XL_TYPE_905B)
2208 			xl_start_90xB_locked(ifp);
2209 		else
2210 			xl_start_locked(ifp);
2211 	}
2212 
2213 	XL_UNLOCK(sc);
2214 }
2215 
2216 #ifdef DEVICE_POLLING
2217 static int
2218 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2219 {
2220 	struct xl_softc *sc = ifp->if_softc;
2221 	int rx_npkts = 0;
2222 
2223 	XL_LOCK(sc);
2224 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2225 		rx_npkts = xl_poll_locked(ifp, cmd, count);
2226 	XL_UNLOCK(sc);
2227 	return (rx_npkts);
2228 }
2229 
2230 static int
2231 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2232 {
2233 	struct xl_softc *sc = ifp->if_softc;
2234 	int rx_npkts;
2235 
2236 	XL_LOCK_ASSERT(sc);
2237 
2238 	sc->rxcycles = count;
2239 	rx_npkts = xl_rxeof(sc);
2240 	if (sc->xl_type == XL_TYPE_905B)
2241 		xl_txeof_90xB(sc);
2242 	else
2243 		xl_txeof(sc);
2244 
2245 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2246 		if (sc->xl_type == XL_TYPE_905B)
2247 			xl_start_90xB_locked(ifp);
2248 		else
2249 			xl_start_locked(ifp);
2250 	}
2251 
2252 	if (cmd == POLL_AND_CHECK_STATUS) {
2253 		u_int16_t status;
2254 
2255 		status = CSR_READ_2(sc, XL_STATUS);
2256 		if (status & XL_INTRS && status != 0xFFFF) {
2257 			CSR_WRITE_2(sc, XL_COMMAND,
2258 			    XL_CMD_INTR_ACK|(status & XL_INTRS));
2259 
2260 			if (status & XL_STAT_TX_COMPLETE) {
2261 				if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2262 				xl_txeoc(sc);
2263 			}
2264 
2265 			if (status & XL_STAT_ADFAIL) {
2266 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2267 				xl_init_locked(sc);
2268 			}
2269 
2270 			if (status & XL_STAT_STATSOFLOW)
2271 				xl_stats_update(sc);
2272 		}
2273 	}
2274 	return (rx_npkts);
2275 }
2276 #endif /* DEVICE_POLLING */
2277 
2278 static void
2279 xl_tick(void *xsc)
2280 {
2281 	struct xl_softc *sc = xsc;
2282 	struct mii_data *mii;
2283 
2284 	XL_LOCK_ASSERT(sc);
2285 
2286 	if (sc->xl_miibus != NULL) {
2287 		mii = device_get_softc(sc->xl_miibus);
2288 		mii_tick(mii);
2289 	}
2290 
2291 	xl_stats_update(sc);
2292 	if (xl_watchdog(sc) == EJUSTRETURN)
2293 		return;
2294 
2295 	callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2296 }
2297 
2298 static void
2299 xl_stats_update(struct xl_softc *sc)
2300 {
2301 	struct ifnet		*ifp = sc->xl_ifp;
2302 	struct xl_stats		xl_stats;
2303 	u_int8_t		*p;
2304 	int			i;
2305 
2306 	XL_LOCK_ASSERT(sc);
2307 
2308 	bzero((char *)&xl_stats, sizeof(struct xl_stats));
2309 
2310 	p = (u_int8_t *)&xl_stats;
2311 
2312 	/* Read all the stats registers. */
2313 	XL_SEL_WIN(6);
2314 
2315 	for (i = 0; i < 16; i++)
2316 		*p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2317 
2318 	if_inc_counter(ifp, IFCOUNTER_IERRORS, xl_stats.xl_rx_overrun);
2319 
2320 	if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2321 	    xl_stats.xl_tx_multi_collision +
2322 	    xl_stats.xl_tx_single_collision +
2323 	    xl_stats.xl_tx_late_collision);
2324 
2325 	/*
2326 	 * Boomerang and cyclone chips have an extra stats counter
2327 	 * in window 4 (BadSSD). We have to read this too in order
2328 	 * to clear out all the stats registers and avoid a statsoflow
2329 	 * interrupt.
2330 	 */
2331 	XL_SEL_WIN(4);
2332 	CSR_READ_1(sc, XL_W4_BADSSD);
2333 	XL_SEL_WIN(7);
2334 }
2335 
2336 /*
2337  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2338  * pointers to the fragment pointers.
2339  */
2340 static int
2341 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head)
2342 {
2343 	struct mbuf		*m_new;
2344 	struct ifnet		*ifp = sc->xl_ifp;
2345 	int			error, i, nseg, total_len;
2346 	u_int32_t		status;
2347 
2348 	XL_LOCK_ASSERT(sc);
2349 
2350 	error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head,
2351 	    sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2352 
2353 	if (error && error != EFBIG) {
2354 		if_printf(ifp, "can't map mbuf (error %d)\n", error);
2355 		return (error);
2356 	}
2357 
2358 	/*
2359 	 * Handle special case: we used up all 63 fragments,
2360 	 * but we have more mbufs left in the chain. Copy the
2361 	 * data into an mbuf cluster. Note that we don't
2362 	 * bother clearing the values in the other fragment
2363 	 * pointers/counters; it wouldn't gain us anything,
2364 	 * and would waste cycles.
2365 	 */
2366 	if (error) {
2367 		m_new = m_collapse(*m_head, M_NOWAIT, XL_MAXFRAGS);
2368 		if (m_new == NULL) {
2369 			m_freem(*m_head);
2370 			*m_head = NULL;
2371 			return (ENOBUFS);
2372 		}
2373 		*m_head = m_new;
2374 
2375 		error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map,
2376 		    *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2377 		if (error) {
2378 			m_freem(*m_head);
2379 			*m_head = NULL;
2380 			if_printf(ifp, "can't map mbuf (error %d)\n", error);
2381 			return (error);
2382 		}
2383 	}
2384 
2385 	KASSERT(nseg <= XL_MAXFRAGS,
2386 	    ("%s: too many DMA segments (%d)", __func__, nseg));
2387 	if (nseg == 0) {
2388 		m_freem(*m_head);
2389 		*m_head = NULL;
2390 		return (EIO);
2391 	}
2392 	bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2393 
2394 	total_len = 0;
2395 	for (i = 0; i < nseg; i++) {
2396 		KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES,
2397 		    ("segment size too large"));
2398 		c->xl_ptr->xl_frag[i].xl_addr =
2399 		    htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr);
2400 		c->xl_ptr->xl_frag[i].xl_len =
2401 		    htole32(sc->xl_cdata.xl_tx_segs[i].ds_len);
2402 		total_len += sc->xl_cdata.xl_tx_segs[i].ds_len;
2403 	}
2404 	c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG);
2405 
2406 	if (sc->xl_type == XL_TYPE_905B) {
2407 		status = XL_TXSTAT_RND_DEFEAT;
2408 
2409 #ifndef XL905B_TXCSUM_BROKEN
2410 		if ((*m_head)->m_pkthdr.csum_flags) {
2411 			if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
2412 				status |= XL_TXSTAT_IPCKSUM;
2413 			if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
2414 				status |= XL_TXSTAT_TCPCKSUM;
2415 			if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
2416 				status |= XL_TXSTAT_UDPCKSUM;
2417 		}
2418 #endif
2419 	} else
2420 		status = total_len;
2421 	c->xl_ptr->xl_status = htole32(status);
2422 	c->xl_ptr->xl_next = 0;
2423 
2424 	c->xl_mbuf = *m_head;
2425 	return (0);
2426 }
2427 
2428 /*
2429  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2430  * to the mbuf data regions directly in the transmit lists. We also save a
2431  * copy of the pointers since the transmit list fragment pointers are
2432  * physical addresses.
2433  */
2434 
2435 static void
2436 xl_start(struct ifnet *ifp)
2437 {
2438 	struct xl_softc		*sc = ifp->if_softc;
2439 
2440 	XL_LOCK(sc);
2441 
2442 	if (sc->xl_type == XL_TYPE_905B)
2443 		xl_start_90xB_locked(ifp);
2444 	else
2445 		xl_start_locked(ifp);
2446 
2447 	XL_UNLOCK(sc);
2448 }
2449 
2450 static void
2451 xl_start_locked(struct ifnet *ifp)
2452 {
2453 	struct xl_softc		*sc = ifp->if_softc;
2454 	struct mbuf		*m_head;
2455 	struct xl_chain		*prev = NULL, *cur_tx = NULL, *start_tx;
2456 	struct xl_chain		*prev_tx;
2457 	int			error;
2458 
2459 	XL_LOCK_ASSERT(sc);
2460 
2461 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2462 	    IFF_DRV_RUNNING)
2463 		return;
2464 	/*
2465 	 * Check for an available queue slot. If there are none,
2466 	 * punt.
2467 	 */
2468 	if (sc->xl_cdata.xl_tx_free == NULL) {
2469 		xl_txeoc(sc);
2470 		xl_txeof(sc);
2471 		if (sc->xl_cdata.xl_tx_free == NULL) {
2472 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2473 			return;
2474 		}
2475 	}
2476 
2477 	start_tx = sc->xl_cdata.xl_tx_free;
2478 
2479 	for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2480 	    sc->xl_cdata.xl_tx_free != NULL;) {
2481 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2482 		if (m_head == NULL)
2483 			break;
2484 
2485 		/* Pick a descriptor off the free list. */
2486 		prev_tx = cur_tx;
2487 		cur_tx = sc->xl_cdata.xl_tx_free;
2488 
2489 		/* Pack the data into the descriptor. */
2490 		error = xl_encap(sc, cur_tx, &m_head);
2491 		if (error) {
2492 			cur_tx = prev_tx;
2493 			if (m_head == NULL)
2494 				break;
2495 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2496 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2497 			break;
2498 		}
2499 
2500 		sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2501 		cur_tx->xl_next = NULL;
2502 
2503 		/* Chain it together. */
2504 		if (prev != NULL) {
2505 			prev->xl_next = cur_tx;
2506 			prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2507 		}
2508 		prev = cur_tx;
2509 
2510 		/*
2511 		 * If there's a BPF listener, bounce a copy of this frame
2512 		 * to him.
2513 		 */
2514 		BPF_MTAP(ifp, cur_tx->xl_mbuf);
2515 	}
2516 
2517 	/*
2518 	 * If there are no packets queued, bail.
2519 	 */
2520 	if (cur_tx == NULL)
2521 		return;
2522 
2523 	/*
2524 	 * Place the request for the upload interrupt
2525 	 * in the last descriptor in the chain. This way, if
2526 	 * we're chaining several packets at once, we'll only
2527 	 * get an interrupt once for the whole chain rather than
2528 	 * once for each packet.
2529 	 */
2530 	cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2531 
2532 	/*
2533 	 * Queue the packets. If the TX channel is clear, update
2534 	 * the downlist pointer register.
2535 	 */
2536 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2537 	xl_wait(sc);
2538 
2539 	if (sc->xl_cdata.xl_tx_head != NULL) {
2540 		sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2541 		sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2542 		    htole32(start_tx->xl_phys);
2543 		sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2544 		    htole32(~XL_TXSTAT_DL_INTR);
2545 		sc->xl_cdata.xl_tx_tail = cur_tx;
2546 	} else {
2547 		sc->xl_cdata.xl_tx_head = start_tx;
2548 		sc->xl_cdata.xl_tx_tail = cur_tx;
2549 	}
2550 	bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2551 	    BUS_DMASYNC_PREWRITE);
2552 	if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2553 		CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2554 
2555 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2556 
2557 	XL_SEL_WIN(7);
2558 
2559 	/*
2560 	 * Set a timeout in case the chip goes out to lunch.
2561 	 */
2562 	sc->xl_wdog_timer = 5;
2563 
2564 	/*
2565 	 * XXX Under certain conditions, usually on slower machines
2566 	 * where interrupts may be dropped, it's possible for the
2567 	 * adapter to chew up all the buffers in the receive ring
2568 	 * and stall, without us being able to do anything about it.
2569 	 * To guard against this, we need to make a pass over the
2570 	 * RX queue to make sure there aren't any packets pending.
2571 	 * Doing it here means we can flush the receive ring at the
2572 	 * same time the chip is DMAing the transmit descriptors we
2573 	 * just gave it.
2574 	 *
2575 	 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2576 	 * nature of their chips in all their marketing literature;
2577 	 * we may as well take advantage of it. :)
2578 	 */
2579 	taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2580 }
2581 
2582 static void
2583 xl_start_90xB_locked(struct ifnet *ifp)
2584 {
2585 	struct xl_softc		*sc = ifp->if_softc;
2586 	struct mbuf		*m_head;
2587 	struct xl_chain		*prev = NULL, *cur_tx = NULL, *start_tx;
2588 	struct xl_chain		*prev_tx;
2589 	int			error, idx;
2590 
2591 	XL_LOCK_ASSERT(sc);
2592 
2593 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2594 	    IFF_DRV_RUNNING)
2595 		return;
2596 
2597 	idx = sc->xl_cdata.xl_tx_prod;
2598 	start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2599 
2600 	for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2601 	    sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) {
2602 		if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2603 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2604 			break;
2605 		}
2606 
2607 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2608 		if (m_head == NULL)
2609 			break;
2610 
2611 		prev_tx = cur_tx;
2612 		cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2613 
2614 		/* Pack the data into the descriptor. */
2615 		error = xl_encap(sc, cur_tx, &m_head);
2616 		if (error) {
2617 			cur_tx = prev_tx;
2618 			if (m_head == NULL)
2619 				break;
2620 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2621 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2622 			break;
2623 		}
2624 
2625 		/* Chain it together. */
2626 		if (prev != NULL)
2627 			prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2628 		prev = cur_tx;
2629 
2630 		/*
2631 		 * If there's a BPF listener, bounce a copy of this frame
2632 		 * to him.
2633 		 */
2634 		BPF_MTAP(ifp, cur_tx->xl_mbuf);
2635 
2636 		XL_INC(idx, XL_TX_LIST_CNT);
2637 		sc->xl_cdata.xl_tx_cnt++;
2638 	}
2639 
2640 	/*
2641 	 * If there are no packets queued, bail.
2642 	 */
2643 	if (cur_tx == NULL)
2644 		return;
2645 
2646 	/*
2647 	 * Place the request for the upload interrupt
2648 	 * in the last descriptor in the chain. This way, if
2649 	 * we're chaining several packets at once, we'll only
2650 	 * get an interrupt once for the whole chain rather than
2651 	 * once for each packet.
2652 	 */
2653 	cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2654 
2655 	/* Start transmission */
2656 	sc->xl_cdata.xl_tx_prod = idx;
2657 	start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2658 	bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2659 	    BUS_DMASYNC_PREWRITE);
2660 
2661 	/*
2662 	 * Set a timeout in case the chip goes out to lunch.
2663 	 */
2664 	sc->xl_wdog_timer = 5;
2665 }
2666 
2667 static void
2668 xl_init(void *xsc)
2669 {
2670 	struct xl_softc		*sc = xsc;
2671 
2672 	XL_LOCK(sc);
2673 	xl_init_locked(sc);
2674 	XL_UNLOCK(sc);
2675 }
2676 
2677 static void
2678 xl_init_locked(struct xl_softc *sc)
2679 {
2680 	struct ifnet		*ifp = sc->xl_ifp;
2681 	int			error, i;
2682 	struct mii_data		*mii = NULL;
2683 
2684 	XL_LOCK_ASSERT(sc);
2685 
2686 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2687 		return;
2688 	/*
2689 	 * Cancel pending I/O and free all RX/TX buffers.
2690 	 */
2691 	xl_stop(sc);
2692 
2693 	/* Reset the chip to a known state. */
2694 	xl_reset(sc);
2695 
2696 	if (sc->xl_miibus == NULL) {
2697 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2698 		xl_wait(sc);
2699 	}
2700 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2701 	xl_wait(sc);
2702 	DELAY(10000);
2703 
2704 	if (sc->xl_miibus != NULL)
2705 		mii = device_get_softc(sc->xl_miibus);
2706 
2707 	/*
2708 	 * Clear WOL status and disable all WOL feature as WOL
2709 	 * would interfere Rx operation under normal environments.
2710 	 */
2711 	if ((sc->xl_flags & XL_FLAG_WOL) != 0) {
2712 		XL_SEL_WIN(7);
2713 		CSR_READ_2(sc, XL_W7_BM_PME);
2714 		CSR_WRITE_2(sc, XL_W7_BM_PME, 0);
2715 	}
2716 	/* Init our MAC address */
2717 	XL_SEL_WIN(2);
2718 	for (i = 0; i < ETHER_ADDR_LEN; i++) {
2719 		CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2720 				IF_LLADDR(sc->xl_ifp)[i]);
2721 	}
2722 
2723 	/* Clear the station mask. */
2724 	for (i = 0; i < 3; i++)
2725 		CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2726 #ifdef notdef
2727 	/* Reset TX and RX. */
2728 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2729 	xl_wait(sc);
2730 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2731 	xl_wait(sc);
2732 #endif
2733 	/* Init circular RX list. */
2734 	error = xl_list_rx_init(sc);
2735 	if (error) {
2736 		device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2737 		    error);
2738 		xl_stop(sc);
2739 		return;
2740 	}
2741 
2742 	/* Init TX descriptors. */
2743 	if (sc->xl_type == XL_TYPE_905B)
2744 		error = xl_list_tx_init_90xB(sc);
2745 	else
2746 		error = xl_list_tx_init(sc);
2747 	if (error) {
2748 		device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2749 		    error);
2750 		xl_stop(sc);
2751 		return;
2752 	}
2753 
2754 	/*
2755 	 * Set the TX freethresh value.
2756 	 * Note that this has no effect on 3c905B "cyclone"
2757 	 * cards but is required for 3c900/3c905 "boomerang"
2758 	 * cards in order to enable the download engine.
2759 	 */
2760 	CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2761 
2762 	/* Set the TX start threshold for best performance. */
2763 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2764 
2765 	/*
2766 	 * If this is a 3c905B, also set the tx reclaim threshold.
2767 	 * This helps cut down on the number of tx reclaim errors
2768 	 * that could happen on a busy network. The chip multiplies
2769 	 * the register value by 16 to obtain the actual threshold
2770 	 * in bytes, so we divide by 16 when setting the value here.
2771 	 * The existing threshold value can be examined by reading
2772 	 * the register at offset 9 in window 5.
2773 	 */
2774 	if (sc->xl_type == XL_TYPE_905B) {
2775 		CSR_WRITE_2(sc, XL_COMMAND,
2776 		    XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2777 	}
2778 
2779 	/* Set RX filter bits. */
2780 	xl_rxfilter(sc);
2781 
2782 	/*
2783 	 * Load the address of the RX list. We have to
2784 	 * stall the upload engine before we can manipulate
2785 	 * the uplist pointer register, then unstall it when
2786 	 * we're finished. We also have to wait for the
2787 	 * stall command to complete before proceeding.
2788 	 * Note that we have to do this after any RX resets
2789 	 * have completed since the uplist register is cleared
2790 	 * by a reset.
2791 	 */
2792 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2793 	xl_wait(sc);
2794 	CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2795 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2796 	xl_wait(sc);
2797 
2798 	if (sc->xl_type == XL_TYPE_905B) {
2799 		/* Set polling interval */
2800 		CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2801 		/* Load the address of the TX list */
2802 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2803 		xl_wait(sc);
2804 		CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2805 		    sc->xl_cdata.xl_tx_chain[0].xl_phys);
2806 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2807 		xl_wait(sc);
2808 	}
2809 
2810 	/*
2811 	 * If the coax transceiver is on, make sure to enable
2812 	 * the DC-DC converter.
2813 	 */
2814 	XL_SEL_WIN(3);
2815 	if (sc->xl_xcvr == XL_XCVR_COAX)
2816 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2817 	else
2818 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2819 
2820 	/*
2821 	 * increase packet size to allow reception of 802.1q or ISL packets.
2822 	 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2823 	 * control register. For 3c90xB/C chips, use the RX packet size
2824 	 * register.
2825 	 */
2826 
2827 	if (sc->xl_type == XL_TYPE_905B)
2828 		CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2829 	else {
2830 		u_int8_t macctl;
2831 		macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2832 		macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2833 		CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2834 	}
2835 
2836 	/* Clear out the stats counters. */
2837 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2838 	xl_stats_update(sc);
2839 	XL_SEL_WIN(4);
2840 	CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2841 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2842 
2843 	/*
2844 	 * Enable interrupts.
2845 	 */
2846 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2847 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2848 #ifdef DEVICE_POLLING
2849 	/* Disable interrupts if we are polling. */
2850 	if (ifp->if_capenable & IFCAP_POLLING)
2851 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2852 	else
2853 #endif
2854 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2855 	if (sc->xl_flags & XL_FLAG_FUNCREG)
2856 	    bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2857 
2858 	/* Set the RX early threshold */
2859 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2860 	CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2861 
2862 	/* Enable receiver and transmitter. */
2863 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2864 	xl_wait(sc);
2865 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2866 	xl_wait(sc);
2867 
2868 	/* XXX Downcall to miibus. */
2869 	if (mii != NULL)
2870 		mii_mediachg(mii);
2871 
2872 	/* Select window 7 for normal operations. */
2873 	XL_SEL_WIN(7);
2874 
2875 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
2876 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2877 
2878 	sc->xl_wdog_timer = 0;
2879 	callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2880 }
2881 
2882 /*
2883  * Set media options.
2884  */
2885 static int
2886 xl_ifmedia_upd(struct ifnet *ifp)
2887 {
2888 	struct xl_softc		*sc = ifp->if_softc;
2889 	struct ifmedia		*ifm = NULL;
2890 	struct mii_data		*mii = NULL;
2891 
2892 	XL_LOCK(sc);
2893 
2894 	if (sc->xl_miibus != NULL)
2895 		mii = device_get_softc(sc->xl_miibus);
2896 	if (mii == NULL)
2897 		ifm = &sc->ifmedia;
2898 	else
2899 		ifm = &mii->mii_media;
2900 
2901 	switch (IFM_SUBTYPE(ifm->ifm_media)) {
2902 	case IFM_100_FX:
2903 	case IFM_10_FL:
2904 	case IFM_10_2:
2905 	case IFM_10_5:
2906 		xl_setmode(sc, ifm->ifm_media);
2907 		XL_UNLOCK(sc);
2908 		return (0);
2909 	}
2910 
2911 	if (sc->xl_media & XL_MEDIAOPT_MII ||
2912 	    sc->xl_media & XL_MEDIAOPT_BTX ||
2913 	    sc->xl_media & XL_MEDIAOPT_BT4) {
2914 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2915 		xl_init_locked(sc);
2916 	} else {
2917 		xl_setmode(sc, ifm->ifm_media);
2918 	}
2919 
2920 	XL_UNLOCK(sc);
2921 
2922 	return (0);
2923 }
2924 
2925 /*
2926  * Report current media status.
2927  */
2928 static void
2929 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2930 {
2931 	struct xl_softc		*sc = ifp->if_softc;
2932 	u_int32_t		icfg;
2933 	u_int16_t		status = 0;
2934 	struct mii_data		*mii = NULL;
2935 
2936 	XL_LOCK(sc);
2937 
2938 	if (sc->xl_miibus != NULL)
2939 		mii = device_get_softc(sc->xl_miibus);
2940 
2941 	XL_SEL_WIN(4);
2942 	status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2943 
2944 	XL_SEL_WIN(3);
2945 	icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2946 	icfg >>= XL_ICFG_CONNECTOR_BITS;
2947 
2948 	ifmr->ifm_active = IFM_ETHER;
2949 	ifmr->ifm_status = IFM_AVALID;
2950 
2951 	if ((status & XL_MEDIASTAT_CARRIER) == 0)
2952 		ifmr->ifm_status |= IFM_ACTIVE;
2953 
2954 	switch (icfg) {
2955 	case XL_XCVR_10BT:
2956 		ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2957 		if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2958 			ifmr->ifm_active |= IFM_FDX;
2959 		else
2960 			ifmr->ifm_active |= IFM_HDX;
2961 		break;
2962 	case XL_XCVR_AUI:
2963 		if (sc->xl_type == XL_TYPE_905B &&
2964 		    sc->xl_media == XL_MEDIAOPT_10FL) {
2965 			ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
2966 			if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2967 				ifmr->ifm_active |= IFM_FDX;
2968 			else
2969 				ifmr->ifm_active |= IFM_HDX;
2970 		} else
2971 			ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2972 		break;
2973 	case XL_XCVR_COAX:
2974 		ifmr->ifm_active = IFM_ETHER|IFM_10_2;
2975 		break;
2976 	/*
2977 	 * XXX MII and BTX/AUTO should be separate cases.
2978 	 */
2979 
2980 	case XL_XCVR_100BTX:
2981 	case XL_XCVR_AUTO:
2982 	case XL_XCVR_MII:
2983 		if (mii != NULL) {
2984 			mii_pollstat(mii);
2985 			ifmr->ifm_active = mii->mii_media_active;
2986 			ifmr->ifm_status = mii->mii_media_status;
2987 		}
2988 		break;
2989 	case XL_XCVR_100BFX:
2990 		ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
2991 		break;
2992 	default:
2993 		if_printf(ifp, "unknown XCVR type: %d\n", icfg);
2994 		break;
2995 	}
2996 
2997 	XL_UNLOCK(sc);
2998 }
2999 
3000 static int
3001 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3002 {
3003 	struct xl_softc		*sc = ifp->if_softc;
3004 	struct ifreq		*ifr = (struct ifreq *) data;
3005 	int			error = 0, mask;
3006 	struct mii_data		*mii = NULL;
3007 
3008 	switch (command) {
3009 	case SIOCSIFFLAGS:
3010 		XL_LOCK(sc);
3011 		if (ifp->if_flags & IFF_UP) {
3012 			if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3013 			    (ifp->if_flags ^ sc->xl_if_flags) &
3014 			    (IFF_PROMISC | IFF_ALLMULTI))
3015 				xl_rxfilter(sc);
3016 			else
3017 				xl_init_locked(sc);
3018 		} else {
3019 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3020 				xl_stop(sc);
3021 		}
3022 		sc->xl_if_flags = ifp->if_flags;
3023 		XL_UNLOCK(sc);
3024 		break;
3025 	case SIOCADDMULTI:
3026 	case SIOCDELMULTI:
3027 		/* XXX Downcall from if_addmulti() possibly with locks held. */
3028 		XL_LOCK(sc);
3029 		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3030 			xl_rxfilter(sc);
3031 		XL_UNLOCK(sc);
3032 		break;
3033 	case SIOCGIFMEDIA:
3034 	case SIOCSIFMEDIA:
3035 		if (sc->xl_miibus != NULL)
3036 			mii = device_get_softc(sc->xl_miibus);
3037 		if (mii == NULL)
3038 			error = ifmedia_ioctl(ifp, ifr,
3039 			    &sc->ifmedia, command);
3040 		else
3041 			error = ifmedia_ioctl(ifp, ifr,
3042 			    &mii->mii_media, command);
3043 		break;
3044 	case SIOCSIFCAP:
3045 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3046 #ifdef DEVICE_POLLING
3047 		if ((mask & IFCAP_POLLING) != 0 &&
3048 		    (ifp->if_capabilities & IFCAP_POLLING) != 0) {
3049 			ifp->if_capenable ^= IFCAP_POLLING;
3050 			if ((ifp->if_capenable & IFCAP_POLLING) != 0) {
3051 				error = ether_poll_register(xl_poll, ifp);
3052 				if (error)
3053 					break;
3054 				XL_LOCK(sc);
3055 				/* Disable interrupts */
3056 				CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3057 				ifp->if_capenable |= IFCAP_POLLING;
3058 				XL_UNLOCK(sc);
3059 			} else {
3060 				error = ether_poll_deregister(ifp);
3061 				/* Enable interrupts. */
3062 				XL_LOCK(sc);
3063 				CSR_WRITE_2(sc, XL_COMMAND,
3064 				    XL_CMD_INTR_ACK | 0xFF);
3065 				CSR_WRITE_2(sc, XL_COMMAND,
3066 				    XL_CMD_INTR_ENB | XL_INTRS);
3067 				if (sc->xl_flags & XL_FLAG_FUNCREG)
3068 					bus_space_write_4(sc->xl_ftag,
3069 					    sc->xl_fhandle, 4, 0x8000);
3070 				XL_UNLOCK(sc);
3071 			}
3072 		}
3073 #endif /* DEVICE_POLLING */
3074 		XL_LOCK(sc);
3075 		if ((mask & IFCAP_TXCSUM) != 0 &&
3076 		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3077 			ifp->if_capenable ^= IFCAP_TXCSUM;
3078 			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3079 				ifp->if_hwassist |= XL905B_CSUM_FEATURES;
3080 			else
3081 				ifp->if_hwassist &= ~XL905B_CSUM_FEATURES;
3082 		}
3083 		if ((mask & IFCAP_RXCSUM) != 0 &&
3084 		    (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3085 			ifp->if_capenable ^= IFCAP_RXCSUM;
3086 		if ((mask & IFCAP_WOL_MAGIC) != 0 &&
3087 		    (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
3088 			ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3089 		XL_UNLOCK(sc);
3090 		break;
3091 	default:
3092 		error = ether_ioctl(ifp, command, data);
3093 		break;
3094 	}
3095 
3096 	return (error);
3097 }
3098 
3099 static int
3100 xl_watchdog(struct xl_softc *sc)
3101 {
3102 	struct ifnet		*ifp = sc->xl_ifp;
3103 	u_int16_t		status = 0;
3104 	int			misintr;
3105 
3106 	XL_LOCK_ASSERT(sc);
3107 
3108 	if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3109 		return (0);
3110 
3111 	xl_rxeof(sc);
3112 	xl_txeoc(sc);
3113 	misintr = 0;
3114 	if (sc->xl_type == XL_TYPE_905B) {
3115 		xl_txeof_90xB(sc);
3116 		if (sc->xl_cdata.xl_tx_cnt == 0)
3117 			misintr++;
3118 	} else {
3119 		xl_txeof(sc);
3120 		if (sc->xl_cdata.xl_tx_head == NULL)
3121 			misintr++;
3122 	}
3123 	if (misintr != 0) {
3124 		device_printf(sc->xl_dev,
3125 		    "watchdog timeout (missed Tx interrupts) -- recovering\n");
3126 		return (0);
3127 	}
3128 
3129 	if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3130 	XL_SEL_WIN(4);
3131 	status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3132 	device_printf(sc->xl_dev, "watchdog timeout\n");
3133 
3134 	if (status & XL_MEDIASTAT_CARRIER)
3135 		device_printf(sc->xl_dev,
3136 		    "no carrier - transceiver cable problem?\n");
3137 
3138 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3139 	xl_init_locked(sc);
3140 
3141 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3142 		if (sc->xl_type == XL_TYPE_905B)
3143 			xl_start_90xB_locked(ifp);
3144 		else
3145 			xl_start_locked(ifp);
3146 	}
3147 
3148 	return (EJUSTRETURN);
3149 }
3150 
3151 /*
3152  * Stop the adapter and free any mbufs allocated to the
3153  * RX and TX lists.
3154  */
3155 static void
3156 xl_stop(struct xl_softc *sc)
3157 {
3158 	int			i;
3159 	struct ifnet		*ifp = sc->xl_ifp;
3160 
3161 	XL_LOCK_ASSERT(sc);
3162 
3163 	sc->xl_wdog_timer = 0;
3164 
3165 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3166 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3167 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3168 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3169 	xl_wait(sc);
3170 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3171 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3172 	DELAY(800);
3173 
3174 #ifdef foo
3175 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3176 	xl_wait(sc);
3177 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3178 	xl_wait(sc);
3179 #endif
3180 
3181 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3182 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3183 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3184 	if (sc->xl_flags & XL_FLAG_FUNCREG)
3185 		bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3186 
3187 	/* Stop the stats updater. */
3188 	callout_stop(&sc->xl_tick_callout);
3189 
3190 	/*
3191 	 * Free data in the RX lists.
3192 	 */
3193 	for (i = 0; i < XL_RX_LIST_CNT; i++) {
3194 		if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3195 			bus_dmamap_unload(sc->xl_mtag,
3196 			    sc->xl_cdata.xl_rx_chain[i].xl_map);
3197 			bus_dmamap_destroy(sc->xl_mtag,
3198 			    sc->xl_cdata.xl_rx_chain[i].xl_map);
3199 			m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3200 			sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3201 		}
3202 	}
3203 	if (sc->xl_ldata.xl_rx_list != NULL)
3204 		bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3205 	/*
3206 	 * Free the TX list buffers.
3207 	 */
3208 	for (i = 0; i < XL_TX_LIST_CNT; i++) {
3209 		if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3210 			bus_dmamap_unload(sc->xl_mtag,
3211 			    sc->xl_cdata.xl_tx_chain[i].xl_map);
3212 			bus_dmamap_destroy(sc->xl_mtag,
3213 			    sc->xl_cdata.xl_tx_chain[i].xl_map);
3214 			m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3215 			sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3216 		}
3217 	}
3218 	if (sc->xl_ldata.xl_tx_list != NULL)
3219 		bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3220 
3221 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3222 }
3223 
3224 /*
3225  * Stop all chip I/O so that the kernel's probe routines don't
3226  * get confused by errant DMAs when rebooting.
3227  */
3228 static int
3229 xl_shutdown(device_t dev)
3230 {
3231 
3232 	return (xl_suspend(dev));
3233 }
3234 
3235 static int
3236 xl_suspend(device_t dev)
3237 {
3238 	struct xl_softc		*sc;
3239 
3240 	sc = device_get_softc(dev);
3241 
3242 	XL_LOCK(sc);
3243 	xl_stop(sc);
3244 	xl_setwol(sc);
3245 	XL_UNLOCK(sc);
3246 
3247 	return (0);
3248 }
3249 
3250 static int
3251 xl_resume(device_t dev)
3252 {
3253 	struct xl_softc		*sc;
3254 	struct ifnet		*ifp;
3255 
3256 	sc = device_get_softc(dev);
3257 	ifp = sc->xl_ifp;
3258 
3259 	XL_LOCK(sc);
3260 
3261 	if (ifp->if_flags & IFF_UP) {
3262 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3263 		xl_init_locked(sc);
3264 	}
3265 
3266 	XL_UNLOCK(sc);
3267 
3268 	return (0);
3269 }
3270 
3271 static void
3272 xl_setwol(struct xl_softc *sc)
3273 {
3274 	struct ifnet		*ifp;
3275 	u_int16_t		cfg, pmstat;
3276 
3277 	if ((sc->xl_flags & XL_FLAG_WOL) == 0)
3278 		return;
3279 
3280 	ifp = sc->xl_ifp;
3281 	XL_SEL_WIN(7);
3282 	/* Clear any pending PME events. */
3283 	CSR_READ_2(sc, XL_W7_BM_PME);
3284 	cfg = 0;
3285 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3286 		cfg |= XL_BM_PME_MAGIC;
3287 	CSR_WRITE_2(sc, XL_W7_BM_PME, cfg);
3288 	/* Enable RX. */
3289 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3290 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3291 	/* Request PME. */
3292 	pmstat = pci_read_config(sc->xl_dev,
3293 	    sc->xl_pmcap + PCIR_POWER_STATUS, 2);
3294 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3295 		pmstat |= PCIM_PSTAT_PMEENABLE;
3296 	else
3297 		pmstat &= ~PCIM_PSTAT_PMEENABLE;
3298 	pci_write_config(sc->xl_dev,
3299 	    sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2);
3300 }
3301